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.\" $OpenBSD: arm_sync_icache.2,v 1.2 2007/05/31 19:19:27 jmc Exp $
.\" $NetBSD: arm_sync_icache.2,v 1.5 2004/02/13 09:56:47 wiz Exp $
.\"
.\" Copyright (c) 1996 Mark Brinicombe
.\" All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
.\" modification, are permitted provided that the following conditions
.\" are met:
.\" 1. Redistributions of source code must retain the above copyright
.\" notice, this list of conditions and the following disclaimer.
.\" 2. Redistributions in binary form must reproduce the above copyright
.\" notice, this list of conditions and the following disclaimer in the
.\" documentation and/or other materials provided with the distribution.
.\" 3. All advertising materials mentioning features or use of this software
.\" must display the following acknowledgement:
.\" This product includes software developed by Mark Brinicombe
.\" 4. Neither the name of the University nor the names of its contributors
.\" may be used to endorse or promote products derived from this software
.\" without specific prior written permission.
.\"
.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
.Dd $Mdocdate: May 31 2007 $
.Dt ARM_SYNC_ICACHE 2 arm
.Os
.Sh NAME
.Nm arm_sync_icache
.Nd clean the CPU data cache and flush the CPU instruction cache
.Sh SYNOPSIS
.In machine/sysarch.h
.Ft int
.Fn arm_sync_icache "u_int addr" "int len"
.Sh DESCRIPTION
.Fn arm_sync_icache
will make sure that all the entries in the processor instruction cache
are synchronized with main memory and that any data in a write back cache
has been cleaned.
Some ARM processors (e.g. SA110) have separate instruction and data
caches, thus any dynamically generated or modified code needs to be
written back from any data caches to main memory and the instruction
cache needs to be synchronized with main memory.
.Pp
On such processors,
.Fn arm_sync_icache
will clean the data cache and invalidate the processor instruction cache
to force reloading from main memory.
On processors that have a shared instruction and data cache and have a
write through cache (e.g. ARM6), no action needs to be taken.
.Pp
The routine takes a start address
.Fa addr
and a length
.Fa len
to describe the area of memory that needs to be cleaned and synchronized.
.Sh ERRORS
.Fn arm_sync_icache
will never fail so will always return 0.
.Sh REFERENCES
StrongARM Data Sheet
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