path: root/share/man/man4/ahc.4

.\"	$OpenBSD: ahc.4,v 1.36 2007/05/31 19:19:48 jmc Exp $
.\"	$NetBSD: ahc.4,v 1.1.2.1 1996/08/25 17:22:14 thorpej Exp $
.\"
.\" Copyright (c) 1995, 1996
.\" 	Justin T. Gibbs.  All rights reserved.
.\"
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.\" modification, are permitted provided that the following conditions
.\" are met:
.\" 1. Redistributions of source code must retain the above copyright
.\"    notice, this list of conditions and the following disclaimer.
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.\"    derived from this software without specific prior written permission.
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.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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.\" NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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.Dd $Mdocdate: May 31 2007 $
.Dt AHC 4
.Os
.Sh NAME
.Nm ahc
.Nd Adaptec VL/EISA/PCI SCSI interface
.Sh SYNOPSIS
.Cd "ahc0	at isa?	" Pq VL
.Cd "ahc*	at eisa?	" Pq EISA
.Cd "ahc*	at pci?	" Pq PCI
.Cd "scsibus* at ahc?"
.Cd "option AHC_ALLOW_MEMIO"
.Cd "option AHC_TMODE_ENABLE"
.Sh DESCRIPTION
This driver provides access to the
.Tn SCSI
bus(es) connected to Adaptec
.Tn AIC7770 ,
.Tn AIC7850 ,
.Tn AIC7860 ,
.Tn AIC7870 ,
.Tn AIC7880 ,
.Tn AIC7890 ,
.Tn AIC7891 ,
.Tn AIC7892 ,
.Tn AIC7895 ,
.Tn AIC7896 ,
.Tn AIC7897
and
.Tn AIC7899
host adapter chips.
These chips are found on many motherboards as well as the following
Adaptec SCSI controller cards:
.Tn 274X(W) ,
.Tn 274X(T) ,
.Tn 284X ,
.Tn 2910 ,
.Tn 2915 ,
.Tn 2920 ,
.Tn 2930C ,
.Tn 2930U2 ,
.Tn 2940 ,
.Tn 2940J ,
.Tn 2940N ,
.Tn 2940U ,
.Tn 2940AU ,
.Tn 2940UW ,
.Tn 2940UW Dual ,
.Tn 2940UW Pro ,
.Tn 2940U2W ,
.Tn 2940U2B ,
.Tn 2950U2W ,
.Tn 2950U2B ,
.Tn 19160B ,
.Tn 29160B ,
.Tn 29160N ,
.Tn 3940 ,
.Tn 3940U ,
.Tn 3940AU ,
.Tn 3940UW ,
.Tn 3940AUW ,
.Tn 3940U2W ,
.Tn 3950U2 ,
.Tn 3960 ,
.Tn 39160 ,
.Tn 3985 ,
and
.Tn 4944UW .
.Pp
Driver features include support for twin and wide buses,
fast, ultra, ultra2 and ultra160 synchronous transfers depending on
controller type, tagged queuing, and SCB paging, and target mode.
.Pp
Memory mapped I/O can be enabled for PCI devices with the
.Dq Dv AHC_ALLOW_MEMIO
configuration option.
Memory mapped I/O is more efficient than the alternative, programmed I/O.
Most PCI BIOSes will map devices so that either technique for communicating
with the card is available.
In some cases,
usually when the PCI device is sitting behind a PCI->PCI bridge,
the BIOS may fail to properly initialize the chip for memory mapped I/O.
The typical symptom of this problem is a system hang if memory mapped I/O
is attempted.
Most modern motherboards perform the initialization correctly and work fine
with this option enabled.
This is the default mode of operation on every architecture except i386.
.Pp
Individual controllers may be configured to operate in the target role through
the
.Dq Dv AHC_TMODE_ENABLE
configuration option.
The value assigned to this option should be a bitmap of all units where target
mode is desired.
For example, a value of 0x25, would enable target mode on units 0, 2, and 5.
A value of 0x8a enables it for units 1, 3, and 7.
.Pp
Per target configuration performed in the
.Tn SCSI-Select
menu, accessible at boot
in
.No non- Ns Tn EISA
models,
or through an
.Tn EISA
configuration utility for
.Tn EISA
models,
is honored by this driver.
This includes synchronous/asynchronous transfers,
maximum synchronous negotiation rate,
wide transfers,
disconnection,
the host adapter's SCSI ID,
and,
in the case of
.Tn EISA
Twin Channel controllers,
the primary channel selection.
For systems that store non-volatile settings in a system specific manner
rather than a serial eeprom directly connected to the aic7xxx controller,
the
.Tn BIOS
must be enabled for the driver to access this information.
This restriction applies to all
.Tn EISA
and many motherboard configurations.
.Pp
Note that I/O addresses are determined automatically by the probe routines,
but care should be taken when using a 284x
.Pq Tn VESA No local bus controller
in an
.Tn EISA
system.
The jumpers setting the I/O area for the 284x should match the
.Tn EISA
slot into which the card is inserted to prevent conflicts with other
.Tn EISA
cards.
.Pp
Performance and feature sets vary throughout the aic7xxx product line.
The following table provides a comparison of the different chips supported by
the
.Nm
driver.
Note that wide and twin channel features, although always supported by a
particular chip, may be disabled in a particular motherboard or card design.
.Bd -ragged -offset indent
.Bl -column "aic7770 " "10 " "EISA/VL  " "10MHz " "16bit " "SCBs " Features
.Em "Chip       MIPS    Bus      MaxSync   MaxWidth  SCBs  Features"
aic7770     10    EISA/VL    10MHz     16Bit     4    1
aic7850     10    PCI/32     10MHz      8Bit     3
aic7860     10    PCI/32     20MHz      8Bit     3
aic7870     10    PCI/32     10MHz     16Bit    16
aic7880     10    PCI/32     20MHz     16Bit    16
aic7890     20    PCI/32     40MHz     16Bit    16        3 4 5 6 7 8
aic7891     20    PCI/64     40MHz     16Bit    16        3 4 5 6 7 8
aic7892     20    PCI/64     80MHz     16Bit    16        3 4 5 6 7 8
aic7895     15    PCI/32     20MHz     16Bit    16      2 3 4 5
aic7895C    15    PCI/32     20MHz     16Bit    16      2 3 4 5     8
aic7896     20    PCI/32     40MHz     16Bit    16      2 3 4 5 6 7 8
aic7897     20    PCI/64     40MHz     16Bit    16      2 3 4 5 6 7 8
aic7899     20    PCI/64     80MHz     16Bit    16      2 3 4 5 6 7 8
.El
.Pp
.Bl -enum -compact
.It
Multiplexed Twin Channel Device - One controller servicing two buses.
.It
Multi-function Twin Channel Device - Two controllers on one chip.
.It
Command Channel Secondary DMA Engine - Allows scatter gather list and
SCB prefetch.
.It
64 Byte SCB Support - SCSI CDB is embedded in the SCB to eliminate an extra DMA.
.It
Block Move Instruction Support - Doubles the speed of certain sequencer
operations.
.It
.Sq Bayonet
style Scatter Gather Engine - Improves S/G prefetch performance.
.It
Queuing Registers - Allows queuing of new transactions without pausing the
sequencer.
.It
Ultra160 support.
.It
Multiple Target IDs - Allows the controller to respond to selection as a target
on multiple SCSI IDs.
.El
.Ed
.Sh SCSI CONTROL BLOCKS (SCBs)
Every transaction sent to a device on the SCSI bus is assigned a
.Sq SCSI Control Block
(SCB).
The SCB contains all of the information required by the controller to process a
transaction.
The chip feature table lists the number of SCBs that can be stored in on-chip
memory.
All chips with model numbers greater than or equal to 7870 allow for the
on-chip SCB space to be augmented with external SRAM up to a maximum of 255
SCBs.
Very few Adaptec controller configurations have external SRAM.
.Pp
If external SRAM is not available,
SCBs are a limited resource.
Using the SCBs in a straight forward manner would only allow the driver to
handle as many concurrent transactions as there are physical SCBs.
To fully utilize the SCSI bus and the devices on it,
requires much more concurrency.
The solution to this problem is
.Em SCB Paging ,
a concept similar to memory paging.
SCB paging takes advantage of the fact that devices usually disconnect from the
SCSI bus for long periods of time without talking to the controller.
The SCBs for disconnected transactions are only of use to the controller when
the transfer is resumed.
When the host queues another transaction for the controller to execute,
the controller firmware will use a free SCB if one is available.
Otherwise, the state of the most recently disconnected (and therefore most
likely to stay disconnected) SCB is saved, via DMA, to host memory,
and the local SCB reused to start the new transaction.
This allows the controller to queue up to 255 transactions regardless of the
amount of SCB space.
Since the local SCB space serves as a cache for disconnected transactions,
the more SCB space available, the less host bus traffic consumed saving and
restoring SCB data.
.Sh SEE ALSO
.Xr ahd 4 ,
.Xr cd 4 ,
.Xr ch 4 ,
.Xr eisa 4 ,
.Xr intro 4 ,
.Xr isa 4 ,
.Xr pci 4 ,
.Xr scsi 4 ,
.Xr sd 4 ,
.Xr ss 4 ,
.Xr st 4 ,
.Xr uk 4
.Sh AUTHORS
The core
.Nm
driver, the
.Tn AIC7xxx
sequencer-code assembler, and the firmware running on the aic7xxx chips
were written by
.An Justin T. Gibbs .
.Pp
The
.Ox
platform dependent code was written by Steve P. Murphree, Jr and Kenneth
R. Westerback.
.Sh BUGS
Some Quantum drives (at least the Empire 2100 and 1080s) will not run on an
.Tn AIC7870
Rev B in synchronous mode at 10MHz.
Controllers with this problem have a 42 MHz clock crystal on them and run
slightly above 10MHz.
This confuses the drive and hangs the bus.
Setting a maximum synchronous negotiation rate of 8MHz in the
.Tn SCSI-Select
utility will allow normal operation.
.Pp
Although the Ultra2 and Ultra160 products have sufficient instruction RAM space
to support both the initiator and target roles concurrently,
this configuration is disabled in favor of allowing the target role to respond
on multiple target ids.
A method for configuring dual role mode should be provided.
.Pp
Tagged Queuing is not supported in target mode.
.Pp
Reselection in target mode fails to function correctly on all high voltage
differential boards as shipped by Adaptec.
Information on how to modify HVD board to work correctly in target mode is
available from Adaptec.