1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
|
/* $OpenBSD: pci_machdep.c,v 1.5 2021/03/22 20:30:21 patrick Exp $ */
/*
* Copyright (c) 2019 Mark Kettenis <kettenis@openbsd.org>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <machine/bus.h>
#include <dev/pci/pcivar.h>
#include <dev/pci/pcireg.h>
void
pci_msi_enable(pci_chipset_tag_t pc, pcitag_t tag,
bus_addr_t addr, uint32_t data)
{
pcireg_t reg;
int off;
if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, ®) == 0)
panic("%s: no msi capability", __func__);
if (reg & PCI_MSI_MC_C64) {
pci_conf_write(pc, tag, off + PCI_MSI_MA, addr);
pci_conf_write(pc, tag, off + PCI_MSI_MAU32, addr >> 32);
pci_conf_write(pc, tag, off + PCI_MSI_MD64, data);
} else {
pci_conf_write(pc, tag, off + PCI_MSI_MA, addr);
pci_conf_write(pc, tag, off + PCI_MSI_MD32, data);
}
pci_conf_write(pc, tag, off, reg | PCI_MSI_MC_MSIE);
}
int
pci_msix_table_map(pci_chipset_tag_t pc, pcitag_t tag,
bus_space_tag_t memt, bus_space_handle_t *memh)
{
bus_addr_t base;
pcireg_t reg, table, type;
int bir, offset;
int off, tblsz;
if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, ®) == 0)
panic("%s: no msix capability", __func__);
table = pci_conf_read(pc, tag, off + PCI_MSIX_TABLE);
bir = (table & PCI_MSIX_TABLE_BIR);
offset = (table & PCI_MSIX_TABLE_OFF);
tblsz = PCI_MSIX_MC_TBLSZ(reg) + 1;
bir = PCI_MAPREG_START + bir * 4;
type = pci_mapreg_type(pc, tag, bir);
if (pci_mapreg_info(pc, tag, bir, type, &base, NULL, NULL) ||
bus_space_map(memt, base + offset, tblsz * 16, 0, memh))
return -1;
return 0;
}
void
pci_msix_table_unmap(pci_chipset_tag_t pc, pcitag_t tag,
bus_space_tag_t memt, bus_space_handle_t memh)
{
pcireg_t reg;
int tblsz;
if (pci_get_capability(pc, tag, PCI_CAP_MSIX, NULL, ®) == 0)
panic("%s: no msix capability", __func__);
tblsz = PCI_MSIX_MC_TBLSZ(reg) + 1;
bus_space_unmap(memt, memh, tblsz * 16);
}
void
pci_msix_enable(pci_chipset_tag_t pc, pcitag_t tag, bus_space_tag_t memt,
int vec, bus_addr_t addr, uint32_t data)
{
bus_space_handle_t memh;
pcireg_t reg;
uint32_t ctrl;
int off;
if (pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, ®) == 0)
panic("%s: no msix capability", __func__);
KASSERT(vec <= PCI_MSIX_MC_TBLSZ(reg));
if (pci_msix_table_map(pc, tag, memt, &memh))
panic("%s: cannot map registers", __func__);
bus_space_write_4(memt, memh, PCI_MSIX_MA(vec), addr);
bus_space_write_4(memt, memh, PCI_MSIX_MAU32(vec), addr >> 32);
bus_space_write_4(memt, memh, PCI_MSIX_MD(vec), data);
bus_space_barrier(memt, memh, PCI_MSIX_MA(vec), 16,
BUS_SPACE_BARRIER_WRITE);
ctrl = bus_space_read_4(memt, memh, PCI_MSIX_VC(vec));
bus_space_write_4(memt, memh, PCI_MSIX_VC(vec),
ctrl & ~PCI_MSIX_VC_MASK);
pci_msix_table_unmap(pc, tag, memt, memh);
pci_conf_write(pc, tag, off, reg | PCI_MSIX_MC_MSIXE);
}
int
_pci_intr_map_msi(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
{
pci_chipset_tag_t pc = pa->pa_pc;
pcitag_t tag = pa->pa_tag;
if ((pa->pa_flags & PCI_FLAGS_MSI_ENABLED) == 0 ||
pci_get_capability(pc, tag, PCI_CAP_MSI, NULL, NULL) == 0)
return -1;
ihp->ih_pc = pa->pa_pc;
ihp->ih_tag = pa->pa_tag;
ihp->ih_type = PCI_MSI;
ihp->ih_dmat = pa->pa_dmat;
return 0;
}
int
_pci_intr_map_msix(struct pci_attach_args *pa, int vec,
pci_intr_handle_t *ihp)
{
pci_chipset_tag_t pc = pa->pa_pc;
pcitag_t tag = pa->pa_tag;
pcireg_t reg, table, type;
int bir, off;
if ((pa->pa_flags & PCI_FLAGS_MSI_ENABLED) == 0 ||
pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, ®) == 0)
return -1;
if (vec > PCI_MSIX_MC_TBLSZ(reg))
return -1;
table = pci_conf_read(pc, tag, off + PCI_MSIX_TABLE);
bir = PCI_MAPREG_START + (table & PCI_MSIX_TABLE_BIR) * 4;
type = pci_mapreg_type(pc, tag, bir);
if (pci_mapreg_assign(pa, bir, type, NULL, NULL))
return -1;
ihp->ih_pc = pa->pa_pc;
ihp->ih_tag = pa->pa_tag;
ihp->ih_intrpin = vec;
ihp->ih_type = PCI_MSIX;
ihp->ih_dmat = pa->pa_dmat;
return 0;
}
|
