1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
|
/* $OpenBSD: intr.h,v 1.11 2019/05/06 03:34:43 mlarkin Exp $ */
/* $NetBSD: intr.h,v 1.12 2003/06/16 20:00:59 thorpej Exp $ */
/*
* Copyright (c) 2001, 2003 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _MACHINE_INTR_H_
#define _MACHINE_INTR_H_
#ifdef _KERNEL
/* Interrupt priority "levels". */
#define IPL_NONE 0 /* nothing */
#define IPL_SOFT 1 /* generic software interrupts */
#define IPL_SOFTCLOCK 2 /* software clock interrupt */
#define IPL_SOFTNET 3 /* software network interrupt */
#define IPL_SOFTTTY 4 /* software serial interrupt */
#define IPL_BIO 5 /* block I/O */
#define IPL_NET 6 /* network */
#define IPL_TTY 7 /* terminals */
#define IPL_VM 8 /* memory allocation */
#define IPL_AUDIO 9 /* audio device */
#define IPL_CLOCK 10 /* clock interrupt */
#define IPL_STATCLOCK 11 /* statistics clock interrupt */
#define IPL_SCHED 12 /* everything */
#define IPL_HIGH 12 /* everything */
#define NIPL 13
/* Interrupt priority "flags". */
#define IPL_MPSAFE 0 /* no "mpsafe" interrupts */
#define IPL_MPFLOOR IPL_NONE /* no MP on armv7 */
/* Interrupt sharing types. */
#define IST_NONE 0 /* none */
#define IST_PULSE 1 /* pulsed */
#define IST_EDGE 2 /* edge-triggered */
#define IST_LEVEL 3 /* level-triggered */
#define IST_LEVEL_LOW IST_LEVEL
#define IST_LEVEL_HIGH 4
#define IST_EDGE_FALLING IST_EDGE
#define IST_EDGE_RISING 5
#define IST_EDGE_BOTH 6
#ifndef _LOCORE
#include <sys/device.h>
#include <sys/queue.h>
int splraise(int);
int spllower(int);
void splx(int);
void arm_do_pending_intr(int);
void arm_set_intr_handler(int (*raise)(int), int (*lower)(int),
void (*x)(int), void (*setipl)(int),
void *(*intr_establish)(int irqno, int level, int (*func)(void *),
void *cookie, char *name),
void (*intr_disestablish)(void *cookie),
const char *(*intr_string)(void *cookie),
void (*intr_handle)(void *));
struct arm_intr_func {
int (*raise)(int);
int (*lower)(int);
void (*x)(int);
void (*setipl)(int);
void *(*intr_establish)(int irqno, int level, int (*func)(void *),
void *cookie, char *name);
void (*intr_disestablish)(void *cookie);
const char *(*intr_string)(void *cookie);
};
extern struct arm_intr_func arm_intr_func;
#define splraise(cpl) (arm_intr_func.raise(cpl))
#define _splraise(cpl) (arm_intr_func.raise(cpl))
#define spllower(cpl) (arm_intr_func.lower(cpl))
#define splx(cpl) (arm_intr_func.x(cpl))
#define splhigh() splraise(IPL_HIGH)
#define splsoft() splraise(IPL_SOFT)
#define splsoftclock() splraise(IPL_SOFTCLOCK)
#define splsoftnet() splraise(IPL_SOFTNET)
#define splbio() splraise(IPL_BIO)
#define splnet() splraise(IPL_NET)
#define spltty() splraise(IPL_TTY)
#define splvm() splraise(IPL_VM)
#define splaudio() splraise(IPL_AUDIO)
#define splclock() splraise(IPL_CLOCK)
#define splstatclock() splraise(IPL_STATCLOCK)
#define spl0() spllower(IPL_NONE)
#define splsched() splhigh()
void intr_barrier(void *);
void arm_init_smask(void); /* XXX */
extern uint32_t arm_smask[NIPL];
void arm_setsoftintr(int si);
#define _setsoftintr arm_setsoftintr
#include <arm/softintr.h>
void *arm_intr_establish(int irqno, int level, int (*func)(void *),
void *cookie, char *name);
void arm_intr_disestablish(void *cookie);
const char *arm_intr_string(void *cookie);
/* XXX - this is probably the wrong location for this */
void arm_clock_register(void (*)(void), void (*)(u_int), void (*)(int),
void (*)(void));
struct cpu_info;
struct interrupt_controller {
int ic_node;
void *ic_cookie;
void *(*ic_establish)(void *, int *, int, int (*)(void *),
void *, char *);
void *(*ic_establish_msi)(void *, uint64_t *, uint64_t *, int,
int (*)(void *), void *, char *);
void (*ic_disestablish)(void *);
void (*ic_enable)(void *);
void (*ic_disable)(void *);
void (*ic_route)(void *, int, struct cpu_info *);
LIST_ENTRY(interrupt_controller) ic_list;
uint32_t ic_phandle;
uint32_t ic_cells;
};
void arm_intr_init_fdt(void);
void arm_intr_register_fdt(struct interrupt_controller *);
void *arm_intr_establish_fdt(int, int, int (*)(void *),
void *, char *);
void *arm_intr_establish_fdt_idx(int, int, int, int (*)(void *),
void *, char *);
void *arm_intr_establish_fdt_imap(int, int *, int, int, int (*)(void *),
void *, char *);
void *arm_intr_establish_fdt_msi(int, uint64_t *, uint64_t *, int ,
int (*)(void *), void *, char *);
void arm_intr_disestablish_fdt(void *);
void arm_intr_enable(void *);
void arm_intr_disable(void *);
void arm_intr_route(void *, int, struct cpu_info *);
void *arm_intr_parent_establish_fdt(void *, int *, int,
int (*)(void *), void *, char *);
void arm_intr_parent_disestablish_fdt(void *);
#ifdef DIAGNOSTIC
/*
* Although this function is implemented in MI code, it must be in this MD
* header because we don't want this header to include MI includes.
*/
void splassert_fail(int, int, const char *);
extern int splassert_ctl;
void arm_splassert_check(int, const char *);
#define splassert(__wantipl) do { \
if (splassert_ctl > 0) { \
arm_splassert_check(__wantipl, __func__); \
} \
} while (0)
#define splsoftassert(wantipl) splassert(wantipl)
#else
#define splassert(wantipl) do { /* nothing */ } while (0)
#define splsoftassert(wantipl) do { /* nothing */ } while (0)
#endif
#endif /* ! _LOCORE */
#define ARM_IRQ_HANDLER arm_intr
#endif /* _KERNEL */
#endif /* _MACHINE_INTR_H_ */
|
