1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
|
/* $OpenBSD: osiop_gsc.c,v 1.13 2022/03/13 08:04:38 mpi Exp $ */
/* $NetBSD: osiop_gsc.c,v 1.6 2002/10/02 05:17:50 thorpej Exp $ */
/*
* Copyright (c) 2001 Matt Fredette. All rights reserved.
* Copyright (c) 2001 Izumi Tsutsui. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Copyright (c) 1998 Michael Shalayeff
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/buf.h>
#include <sys/malloc.h>
#include <scsi/scsi_all.h>
#include <scsi/scsiconf.h>
#include <machine/cpu.h>
#include <machine/intr.h>
#include <machine/iomod.h>
#include <machine/autoconf.h>
#include <machine/bus.h>
#include <dev/ic/osiopreg.h>
#include <dev/ic/osiopvar.h>
#include <hppa/dev/cpudevs.h>
#include <hppa/gsc/gscbusvar.h>
/* #include <hppa/hppa/machdep.h> */
#define OSIOP_GSC_RESET 0x0000
#define OSIOP_GSC_OFFSET 0x0100
int osiop_gsc_match(struct device *, void *, void *);
void osiop_gsc_attach(struct device *, struct device *, void *);
int osiop_gsc_intr(void *);
const struct cfattach osiop_gsc_ca = {
sizeof(struct osiop_softc), osiop_gsc_match, osiop_gsc_attach
};
int
osiop_gsc_match(parent, match, aux)
struct device *parent;
void *match, *aux;
{
struct gsc_attach_args *ga = aux;
if (ga->ga_type.iodc_type != HPPA_TYPE_FIO ||
ga->ga_type.iodc_sv_model != HPPA_FIO_GSCSI)
return 0;
return 1;
}
void
osiop_gsc_attach(parent, self, aux)
struct device *parent, *self;
void *aux;
{
struct osiop_softc *sc = (void *)self;
struct gsc_attach_args *ga = aux;
bus_space_handle_t ioh;
sc->sc_bst = ga->ga_iot;
sc->sc_dmat = ga->ga_dmatag;
if (bus_space_map(sc->sc_bst, ga->ga_hpa,
OSIOP_GSC_OFFSET + OSIOP_NREGS, 0, &ioh))
panic("osiop_gsc_attach: couldn't map I/O ports");
if (bus_space_subregion(sc->sc_bst, ioh,
OSIOP_GSC_OFFSET, OSIOP_NREGS, &sc->sc_reg))
panic("osiop_gsc_attach: couldn't get chip ports");
sc->sc_clock_freq = ga->ga_ca.ca_pdc_iodc_read->filler2[14] / 1000000;
if (!sc->sc_clock_freq)
sc->sc_clock_freq = 50;
sc->sc_dcntl = OSIOP_DCNTL_EA;
/* XXX set burst mode to 8 words (32 bytes) */
sc->sc_ctest7 = OSIOP_CTEST7_CDIS;
sc->sc_dmode = OSIOP_DMODE_BL8; /* | OSIOP_DMODE_FC2 */
sc->sc_flags = 0;
sc->sc_id = 7; /* XXX */
/*
* Reset the SCSI subsystem.
*/
bus_space_write_1(sc->sc_bst, ioh, OSIOP_GSC_RESET, 0);
DELAY(1000);
/*
* Call common attachment
*/
#ifdef OSIOP_DEBUG
{
extern int osiop_debug;
osiop_debug = -1;
}
#endif /* OSIOP_DEBUG */
osiop_attach(sc);
(void)gsc_intr_establish((struct gsc_softc *)parent,
ga->ga_irq, IPL_BIO, osiop_gsc_intr, sc, sc->sc_dev.dv_xname);
}
/*
* interrupt handler
*/
int
osiop_gsc_intr(arg)
void *arg;
{
struct osiop_softc *sc = arg;
u_int8_t istat;
/* This is potentially nasty, since the IRQ is level triggered... */
if (sc->sc_flags & OSIOP_INTSOFF)
return (0);
istat = osiop_read_1(sc, OSIOP_ISTAT);
if ((istat & (OSIOP_ISTAT_SIP | OSIOP_ISTAT_DIP)) == 0)
return (0);
/* Save interrupt details for the back-end interrupt handler */
sc->sc_sstat0 = osiop_read_1(sc, OSIOP_SSTAT0);
sc->sc_istat = istat;
/*
* Per page 4-18 of the LSI 53C710 Technical Manual,
* "insert a delay equivalent to 12 BCLK periods between
* the reads [of DSTAT and SSTAT0] to ensure that the
* interrupts clear properly." 1 BCLK = 40ns. Pg. 6-10.
*/
DELAY(25);
sc->sc_dstat = osiop_read_1(sc, OSIOP_DSTAT);
/* Deal with the interrupt */
osiop_intr(sc);
#ifdef USELEDS
ledctl(PALED_DISK, 0, 0);
#endif
return (1);
}
|