1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
|
/* $OpenBSD: interrupt.c,v 1.49 2009/10/22 22:08:54 miod Exp $ */
/*
* Copyright (c) 2001-2004 Opsycon AB (www.opsycon.se / www.opsycon.com)
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/user.h>
#include <uvm/uvm_extern.h>
#include <machine/cpu.h>
#include <machine/intr.h>
#include <machine/frame.h>
#include <mips64/rm7000.h>
#ifdef DDB
#include <mips64/db_machdep.h>
#include <ddb/db_sym.h>
#endif
void dummy_splx(int);
void interrupt(struct trap_frame *);
static struct evcount soft_count;
static int soft_irq = 0;
uint32_t idle_mask;
int last_low_int;
struct {
uint32_t int_mask;
uint32_t (*int_hand)(uint32_t, struct trap_frame *);
} cpu_int_tab[NLOWINT];
int_f *splx_hand = &dummy_splx;
/*
* Modern versions of MIPS processors have extended interrupt
* capabilities. How these are handled differs from implementation
* to implementation. This code tries to hide away some of these
* in "higher level" interrupt code.
*
* Basically there are <n> interrupt inputs to the processor and
* typically the HW designer ties these interrupts to various
* sources in the HW. The low level code does not deal with interrupts
* in more than it dispatches handling to the code that has registered
* an interrupt handler for that particular interrupt. More than one
* handler can register to an interrupt input and one handler may register
* for more than one interrupt input. A handler is only called once even
* if it registers for more than one interrupt input.
*
* The interrupt mechanism in this port uses a delayed masking model
* where interrupts are not really masked when doing an spl(). Instead
* a masked interrupt will be taken and validated in the various
* handlers. If the handler finds that an interrupt is masked it will
* register this interrupt as pending and return a new mask to this
* code that will turn off the interrupt hardware wise. Later when
* the pending interrupt is unmasked it will be processed as usual
* and the regular hardware mask will be restored.
*/
/*
* Handle an interrupt. Both kernel and user mode are handled here.
*
* The interrupt handler is called with the CR_INT bits set that
* were given when the handler was registered.
* The handler should return a similar word with a mask indicating
* which CR_INT bits have been handled.
*/
void
interrupt(struct trap_frame *trapframe)
{
struct cpu_info *ci = curcpu();
u_int32_t pending;
int i, s;
/*
* Paranoic? Perhaps. But if we got here with the enable
* bit reset a mtc0 COP_0_STATUS_REG may have been interrupted.
* If this was a disable and the pipeline had advanced long
* enough... i don't know but better safe than sorry...
* The main effect is not the interrupts but the spl mechanism.
*/
if (!(trapframe->sr & SR_INT_ENAB))
return;
#ifdef DEBUG_INTERRUPT
trapdebug_enter(trapframe, 0);
#endif
uvmexp.intrs++;
/* Mask out interrupts from cause that are unmasked */
pending = trapframe->cause & CR_IPEND & trapframe->sr;
if (pending & SOFT_INT_MASK_0) {
clearsoftintr0();
soft_count.ec_count++;
}
#ifdef RM7K_PERFCNTR
if (pending & CR_INT_PERF)
rm7k_perfintr(trapframe);
#endif
for (i = 0; i <= last_low_int; i++) {
uint32_t active;
active = cpu_int_tab[i].int_mask & pending;
if (active != 0)
(*cpu_int_tab[i].int_hand)(active, trapframe);
}
/*
* Dispatch soft interrupts if current ipl allows them.
*/
if (ci->ci_ipl < IPL_SOFTINT && ci->ci_softpending != 0) {
s = splsoft();
dosoftint();
__asm__ (".set noreorder\n");
ci->ci_ipl = s; /* no-overhead splx */
__asm__ ("sync\n\t.set reorder\n");
}
}
/*
* Set up handler for external interrupt events.
* Use CR_INT_<n> to select the proper interrupt condition to dispatch on.
* We also enable the software ints here since they are always on.
*/
void
set_intr(int pri, uint32_t mask,
uint32_t (*int_hand)(uint32_t, struct trap_frame *))
{
if ((idle_mask & SOFT_INT_MASK) == 0)
evcount_attach(&soft_count, "soft", (void *)&soft_irq,
&evcount_intr);
if (pri < 0 || pri >= NLOWINT)
panic("set_intr: too high priority (%d), increase NLOWINT",
pri);
if (pri > last_low_int)
last_low_int = pri;
if ((mask & ~CR_IPEND) != 0)
panic("set_intr: invalid mask 0x%x", mask);
if (cpu_int_tab[pri].int_mask != 0 &&
(cpu_int_tab[pri].int_mask != mask ||
cpu_int_tab[pri].int_hand != int_hand))
panic("set_intr: int already set at pri %d", pri);
cpu_int_tab[pri].int_hand = int_hand;
cpu_int_tab[pri].int_mask = mask;
idle_mask |= mask | SOFT_INT_MASK;
}
void
dummy_splx(int newcpl)
{
/* Dummy handler */
}
/*
* splinit() is special in that sense that it require us to update
* the interrupt mask in the CPU since it may be the first time we arm
* the interrupt system. This function is called right after
* autoconfiguration has completed in autoconf.c.
* We enable everything in idle_mask.
*/
void
splinit()
{
struct proc *p = curproc;
struct pcb *pcb = &p->p_addr->u_pcb;
u_int32_t sr;
/*
* Update proc0 pcb to contain proper values.
*/
pcb->pcb_context.val[13] = IPL_NONE;
#ifdef RM7000_ICR
pcb->pcb_context.val[12] = (idle_mask << 8) & IC_INT_MASK;
#endif
pcb->pcb_context.val[11] = (pcb->pcb_regs.sr & ~SR_INT_MASK) |
(idle_mask & SR_INT_MASK);
spl0();
sr = updateimask(0);
sr |= SR_INT_ENAB;
setsr(sr);
}
int
splraise(int newipl)
{
struct cpu_info *ci = curcpu();
int oldipl;
__asm__ (".set noreorder\n");
oldipl = ci->ci_ipl;
if (oldipl < newipl) {
/* XXX to kill warning about dla being used in a delay slot */
__asm__("nop");
ci->ci_ipl = newipl;
}
__asm__ ("sync\n\t.set reorder\n");
return oldipl;
}
void
splx(int newipl)
{
(*splx_hand)(newipl);
}
int
spllower(int newipl)
{
struct cpu_info *ci = curcpu();
int oldipl;
oldipl = ci->ci_ipl;
splx(newipl);
return oldipl;
}
|
