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/* $NetBSD: cpu.h,v 1.20 1995/12/21 05:02:10 mycroft Exp $ */
/*
* Copyright (c) 1994 Gordon W. Ross
* Copyright (c) 1993 Adam Glass
* Copyright (c) 1988 University of Utah.
* Copyright (c) 1982, 1990 The Regents of the University of California.
* All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* the Systems Programming Group of the University of Utah Computer
* Science Department.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from: Utah Hdr: cpu.h 1.16 91/03/25
* from: @(#)cpu.h 7.7 (Berkeley) 6/27/91
* cpu.h,v 1.2 1993/05/22 07:58:17 cgd Exp
*/
#ifndef _SUN3_CPU_H_
#define _SUN3_CPU_H_
#ifdef _KERNEL
/*
* Exported definitions unique to sun3/68k cpu support.
*/
/*
* definitions of cpu-dependent requirements
* referenced in generic code
*/
#define cpu_swapin(p) /* nothing */
#define cpu_wait(p) /* nothing */
/*
* Arguments to hardclock and gatherstats encapsulate the previous
* machine state in an opaque clockframe. One the sun3, we use
* what the hardware pushes on an interrupt (frame format 0).
*/
struct clockframe {
u_short sr; /* sr at time of interrupt */
u_long pc; /* pc at time of interrupt */
u_short vo; /* vector offset (4-word frame) */
};
#define CLKF_USERMODE(framep) (((framep)->sr & PSL_S) == 0)
#define CLKF_BASEPRI(framep) (((framep)->sr & PSL_IPL) == 0)
#define CLKF_PC(framep) ((framep)->pc)
#if 0
/* We would like to do it this way... */
#define CLKF_INTR(framep) (((framep)->sr & PSL_M) == 0)
#else
/* but until we start using PSL_M, we have to do this instead */
#define CLKF_INTR(framep) (0) /* XXX */
#endif
extern int astpending; /* need to trap before returning to user mode */
#define aston() (astpending++)
/*
* Preempt the current process if in interrupt from user mode,
* or after the current trap/syscall if in system mode.
*/
extern int want_resched; /* resched() was called */
#define need_resched() { want_resched++; aston(); }
/*
* Give a profiling tick to the current process when the user profiling
* buffer pages are invalid. On the sun3, request an ast to send us
* through trap, marking the proc as needing a profiling tick.
*/
#define need_proftick(p) ((p)->p_flag |= P_OWEUPC, aston())
/*
* Notify the current process (p) that it has a signal pending,
* process as soon as possible.
*/
#define signotify(p) aston()
/*
* Software Interrupt Register (SIR)
* The sun3 has a real software interrupt register set by
* isr_soft_request() so this scheme just multiplexes four
* software interrupt `sources' on the level one handler.
*/
union sun3sir {
int sir_any;
char sir_which[4];
} sun3sir;
#define SIR_NET 0
#define SIR_CLOCK 1
#define SIR_SPARE2 2
#define SIR_SPARE3 3
#define setsoftint() isr_soft_request(1)
#define setsoftnet() (sun3sir.sir_which[SIR_NET] = 1, setsoftint())
#define setsoftclock() (sun3sir.sir_which[SIR_CLOCK] = 1, setsoftint())
/*
* CTL_MACHDEP definitions.
*/
#define CPU_CONSDEV 1 /* dev_t: console terminal device */
#define CPU_MAXID 2 /* number of valid machdep ids */
#define CTL_MACHDEP_NAMES { \
{ 0, 0 }, \
{ "console_device", CTLTYPE_STRUCT }, \
}
/* values for cpu_machine_id */
#define CPU_ARCH_MASK 0xf0
#define SUN3_ARCH 0x10
#define SUN3_IMPL_MASK 0x0f
#define SUN3_MACH_160 0x01
#define SUN3_MACH_50 0x02
#define SUN3_MACH_260 0x03
#define SUN3_MACH_110 0x04
#define SUN3_MACH_60 0x07
#define SUN3_MACH_E 0x08
extern unsigned char cpu_machine_id;
/* 680X0 function codes */
#define FC_USERD 1 /* user data space */
#define FC_USERP 2 /* user program space */
#define FC_CONTROL 3 /* sun control space */
#define FC_SUPERD 5 /* supervisor data space */
#define FC_SUPERP 6 /* supervisor program space */
#define FC_CPU 7 /* CPU space */
/* fields in the 68020 cache control register */
#define IC_ENABLE 0x0001 /* enable instruction cache */
#define IC_FREEZE 0x0002 /* freeze instruction cache */
#define IC_CE 0x0004 /* clear instruction cache entry */
#define IC_CLR 0x0008 /* clear entire instruction cache */
#define IC_CLEAR (IC_CLR|IC_ENABLE)
#endif /* _KERNEL */
/*
* CTL_MACHDEP definitions.
*/
#define CPU_CONSDEV 1 /* dev_t: console terminal device */
#define CPU_MAXID 2 /* number of valid machdep ids */
#define CTL_MACHDEP_NAMES { \
{ 0, 0 }, \
{ "console_device", CTLTYPE_STRUCT }, \
}
#endif /* !_SUN3_CPU_H_ */
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