blob: 16f7b82c15287918c60b9082561480740f59dd3d (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
|
/* $OpenBSD: atareg.h,v 1.4 2001/06/25 19:31:47 csapuntz Exp $ */
/* $NetBSD: atareg.h,v 1.5 1999/01/18 20:06:24 bouyer Exp $ */
#ifndef __DEV_ATA_ATAREG_H__
#define __DEV_ATA_ATAREG_H__
/*
* Drive parameter structure for ATA/ATAPI.
* Bit fields: WDC_* : common to ATA/ATAPI
* ATA_* : ATA only
* ATAPI_* : ATAPI only.
*/
struct ataparams {
/* drive info */
u_int16_t atap_config; /* 0: general configuration */
#define WDC_CFG_ATAPI_MASK 0xc000
#define WDC_CFG_ATAPI 0x8000
#define ATA_CFG_REMOVABLE 0x0080
#define ATA_CFG_FIXED 0x0040
#define ATAPI_CFG_TYPE_MASK 0x1f00
#define ATAPI_CFG_TYPE(x) (((x) & ATAPI_CFG_TYPE_MASK) >> 8)
#define ATAPI_CFG_TYPE_DIRECT 0x00
#define ATAPI_CFG_TYPE_SEQUENTIAL 0x01
#define ATAPI_CFG_TYPE_CDROM 0x05
#define ATAPI_CFG_TYPE_OPTICAL 0x07
#define ATAPI_CFG_TYPE_NODEVICE 0x1F
#define ATAPI_CFG_REMOV 0x0080
#define ATAPI_CFG_DRQ_MASK 0x0060
#define ATAPI_CFG_STD_DRQ 0x0000
#define ATAPI_CFG_IRQ_DRQ 0x0020
#define ATAPI_CFG_ACCEL_DRQ 0x0040
#define ATAPI_CFG_CMD_MASK 0x0003
#define ATAPI_CFG_CMD_12 0x0000
#define ATAPI_CFG_CMD_16 0x0001
/* words 1-9 are ATA only */
u_int16_t atap_cylinders; /* 1: # of non-removable cylinders */
u_int16_t __reserved1;
u_int16_t atap_heads; /* 3: # of heads */
u_int16_t __retired1[2]; /* 4-5: # of unform. bytes/track */
u_int16_t atap_sectors; /* 6: # of sectors */
u_int16_t __retired2[3];
u_int8_t atap_serial[20]; /* 10-19: serial number */
u_int16_t __retired3[2];
u_int16_t __obsolete1;
u_int8_t atap_revision[8]; /* 23-26: firmware revision */
u_int8_t atap_model[40]; /* 27-46: model number */
u_int16_t atap_multi; /* 47: maximum sectors per irq (ATA) */
u_int16_t __reserved2;
u_int16_t atap_capabilities1; /* 49: capability flags */
#define WDC_CAP_IORDY 0x0800
#define WDC_CAP_IORDY_DSBL 0x0400
#define WDC_CAP_LBA 0x0200
#define WDC_CAP_DMA 0x0100
#define ATA_CAP_STBY 0x2000
#define ATAPI_CAP_INTERL_DMA 0x8000
#define ATAPI_CAP_CMD_QUEUE 0x4000
#define ATAPI_CAP_OVERLP 0x2000
#define ATAPI_CAP_ATA_RST 0x1000
u_int16_t atap_capabilities2; /* 50: capability flags (ATA) */
#if BYTE_ORDER == LITTLE_ENDIAN
u_int8_t __junk2;
u_int8_t atap_oldpiotiming; /* 51: old PIO timing mode */
u_int8_t __junk3;
u_int8_t atap_olddmatiming; /* 52: old DMA timing mode (ATA) */
#else
u_int8_t atap_oldpiotiming; /* 51: old PIO timing mode */
u_int8_t __junk2;
u_int8_t atap_olddmatiming; /* 52: old DMA timing mode (ATA) */
u_int8_t __junk3;
#endif
u_int16_t atap_extensions; /* 53: extentions supported */
#define WDC_EXT_UDMA_MODES 0x0004
#define WDC_EXT_MODES 0x0002
#define WDC_EXT_GEOM 0x0001
/* words 54-62 are ATA only */
u_int16_t atap_curcylinders; /* 54: current logical cyliners */
u_int16_t atap_curheads; /* 55: current logical heads */
u_int16_t atap_cursectors; /* 56: current logical sectors/tracks */
u_int16_t atap_curcapacity[2]; /* 57-58: current capacity */
u_int16_t atap_curmulti; /* 59: current multi-sector setting */
#define WDC_MULTI_VALID 0x0100
#define WDC_MULTI_MASK 0x00ff
u_int16_t atap_capacity[2]; /* 60-61: total capacity (LBA only) */
u_int16_t __retired4;
#if BYTE_ORDER == LITTLE_ENDIAN
u_int8_t atap_dmamode_supp; /* 63: multiword DMA mode supported */
u_int8_t atap_dmamode_act; /* multiword DMA mode active */
u_int8_t atap_piomode_supp; /* 64: PIO mode supported */
u_int8_t __junk4;
#else
u_int8_t atap_dmamode_act; /* multiword DMA mode active */
u_int8_t atap_dmamode_supp; /* 63: multiword DMA mode supported */
u_int8_t __junk4;
u_int8_t atap_piomode_supp; /* 64: PIO mode supported */
#endif
u_int16_t atap_dmatiming_mimi; /* 65: minimum DMA cycle time */
u_int16_t atap_dmatiming_recom; /* 66: recomended DMA cycle time */
u_int16_t atap_piotiming; /* 67: mini PIO cycle time without FC */
u_int16_t atap_piotiming_iordy; /* 68: mini PIO cycle time with IORDY FC */
u_int16_t __reserved3[2];
/* words 71-72 are ATAPI only */
u_int16_t atap_pkt_br; /* 71: time (ns) to bus release */
u_int16_t atap_pkt_bsyclr; /* 72: tme to clear BSY after service */
u_int16_t __reserved4[2];
u_int16_t atap_queuedepth; /* 75: */
#define WDC_QUEUE_DEPTH_MASK 0x0F
u_int16_t __reserved5[4];
u_int16_t atap_ata_major; /* 80: Major version number */
#define WDC_VER_ATA1 0x0002
#define WDC_VER_ATA2 0x0004
#define WDC_VER_ATA3 0x0008
#define WDC_VER_ATA4 0x0010
#define WDC_VER_ATA5 0x0020
#define WDC_VER_ATA6 0x0040
#define WDC_VER_ATA7 0x0080
#define WDC_VER_ATA8 0x0100
#define WDC_VER_ATA9 0x0200
#define WDC_VER_ATA10 0x0400
#define WDC_VER_ATA11 0x0800
#define WDC_VER_ATA12 0x1000
#define WDC_VER_ATA13 0x2000
#define WDC_VER_ATA14 0x4000
u_int16_t atap_ata_minor; /* 81: Minor version number */
u_int16_t atap_cmd_set1; /* 82: command set suported */
#define WDC_CMD1_NOP 0x4000
#define WDC_CMD1_RB 0x2000
#define WDC_CMD1_WB 0x1000
#define WDC_CMD1_HPA 0x0400
#define WDC_CMD1_DVRST 0x0200
#define WDC_CMD1_SRV 0x0100
#define WDC_CMD1_RLSE 0x0080
#define WDC_CMD1_AHEAD 0x0040
#define WDC_CMD1_CACHE 0x0020
#define WDC_CMD1_PKT 0x0010
#define WDC_CMD1_PM 0x0008
#define WDC_CMD1_REMOV 0x0004
#define WDC_CMD1_SEC 0x0002
#define WDC_CMD1_SMART 0x0001
u_int16_t atap_cmd_set2; /* 83: command set suported */
#define ATAPI_CMD2_FCE 0x2000 /* Flush Cache Ext supported */
#define ATAPI_CMD2_FC 0x1000 /* Flush Cache supported */
#define ATAPI_CMD2_DCO 0x0800 /* Device Configuration Overlay supported */
#define ATAPI_CMD2_48AD 0x0400 /* 48bit address supported */
#define ATAPI_CMD2_AAM 0x0200 /* Automatic Acoustic Management supported */
#define ATAPI_CMD2_SM 0x0100 /* Set Max security extension supported */
#define ATAPI_CMD2_SF 0x0040 /* Set Features subcommand required */
#define ATAPI_CMD2_PUIS 0x0020 /* Power up in standby supported */
#define WDC_CMD2_RMSN 0x0010
#define ATA_CMD2_APM 0x0008
#define ATA_CMD2_CFA 0x0004
#define ATA_CMD2_RWQ 0x0002
#define WDC_CMD2_DM 0x0001 /* Download Microcode supported */
u_int16_t atap_cmd_ext; /* 84: command/features supp. ext. */
#define ATAPI_CMDE_MSER 0x0004 /* Media serial number supported */
#define ATAPI_CMDE_TEST 0x0002 /* SMART self-test supported */
#define ATAPI_CMDE_SLOG 0x0001 /* SMART error logging supported */
u_int16_t atap_cmd1_en; /* 85: cmd/features enabled */
/* bits are the same as atap_cmd_set1 */
u_int16_t atap_cmd2_en; /* 86: cmd/features enabled */
/* bits are the same as atap_cmd_set2 */
u_int16_t atap_cmd_def; /* 87: cmd/features default */
/* bits are NOT the same as atap_cmd_ext */
#if BYTE_ORDER == LITTLE_ENDIAN
u_int8_t atap_udmamode_supp; /* 88: Ultra-DMA mode supported */
u_int8_t atap_udmamode_act; /* Ultra-DMA mode active */
#else
u_int8_t atap_udmamode_act; /* Ultra-DMA mode active */
u_int8_t atap_udmamode_supp; /* 88: Ultra-DMA mode supported */
#endif
/* 89-92 are ATA-only */
u_int16_t atap_seu_time; /* 89: Sec. Erase Unit compl. time */
u_int16_t atap_eseu_time; /* 90: Enhanced SEU compl. time */
u_int16_t atap_apm_val; /* 91: current APM value */
u_int16_t atap_mpasswd_rev; /* 92: Master Password revision */
u_int16_t atap_hwreset_res; /* 93: Hardware reset value */
#define ATA_HWRES_CBLID 0x2000 /* CBLID above Vih */
#define ATA_HWRES_D1_PDIAG 0x0800 /* Device 1 PDIAG detect OK */
#define ATA_HWRES_D1_CSEL 0x0400 /* Device 1 used CSEL for address */
#define ATA_HWRES_D1_JUMP 0x0200 /* Device 1 jumpered to address */
#define ATA_HWRES_D0_SEL 0x0040 /* Device 0 responds when Dev 1 selected */
#define ATA_HWRES_D0_DASP 0x0020 /* Device 0 DASP detect OK */
#define ATA_HWRES_D0_PDIAG 0x0010 /* Device 0 PDIAG detect OK */
#define ATA_HWRES_D0_DIAG 0x0008 /* Device 0 diag OK */
#define ATA_HWRES_D0_CSEL 0x0004 /* Device 0 used CSEL for address */
#define ATA_HWRES_D0_JUMP 0x0002 /* Device 0 jumpered to address */
#if BYTE_ORDER == LITTLE_ENDIAN
u_int8_t atap_acoustic_val; /* 94: Current acoustic level */
u_int8_t atap_acoustic_def; /* recommended level */
#else
u_int8_t atap_acoustic_def; /* recommended level */
u_int8_t atap_acoustic_val; /* 94: Current acoustic level */
#endif
u_int16_t __reserved6[5]; /* 95-99: reserved */
u_int16_t atap_max_lba[4]; /* 100-103: Max. user LBA add */
u_int16_t __reserved7[23]; /* 104-126: reserved */
u_int16_t atap_rmsn_supp; /* 127: remov. media status notif. */
#define WDC_RMSN_SUPP_MASK 0x0003
#define WDC_RMSN_SUPP 0x0001
u_int16_t atap_sec_st; /* 128: security status */
#define WDC_SEC_LEV_MAX 0x0100
#define WDC_SEC_ESE_SUPP 0x0020
#define WDC_SEC_EXP 0x0010
#define WDC_SEC_FROZEN 0x0008
#define WDC_SEC_LOCKED 0x0004
#define WDC_SEC_EN 0x0002
#define WDC_SEC_SUPP 0x0001
u_int16_t __reserved8[31]; /* 129-159: vendor specific */
u_int16_t atap_cfa_power; /* 160: CFA powermode */
#define ATAPI_CFA_MAX_MASK 0x0FFF
#define ATAPI_CFA_MODE1_DIS 0x1000 /* CFA Mode 1 Disabled */
#define ATAPI_CFA_MODE1_REQ 0x2000 /* CFA Mode 1 Required */
#define ATAPI_CFA_WORD160 0x8000 /* Word 160 supported */
u_int16_t __reserved9[31]; /* 161-175: reserved for CFA */
u_int8_t atap_media_serial[60]; /* 176-205: media serial number */
u_int16_t __reserved10[49]; /* 206-254: reserved */
#if BYTE_ORDER == LITTLE_ENDIAN
u_int8_t atap_signature; /* 255: Signature */
u_int8_t atap_checksum; /* Checksum */
#else
u_int8_t atap_checksum; /* Checksum */
u_int8_t atap_signature; /* 255: Signature */
#endif
};
#endif
|
