Import Mesa 21.1.5

1 files changed, 4 insertions, 9 deletions

diff --git a/lib/mesa/src/intel/common/intel_clflush.h b/lib/mesa/src/intel/common/intel_clflush.h
index a4f33cbe1..f3102e952 100644
--- a/lib/mesa/src/intel/common/intel_clflush.h
+++ b/lib/mesa/src/intel/common/intel_clflush.h
@@ -27,9 +27,8 @@
 #define CACHELINE_SIZE 64
 #define CACHELINE_MASK 63
 
-#ifdef SUPPORT_INTEL_INTEGRATED_GPUS
 static inline void
-intel_clflush_range(void *start, size_t size)
+gen_clflush_range(void *start, size_t size)
 {
    void *p = (void *) (((uintptr_t) start) & ~CACHELINE_MASK);
    void *end = start + size;
@@ -44,16 +43,13 @@ static inline void
 intel_flush_range(void *start, size_t size)
 {
    __builtin_ia32_mfence();
-   intel_clflush_range(start, size);
+   gen_clflush_range(start, size);
 }
 
 static inline void
-intel_invalidate_range(void *start, size_t size)
+gen_invalidate_range(void *start, size_t size)
 {
-   if (size == 0)
-      return;
-
-   intel_clflush_range(start, size);
+   gen_clflush_range(start, size);
 
    /* Modern Atom CPUs (Baytrail+) have issues with clflush serialization,
     * where mfence is not a sufficient synchronization barrier.  We must
@@ -68,6 +64,5 @@ intel_invalidate_range(void *start, size_t size)
    __builtin_ia32_clflush(start + size - 1);
    __builtin_ia32_mfence();
 }
-#endif /* SUPPORT_INTEL_INTEGRATED_GPUS */
 
 #endif