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authorMatthieu Herrb <matthieu@cvs.openbsd.org>2012-06-07 20:55:35 +0000
committerMatthieu Herrb <matthieu@cvs.openbsd.org>2012-06-07 20:55:35 +0000
commit8c76ea5c7237ec06667e55640e75748417b2ff22 (patch)
treeb884bc24fb703f4cc75635783ffb227eec3d887f /driver/xf86-video-ati/src
parent3651d096b7e018eae54972ed76b9a0e6912c3d0f (diff)
Update to xf86-video-ati 6.14.4. Tested by jasper@, krw@, mpi@, shadchin@
Diffstat (limited to 'driver/xf86-video-ati/src')
-rw-r--r--driver/xf86-video-ati/src/ati_pciids_gen.h26
-rw-r--r--driver/xf86-video-ati/src/drmmode_display.c161
-rw-r--r--driver/xf86-video-ati/src/drmmode_display.h1
-rw-r--r--driver/xf86-video-ati/src/evergreen_accel.c190
-rw-r--r--driver/xf86-video-ati/src/evergreen_exa.c45
-rw-r--r--driver/xf86-video-ati/src/evergreen_state.h7
-rw-r--r--driver/xf86-video-ati/src/evergreen_textured_videofuncs.c7
-rw-r--r--driver/xf86-video-ati/src/pcidb/ati_pciids.csv26
-rw-r--r--driver/xf86-video-ati/src/r600_exa.c86
-rw-r--r--driver/xf86-video-ati/src/r600_state.h6
-rw-r--r--driver/xf86-video-ati/src/r600_textured_videofuncs.c20
-rw-r--r--driver/xf86-video-ati/src/r6xx_accel.c75
-rw-r--r--driver/xf86-video-ati/src/radeon.h21
-rw-r--r--driver/xf86-video-ati/src/radeon_chipinfo_gen.h26
-rw-r--r--driver/xf86-video-ati/src/radeon_chipset_gen.h26
-rw-r--r--driver/xf86-video-ati/src/radeon_commonfuncs.c17
-rw-r--r--driver/xf86-video-ati/src/radeon_crtc.c27
-rw-r--r--driver/xf86-video-ati/src/radeon_dri2.c162
-rw-r--r--driver/xf86-video-ati/src/radeon_driver.c73
-rw-r--r--driver/xf86-video-ati/src/radeon_drm.h23
-rw-r--r--driver/xf86-video-ati/src/radeon_exa.c87
-rw-r--r--driver/xf86-video-ati/src/radeon_kms.c84
-rw-r--r--driver/xf86-video-ati/src/radeon_output.c4
-rw-r--r--driver/xf86-video-ati/src/radeon_pci_chipset_gen.h26
-rw-r--r--driver/xf86-video-ati/src/radeon_pci_device_match_gen.h26
-rw-r--r--driver/xf86-video-ati/src/radeon_probe.h7
-rw-r--r--driver/xf86-video-ati/src/radeon_textured_video.c17
-rw-r--r--driver/xf86-video-ati/src/radeon_textured_videofuncs.c68
-rw-r--r--driver/xf86-video-ati/src/radeon_video.c6
29 files changed, 1052 insertions, 298 deletions
diff --git a/driver/xf86-video-ati/src/ati_pciids_gen.h b/driver/xf86-video-ati/src/ati_pciids_gen.h
index ff7c91b7b..77e41ac80 100644
--- a/driver/xf86-video-ati/src/ati_pciids_gen.h
+++ b/driver/xf86-video-ati/src/ati_pciids_gen.h
@@ -85,6 +85,7 @@
#define PCI_CHIP_RV250_Ld 0x4C64
#define PCI_CHIP_RV250_Lf 0x4C66
#define PCI_CHIP_RV250_Lg 0x4C67
+#define PCI_CHIP_RV280_4C6E 0x4C6E
#define PCI_CHIP_RAGE128MF 0x4D46
#define PCI_CHIP_RAGE128ML 0x4D4C
#define PCI_CHIP_R300_ND 0x4E44
@@ -460,6 +461,8 @@
#define PCI_CHIP_SUMO_9647 0x9647
#define PCI_CHIP_SUMO_9648 0x9648
#define PCI_CHIP_SUMO_964A 0x964A
+#define PCI_CHIP_SUMO_964B 0x964B
+#define PCI_CHIP_SUMO_964C 0x964C
#define PCI_CHIP_SUMO_964E 0x964E
#define PCI_CHIP_SUMO_964F 0x964F
#define PCI_CHIP_RS880_9710 0x9710
@@ -474,6 +477,8 @@
#define PCI_CHIP_PALM_9805 0x9805
#define PCI_CHIP_PALM_9806 0x9806
#define PCI_CHIP_PALM_9807 0x9807
+#define PCI_CHIP_PALM_9808 0x9808
+#define PCI_CHIP_PALM_9809 0x9809
#define PCI_CHIP_CYPRESS_6880 0x6880
#define PCI_CHIP_CYPRESS_6888 0x6888
#define PCI_CHIP_CYPRESS_6889 0x6889
@@ -515,6 +520,7 @@
#define PCI_CHIP_CEDAR_68F2 0x68F2
#define PCI_CHIP_CEDAR_68F8 0x68F8
#define PCI_CHIP_CEDAR_68F9 0x68F9
+#define PCI_CHIP_CEDAR_68FA 0x68FA
#define PCI_CHIP_CEDAR_68FE 0x68FE
#define PCI_CHIP_CAYMAN_6700 0x6700
#define PCI_CHIP_CAYMAN_6701 0x6701
@@ -555,9 +561,20 @@
#define PCI_CHIP_TURKS_6748 0x6748
#define PCI_CHIP_TURKS_6749 0x6749
#define PCI_CHIP_TURKS_6750 0x6750
+#define PCI_CHIP_TURKS_6751 0x6751
#define PCI_CHIP_TURKS_6758 0x6758
#define PCI_CHIP_TURKS_6759 0x6759
+#define PCI_CHIP_TURKS_675B 0x675B
+#define PCI_CHIP_TURKS_675D 0x675D
#define PCI_CHIP_TURKS_675F 0x675F
+#define PCI_CHIP_TURKS_6840 0x6840
+#define PCI_CHIP_TURKS_6841 0x6841
+#define PCI_CHIP_TURKS_6842 0x6842
+#define PCI_CHIP_TURKS_6843 0x6843
+#define PCI_CHIP_TURKS_6849 0x6849
+#define PCI_CHIP_TURKS_6850 0x6850
+#define PCI_CHIP_TURKS_6858 0x6858
+#define PCI_CHIP_TURKS_6859 0x6859
#define PCI_CHIP_CAICOS_6760 0x6760
#define PCI_CHIP_CAICOS_6761 0x6761
#define PCI_CHIP_CAICOS_6762 0x6762
@@ -568,5 +585,14 @@
#define PCI_CHIP_CAICOS_6767 0x6767
#define PCI_CHIP_CAICOS_6768 0x6768
#define PCI_CHIP_CAICOS_6770 0x6770
+#define PCI_CHIP_CAICOS_6772 0x6772
#define PCI_CHIP_CAICOS_6778 0x6778
#define PCI_CHIP_CAICOS_6779 0x6779
+#define PCI_CHIP_CAICOS_677B 0x677B
+#define PCI_CHIP_ARUBA_9900 0x9900
+#define PCI_CHIP_ARUBA_9901 0x9901
+#define PCI_CHIP_ARUBA_9903 0x9903
+#define PCI_CHIP_ARUBA_9904 0x9904
+#define PCI_CHIP_ARUBA_990f 0x990f
+#define PCI_CHIP_ARUBA_9990 0x9990
+#define PCI_CHIP_ARUBA_9991 0x9991
diff --git a/driver/xf86-video-ati/src/drmmode_display.c b/driver/xf86-video-ati/src/drmmode_display.c
index 05f764374..f11fc8c80 100644
--- a/driver/xf86-video-ati/src/drmmode_display.c
+++ b/driver/xf86-video-ati/src/drmmode_display.c
@@ -49,12 +49,16 @@
#include <X11/extensions/dpms.h>
#endif
-static PixmapPtr drmmode_create_bo_pixmap(ScreenPtr pScreen,
+static PixmapPtr drmmode_create_bo_pixmap(ScrnInfoPtr pScrn,
int width, int height,
int depth, int bpp,
- int pitch, struct radeon_bo *bo)
+ int pitch, int tiling,
+ struct radeon_bo *bo)
{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ ScreenPtr pScreen = pScrn->pScreen;
PixmapPtr pixmap;
+ struct radeon_surface *surface;
pixmap = (*pScreen->CreatePixmap)(pScreen, 0, 0, depth, 0);
if (!pixmap)
@@ -67,6 +71,39 @@ static PixmapPtr drmmode_create_bo_pixmap(ScreenPtr pScreen,
exaMoveInPixmap(pixmap);
radeon_set_pixmap_bo(pixmap, bo);
+ if (info->ChipFamily >= CHIP_FAMILY_R600) {
+ surface = radeon_get_pixmap_surface(pixmap);
+ if (surface) {
+ memset(surface, 0, sizeof(struct radeon_surface));
+ surface->npix_x = width;
+ surface->npix_y = height;
+ surface->npix_z = 1;
+ surface->blk_w = 1;
+ surface->blk_h = 1;
+ surface->blk_d = 1;
+ surface->array_size = 1;
+ surface->last_level = 0;
+ surface->bpe = bpp / 8;
+ surface->nsamples = 1;
+ surface->flags = RADEON_SURF_SCANOUT;
+ surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
+ surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
+ if (tiling & RADEON_TILING_MICRO) {
+ surface->flags = RADEON_SURF_CLR(surface->flags, MODE);
+ surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
+ }
+ if (tiling & RADEON_TILING_MACRO) {
+ surface->flags = RADEON_SURF_CLR(surface->flags, MODE);
+ surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
+ }
+ if (radeon_surface_best(info->surf_man, surface)) {
+ return NULL;
+ }
+ if (radeon_surface_init(info->surf_man, surface)) {
+ return NULL;
+ }
+ }
+ }
return pixmap;
}
@@ -159,7 +196,6 @@ create_pixmap_for_fbcon(drmmode_ptr drmmode,
{
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
drmmode_crtc_private_ptr drmmode_crtc;
- ScreenPtr pScreen = pScrn->pScreen;
PixmapPtr pixmap;
struct radeon_bo *bo;
drmModeFBPtr fbcon;
@@ -185,9 +221,9 @@ create_pixmap_for_fbcon(drmmode_ptr drmmode,
return NULL;
}
- pixmap = drmmode_create_bo_pixmap(pScreen, fbcon->width, fbcon->height,
+ pixmap = drmmode_create_bo_pixmap(pScrn, fbcon->width, fbcon->height,
fbcon->depth, fbcon->bpp,
- fbcon->pitch, bo);
+ fbcon->pitch, 0, bo);
if (!pixmap)
return NULL;
@@ -225,9 +261,13 @@ void drmmode_copy_fb(ScrnInfoPtr pScrn, drmmode_ptr drmmode)
return;
if (info->allowColorTiling) {
- if (info->ChipFamily >= CHIP_FAMILY_R600)
- tiling_flags |= RADEON_TILING_MICRO;
- else
+ if (info->ChipFamily >= CHIP_FAMILY_R600) {
+ if (info->allowColorTiling2D) {
+ tiling_flags |= RADEON_TILING_MACRO;
+ } else {
+ tiling_flags |= RADEON_TILING_MICRO;
+ }
+ } else
tiling_flags |= RADEON_TILING_MACRO;
}
@@ -235,10 +275,10 @@ void drmmode_copy_fb(ScrnInfoPtr pScrn, drmmode_ptr drmmode)
drmmode_get_pitch_align(pScrn, info->CurrentLayout.pixel_bytes, tiling_flags)) *
info->CurrentLayout.pixel_bytes;
- dst = drmmode_create_bo_pixmap(pScreen, pScrn->virtualX,
+ dst = drmmode_create_bo_pixmap(pScrn, pScrn->virtualX,
pScrn->virtualY, pScrn->depth,
pScrn->bitsPerPixel, pitch,
- info->front_bo);
+ tiling_flags, info->front_bo);
if (!dst)
goto out_free_src;
@@ -251,6 +291,9 @@ void drmmode_copy_fb(ScrnInfoPtr pScrn, drmmode_ptr drmmode)
info->accel_state->exa->DoneCopy (dst);
radeon_cs_flush_indirect(pScrn);
+#if GET_ABI_MAJOR(ABI_VIDEODRV_VERSION) >= 10
+ pScreen->canDoBGNoneRoot = TRUE;
+#endif
drmmode_destroy_bo_pixmap(dst);
out_free_src:
drmmode_destroy_bo_pixmap(src);
@@ -289,6 +332,9 @@ drmmode_set_mode_major(xf86CrtcPtr crtc, DisplayModePtr mode,
pitch = RADEON_ALIGN(pScrn->displayWidth, drmmode_get_pitch_align(pScrn, info->CurrentLayout.pixel_bytes, tiling_flags)) *
info->CurrentLayout.pixel_bytes;
height = RADEON_ALIGN(pScrn->virtualY, drmmode_get_height_align(pScrn, tiling_flags));
+ if (info->ChipFamily >= CHIP_FAMILY_R600) {
+ pitch = info->front_surface.level[0].pitch_bytes;
+ }
if (drmmode->fb_id == 0) {
ret = drmModeAddFB(drmmode->fd,
@@ -500,12 +546,12 @@ drmmode_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height)
rotate_pitch = RADEON_ALIGN(width, drmmode_get_pitch_align(pScrn, drmmode->cpp, 0)) * drmmode->cpp;
- rotate_pixmap = drmmode_create_bo_pixmap(pScrn->pScreen,
+ rotate_pixmap = drmmode_create_bo_pixmap(pScrn,
width, height,
pScrn->depth,
pScrn->bitsPerPixel,
rotate_pitch,
- drmmode_crtc->rotate_bo);
+ 0, drmmode_crtc->rotate_bo);
if (rotate_pixmap == NULL) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Couldn't allocate shadow pixmap for rotated CRTC\n");
@@ -1011,7 +1057,7 @@ drmmode_output_init(ScrnInfoPtr pScrn, drmmode_ptr drmmode, int num, int *num_dv
output->doubleScanAllowed = TRUE;
output->driver_private = drmmode_output;
- output->possible_crtcs = 0x7f;
+ output->possible_crtcs = 0xffffffff;
for (i = 0; i < koutput->count_encoders; i++) {
output->possible_crtcs &= kencoders[i]->possible_crtcs;
}
@@ -1203,7 +1249,9 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height)
int screen_size;
int cpp = info->CurrentLayout.pixel_bytes;
struct radeon_bo *front_bo;
- uint32_t tiling_flags = 0;
+ struct radeon_surface surface;
+ struct radeon_surface *psurface;
+ uint32_t tiling_flags = 0, base_align;
PixmapPtr ppix = screen->GetScreenPixmap(screen);
void *fb_shadow;
@@ -1217,15 +1265,69 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height)
radeon_bo_wait(front_bo);
if (info->allowColorTiling) {
- if (info->ChipFamily >= CHIP_FAMILY_R600)
- tiling_flags |= RADEON_TILING_MICRO;
- else
+ if (info->ChipFamily >= CHIP_FAMILY_R600) {
+ if (info->allowColorTiling2D) {
+ tiling_flags |= RADEON_TILING_MACRO;
+ } else {
+ tiling_flags |= RADEON_TILING_MICRO;
+ }
+ } else
tiling_flags |= RADEON_TILING_MACRO;
}
pitch = RADEON_ALIGN(width, drmmode_get_pitch_align(scrn, cpp, tiling_flags)) * cpp;
height = RADEON_ALIGN(height, drmmode_get_height_align(scrn, tiling_flags));
screen_size = RADEON_ALIGN(pitch * height, RADEON_GPU_PAGE_SIZE);
+ base_align = 4096;
+ if (info->ChipFamily >= CHIP_FAMILY_R600) {
+ memset(&surface, 0, sizeof(struct radeon_surface));
+ surface.npix_x = width;
+ surface.npix_y = height;
+ surface.npix_z = 1;
+ surface.blk_w = 1;
+ surface.blk_h = 1;
+ surface.blk_d = 1;
+ surface.array_size = 1;
+ surface.last_level = 0;
+ surface.bpe = cpp;
+ surface.nsamples = 1;
+ surface.flags = RADEON_SURF_SCANOUT;
+ surface.flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
+ surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
+ if (tiling_flags & RADEON_TILING_MICRO) {
+ surface.flags = RADEON_SURF_CLR(surface.flags, MODE);
+ surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
+ }
+ if (tiling_flags & RADEON_TILING_MACRO) {
+ surface.flags = RADEON_SURF_CLR(surface.flags, MODE);
+ surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
+ }
+ if (radeon_surface_best(info->surf_man, &surface)) {
+ return FALSE;
+ }
+ if (radeon_surface_init(info->surf_man, &surface)) {
+ return FALSE;
+ }
+ screen_size = surface.bo_size;
+ base_align = surface.bo_alignment;
+ pitch = surface.level[0].pitch_bytes;
+ tiling_flags = 0;
+ switch (surface.level[0].mode) {
+ case RADEON_SURF_MODE_2D:
+ tiling_flags |= RADEON_TILING_MACRO;
+ tiling_flags |= surface.bankw << RADEON_TILING_EG_BANKW_SHIFT;
+ tiling_flags |= surface.bankh << RADEON_TILING_EG_BANKH_SHIFT;
+ tiling_flags |= surface.mtilea << RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT;
+ tiling_flags |= eg_tile_split(surface.tile_split) << RADEON_TILING_EG_TILE_SPLIT_SHIFT;
+ break;
+ case RADEON_SURF_MODE_1D:
+ tiling_flags |= RADEON_TILING_MICRO;
+ break;
+ default:
+ break;
+ }
+ info->front_surface = surface;
+ }
xf86DrvMsg(scrn->scrnIndex, X_INFO,
"Allocate new frame buffer %dx%d stride %d\n",
@@ -1241,7 +1343,7 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height)
scrn->virtualY = height;
scrn->displayWidth = pitch / cpp;
- info->front_bo = radeon_bo_open(info->bufmgr, 0, screen_size, 0, RADEON_GEM_DOMAIN_VRAM, 0);
+ info->front_bo = radeon_bo_open(info->bufmgr, 0, screen_size, base_align, RADEON_GEM_DOMAIN_VRAM, 0);
if (!info->front_bo)
goto fail;
@@ -1267,6 +1369,8 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height)
if (!info->r600_shadow_fb) {
radeon_set_pixmap_bo(ppix, info->front_bo);
+ psurface = radeon_get_pixmap_surface(ppix);
+ *psurface = info->front_surface;
screen->ModifyPixmapHeader(ppix,
width, height, -1, -1, pitch, NULL);
} else {
@@ -1376,9 +1480,7 @@ drm_wakeup_handler(pointer data, int err, pointer p)
Bool drmmode_pre_init(ScrnInfoPtr pScrn, drmmode_ptr drmmode, int cpp)
{
- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
xf86CrtcConfigPtr xf86_config;
- RADEONInfoPtr info = RADEONPTR(pScrn);
int i, num_dvi = 0, num_hdmi = 0;
xf86CrtcConfigInit(pScrn, &drmmode_xf86crtc_config_funcs);
@@ -1408,14 +1510,22 @@ Bool drmmode_pre_init(ScrnInfoPtr pScrn, drmmode_ptr drmmode, int cpp)
#ifdef __linux__
drmmode->event_context.page_flip_handler = drmmode_flip_handler;
#endif
- if (!pRADEONEnt->fd_wakeup_registered && info->dri->pKernelDRMVersion->version_minor >= 4) {
+
+ return TRUE;
+}
+
+void drmmode_init(ScrnInfoPtr pScrn, drmmode_ptr drmmode)
+{
+ RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+
+ if (pRADEONEnt->fd_wakeup_registered != serverGeneration &&
+ info->dri->pKernelDRMVersion->version_minor >= 4) {
AddGeneralSocket(drmmode->fd);
RegisterBlockAndWakeupHandlers((BlockHandlerProcPtr)NoopDDA,
drm_wakeup_handler, drmmode);
- pRADEONEnt->fd_wakeup_registered = TRUE;
+ pRADEONEnt->fd_wakeup_registered = serverGeneration;
}
-
- return TRUE;
}
Bool drmmode_set_bufmgr(ScrnInfoPtr pScrn, drmmode_ptr drmmode, struct radeon_bo_manager *bufmgr)
@@ -1672,6 +1782,9 @@ Bool radeon_do_pageflip(ScrnInfoPtr scrn, struct radeon_bo *new_front, void *dat
pitch = RADEON_ALIGN(scrn->displayWidth, drmmode_get_pitch_align(scrn, info->CurrentLayout.pixel_bytes, tiling_flags)) *
info->CurrentLayout.pixel_bytes;
height = RADEON_ALIGN(scrn->virtualY, drmmode_get_height_align(scrn, tiling_flags));
+ if (info->ChipFamily >= CHIP_FAMILY_R600 && info->surf_man) {
+ pitch = info->front_surface.level[0].pitch_bytes;
+ }
/*
* Create a new handle for the back buffer
diff --git a/driver/xf86-video-ati/src/drmmode_display.h b/driver/xf86-video-ati/src/drmmode_display.h
index eb271f5f5..dff03929e 100644
--- a/driver/xf86-video-ati/src/drmmode_display.h
+++ b/driver/xf86-video-ati/src/drmmode_display.h
@@ -99,6 +99,7 @@ typedef struct {
extern Bool drmmode_pre_init(ScrnInfoPtr pScrn, drmmode_ptr drmmode, int cpp);
+extern void drmmode_init(ScrnInfoPtr pScrn, drmmode_ptr drmmode);
extern Bool drmmode_set_bufmgr(ScrnInfoPtr pScrn, drmmode_ptr drmmode, struct radeon_bo_manager *bufmgr);
extern void drmmode_set_cursor(ScrnInfoPtr scrn, drmmode_ptr drmmode, int id, struct radeon_bo *bo);
void drmmode_adjust_frame(ScrnInfoPtr pScrn, drmmode_ptr drmmode, int x, int y, int flags);
diff --git a/driver/xf86-video-ati/src/evergreen_accel.c b/driver/xf86-video-ati/src/evergreen_accel.c
index 5c95e201f..581aaf6e4 100644
--- a/driver/xf86-video-ati/src/evergreen_accel.c
+++ b/driver/xf86-video-ati/src/evergreen_accel.c
@@ -75,6 +75,57 @@ evergreen_start_3d(ScrnInfoPtr pScrn)
}
+unsigned eg_tile_split(unsigned tile_split)
+{
+ switch (tile_split) {
+ case 64: tile_split = 0; break;
+ case 128: tile_split = 1; break;
+ case 256: tile_split = 2; break;
+ case 512: tile_split = 3; break;
+ case 1024: tile_split = 4; break;
+ case 2048: tile_split = 5; break;
+ default:
+ case 4096: tile_split = 6; break;
+ }
+ return tile_split;
+}
+
+static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
+{
+ switch (macro_tile_aspect) {
+ default:
+ case 1: macro_tile_aspect = 0; break;
+ case 2: macro_tile_aspect = 1; break;
+ case 4: macro_tile_aspect = 2; break;
+ case 8: macro_tile_aspect = 3; break;
+ }
+ return macro_tile_aspect;
+}
+
+static unsigned eg_bank_wh(unsigned bankwh)
+{
+ switch (bankwh) {
+ default:
+ case 1: bankwh = 0; break;
+ case 2: bankwh = 1; break;
+ case 4: bankwh = 2; break;
+ case 8: bankwh = 3; break;
+ }
+ return bankwh;
+}
+
+static unsigned eg_nbanks(unsigned nbanks)
+{
+ switch (nbanks) {
+ default:
+ case 2: nbanks = 0; break;
+ case 4: nbanks = 1; break;
+ case 8: nbanks = 2; break;
+ case 16: nbanks = 3; break;
+ }
+ return nbanks;
+}
+
/*
* Setup of functional groups
*/
@@ -154,12 +205,59 @@ void
evergreen_set_render_target(ScrnInfoPtr pScrn, cb_config_t *cb_conf, uint32_t domain)
{
uint32_t cb_color_info, cb_color_attrib = 0, cb_color_dim;
- int pitch, slice, h;
+ unsigned pitch, slice, w, h, array_mode, nbanks;
+ uint32_t tile_split, macro_aspect, bankw, bankh;
RADEONInfoPtr info = RADEONPTR(pScrn);
+#if defined(XF86DRM_MODE)
+ if (cb_conf->surface) {
+ switch (cb_conf->surface->level[0].mode) {
+ case RADEON_SURF_MODE_1D:
+ array_mode = 2;
+ break;
+ case RADEON_SURF_MODE_2D:
+ array_mode = 4;
+ break;
+ default:
+ array_mode = 0;
+ break;
+ }
+ w = cb_conf->surface->level[0].npix_x;
+ h = cb_conf->surface->level[0].npix_y;
+ pitch = (cb_conf->surface->level[0].nblk_x >> 3) - 1;
+ slice = ((cb_conf->surface->level[0].nblk_x * cb_conf->surface->level[0].nblk_y) / 64) - 1;
+ tile_split = cb_conf->surface->tile_split;
+ macro_aspect = cb_conf->surface->mtilea;
+ bankw = cb_conf->surface->bankw;
+ bankh = cb_conf->surface->bankh;
+ tile_split = eg_tile_split(tile_split);
+ macro_aspect = eg_macro_tile_aspect(macro_aspect);
+ bankw = eg_bank_wh(bankw);
+ bankh = eg_bank_wh(bankh);
+ } else
+#endif
+ {
+ pitch = (cb_conf->w / 8) - 1;
+ h = RADEON_ALIGN(cb_conf->h, 8);
+ slice = ((cb_conf->w * h) / 64) - 1;
+ array_mode = cb_conf->array_mode;
+ w = cb_conf->w;
+ tile_split = 4;
+ macro_aspect = 0;
+ bankw = 0;
+ bankh = 0;
+ }
+ nbanks = info->num_banks;
+ nbanks = eg_nbanks(nbanks);
+
+ cb_color_attrib |= (tile_split << CB_COLOR0_ATTRIB__TILE_SPLIT_shift)|
+ (nbanks << CB_COLOR0_ATTRIB__NUM_BANKS_shift) |
+ (bankw << CB_COLOR0_ATTRIB__BANK_WIDTH_shift) |
+ (bankh << CB_COLOR0_ATTRIB__BANK_HEIGHT_shift) |
+ (macro_aspect << CB_COLOR0_ATTRIB__MACRO_TILE_ASPECT_shift);
cb_color_info = ((cb_conf->endian << ENDIAN_shift) |
(cb_conf->format << CB_COLOR0_INFO__FORMAT_shift) |
- (cb_conf->array_mode << CB_COLOR0_INFO__ARRAY_MODE_shift) |
+ (array_mode << CB_COLOR0_INFO__ARRAY_MODE_shift) |
(cb_conf->number_type << NUMBER_TYPE_shift) |
(cb_conf->comp_swap << COMP_SWAP_shift) |
(cb_conf->source_format << SOURCE_FORMAT_shift) |
@@ -185,10 +283,6 @@ evergreen_set_render_target(ScrnInfoPtr pScrn, cb_config_t *cb_conf, uint32_t do
if (cb_conf->non_disp_tiling)
cb_color_attrib |= CB_COLOR0_ATTRIB__NON_DISP_TILING_ORDER_bit;
- pitch = (cb_conf->w / 8) - 1;
- h = RADEON_ALIGN(cb_conf->h, 8);
- slice = ((cb_conf->w * h) / 64) - 1;
-
switch (cb_conf->resource_type) {
case BUFFER:
/* number of elements in the surface */
@@ -196,7 +290,7 @@ evergreen_set_render_target(ScrnInfoPtr pScrn, cb_config_t *cb_conf, uint32_t do
break;
default:
/* w/h of the surface */
- cb_color_dim = (((cb_conf->w - 1) << WIDTH_MAX_shift) |
+ cb_color_dim = (((w - 1) << WIDTH_MAX_shift) |
((cb_conf->h - 1) << HEIGHT_MAX_shift));
break;
}
@@ -284,9 +378,6 @@ void evergreen_cp_wait_vline_sync(ScrnInfoPtr pScrn, PixmapPtr pPix,
drmmode_crtc = crtc->driver_private;
- if (stop < start)
- return;
-
if (!crtc->enabled)
return;
@@ -306,16 +397,12 @@ void evergreen_cp_wait_vline_sync(ScrnInfoPtr pScrn, PixmapPtr pPix,
return;
}
- start = max(start, 0);
- stop = min(stop, crtc->mode.VDisplay);
+ start = max(start, crtc->y);
+ stop = min(stop, crtc->y + crtc->mode.VDisplay);
- if (start > crtc->mode.VDisplay)
+ if (start >= stop)
return;
- /* on r5xx+ vline starts at viewport_y */
- start += crtc->y;
- stop += crtc->y;
-
BEGIN_BATCH(11);
/* set the VLINE range */
EREG(EVERGREEN_VLINE_START_END, /* this is just a marker */
@@ -479,6 +566,17 @@ evergreen_set_alu_consts(ScrnInfoPtr pScrn, const_config_t *const_conf, uint32_t
if (size == 0)
size = 1;
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ {
+ uint32_t count = size << 4, *p = const_conf->cpu_ptr;
+
+ while(count--) {
+ *p = cpu_to_le32(*p);
+ p++;
+ }
+ }
+#endif
+
/* flush SQ cache */
evergreen_cp_set_surface_sync(pScrn, SH_ACTION_ENA_bit,
const_conf->size_bytes, const_conf->const_addr,
@@ -563,7 +661,8 @@ evergreen_set_vtx_resource(ScrnInfoPtr pScrn, vtx_resource_t *res, uint32_t doma
(info->ChipFamily == CHIP_FAMILY_SUMO) ||
(info->ChipFamily == CHIP_FAMILY_SUMO2) ||
(info->ChipFamily == CHIP_FAMILY_CAICOS) ||
- (info->ChipFamily == CHIP_FAMILY_CAYMAN))
+ (info->ChipFamily == CHIP_FAMILY_CAYMAN) ||
+ (info->ChipFamily == CHIP_FAMILY_ARUBA))
evergreen_cp_set_surface_sync(pScrn, TC_ACTION_ENA_bit,
accel_state->vbo.vb_offset, accel_state->vbo.vb_mc_addr,
res->bo,
@@ -597,17 +696,53 @@ evergreen_set_tex_resource(ScrnInfoPtr pScrn, tex_resource_t *tex_res, uint32_t
RADEONInfoPtr info = RADEONPTR(pScrn);
uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
uint32_t sq_tex_resource_word5, sq_tex_resource_word6, sq_tex_resource_word7;
+ uint32_t array_mode, pitch, tile_split, macro_aspect, bankw, bankh, nbanks;
+
+#if defined(XF86DRM_MODE)
+ if (tex_res->surface) {
+ switch (tex_res->surface->level[0].mode) {
+ case RADEON_SURF_MODE_1D:
+ array_mode = 2;
+ break;
+ case RADEON_SURF_MODE_2D:
+ array_mode = 4;
+ break;
+ default:
+ array_mode = 0;
+ break;
+ }
+ pitch = tex_res->surface->level[0].nblk_x >> 3;
+ tile_split = tex_res->surface->tile_split;
+ macro_aspect = tex_res->surface->mtilea;
+ bankw = tex_res->surface->bankw;
+ bankh = tex_res->surface->bankh;
+ tile_split = eg_tile_split(tile_split);
+ macro_aspect = eg_macro_tile_aspect(macro_aspect);
+ bankw = eg_bank_wh(bankw);
+ bankh = eg_bank_wh(bankh);
+ } else
+#endif
+ {
+ array_mode = tex_res->array_mode;
+ pitch = (tex_res->pitch + 7) >> 3;
+ tile_split = 4;
+ macro_aspect = 0;
+ bankw = 0;
+ bankh = 0;
+ }
+ nbanks = info->num_banks;
+ nbanks = eg_nbanks(nbanks);
sq_tex_resource_word0 = (tex_res->dim << DIM_shift);
if (tex_res->w)
- sq_tex_resource_word0 |= (((((tex_res->pitch + 7) >> 3) - 1) << PITCH_shift) |
- ((tex_res->w - 1) << TEX_WIDTH_shift));
+ sq_tex_resource_word0 |= ( ((pitch - 1) << PITCH_shift) |
+ ((tex_res->w - 1) << TEX_WIDTH_shift) );
if (tex_res->tile_type)
sq_tex_resource_word0 |= SQ_TEX_RESOURCE_WORD0_0__NON_DISP_TILING_ORDER_bit;
- sq_tex_resource_word1 = (tex_res->array_mode << SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift);
+ sq_tex_resource_word1 = (array_mode << SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift);
if (tex_res->h)
sq_tex_resource_word1 |= ((tex_res->h - 1) << TEX_HEIGHT_shift);
@@ -636,12 +771,17 @@ evergreen_set_tex_resource(ScrnInfoPtr pScrn, tex_resource_t *tex_res, uint32_t
(tex_res->last_array << LAST_ARRAY_shift));
sq_tex_resource_word6 = ((tex_res->min_lod << SQ_TEX_RESOURCE_WORD6_0__MIN_LOD_shift) |
- (tex_res->perf_modulation << PERF_MODULATION_shift));
+ (tex_res->perf_modulation << PERF_MODULATION_shift) |
+ (tile_split << SQ_TEX_RESOURCE_WORD6_0__TILE_SPLIT_shift));
if (tex_res->interlaced)
sq_tex_resource_word6 |= INTERLACED_bit;
sq_tex_resource_word7 = ((tex_res->format << SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift) |
+ (macro_aspect << SQ_TEX_RESOURCE_WORD7_0__MACRO_TILE_ASPECT_shift) |
+ (nbanks << SQ_TEX_RESOURCE_WORD7_0__NUM_BANKS_shift) |
+ (bankw << SQ_TEX_RESOURCE_WORD7_0__BANK_WIDTH_shift) |
+ (bankh << SQ_TEX_RESOURCE_WORD7_0__BANK_HEIGHT_shift) |
(SQ_TEX_VTX_VALID_TEXTURE << SQ_TEX_RESOURCE_WORD7_0__TYPE_shift));
/* flush texture cache */
@@ -725,8 +865,8 @@ evergreen_fix_scissor_coordinates(ScrnInfoPtr pScrn, int *x1, int *y1, int *x2,
if (*y2 == 0)
*y1 = 1;
- /* cayman only */
- if (info->ChipFamily == CHIP_FAMILY_CAYMAN) {
+ /* cayman/tn only */
+ if (info->ChipFamily >= CHIP_FAMILY_CAYMAN) {
/* cliprects aren't affected so we can use them to clip if we need
* a true 1x1 clip region
*/
@@ -831,7 +971,7 @@ evergreen_set_default_state(ScrnInfoPtr pScrn)
RADEONInfoPtr info = RADEONPTR(pScrn);
struct radeon_accel_state *accel_state = info->accel_state;
- if (info->ChipFamily == CHIP_FAMILY_CAYMAN) {
+ if (info->ChipFamily >= CHIP_FAMILY_CAYMAN) {
cayman_set_default_state(pScrn);
return;
}
diff --git a/driver/xf86-video-ati/src/evergreen_exa.c b/driver/xf86-video-ati/src/evergreen_exa.c
index 6becbb328..cee3ec250 100644
--- a/driver/xf86-video-ati/src/evergreen_exa.c
+++ b/driver/xf86-video-ati/src/evergreen_exa.c
@@ -77,6 +77,7 @@ EVERGREENPrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
dst.offset = 0;
dst.bo = radeon_get_pixmap_bo(pPix);
dst.tiling_flags = radeon_get_pixmap_tiling(pPix);
+ dst.surface = radeon_get_pixmap_surface(pPix);
dst.pitch = exaGetPixmapPitch(pPix) / (pPix->drawable.bitsPerPixel / 8);
dst.width = pPix->drawable.width;
@@ -129,6 +130,7 @@ EVERGREENPrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
cb_conf.h = accel_state->dst_obj.height;
cb_conf.base = accel_state->dst_obj.offset;
cb_conf.bo = accel_state->dst_obj.bo;
+ cb_conf.surface = accel_state->dst_obj.surface;
if (accel_state->dst_obj.bpp == 8) {
cb_conf.format = COLOR_8;
@@ -159,7 +161,7 @@ EVERGREENPrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
cb_conf.pmask |= 8; /* A */
cb_conf.rop = accel_state->rop;
if (accel_state->dst_obj.tiling_flags == 0) {
- cb_conf.array_mode = 1;
+ cb_conf.array_mode = 0;
cb_conf.non_disp_tiling = 1;
}
evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
@@ -172,6 +174,7 @@ EVERGREENPrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
ps_alu_consts = radeon_vbo_space(pScrn, &accel_state->cbuf, 256);
ps_const_conf.bo = accel_state->cbuf.vb_bo;
ps_const_conf.const_addr = accel_state->cbuf.vb_mc_addr + accel_state->cbuf.vb_offset;
+ ps_const_conf.cpu_ptr = (uint32_t *)(char *)ps_alu_consts;
if (accel_state->dst_obj.bpp == 16) {
r = (fg >> 11) & 0x1f;
g = (fg >> 5) & 0x3f;
@@ -312,6 +315,7 @@ EVERGREENDoPrepareCopy(ScrnInfoPtr pScrn)
tex_res.size = accel_state->src_size[0];
tex_res.bo = accel_state->src_obj[0].bo;
tex_res.mip_bo = accel_state->src_obj[0].bo;
+ tex_res.surface = accel_state->src_obj[0].surface;
if (accel_state->src_obj[0].bpp == 8) {
tex_res.format = FMT_8;
tex_res.dst_sel_x = SQ_SEL_1; /* R */
@@ -336,7 +340,7 @@ EVERGREENDoPrepareCopy(ScrnInfoPtr pScrn)
tex_res.last_level = 0;
tex_res.perf_modulation = 0;
if (accel_state->src_obj[0].tiling_flags == 0)
- tex_res.array_mode = 1;
+ tex_res.array_mode = 0;
evergreen_set_tex_resource(pScrn, &tex_res, accel_state->src_obj[0].domain);
tex_samp.id = 0;
@@ -355,6 +359,7 @@ EVERGREENDoPrepareCopy(ScrnInfoPtr pScrn)
cb_conf.h = accel_state->dst_obj.height;
cb_conf.base = accel_state->dst_obj.offset;
cb_conf.bo = accel_state->dst_obj.bo;
+ cb_conf.surface = accel_state->dst_obj.surface;
if (accel_state->dst_obj.bpp == 8) {
cb_conf.format = COLOR_8;
cb_conf.comp_swap = 3; /* A */
@@ -378,7 +383,7 @@ EVERGREENDoPrepareCopy(ScrnInfoPtr pScrn)
cb_conf.pmask |= 8; /* A */
cb_conf.rop = accel_state->rop;
if (accel_state->dst_obj.tiling_flags == 0) {
- cb_conf.array_mode = 1;
+ cb_conf.array_mode = 0;
cb_conf.non_disp_tiling = 1;
}
evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
@@ -466,6 +471,8 @@ EVERGREENPrepareCopy(PixmapPtr pSrc, PixmapPtr pDst,
dst_obj.offset = 0;
src_obj.bo = radeon_get_pixmap_bo(pSrc);
dst_obj.bo = radeon_get_pixmap_bo(pDst);
+ dst_obj.surface = radeon_get_pixmap_surface(pDst);
+ src_obj.surface = radeon_get_pixmap_surface(pSrc);
dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
if (radeon_get_pixmap_bo(pSrc) == radeon_get_pixmap_bo(pDst))
@@ -494,6 +501,9 @@ EVERGREENPrepareCopy(PixmapPtr pSrc, PixmapPtr pDst,
drmmode_get_height_align(pScrn, accel_state->dst_obj.tiling_flags));
unsigned long size = height * accel_state->dst_obj.pitch * pDst->drawable.bitsPerPixel/8;
+ if (accel_state->dst_obj.surface)
+ size = accel_state->dst_obj.surface->bo_size;
+
if (accel_state->copy_area_bo) {
radeon_bo_unref(accel_state->copy_area_bo);
accel_state->copy_area_bo = NULL;
@@ -505,7 +515,7 @@ EVERGREENPrepareCopy(PixmapPtr pSrc, PixmapPtr pDst,
RADEON_FALLBACK(("temp copy surface alloc failed\n"));
radeon_cs_space_add_persistent_bo(info->cs, accel_state->copy_area_bo,
- RADEON_GEM_DOMAIN_VRAM, RADEON_GEM_DOMAIN_VRAM);
+ 0, RADEON_GEM_DOMAIN_VRAM);
if (radeon_cs_space_check(info->cs)) {
radeon_bo_unref(accel_state->copy_area_bo);
accel_state->copy_area_bo = NULL;
@@ -574,12 +584,17 @@ EVERGREENCopy(PixmapPtr pDst,
uint32_t orig_src_tiling_flags = accel_state->src_obj[0].tiling_flags;
uint32_t orig_dst_tiling_flags = accel_state->dst_obj.tiling_flags;
struct radeon_bo *orig_bo = accel_state->dst_obj.bo;
+ int orig_rop = accel_state->rop;
+ struct radeon_surface *orig_dst_surface = accel_state->dst_obj.surface;
+ struct radeon_surface *orig_src_surface = accel_state->src_obj[0].surface;
/* src to tmp */
accel_state->dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
accel_state->dst_obj.bo = accel_state->copy_area_bo;
accel_state->dst_obj.offset = 0;
accel_state->dst_obj.tiling_flags = 0;
+ accel_state->rop = 3;
+ accel_state->dst_obj.surface = NULL;
EVERGREENDoPrepareCopy(pScrn);
EVERGREENAppendCopyVertex(pScrn, srcX, srcY, dstX, dstY, w, h);
EVERGREENDoCopy(pScrn);
@@ -589,10 +604,13 @@ EVERGREENCopy(PixmapPtr pDst,
accel_state->src_obj[0].bo = accel_state->copy_area_bo;
accel_state->src_obj[0].offset = 0;
accel_state->src_obj[0].tiling_flags = 0;
+ accel_state->src_obj[0].surface = NULL;
accel_state->dst_obj.domain = orig_dst_domain;
accel_state->dst_obj.bo = orig_bo;
accel_state->dst_obj.offset = 0;
accel_state->dst_obj.tiling_flags = orig_dst_tiling_flags;
+ accel_state->rop = orig_rop;
+ accel_state->dst_obj.surface = orig_dst_surface;
EVERGREENDoPrepareCopy(pScrn);
EVERGREENAppendCopyVertex(pScrn, dstX, dstY, dstX, dstY, w, h);
EVERGREENDoCopyVline(pDst);
@@ -602,6 +620,7 @@ EVERGREENCopy(PixmapPtr pDst,
accel_state->src_obj[0].bo = orig_bo;
accel_state->src_obj[0].offset = 0;
accel_state->src_obj[0].tiling_flags = orig_src_tiling_flags;
+ accel_state->src_obj[0].surface = orig_src_surface;
} else
EVERGREENAppendCopyVertex(pScrn, srcX, srcY, dstX, dstY, w, h);
@@ -847,6 +866,7 @@ static Bool EVERGREENTextureSetup(PicturePtr pPict, PixmapPtr pPix,
tex_res.format = EVERGREENTexFormats[i].card_fmt;
tex_res.bo = accel_state->src_obj[unit].bo;
tex_res.mip_bo = accel_state->src_obj[unit].bo;
+ tex_res.surface = accel_state->src_obj[unit].surface;
#if X_BYTE_ORDER == X_BIG_ENDIAN
switch (accel_state->src_obj[unit].bpp) {
@@ -979,7 +999,7 @@ static Bool EVERGREENTextureSetup(PicturePtr pPict, PixmapPtr pPix,
tex_res.last_level = 0;
tex_res.perf_modulation = 0;
if (accel_state->src_obj[unit].tiling_flags == 0)
- tex_res.array_mode = 1;
+ tex_res.array_mode = 0;
evergreen_set_tex_resource (pScrn, &tex_res, accel_state->src_obj[unit].domain);
tex_samp.id = unit;
@@ -1129,9 +1149,10 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr pSrcPicture,
dst_obj.offset = 0;
src_obj.bo = radeon_get_pixmap_bo(pSrc);
dst_obj.bo = radeon_get_pixmap_bo(pDst);
+ dst_obj.surface = radeon_get_pixmap_surface(pDst);
+ src_obj.surface = radeon_get_pixmap_surface(pSrc);
dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
-
src_obj.pitch = exaGetPixmapPitch(pSrc) / (pSrc->drawable.bitsPerPixel / 8);
dst_obj.pitch = exaGetPixmapPitch(pDst) / (pDst->drawable.bitsPerPixel / 8);
@@ -1150,7 +1171,7 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr pSrcPicture,
mask_obj.bo = radeon_get_pixmap_bo(pMask);
mask_obj.tiling_flags = radeon_get_pixmap_tiling(pMask);
mask_obj.pitch = exaGetPixmapPitch(pMask) / (pMask->drawable.bitsPerPixel / 8);
-
+ mask_obj.surface = radeon_get_pixmap_surface(pMask);
mask_obj.width = pMask->drawable.width;
mask_obj.height = pMask->drawable.height;
mask_obj.bpp = pMask->drawable.bitsPerPixel;
@@ -1258,6 +1279,7 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr pSrcPicture,
cb_conf.base = accel_state->dst_obj.offset;
cb_conf.format = dst_format;
cb_conf.bo = accel_state->dst_obj.bo;
+ cb_conf.surface = accel_state->dst_obj.surface;
switch (pDstPicture->format) {
case PICT_a8r8g8b8:
@@ -1291,7 +1313,7 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr pSrcPicture,
cb_conf.rop = 3;
cb_conf.pmask = 0xf;
if (accel_state->dst_obj.tiling_flags == 0) {
- cb_conf.array_mode = 1;
+ cb_conf.array_mode = 0;
cb_conf.non_disp_tiling = 1;
}
#if X_BYTE_ORDER == X_BIG_ENDIAN
@@ -1320,6 +1342,7 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr pSrcPicture,
vs_const_conf.bo = accel_state->cbuf.vb_bo;
vs_const_conf.const_addr = accel_state->cbuf.vb_mc_addr + accel_state->cbuf.vb_offset;
+ vs_const_conf.cpu_ptr = (uint32_t *)(char *)cbuf;
EVERGREENXFormSetup(pSrcPicture, pSrc, 0, cbuf);
if (pMask)
EVERGREENXFormSetup(pMaskPicture, pMask, 1, cbuf);
@@ -1495,6 +1518,7 @@ EVERGREENUploadToScreen(PixmapPtr pDst, int x, int y, int w, int h,
src_obj.domain = RADEON_GEM_DOMAIN_GTT;
src_obj.bo = scratch;
src_obj.tiling_flags = 0;
+ src_obj.surface = NULL;
dst_obj.pitch = dst_pitch_hw;
dst_obj.width = pDst->drawable.width;
@@ -1504,6 +1528,7 @@ EVERGREENUploadToScreen(PixmapPtr pDst, int x, int y, int w, int h,
dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
dst_obj.bo = radeon_get_pixmap_bo(pDst);
dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
+ dst_obj.surface = radeon_get_pixmap_surface(pDst);
if (!R600SetAccelState(pScrn,
&src_obj,
@@ -1634,6 +1659,7 @@ EVERGREENDownloadFromScreen(PixmapPtr pSrc, int x, int y, int w,
src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT;
src_obj.bo = radeon_get_pixmap_bo(pSrc);
src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
+ src_obj.surface = radeon_get_pixmap_surface(pSrc);
dst_obj.pitch = scratch_pitch;
dst_obj.width = w;
@@ -1643,6 +1669,7 @@ EVERGREENDownloadFromScreen(PixmapPtr pSrc, int x, int y, int w,
dst_obj.bpp = bpp;
dst_obj.domain = RADEON_GEM_DOMAIN_GTT;
dst_obj.tiling_flags = 0;
+ dst_obj.surface = NULL;
if (!R600SetAccelState(pScrn,
&src_obj,
@@ -1931,7 +1958,7 @@ EVERGREENDrawInit(ScreenPtr pScreen)
if (!EVERGREENAllocShaders(pScrn, pScreen))
return FALSE;
- if (info->ChipFamily == CHIP_FAMILY_CAYMAN) {
+ if (info->ChipFamily >= CHIP_FAMILY_CAYMAN) {
if (!CAYMANLoadShaders(pScrn))
return FALSE;
} else {
diff --git a/driver/xf86-video-ati/src/evergreen_state.h b/driver/xf86-video-ati/src/evergreen_state.h
index 40fec229f..5a29f8fcb 100644
--- a/driver/xf86-video-ati/src/evergreen_state.h
+++ b/driver/xf86-video-ati/src/evergreen_state.h
@@ -93,6 +93,9 @@ typedef struct {
int blend_enable;
uint32_t blendcntl;
struct radeon_bo *bo;
+#ifdef XF86DRM_MODE
+ struct radeon_surface *surface;
+#endif
} cb_config_t;
/* Shader */
@@ -120,6 +123,7 @@ typedef struct {
int size_bytes;
uint64_t const_addr;
struct radeon_bo *bo;
+ uint32_t *cpu_ptr;
} const_config_t;
/* Vertex buffer / vtx resource */
@@ -178,6 +182,9 @@ typedef struct {
int min_lod;
struct radeon_bo *bo;
struct radeon_bo *mip_bo;
+#ifdef XF86DRM_MODE
+ struct radeon_surface *surface;
+#endif
} tex_resource_t;
/* Texture sampler */
diff --git a/driver/xf86-video-ati/src/evergreen_textured_videofuncs.c b/driver/xf86-video-ati/src/evergreen_textured_videofuncs.c
index 6200cdc27..8ca8e6273 100644
--- a/driver/xf86-video-ati/src/evergreen_textured_videofuncs.c
+++ b/driver/xf86-video-ati/src/evergreen_textured_videofuncs.c
@@ -158,6 +158,7 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
src_obj.offset = 0;
dst_obj.bo = radeon_get_pixmap_bo(pPixmap);
dst_obj.tiling_flags = radeon_get_pixmap_tiling(pPixmap);
+ dst_obj.surface = radeon_get_pixmap_surface(pPixmap);
dst_obj.pitch = exaGetPixmapPitch(pPixmap) / (pPixmap->drawable.bitsPerPixel / 8);
@@ -168,6 +169,7 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT;
src_obj.bo = pPriv->src_bo[pPriv->currentBuffer];
src_obj.tiling_flags = 0;
+ src_obj.surface = NULL;
dst_obj.width = pPixmap->drawable.width;
dst_obj.height = pPixmap->drawable.height;
@@ -248,6 +250,7 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.size = accel_state->src_size[0];
tex_res.bo = accel_state->src_obj[0].bo;
tex_res.mip_bo = accel_state->src_obj[0].bo;
+ tex_res.surface = NULL;
tex_res.format = FMT_8;
tex_res.dst_sel_x = SQ_SEL_X; /* Y */
@@ -340,6 +343,7 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.size = accel_state->src_size[0];
tex_res.bo = accel_state->src_obj[0].bo;
tex_res.mip_bo = accel_state->src_obj[0].bo;
+ tex_res.surface = NULL;
tex_res.format = FMT_8_8;
if (pPriv->id == FOURCC_UYVY)
@@ -406,6 +410,7 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
cb_conf.h = accel_state->dst_obj.height;
cb_conf.base = accel_state->dst_obj.offset;
cb_conf.bo = accel_state->dst_obj.bo;
+ cb_conf.surface = accel_state->dst_obj.surface;
switch (accel_state->dst_obj.bpp) {
case 16:
@@ -449,6 +454,7 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
ps_alu_consts = radeon_vbo_space(pScrn, &accel_state->cbuf, 256);
ps_const_conf.bo = accel_state->cbuf.vb_bo;
ps_const_conf.const_addr = accel_state->cbuf.vb_mc_addr + accel_state->cbuf.vb_offset;
+ ps_const_conf.cpu_ptr = (uint32_t *)(char *)ps_alu_consts;
ps_alu_consts[0] = off[0];
ps_alu_consts[1] = off[1];
@@ -474,6 +480,7 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
vs_alu_consts = radeon_vbo_space(pScrn, &accel_state->cbuf, 256);
vs_const_conf.bo = accel_state->cbuf.vb_bo;
vs_const_conf.const_addr = accel_state->cbuf.vb_mc_addr + accel_state->cbuf.vb_offset;
+ vs_const_conf.cpu_ptr = (uint32_t *)(char *)vs_alu_consts;
vs_alu_consts[0] = 1.0 / pPriv->w;
vs_alu_consts[1] = 1.0 / pPriv->h;
diff --git a/driver/xf86-video-ati/src/pcidb/ati_pciids.csv b/driver/xf86-video-ati/src/pcidb/ati_pciids.csv
index 131e56c65..337643821 100644
--- a/driver/xf86-video-ati/src/pcidb/ati_pciids.csv
+++ b/driver/xf86-video-ati/src/pcidb/ati_pciids.csv
@@ -86,6 +86,7 @@
"0x4C64","RV250_Ld","RV250",1,,,,,"ATI FireGL Mobility 9000 (M9) Ld (AGP)"
"0x4C66","RV250_Lf","RV250",1,,,,,"ATI Radeon Mobility 9000 (M9) Lf (AGP)"
"0x4C67","RV250_Lg","RV250",1,,,,,"ATI Radeon Mobility 9000 (M9) Lg (AGP)"
+"0x4C6E","RV280_4C6E","RV280",1,,,,,"ATI FireMV 2400 PCI"
"0x4D46","RAGE128MF","R128",,,,,,
"0x4D4C","RAGE128ML","R128",,,,,,
"0x4E44","R300_ND","R300",,,,,,"ATI Radeon 9700 Pro ND (AGP)"
@@ -461,6 +462,8 @@
"0x9647","SUMO_9647","SUMO",1,1,,,1,"SUMO"
"0x9648","SUMO_9648","SUMO",1,1,,,1,"SUMO"
"0x964A","SUMO_964A","SUMO",,1,,,1,"SUMO"
+"0x964B","SUMO_964B","SUMO",,1,,,1,"SUMO"
+"0x964C","SUMO_964C","SUMO",,1,,,1,"SUMO"
"0x964E","SUMO_964E","SUMO",1,1,,,1,"SUMO"
"0x964F","SUMO_964F","SUMO",1,1,,,1,"SUMO"
"0x9710","RS880_9710","RS880",,1,,,1,"ATI Radeon HD 4200"
@@ -475,6 +478,8 @@
"0x9805","PALM_9805","PALM",,1,,,1,"AMD Radeon HD 6250 Graphics"
"0x9806","PALM_9806","PALM",,1,,,1,"AMD Radeon HD 6300 Series Graphics"
"0x9807","PALM_9807","PALM",,1,,,1,"AMD Radeon HD 6200 Series Graphics"
+"0x9808","PALM_9808","PALM",,1,,,1,"PALM"
+"0x9809","PALM_9809","PALM",,1,,,1,"PALM"
"0x6880","CYPRESS_6880","CYPRESS",1,,,,,"CYPRESS"
"0x6888","CYPRESS_6888","CYPRESS",,,,,,"ATI FirePro (FireGL) Graphics Adapter"
"0x6889","CYPRESS_6889","CYPRESS",,,,,,"ATI FirePro (FireGL) Graphics Adapter"
@@ -516,6 +521,7 @@
"0x68F2","CEDAR_68F2","CEDAR",,,,,,"ATI FirePro 2270"
"0x68F8","CEDAR_68F8","CEDAR",,,,,,"CEDAR"
"0x68F9","CEDAR_68F9","CEDAR",,,,,,"ATI Radeon HD 5450"
+"0x68FA","CEDAR_68FA","CEDAR",,,,,,"CEDAR"
"0x68FE","CEDAR_68FE","CEDAR",,,,,,"CEDAR"
"0x6700","CAYMAN_6700","CAYMAN",,,,,,"CAYMAN"
"0x6701","CAYMAN_6701","CAYMAN",,,,,,"CAYMAN"
@@ -556,9 +562,20 @@
"0x6748","TURKS_6748","TURKS",,,,,,"TURKS"
"0x6749","TURKS_6749","TURKS",,,,,,"TURKS"
"0x6750","TURKS_6750","TURKS",,,,,,"TURKS"
+"0x6751","TURKS_6751","TURKS",,,,,,"TURKS"
"0x6758","TURKS_6758","TURKS",,,,,,"TURKS"
"0x6759","TURKS_6759","TURKS",,,,,,"TURKS"
+"0x675B","TURKS_675B","TURKS",,,,,,"TURKS"
+"0x675D","TURKS_675D","TURKS",,,,,,"TURKS"
"0x675F","TURKS_675F","TURKS",,,,,,"TURKS"
+"0x6840","TURKS_6840","TURKS",1,,,,,"TURKS"
+"0x6841","TURKS_6841","TURKS",1,,,,,"TURKS"
+"0x6842","TURKS_6842","TURKS",1,,,,,"TURKS"
+"0x6843","TURKS_6843","TURKS",1,,,,,"TURKS"
+"0x6849","TURKS_6849","TURKS",,,,,,"TURKS"
+"0x6850","TURKS_6850","TURKS",,,,,,"TURKS"
+"0x6858","TURKS_6858","TURKS",,,,,,"TURKS"
+"0x6859","TURKS_6859","TURKS",,,,,,"TURKS"
"0x6760","CAICOS_6760","CAICOS",1,,,,,"CAICOS"
"0x6761","CAICOS_6761","CAICOS",1,,,,,"CAICOS"
"0x6762","CAICOS_6762","CAICOS",,,,,,"CAICOS"
@@ -569,5 +586,14 @@
"0x6767","CAICOS_6767","CAICOS",,,,,,"CAICOS"
"0x6768","CAICOS_6768","CAICOS",,,,,,"CAICOS"
"0x6770","CAICOS_6770","CAICOS",,,,,,"CAICOS"
+"0x6772","CAICOS_6772","CAICOS",,,,,,"CAICOS"
"0x6778","CAICOS_6778","CAICOS",,,,,,"CAICOS"
"0x6779","CAICOS_6779","CAICOS",,,,,,"CAICOS"
+"0x677B","CAICOS_677B","CAICOS",,,,,,"CAICOS"
+"0x9900","ARUBA_9900","ARUBA",1,,,,,"ARUBA"
+"0x9901","ARUBA_9901","ARUBA",,,,,,"ARUBA"
+"0x9903","ARUBA_9903","ARUBA",1,,,,,"ARUBA"
+"0x9904","ARUBA_9904","ARUBA",,,,,,"ARUBA"
+"0x990f","ARUBA_990f","ARUBA",,,,,,"ARUBA"
+"0x9990","ARUBA_9990","ARUBA",1,,,,,"ARUBA"
+"0x9991","ARUBA_9991","ARUBA",,,,,,"ARUBA"
diff --git a/driver/xf86-video-ati/src/r600_exa.c b/driver/xf86-video-ati/src/r600_exa.c
index 71e1393f5..e1eb62f14 100644
--- a/driver/xf86-video-ati/src/r600_exa.c
+++ b/driver/xf86-video-ati/src/r600_exa.c
@@ -62,15 +62,11 @@ R600SetAccelState(ScrnInfoPtr pScrn,
memcpy(&accel_state->src_obj[0], src0, sizeof(struct r600_accel_object));
accel_state->src_size[0] = src0->pitch * src0->height * (src0->bpp/8);
#if defined(XF86DRM_MODE)
- if (info->cs) {
- pitch_align = drmmode_get_pitch_align(pScrn,
- accel_state->src_obj[0].bpp / 8,
- accel_state->src_obj[0].tiling_flags) - 1;
- base_align = drmmode_get_base_align(pScrn,
- accel_state->src_obj[0].bpp / 8,
- accel_state->src_obj[0].tiling_flags) - 1;
+ if (info->cs && src0->surface) {
+ accel_state->src_size[0] = src0->surface->bo_size;
}
#endif
+
/* bad pitch */
if (accel_state->src_obj[0].pitch & pitch_align)
RADEON_FALLBACK(("Bad src pitch 0x%08x\n", accel_state->src_obj[0].pitch));
@@ -88,15 +84,11 @@ R600SetAccelState(ScrnInfoPtr pScrn,
memcpy(&accel_state->src_obj[1], src1, sizeof(struct r600_accel_object));
accel_state->src_size[1] = src1->pitch * src1->height * (src1->bpp/8);
#if defined(XF86DRM_MODE)
- if (info->cs) {
- pitch_align = drmmode_get_pitch_align(pScrn,
- accel_state->src_obj[1].bpp / 8,
- accel_state->src_obj[1].tiling_flags) - 1;
- base_align = drmmode_get_base_align(pScrn,
- accel_state->src_obj[1].bpp / 8,
- accel_state->src_obj[1].tiling_flags) - 1;
+ if (info->cs && src1->surface) {
+ accel_state->src_size[1] = src1->surface->bo_size;
}
#endif
+
/* bad pitch */
if (accel_state->src_obj[1].pitch & pitch_align)
RADEON_FALLBACK(("Bad src pitch 0x%08x\n", accel_state->src_obj[1].pitch));
@@ -113,15 +105,13 @@ R600SetAccelState(ScrnInfoPtr pScrn,
memcpy(&accel_state->dst_obj, dst, sizeof(struct r600_accel_object));
accel_state->dst_size = dst->pitch * dst->height * (dst->bpp/8);
#if defined(XF86DRM_MODE)
- if (info->cs) {
- pitch_align = drmmode_get_pitch_align(pScrn,
- accel_state->dst_obj.bpp / 8,
- accel_state->dst_obj.tiling_flags) - 1;
- base_align = drmmode_get_base_align(pScrn,
- accel_state->dst_obj.bpp / 8,
- accel_state->dst_obj.tiling_flags) - 1;
- }
+ if (info->cs && dst->surface) {
+ accel_state->dst_size = dst->surface->bo_size;
+ } else
#endif
+ {
+ accel_state->dst_obj.tiling_flags = 0;
+ }
if (accel_state->dst_obj.pitch & pitch_align)
RADEON_FALLBACK(("Bad dst pitch 0x%08x\n", accel_state->dst_obj.pitch));
@@ -197,6 +187,7 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
dst.offset = 0;
dst.bo = radeon_get_pixmap_bo(pPix);
dst.tiling_flags = radeon_get_pixmap_tiling(pPix);
+ dst.surface = radeon_get_pixmap_surface(pPix);
} else
#endif
{
@@ -254,6 +245,9 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
cb_conf.h = accel_state->dst_obj.height;
cb_conf.base = accel_state->dst_obj.offset;
cb_conf.bo = accel_state->dst_obj.bo;
+#ifdef XF86DRM_MODE
+ cb_conf.surface = accel_state->dst_obj.surface;
+#endif
if (accel_state->dst_obj.bpp == 8) {
cb_conf.format = COLOR_8;
@@ -284,7 +278,7 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
cb_conf.pmask |= 8; /* A */
cb_conf.rop = accel_state->rop;
if (accel_state->dst_obj.tiling_flags == 0)
- cb_conf.array_mode = 1;
+ cb_conf.array_mode = 0;
r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain);
r600_set_spi(pScrn, accel_state->ib, 0, 0);
@@ -433,6 +427,9 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn)
tex_res.size = accel_state->src_size[0];
tex_res.bo = accel_state->src_obj[0].bo;
tex_res.mip_bo = accel_state->src_obj[0].bo;
+#ifdef XF86DRM_MODE
+ tex_res.surface = accel_state->src_obj[0].surface;
+#endif
if (accel_state->src_obj[0].bpp == 8) {
tex_res.format = FMT_8;
tex_res.dst_sel_x = SQ_SEL_1; /* R */
@@ -477,6 +474,9 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn)
cb_conf.h = accel_state->dst_obj.height;
cb_conf.base = accel_state->dst_obj.offset;
cb_conf.bo = accel_state->dst_obj.bo;
+#ifdef XF86DRM_MODE
+ cb_conf.surface = accel_state->dst_obj.surface;
+#endif
if (accel_state->dst_obj.bpp == 8) {
cb_conf.format = COLOR_8;
cb_conf.comp_swap = 3; /* A */
@@ -501,7 +501,7 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn)
cb_conf.pmask |= 8; /* A */
cb_conf.rop = accel_state->rop;
if (accel_state->dst_obj.tiling_flags == 0)
- cb_conf.array_mode = 1;
+ cb_conf.array_mode = 0;
r600_set_render_target(pScrn, accel_state->ib, &cb_conf, accel_state->dst_obj.domain);
r600_set_spi(pScrn, accel_state->ib, (1 - 1), 1);
@@ -591,6 +591,8 @@ R600PrepareCopy(PixmapPtr pSrc, PixmapPtr pDst,
dst_obj.bo = radeon_get_pixmap_bo(pDst);
dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
+ src_obj.surface = radeon_get_pixmap_surface(pSrc);
+ dst_obj.surface = radeon_get_pixmap_surface(pDst);
if (radeon_get_pixmap_bo(pSrc) == radeon_get_pixmap_bo(pDst))
accel_state->same_surface = TRUE;
} else
@@ -624,12 +626,12 @@ R600PrepareCopy(PixmapPtr pSrc, PixmapPtr pDst,
if (accel_state->same_surface == TRUE) {
#if defined(XF86DRM_MODE)
- unsigned height = RADEON_ALIGN(pDst->drawable.height,
- drmmode_get_height_align(pScrn, accel_state->dst_obj.tiling_flags));
+ unsigned long size = accel_state->dst_obj.surface->bo_size;
+ unsigned long align = accel_state->dst_obj.surface->bo_alignment;
#else
unsigned height = pDst->drawable.height;
-#endif
unsigned long size = height * accel_state->dst_obj.pitch * pDst->drawable.bitsPerPixel/8;
+#endif
#if defined(XF86DRM_MODE)
if (info->cs) {
@@ -637,14 +639,14 @@ R600PrepareCopy(PixmapPtr pSrc, PixmapPtr pDst,
radeon_bo_unref(accel_state->copy_area_bo);
accel_state->copy_area_bo = NULL;
}
- accel_state->copy_area_bo = radeon_bo_open(info->bufmgr, 0, size, 0,
+ accel_state->copy_area_bo = radeon_bo_open(info->bufmgr, 0, size, align,
RADEON_GEM_DOMAIN_VRAM,
0);
if (accel_state->copy_area_bo == NULL)
RADEON_FALLBACK(("temp copy surface alloc failed\n"));
radeon_cs_space_add_persistent_bo(info->cs, accel_state->copy_area_bo,
- RADEON_GEM_DOMAIN_VRAM, RADEON_GEM_DOMAIN_VRAM);
+ 0, RADEON_GEM_DOMAIN_VRAM);
if (radeon_cs_space_check(info->cs)) {
radeon_bo_unref(accel_state->copy_area_bo);
accel_state->copy_area_bo = NULL;
@@ -730,6 +732,7 @@ R600Copy(PixmapPtr pDst,
uint32_t orig_src_tiling_flags = accel_state->src_obj[0].tiling_flags;
uint32_t orig_dst_tiling_flags = accel_state->dst_obj.tiling_flags;
struct radeon_bo *orig_bo = accel_state->dst_obj.bo;
+ int orig_rop = accel_state->rop;
#if defined(XF86DRM_MODE)
if (info->cs) {
@@ -747,6 +750,7 @@ R600Copy(PixmapPtr pDst,
accel_state->dst_obj.bo = accel_state->copy_area_bo;
accel_state->dst_obj.offset = tmp_offset;
accel_state->dst_obj.tiling_flags = 0;
+ accel_state->rop = 3;
R600DoPrepareCopy(pScrn);
R600AppendCopyVertex(pScrn, srcX, srcY, dstX, dstY, w, h);
R600DoCopy(pScrn);
@@ -760,6 +764,7 @@ R600Copy(PixmapPtr pDst,
accel_state->dst_obj.bo = orig_bo;
accel_state->dst_obj.offset = orig_offset;
accel_state->dst_obj.tiling_flags = orig_dst_tiling_flags;
+ accel_state->rop = orig_rop;
R600DoPrepareCopy(pScrn);
R600AppendCopyVertex(pScrn, dstX, dstY, dstX, dstY, w, h);
R600DoCopyVline(pDst);
@@ -976,6 +981,9 @@ static Bool R600TextureSetup(PicturePtr pPict, PixmapPtr pPix,
tex_res.format = R600TexFormats[i].card_fmt;
tex_res.bo = accel_state->src_obj[unit].bo;
tex_res.mip_bo = accel_state->src_obj[unit].bo;
+#ifdef XF86DRM_MODE
+ tex_res.surface = accel_state->src_obj[unit].surface;
+#endif
tex_res.request_size = 1;
#if X_BYTE_ORDER == X_BIG_ENDIAN
@@ -1291,6 +1299,8 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
dst_obj.bo = radeon_get_pixmap_bo(pDst);
dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
+ dst_obj.surface = radeon_get_pixmap_surface(pDst);
+ src_obj.surface = radeon_get_pixmap_surface(pSrc);
} else
#endif
{
@@ -1318,6 +1328,7 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
mask_obj.offset = 0;
mask_obj.bo = radeon_get_pixmap_bo(pMask);
mask_obj.tiling_flags = radeon_get_pixmap_tiling(pMask);
+ mask_obj.surface = radeon_get_pixmap_surface(pMask);
} else
#endif
{
@@ -1429,6 +1440,9 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
cb_conf.base = accel_state->dst_obj.offset;
cb_conf.format = dst_format;
cb_conf.bo = accel_state->dst_obj.bo;
+#ifdef XF86DRM_MODE
+ cb_conf.surface = accel_state->dst_obj.surface;
+#endif
switch (pDstPicture->format) {
case PICT_a8r8g8b8:
@@ -1462,7 +1476,7 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
cb_conf.pmask = 0xf;
cb_conf.rop = 3;
if (accel_state->dst_obj.tiling_flags == 0)
- cb_conf.array_mode = 1;
+ cb_conf.array_mode = 0;
#if X_BYTE_ORDER == X_BIG_ENDIAN
switch (dst_obj.bpp) {
case 16:
@@ -1865,6 +1879,9 @@ R600UploadToScreenCS(PixmapPtr pDst, int x, int y, int w, int h,
src_obj.domain = RADEON_GEM_DOMAIN_GTT;
src_obj.bo = scratch;
src_obj.tiling_flags = 0;
+#ifdef XF86DRM_MODE
+ src_obj.surface = NULL;
+#endif
dst_obj.pitch = dst_pitch_hw;
dst_obj.width = pDst->drawable.width;
@@ -1874,6 +1891,9 @@ R600UploadToScreenCS(PixmapPtr pDst, int x, int y, int w, int h,
dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
dst_obj.bo = radeon_get_pixmap_bo(pDst);
dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
+#ifdef XF86DRM_MODE
+ dst_obj.surface = radeon_get_pixmap_surface(pDst);
+#endif
if (!R600SetAccelState(pScrn,
&src_obj,
@@ -2000,6 +2020,9 @@ R600DownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w,
src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT;
src_obj.bo = radeon_get_pixmap_bo(pSrc);
src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
+#ifdef XF86DRM_MODE
+ src_obj.surface = radeon_get_pixmap_surface(pSrc);
+#endif
dst_obj.pitch = scratch_pitch;
dst_obj.width = w;
@@ -2009,6 +2032,9 @@ R600DownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w,
dst_obj.bpp = bpp;
dst_obj.domain = RADEON_GEM_DOMAIN_GTT;
dst_obj.tiling_flags = 0;
+#ifdef XF86DRM_MODE
+ dst_obj.surface = NULL;
+#endif
if (!R600SetAccelState(pScrn,
&src_obj,
diff --git a/driver/xf86-video-ati/src/r600_state.h b/driver/xf86-video-ati/src/r600_state.h
index d5785cdd8..f6d5a8806 100644
--- a/driver/xf86-video-ati/src/r600_state.h
+++ b/driver/xf86-video-ati/src/r600_state.h
@@ -56,6 +56,9 @@ typedef struct {
int blend_enable;
uint32_t blendcntl;
struct radeon_bo *bo;
+#ifdef XF86DRM_MODE
+ struct radeon_surface *surface;
+#endif
} cb_config_t;
/* Depth buffer */
@@ -142,6 +145,9 @@ typedef struct {
int interlaced;
struct radeon_bo *bo;
struct radeon_bo *mip_bo;
+#ifdef XF86DRM_MODE
+ struct radeon_surface *surface;
+#endif
} tex_resource_t;
/* Texture sampler */
diff --git a/driver/xf86-video-ati/src/r600_textured_videofuncs.c b/driver/xf86-video-ati/src/r600_textured_videofuncs.c
index aab43f3a7..62da992ca 100644
--- a/driver/xf86-video-ati/src/r600_textured_videofuncs.c
+++ b/driver/xf86-video-ati/src/r600_textured_videofuncs.c
@@ -170,6 +170,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
src_obj.offset = 0;
dst_obj.bo = radeon_get_pixmap_bo(pPixmap);
dst_obj.tiling_flags = radeon_get_pixmap_tiling(pPixmap);
+ dst_obj.surface = radeon_get_pixmap_surface(pPixmap);
} else
#endif
{
@@ -186,6 +187,9 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT;
src_obj.bo = pPriv->src_bo[pPriv->currentBuffer];
src_obj.tiling_flags = 0;
+#ifdef XF86DRM_MODE
+ src_obj.surface = NULL;
+#endif
dst_obj.width = pPixmap->drawable.width;
dst_obj.height = pPixmap->drawable.height;
@@ -270,6 +274,9 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
tex_res.size = accel_state->src_size[0];
tex_res.bo = accel_state->src_obj[0].bo;
tex_res.mip_bo = accel_state->src_obj[0].bo;
+#ifdef XF86DRM_MODE
+ tex_res.surface = NULL;
+#endif
tex_res.format = FMT_8;
tex_res.dst_sel_x = SQ_SEL_X; /* Y */
@@ -431,6 +438,9 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
cb_conf.h = accel_state->dst_obj.height;
cb_conf.base = accel_state->dst_obj.offset;
cb_conf.bo = accel_state->dst_obj.bo;
+#ifdef XF86DRM_MODE
+ cb_conf.surface = accel_state->dst_obj.surface;
+#endif
switch (accel_state->dst_obj.bpp) {
case 16:
@@ -493,7 +503,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
}
while (nBox--) {
- int srcX, srcY, srcw, srch;
+ float srcX, srcY, srcw, srch;
int dstX, dstY, dstw, dsth;
float *vb;
@@ -505,13 +515,13 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
srcX = pPriv->src_x;
srcX += ((pBox->x1 - pPriv->drw_x) *
- pPriv->src_w) / pPriv->dst_w;
+ pPriv->src_w) / (float)pPriv->dst_w;
srcY = pPriv->src_y;
srcY += ((pBox->y1 - pPriv->drw_y) *
- pPriv->src_h) / pPriv->dst_h;
+ pPriv->src_h) / (float)pPriv->dst_h;
- srcw = (pPriv->src_w * dstw) / pPriv->dst_w;
- srch = (pPriv->src_h * dsth) / pPriv->dst_h;
+ srcw = (pPriv->src_w * dstw) / (float)pPriv->dst_w;
+ srch = (pPriv->src_h * dsth) / (float)pPriv->dst_h;
vb = radeon_vbo_space(pScrn, &accel_state->vbo, 16);
diff --git a/driver/xf86-video-ati/src/r6xx_accel.c b/driver/xf86-video-ati/src/r6xx_accel.c
index 752165b70..8d2542411 100644
--- a/driver/xf86-video-ati/src/r6xx_accel.c
+++ b/driver/xf86-video-ati/src/r6xx_accel.c
@@ -223,12 +223,37 @@ void
r600_set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf, uint32_t domain)
{
uint32_t cb_color_info, cb_color_control;
- int pitch, slice, h;
+ unsigned pitch, slice, h, array_mode;
RADEONInfoPtr info = RADEONPTR(pScrn);
+
+#if defined(XF86DRM_MODE)
+ if (cb_conf->surface) {
+ switch (cb_conf->surface->level[0].mode) {
+ case RADEON_SURF_MODE_1D:
+ array_mode = 2;
+ break;
+ case RADEON_SURF_MODE_2D:
+ array_mode = 4;
+ break;
+ default:
+ array_mode = 0;
+ break;
+ }
+ pitch = (cb_conf->surface->level[0].nblk_x >> 3) - 1;
+ slice = ((cb_conf->surface->level[0].nblk_x * cb_conf->surface->level[0].nblk_y) / 64) - 1;
+ } else
+#endif
+ {
+ array_mode = cb_conf->array_mode;
+ pitch = (cb_conf->w / 8) - 1;
+ h = RADEON_ALIGN(cb_conf->h, 8);
+ slice = ((cb_conf->w * h) / 64) - 1;
+ }
+
cb_color_info = ((cb_conf->endian << ENDIAN_shift) |
(cb_conf->format << CB_COLOR0_INFO__FORMAT_shift) |
- (cb_conf->array_mode << CB_COLOR0_INFO__ARRAY_MODE_shift) |
+ (array_mode << CB_COLOR0_INFO__ARRAY_MODE_shift) |
(cb_conf->number_type << NUMBER_TYPE_shift) |
(cb_conf->comp_swap << COMP_SWAP_shift) |
(cb_conf->tile_mode << CB_COLOR0_INFO__TILE_MODE_shift));
@@ -251,10 +276,6 @@ r600_set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf, ui
if (cb_conf->source_format)
cb_color_info |= SOURCE_FORMAT_bit;
- pitch = (cb_conf->w / 8) - 1;
- h = RADEON_ALIGN(cb_conf->h, 8);
- slice = ((cb_conf->w * h) / 64) - 1;
-
BEGIN_BATCH(3 + 2);
EREG(ib, (CB_COLOR0_BASE + (4 * cb_conf->id)), (cb_conf->base >> 8));
RELOC_BATCH(cb_conf->bo, 0, domain);
@@ -345,9 +366,6 @@ r600_cp_wait_vline_sync(ScrnInfoPtr pScrn, drmBufPtr ib, PixmapPtr pPix,
if (!crtc)
return;
- if (stop < start)
- return;
-
if (!crtc->enabled)
return;
@@ -367,16 +385,12 @@ r600_cp_wait_vline_sync(ScrnInfoPtr pScrn, drmBufPtr ib, PixmapPtr pPix,
return;
}
- start = max(start, 0);
- stop = min(stop, crtc->mode.VDisplay);
+ start = max(start, crtc->y);
+ stop = min(stop, crtc->y + crtc->mode.VDisplay);
- if (start > crtc->mode.VDisplay)
+ if (start >= stop)
return;
- /* on r5xx+ vline starts at viewport_y */
- start += crtc->y;
- stop += crtc->y;
-
#if defined(XF86DRM_MODE)
if (info->cs) {
drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
@@ -609,12 +623,34 @@ r600_set_tex_resource(ScrnInfoPtr pScrn, drmBufPtr ib, tex_resource_t *tex_res,
RADEONInfoPtr info = RADEONPTR(pScrn);
uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
uint32_t sq_tex_resource_word5, sq_tex_resource_word6;
+ uint32_t array_mode, pitch;
+
+#if defined(XF86DRM_MODE)
+ if (tex_res->surface) {
+ switch (tex_res->surface->level[0].mode) {
+ case RADEON_SURF_MODE_1D:
+ array_mode = 2;
+ break;
+ case RADEON_SURF_MODE_2D:
+ array_mode = 4;
+ break;
+ default:
+ array_mode = 0;
+ break;
+ }
+ pitch = tex_res->surface->level[0].nblk_x >> 3;
+ } else
+#endif
+ {
+ array_mode = tex_res->tile_mode;
+ pitch = (tex_res->pitch + 7) >> 3;
+ }
sq_tex_resource_word0 = ((tex_res->dim << DIM_shift) |
- (tex_res->tile_mode << SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift));
+ (array_mode << SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift));
if (tex_res->w)
- sq_tex_resource_word0 |= (((((tex_res->pitch + 7) >> 3) - 1) << PITCH_shift) |
+ sq_tex_resource_word0 |= (((pitch - 1) << PITCH_shift) |
((tex_res->w - 1) << TEX_WIDTH_shift));
if (tex_res->tile_type)
@@ -1125,7 +1161,7 @@ r600_set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
r600_fs_setup(pScrn, ib, &fs_conf, RADEON_GEM_DOMAIN_VRAM);
// VGT
- BEGIN_BATCH(43);
+ BEGIN_BATCH(46);
PACK0(ib, VGT_MAX_VTX_INDX, 4);
E32(ib, 0xffffff); // VGT_MAX_VTX_INDX
E32(ib, 0); // VGT_MIN_VTX_INDX
@@ -1164,6 +1200,7 @@ r600_set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
E32(ib, 0); // VGT_VTX_CNT_EN
EREG(ib, VGT_STRMOUT_BUFFER_EN, 0);
+ EREG(ib, SX_MISC, 0);
END_BATCH();
}
diff --git a/driver/xf86-video-ati/src/radeon.h b/driver/xf86-video-ati/src/radeon.h
index 73d6db1e9..ce9508c33 100644
--- a/driver/xf86-video-ati/src/radeon.h
+++ b/driver/xf86-video-ati/src/radeon.h
@@ -91,6 +91,7 @@
#include "radeon_cs.h"
#include "radeon_dri2.h"
#include "drmmode_display.h"
+#include "radeon_surface.h"
#else
#include "radeon_dummy_bufmgr.h"
#endif
@@ -183,6 +184,7 @@ typedef enum {
OPTION_PANEL_SIZE,
OPTION_MIN_DOTCLOCK,
OPTION_COLOR_TILING,
+ OPTION_COLOR_TILING_2D,
#ifdef XvExtension
OPTION_VIDEO_KEY,
OPTION_RAGE_THEATRE_CRYSTAL,
@@ -442,6 +444,9 @@ typedef struct _atomBiosHandle *atomBiosHandlePtr;
struct radeon_exa_pixmap_priv {
struct radeon_bo *bo;
uint32_t tiling_flags;
+#ifdef XF86DRM_MODE
+ struct radeon_surface surface;
+#endif
Bool bo_mapped;
};
@@ -621,6 +626,9 @@ struct r600_accel_object {
uint32_t domain;
struct radeon_bo *bo;
uint32_t tiling_flags;
+#if defined(XF86DRM_MODE)
+ struct radeon_surface *surface;
+#endif
};
struct radeon_vbo_object {
@@ -792,7 +800,9 @@ struct radeon_accel_state {
typedef struct {
EntityInfoPtr pEnt;
pciVideoPtr PciInfo;
+#ifndef XSERVER_LIBPCIACCESS
PCITAG PciTag;
+#endif
int Chipset;
RADEONChipFamily ChipFamily;
RADEONErrata ChipErrata;
@@ -887,6 +897,7 @@ typedef struct {
/* accel */
Bool RenderAccel; /* Render */
Bool allowColorTiling;
+ Bool allowColorTiling2D;
Bool tilingEnabled; /* mirror of sarea->tiling_enabled */
struct radeon_accel_state *accel_state;
Bool accelOn;
@@ -1001,7 +1012,7 @@ typedef struct {
struct radeon_cs_manager *csm;
struct radeon_cs *cs;
- struct radeon_bo *cursor_bo[6];
+ struct radeon_bo *cursor_bo[32];
uint64_t vram_size;
uint64_t gart_size;
drmmode_rec drmmode;
@@ -1012,6 +1023,8 @@ typedef struct {
int num_channels;
int num_banks;
int r7xx_bank_op;
+ struct radeon_surface_manager *surf_man;
+ struct radeon_surface front_surface;
#else
/* fake bool */
Bool cs;
@@ -1070,6 +1083,7 @@ extern void RADEONRestoreLVDSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore)
extern void RADEONRestoreRMXRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore);
extern void RADEONSaveDACRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
extern void RADEONSaveFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
+extern void radeon_save_palette_on_demand(ScrnInfoPtr pScrn, int palID);
extern void RADEONGetTVDacAdjInfo(ScrnInfoPtr pScrn, radeon_tvdac_ptr tvdac);
extern void RADEONGetTMDSInfoFromTable(ScrnInfoPtr pScrn, radeon_tmds_ptr tmds);
@@ -1144,6 +1158,7 @@ extern void RADEONWaitForVLineMMIO(ScrnInfoPtr pScrn, PixmapPtr pPix,
/* radeon_crtc.c */
extern void radeon_crtc_dpms(xf86CrtcPtr crtc, int mode);
+extern void radeon_do_crtc_dpms(xf86CrtcPtr crtc, int mode);
extern void radeon_crtc_load_lut(xf86CrtcPtr crtc);
extern void radeon_crtc_modeset_ioctl(xf86CrtcPtr crtc, Bool post);
extern Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask);
@@ -1227,6 +1242,7 @@ extern void RADEONPMFini(ScrnInfoPtr pScrn);
#ifdef USE_EXA
/* radeon_exa.c */
+extern unsigned eg_tile_split(unsigned tile_split);
extern Bool RADEONSetupMemEXA(ScreenPtr pScreen);
extern Bool radeon_transform_is_affine_or_scaled(PictTransformPtr t);
@@ -1318,6 +1334,7 @@ extern void radeon_ddx_cs_start(ScrnInfoPtr pScrn,
int num, const char *file,
const char *func, int line);
void radeon_kms_update_vram_limit(ScrnInfoPtr pScrn, int new_fb_size);
+struct radeon_surface *radeon_get_pixmap_surface(PixmapPtr pPix);
#endif
struct radeon_bo *radeon_get_pixmap_bo(PixmapPtr pPix);
void radeon_set_pixmap_bo(PixmapPtr pPix, struct radeon_bo *bo);
@@ -1665,6 +1682,8 @@ static __inline__ int radeon_timedout(const struct timeval *endtime)
enum {
RADEON_CREATE_PIXMAP_TILING_MACRO = 0x10000000,
RADEON_CREATE_PIXMAP_TILING_MICRO = 0x20000000,
+ RADEON_CREATE_PIXMAP_DEPTH = 0x40000000, /* for r200 */
+ RADEON_CREATE_PIXMAP_SZBUFFER = 0x80000000, /* for eg */
};
#endif /* _RADEON_H_ */
diff --git a/driver/xf86-video-ati/src/radeon_chipinfo_gen.h b/driver/xf86-video-ati/src/radeon_chipinfo_gen.h
index fcf6b3362..a57882502 100644
--- a/driver/xf86-video-ati/src/radeon_chipinfo_gen.h
+++ b/driver/xf86-video-ati/src/radeon_chipinfo_gen.h
@@ -53,6 +53,7 @@ static RADEONCardInfo RADEONCards[] = {
{ 0x4C64, CHIP_FAMILY_RV250, 1, 0, 0, 0, 0 },
{ 0x4C66, CHIP_FAMILY_RV250, 1, 0, 0, 0, 0 },
{ 0x4C67, CHIP_FAMILY_RV250, 1, 0, 0, 0, 0 },
+ { 0x4C6E, CHIP_FAMILY_RV280, 1, 0, 0, 0, 0 },
{ 0x4E44, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 },
{ 0x4E45, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 },
{ 0x4E46, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 },
@@ -380,6 +381,8 @@ static RADEONCardInfo RADEONCards[] = {
{ 0x9647, CHIP_FAMILY_SUMO, 1, 1, 0, 0, 1 },
{ 0x9648, CHIP_FAMILY_SUMO, 1, 1, 0, 0, 1 },
{ 0x964A, CHIP_FAMILY_SUMO, 0, 1, 0, 0, 1 },
+ { 0x964B, CHIP_FAMILY_SUMO, 0, 1, 0, 0, 1 },
+ { 0x964C, CHIP_FAMILY_SUMO, 0, 1, 0, 0, 1 },
{ 0x964E, CHIP_FAMILY_SUMO, 1, 1, 0, 0, 1 },
{ 0x964F, CHIP_FAMILY_SUMO, 1, 1, 0, 0, 1 },
{ 0x9710, CHIP_FAMILY_RS880, 0, 1, 0, 0, 1 },
@@ -394,6 +397,8 @@ static RADEONCardInfo RADEONCards[] = {
{ 0x9805, CHIP_FAMILY_PALM, 0, 1, 0, 0, 1 },
{ 0x9806, CHIP_FAMILY_PALM, 0, 1, 0, 0, 1 },
{ 0x9807, CHIP_FAMILY_PALM, 0, 1, 0, 0, 1 },
+ { 0x9808, CHIP_FAMILY_PALM, 0, 1, 0, 0, 1 },
+ { 0x9809, CHIP_FAMILY_PALM, 0, 1, 0, 0, 1 },
{ 0x6880, CHIP_FAMILY_CYPRESS, 1, 0, 0, 0, 0 },
{ 0x6888, CHIP_FAMILY_CYPRESS, 0, 0, 0, 0, 0 },
{ 0x6889, CHIP_FAMILY_CYPRESS, 0, 0, 0, 0, 0 },
@@ -435,6 +440,7 @@ static RADEONCardInfo RADEONCards[] = {
{ 0x68F2, CHIP_FAMILY_CEDAR, 0, 0, 0, 0, 0 },
{ 0x68F8, CHIP_FAMILY_CEDAR, 0, 0, 0, 0, 0 },
{ 0x68F9, CHIP_FAMILY_CEDAR, 0, 0, 0, 0, 0 },
+ { 0x68FA, CHIP_FAMILY_CEDAR, 0, 0, 0, 0, 0 },
{ 0x68FE, CHIP_FAMILY_CEDAR, 0, 0, 0, 0, 0 },
{ 0x6700, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 },
{ 0x6701, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 },
@@ -475,9 +481,20 @@ static RADEONCardInfo RADEONCards[] = {
{ 0x6748, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
{ 0x6749, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
{ 0x6750, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
+ { 0x6751, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
{ 0x6758, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
{ 0x6759, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
+ { 0x675B, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
+ { 0x675D, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
{ 0x675F, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
+ { 0x6840, CHIP_FAMILY_TURKS, 1, 0, 0, 0, 0 },
+ { 0x6841, CHIP_FAMILY_TURKS, 1, 0, 0, 0, 0 },
+ { 0x6842, CHIP_FAMILY_TURKS, 1, 0, 0, 0, 0 },
+ { 0x6843, CHIP_FAMILY_TURKS, 1, 0, 0, 0, 0 },
+ { 0x6849, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
+ { 0x6850, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
+ { 0x6858, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
+ { 0x6859, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
{ 0x6760, CHIP_FAMILY_CAICOS, 1, 0, 0, 0, 0 },
{ 0x6761, CHIP_FAMILY_CAICOS, 1, 0, 0, 0, 0 },
{ 0x6762, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 },
@@ -488,6 +505,15 @@ static RADEONCardInfo RADEONCards[] = {
{ 0x6767, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 },
{ 0x6768, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 },
{ 0x6770, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 },
+ { 0x6772, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 },
{ 0x6778, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 },
{ 0x6779, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 },
+ { 0x677B, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 },
+ { 0x9900, CHIP_FAMILY_ARUBA, 1, 0, 0, 0, 0 },
+ { 0x9901, CHIP_FAMILY_ARUBA, 0, 0, 0, 0, 0 },
+ { 0x9903, CHIP_FAMILY_ARUBA, 1, 0, 0, 0, 0 },
+ { 0x9904, CHIP_FAMILY_ARUBA, 0, 0, 0, 0, 0 },
+ { 0x990f, CHIP_FAMILY_ARUBA, 0, 0, 0, 0, 0 },
+ { 0x9990, CHIP_FAMILY_ARUBA, 1, 0, 0, 0, 0 },
+ { 0x9991, CHIP_FAMILY_ARUBA, 0, 0, 0, 0, 0 },
};
diff --git a/driver/xf86-video-ati/src/radeon_chipset_gen.h b/driver/xf86-video-ati/src/radeon_chipset_gen.h
index 0303a5dcb..e7f7379a0 100644
--- a/driver/xf86-video-ati/src/radeon_chipset_gen.h
+++ b/driver/xf86-video-ati/src/radeon_chipset_gen.h
@@ -53,6 +53,7 @@ static SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_RV250_Ld, "ATI FireGL Mobility 9000 (M9) Ld (AGP)" },
{ PCI_CHIP_RV250_Lf, "ATI Radeon Mobility 9000 (M9) Lf (AGP)" },
{ PCI_CHIP_RV250_Lg, "ATI Radeon Mobility 9000 (M9) Lg (AGP)" },
+ { PCI_CHIP_RV280_4C6E, "ATI FireMV 2400 PCI" },
{ PCI_CHIP_R300_ND, "ATI Radeon 9700 Pro ND (AGP)" },
{ PCI_CHIP_R300_NE, "ATI Radeon 9700/9500Pro NE (AGP)" },
{ PCI_CHIP_R300_NF, "ATI Radeon 9600TX NF (AGP)" },
@@ -380,6 +381,8 @@ static SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_SUMO_9647, "SUMO" },
{ PCI_CHIP_SUMO_9648, "SUMO" },
{ PCI_CHIP_SUMO_964A, "SUMO" },
+ { PCI_CHIP_SUMO_964B, "SUMO" },
+ { PCI_CHIP_SUMO_964C, "SUMO" },
{ PCI_CHIP_SUMO_964E, "SUMO" },
{ PCI_CHIP_SUMO_964F, "SUMO" },
{ PCI_CHIP_RS880_9710, "ATI Radeon HD 4200" },
@@ -394,6 +397,8 @@ static SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_PALM_9805, "AMD Radeon HD 6250 Graphics" },
{ PCI_CHIP_PALM_9806, "AMD Radeon HD 6300 Series Graphics" },
{ PCI_CHIP_PALM_9807, "AMD Radeon HD 6200 Series Graphics" },
+ { PCI_CHIP_PALM_9808, "PALM" },
+ { PCI_CHIP_PALM_9809, "PALM" },
{ PCI_CHIP_CYPRESS_6880, "CYPRESS" },
{ PCI_CHIP_CYPRESS_6888, "ATI FirePro (FireGL) Graphics Adapter" },
{ PCI_CHIP_CYPRESS_6889, "ATI FirePro (FireGL) Graphics Adapter" },
@@ -435,6 +440,7 @@ static SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_CEDAR_68F2, "ATI FirePro 2270" },
{ PCI_CHIP_CEDAR_68F8, "CEDAR" },
{ PCI_CHIP_CEDAR_68F9, "ATI Radeon HD 5450" },
+ { PCI_CHIP_CEDAR_68FA, "CEDAR" },
{ PCI_CHIP_CEDAR_68FE, "CEDAR" },
{ PCI_CHIP_CAYMAN_6700, "CAYMAN" },
{ PCI_CHIP_CAYMAN_6701, "CAYMAN" },
@@ -475,9 +481,20 @@ static SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_TURKS_6748, "TURKS" },
{ PCI_CHIP_TURKS_6749, "TURKS" },
{ PCI_CHIP_TURKS_6750, "TURKS" },
+ { PCI_CHIP_TURKS_6751, "TURKS" },
{ PCI_CHIP_TURKS_6758, "TURKS" },
{ PCI_CHIP_TURKS_6759, "TURKS" },
+ { PCI_CHIP_TURKS_675B, "TURKS" },
+ { PCI_CHIP_TURKS_675D, "TURKS" },
{ PCI_CHIP_TURKS_675F, "TURKS" },
+ { PCI_CHIP_TURKS_6840, "TURKS" },
+ { PCI_CHIP_TURKS_6841, "TURKS" },
+ { PCI_CHIP_TURKS_6842, "TURKS" },
+ { PCI_CHIP_TURKS_6843, "TURKS" },
+ { PCI_CHIP_TURKS_6849, "TURKS" },
+ { PCI_CHIP_TURKS_6850, "TURKS" },
+ { PCI_CHIP_TURKS_6858, "TURKS" },
+ { PCI_CHIP_TURKS_6859, "TURKS" },
{ PCI_CHIP_CAICOS_6760, "CAICOS" },
{ PCI_CHIP_CAICOS_6761, "CAICOS" },
{ PCI_CHIP_CAICOS_6762, "CAICOS" },
@@ -488,7 +505,16 @@ static SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_CAICOS_6767, "CAICOS" },
{ PCI_CHIP_CAICOS_6768, "CAICOS" },
{ PCI_CHIP_CAICOS_6770, "CAICOS" },
+ { PCI_CHIP_CAICOS_6772, "CAICOS" },
{ PCI_CHIP_CAICOS_6778, "CAICOS" },
{ PCI_CHIP_CAICOS_6779, "CAICOS" },
+ { PCI_CHIP_CAICOS_677B, "CAICOS" },
+ { PCI_CHIP_ARUBA_9900, "ARUBA" },
+ { PCI_CHIP_ARUBA_9901, "ARUBA" },
+ { PCI_CHIP_ARUBA_9903, "ARUBA" },
+ { PCI_CHIP_ARUBA_9904, "ARUBA" },
+ { PCI_CHIP_ARUBA_990f, "ARUBA" },
+ { PCI_CHIP_ARUBA_9990, "ARUBA" },
+ { PCI_CHIP_ARUBA_9991, "ARUBA" },
{ -1, NULL }
};
diff --git a/driver/xf86-video-ati/src/radeon_commonfuncs.c b/driver/xf86-video-ati/src/radeon_commonfuncs.c
index 728194904..e0b026f1b 100644
--- a/driver/xf86-video-ati/src/radeon_commonfuncs.c
+++ b/driver/xf86-video-ati/src/radeon_commonfuncs.c
@@ -839,9 +839,6 @@ void FUNC_NAME(RADEONWaitForVLine)(ScrnInfoPtr pScrn, PixmapPtr pPix,
if (!crtc)
return;
- if (stop < start)
- return;
-
if (!crtc->enabled)
return;
@@ -861,16 +858,16 @@ void FUNC_NAME(RADEONWaitForVLine)(ScrnInfoPtr pScrn, PixmapPtr pPix,
return;
}
- start = max(start, 0);
- stop = min(stop, crtc->mode.VDisplay);
+ start = max(start, crtc->y);
+ stop = min(stop, crtc->y + crtc->mode.VDisplay);
- if (start > crtc->mode.VDisplay)
+ if (start >= stop)
return;
- if (IS_AVIVO_VARIANT) {
- /* on r5xx+ vline starts at viewport_y */
- start += crtc->y;
- stop += crtc->y;
+ if (!IS_AVIVO_VARIANT) {
+ /* on pre-r5xx vline starts at CRTC scanout */
+ start -= crtc->y;
+ stop -= crtc->y;
}
#if defined(ACCEL_CP) && defined(XF86DRM_MODE)
diff --git a/driver/xf86-video-ati/src/radeon_crtc.c b/driver/xf86-video-ati/src/radeon_crtc.c
index d0daa484a..ade12283e 100644
--- a/driver/xf86-video-ati/src/radeon_crtc.c
+++ b/driver/xf86-video-ati/src/radeon_crtc.c
@@ -69,18 +69,12 @@ RADEONInitDispBandwidthAVIVO(ScrnInfoPtr pScrn,
DisplayModePtr mode2, int pixel_bytes2);
void
-radeon_crtc_dpms(xf86CrtcPtr crtc, int mode)
+radeon_do_crtc_dpms(xf86CrtcPtr crtc, int mode)
{
RADEONInfoPtr info = RADEONPTR(crtc->scrn);
RADEONEntPtr pRADEONEnt = RADEONEntPriv(crtc->scrn);
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
xf86CrtcPtr crtc0 = pRADEONEnt->pCrtc[0];
-
- if ((mode == DPMSModeOn) && radeon_crtc->enabled)
- return;
-
- if (mode == DPMSModeOff)
- radeon_crtc_modeset_ioctl(crtc, FALSE);
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
if (IS_AVIVO_VARIANT || info->r4xx_atom) {
atombios_crtc_dpms(crtc, mode);
@@ -101,6 +95,20 @@ radeon_crtc_dpms(xf86CrtcPtr crtc, int mode)
legacy_crtc_dpms(crtc0, mode);
}
}
+}
+
+void
+radeon_crtc_dpms(xf86CrtcPtr crtc, int mode)
+{
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+
+ if ((mode == DPMSModeOn) && radeon_crtc->enabled)
+ return;
+
+ if (mode == DPMSModeOff)
+ radeon_crtc_modeset_ioctl(crtc, FALSE);
+
+ radeon_do_crtc_dpms(crtc, mode);
if (mode != DPMSModeOff) {
radeon_crtc_modeset_ioctl(crtc, TRUE);
@@ -511,6 +519,8 @@ radeon_crtc_load_lut(xf86CrtcPtr crtc)
if (!crtc->enabled)
return;
+ radeon_save_palette_on_demand(pScrn, radeon_crtc->crtc_id);
+
if (IS_DCE4_VARIANT) {
OUTREG(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
@@ -559,7 +569,6 @@ radeon_crtc_load_lut(xf86CrtcPtr crtc)
if (IS_AVIVO_VARIANT)
OUTREG(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
}
-
}
static void
diff --git a/driver/xf86-video-ati/src/radeon_dri2.c b/driver/xf86-video-ati/src/radeon_dri2.c
index 8789d7359..8bd3f6671 100644
--- a/driver/xf86-video-ati/src/radeon_dri2.c
+++ b/driver/xf86-video-ati/src/radeon_dri2.c
@@ -40,6 +40,13 @@
#if HAVE_LIST_H
#include "list.h"
+#if !HAVE_XORG_LIST
+#define xorg_list list
+#define xorg_list_init list_init
+#define xorg_list_add list_add
+#define xorg_list_del list_del
+#define xorg_list_for_each_entry list_for_each_entry
+#endif
#endif
#ifdef RADEON_DRI2
@@ -121,6 +128,8 @@ radeon_dri2_create_buffers(DrawablePtr drawable,
flags = RADEON_CREATE_PIXMAP_TILING_MICRO;
else
flags = RADEON_CREATE_PIXMAP_TILING_MACRO | RADEON_CREATE_PIXMAP_TILING_MICRO;
+ if (IS_R200_3D || info->ChipFamily == CHIP_FAMILY_RV200 || info->ChipFamily == CHIP_FAMILY_RADEON)
+ flags |= RADEON_CREATE_PIXMAP_DEPTH;
break;
case DRI2BufferDepthStencil:
if (info->ChipFamily >= CHIP_FAMILY_R600) {
@@ -132,6 +141,8 @@ radeon_dri2_create_buffers(DrawablePtr drawable,
need_enlarge = 1;
} else
flags = RADEON_CREATE_PIXMAP_TILING_MACRO | RADEON_CREATE_PIXMAP_TILING_MICRO;
+ if (IS_R200_3D || info->ChipFamily == CHIP_FAMILY_RV200 || info->ChipFamily == CHIP_FAMILY_RADEON)
+ flags |= RADEON_CREATE_PIXMAP_DEPTH;
break;
case DRI2BufferBackLeft:
case DRI2BufferBackRight:
@@ -240,10 +251,10 @@ radeon_dri2_create_buffer(DrawablePtr drawable,
struct dri2_buffer_priv *privates;
PixmapPtr pixmap, depth_pixmap;
struct radeon_exa_pixmap_priv *driver_priv;
- int need_enlarge = 0;
int flags;
unsigned front_width;
uint32_t tiling = 0;
+ unsigned aligned_width = drawable->width;
pixmap = pScreen->GetScreenPixmap(pScreen);
front_width = pixmap->drawable.width;
@@ -267,32 +278,48 @@ radeon_dri2_create_buffer(DrawablePtr drawable,
/* macro is the preferred setting, but the 2D detiling for software
* fallbacks in mesa still has issues on some configurations
*/
- if (info->ChipFamily >= CHIP_FAMILY_R600)
- flags = RADEON_CREATE_PIXMAP_TILING_MICRO;
- else
+ if (info->ChipFamily >= CHIP_FAMILY_R600) {
+ if (info->allowColorTiling2D) {
+ flags = RADEON_CREATE_PIXMAP_TILING_MACRO;
+ } else {
+ flags = RADEON_CREATE_PIXMAP_TILING_MICRO;
+ }
+ if (info->ChipFamily >= CHIP_FAMILY_CEDAR)
+ flags |= RADEON_CREATE_PIXMAP_SZBUFFER;
+ } else
flags = RADEON_CREATE_PIXMAP_TILING_MACRO | RADEON_CREATE_PIXMAP_TILING_MICRO;
+ if (IS_R200_3D || info->ChipFamily == CHIP_FAMILY_RV200 || info->ChipFamily == CHIP_FAMILY_RADEON)
+ flags |= RADEON_CREATE_PIXMAP_DEPTH;
break;
case DRI2BufferDepthStencil:
/* macro is the preferred setting, but the 2D detiling for software
* fallbacks in mesa still has issues on some configurations
*/
if (info->ChipFamily >= CHIP_FAMILY_R600) {
- flags = RADEON_CREATE_PIXMAP_TILING_MICRO;
+ if (info->allowColorTiling2D) {
+ flags = RADEON_CREATE_PIXMAP_TILING_MACRO;
+ } else {
+ flags = RADEON_CREATE_PIXMAP_TILING_MICRO;
+ }
if (info->ChipFamily >= CHIP_FAMILY_CEDAR)
- need_enlarge = 1;
+ flags |= RADEON_CREATE_PIXMAP_SZBUFFER;
} else
flags = RADEON_CREATE_PIXMAP_TILING_MACRO | RADEON_CREATE_PIXMAP_TILING_MICRO;
+ if (IS_R200_3D || info->ChipFamily == CHIP_FAMILY_RV200 || info->ChipFamily == CHIP_FAMILY_RADEON)
+ flags |= RADEON_CREATE_PIXMAP_DEPTH;
+
break;
case DRI2BufferBackLeft:
case DRI2BufferBackRight:
case DRI2BufferFakeFrontLeft:
case DRI2BufferFakeFrontRight:
- if (info->ChipFamily >= CHIP_FAMILY_R600)
- /* macro is the preferred setting, but the 2D detiling for software
- * fallbacks in mesa still has issues on some configurations
- */
- flags = RADEON_CREATE_PIXMAP_TILING_MICRO;
- else
+ if (info->ChipFamily >= CHIP_FAMILY_R600) {
+ if (info->allowColorTiling2D) {
+ flags = RADEON_CREATE_PIXMAP_TILING_MACRO;
+ } else {
+ flags = RADEON_CREATE_PIXMAP_TILING_MICRO;
+ }
+ } else
flags = RADEON_CREATE_PIXMAP_TILING_MACRO;
break;
default:
@@ -304,39 +331,6 @@ radeon_dri2_create_buffer(DrawablePtr drawable,
if (flags & RADEON_CREATE_PIXMAP_TILING_MACRO)
tiling |= RADEON_TILING_MACRO;
- if (need_enlarge) {
- /* evergreen uses separate allocations for depth and stencil
- * so we make an extra large depth buffer to cover stencil
- * as well.
- */
- int depth = (format != 0) ? format : drawable->depth;
- unsigned aligned_width = drawable->width;
- unsigned width_align = drmmode_get_pitch_align(pScrn, drawable->depth / 8, tiling);
- unsigned aligned_height;
- unsigned height_align = drmmode_get_height_align(pScrn, tiling);
- unsigned base_align = drmmode_get_base_align(pScrn, drawable->depth / 8, tiling);
- unsigned pitch_bytes;
- unsigned size;
-
- if (aligned_width == front_width)
- aligned_width = pScrn->virtualX;
- aligned_width = RADEON_ALIGN(aligned_width, width_align);
- pitch_bytes = aligned_width * (depth / 8);
- aligned_height = RADEON_ALIGN(drawable->height, height_align);
- size = pitch_bytes * aligned_height;
- size = RADEON_ALIGN(size, base_align);
- /* add additional size for stencil */
- size += aligned_width * aligned_height;
- aligned_height = RADEON_ALIGN(size / pitch_bytes, height_align);
-
- pixmap = (*pScreen->CreatePixmap)(pScreen,
- aligned_width,
- aligned_height,
- (format != 0)?format:drawable->depth,
- flags);
-
- } else {
- unsigned aligned_width = drawable->width;
if (aligned_width == front_width)
aligned_width = pScrn->virtualX;
@@ -346,7 +340,6 @@ radeon_dri2_create_buffer(DrawablePtr drawable,
drawable->height,
(format != 0)?format:drawable->depth,
flags);
- }
}
if (!pixmap)
@@ -529,11 +522,11 @@ typedef struct _DRI2FrameEvent {
Bool valid;
- struct list link;
+ struct xorg_list link;
} DRI2FrameEventRec, *DRI2FrameEventPtr;
typedef struct _DRI2ClientEvents {
- struct list reference_list;
+ struct xorg_list reference_list;
} DRI2ClientEventsRec, *DRI2ClientEventsPtr;
#if HAS_DEVPRIVATEKEYREC
@@ -552,7 +545,7 @@ DevPrivateKey DRI2ClientEventsPrivateKey = &DRI2ClientEventsPrivateKeyIndex;
dixLookupPrivate(&(pClient)->devPrivates, DRI2ClientEventsPrivateKey))
static int
-ListAddDRI2ClientEvents(ClientPtr client, struct list *entry)
+ListAddDRI2ClientEvents(ClientPtr client, struct xorg_list *entry)
{
DRI2ClientEventsPtr pClientPriv;
pClientPriv = GetDRI2ClientEvents(client);
@@ -561,12 +554,12 @@ ListAddDRI2ClientEvents(ClientPtr client, struct list *entry)
return BadAlloc;
}
- list_add(entry, &pClientPriv->reference_list);
+ xorg_list_add(entry, &pClientPriv->reference_list);
return 0;
}
static void
-ListDelDRI2ClientEvents(ClientPtr client, struct list *entry)
+ListDelDRI2ClientEvents(ClientPtr client, struct xorg_list *entry)
{
DRI2ClientEventsPtr pClientPriv;
pClientPriv = GetDRI2ClientEvents(client);
@@ -574,7 +567,23 @@ ListDelDRI2ClientEvents(ClientPtr client, struct list *entry)
if (!pClientPriv) {
return;
}
- list_del(entry);
+ xorg_list_del(entry);
+}
+
+static void
+radeon_dri2_ref_buffer(BufferPtr buffer)
+{
+ struct dri2_buffer_priv *private = buffer->driverPrivate;
+ private->refcnt++;
+}
+
+static void
+radeon_dri2_unref_buffer(BufferPtr buffer)
+{
+ if (buffer) {
+ struct dri2_buffer_priv *private = buffer->driverPrivate;
+ radeon_dri2_destroy_buffer(&(private->pixmap->drawable), buffer);
+ }
}
static void
@@ -588,7 +597,7 @@ radeon_dri2_client_state_changed(CallbackListPtr *ClientStateCallback, pointer d
switch (pClient->clientState) {
case ClientStateInitial:
- list_init(&pClientEventsPriv->reference_list);
+ xorg_list_init(&pClientEventsPriv->reference_list);
break;
case ClientStateRunning:
break;
@@ -596,8 +605,10 @@ radeon_dri2_client_state_changed(CallbackListPtr *ClientStateCallback, pointer d
case ClientStateRetained:
case ClientStateGone:
if (pClientEventsPriv) {
- list_for_each_entry(ref, &pClientEventsPriv->reference_list, link) {
+ xorg_list_for_each_entry(ref, &pClientEventsPriv->reference_list, link) {
ref->valid = FALSE;
+ radeon_dri2_unref_buffer(ref->front);
+ radeon_dri2_unref_buffer(ref->back);
}
}
break;
@@ -606,22 +617,6 @@ radeon_dri2_client_state_changed(CallbackListPtr *ClientStateCallback, pointer d
}
}
-static void
-radeon_dri2_ref_buffer(BufferPtr buffer)
-{
- struct dri2_buffer_priv *private = buffer->driverPrivate;
- private->refcnt++;
-}
-
-static void
-radeon_dri2_unref_buffer(BufferPtr buffer)
-{
- if (buffer) {
- struct dri2_buffer_priv *private = buffer->driverPrivate;
- radeon_dri2_destroy_buffer(&(private->pixmap->drawable), buffer);
- }
-}
-
static int radeon_dri2_drawable_crtc(DrawablePtr pDraw)
{
ScreenPtr pScreen = pDraw->pScreen;
@@ -743,6 +738,16 @@ can_exchange(ScrnInfoPtr pScrn, DrawablePtr draw,
return TRUE;
}
+static Bool
+can_flip(ScrnInfoPtr pScrn, DrawablePtr draw,
+ DRI2BufferPtr front, DRI2BufferPtr back)
+{
+ return draw->type == DRAWABLE_WINDOW &&
+ RADEONPTR(pScrn)->allowPageFlip &&
+ DRI2CanFlip(draw) &&
+ can_exchange(pScrn, draw, front, back);
+}
+
static void
radeon_dri2_exchange_buffers(DrawablePtr draw, DRI2BufferPtr front, DRI2BufferPtr back)
{
@@ -782,7 +787,6 @@ void radeon_dri2_frame_event_handler(unsigned int frame, unsigned int tv_sec,
unsigned int tv_usec, void *event_data)
{
DRI2FrameEventPtr event = event_data;
- RADEONInfoPtr info;
DrawablePtr drawable;
ScreenPtr screen;
ScrnInfoPtr scrn;
@@ -801,13 +805,10 @@ void radeon_dri2_frame_event_handler(unsigned int frame, unsigned int tv_sec,
screen = drawable->pScreen;
scrn = xf86Screens[screen->myNum];
- info = RADEONPTR(scrn);
switch (event->type) {
case DRI2_FLIP:
- if (info->allowPageFlip &&
- DRI2CanFlip(drawable) &&
- can_exchange(scrn, drawable, event->front, event->back) &&
+ if (can_flip(scrn, drawable, event->front, event->back) &&
radeon_dri2_schedule_flip(scrn,
event->client,
drawable,
@@ -850,10 +851,11 @@ void radeon_dri2_frame_event_handler(unsigned int frame, unsigned int tv_sec,
}
cleanup:
- radeon_dri2_unref_buffer(event->front);
- radeon_dri2_unref_buffer(event->back);
- if (event->valid)
+ if (event->valid) {
+ radeon_dri2_unref_buffer(event->front);
+ radeon_dri2_unref_buffer(event->back);
ListDelDRI2ClientEvents(event->client, &event->link);
+ }
free(event);
}
@@ -1182,9 +1184,7 @@ static int radeon_dri2_schedule_swap(ClientPtr client, DrawablePtr draw,
current_msc = vbl.reply.sequence;
/* Flips need to be submitted one frame before */
- if (info->allowPageFlip &&
- DRI2CanFlip(draw) &&
- can_exchange(scrn, draw, front, back)) {
+ if (can_flip(scrn, draw, front, back)) {
swap_type = DRI2_FLIP;
flip = 1;
}
diff --git a/driver/xf86-video-ati/src/radeon_driver.c b/driver/xf86-video-ati/src/radeon_driver.c
index 293897a9e..2f22fe375 100644
--- a/driver/xf86-video-ati/src/radeon_driver.c
+++ b/driver/xf86-video-ati/src/radeon_driver.c
@@ -3023,9 +3023,11 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
}
info->PciInfo = xf86GetPciInfoForEntity(info->pEnt->index);
+#ifndef XSERVER_LIBPCIACCESS
info->PciTag = pciTag(PCI_DEV_BUS(info->PciInfo),
PCI_DEV_DEV(info->PciInfo),
PCI_DEV_FUNC(info->PciInfo));
+#endif
info->MMIOAddr = PCI_REGION_BASE(info->PciInfo, 2, REGION_MEM) & ~0xffULL;
info->MMIOSize = PCI_REGION_SIZE(info->PciInfo, 2);
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "TOTO SAYS %016llx\n",
@@ -3129,8 +3131,10 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
} else
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "VGAAccess option set to FALSE,"
" VGA module load skipped\n");
- if (info->VGAAccess)
+ if (info->VGAAccess) {
+ vgaHWSetStdFuncs(VGAHWPTR(pScrn));
vgaHWGetIOBase(VGAHWPTR(pScrn));
+ }
#endif
@@ -4473,22 +4477,17 @@ static void RADEONSaveMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
}
/* Read palette data */
-static void RADEONSavePalette(ScrnInfoPtr pScrn, RADEONSavePtr save)
+static void RADEONSavePalette(ScrnInfoPtr pScrn, int palID, RADEONSavePtr save)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
int i;
- PAL_SELECT(1);
+ PAL_SELECT(palID);
INPAL_START(0);
- for (i = 0; i < 256; i++) {
- save->palette2[i] = INREG(RADEON_PALETTE_30_DATA);
- }
- PAL_SELECT(0);
- INPAL_START(0);
for (i = 0; i < 256; i++) {
- save->palette[i] = INREG(RADEON_PALETTE_30_DATA);
+ save->palette[palID][i] = INREG(RADEON_PALETTE_30_DATA);
}
}
@@ -4498,16 +4497,21 @@ static void RADEONRestorePalette(ScrnInfoPtr pScrn, RADEONSavePtr restore)
unsigned char *RADEONMMIO = info->MMIO;
int i;
- PAL_SELECT(1);
- OUTPAL_START(0);
- for (i = 0; i < 256; i++) {
- OUTREG(RADEON_PALETTE_30_DATA, restore->palette2[i]);
+ if (restore->palette_saved[1]) {
+ ErrorF("Restore Palette 2\n");
+ PAL_SELECT(1);
+ OUTPAL_START(0);
+ for (i = 0; i < 256; i++) {
+ OUTREG(RADEON_PALETTE_30_DATA, restore->palette[1][i]);
+ }
}
-
- PAL_SELECT(0);
- OUTPAL_START(0);
- for (i = 0; i < 256; i++) {
- OUTREG(RADEON_PALETTE_30_DATA, restore->palette[i]);
+ if (restore->palette_saved[0]) {
+ ErrorF("Restore Palette 1\n");
+ PAL_SELECT(0);
+ OUTPAL_START(0);
+ for (i = 0; i < 256; i++) {
+ OUTREG(RADEON_PALETTE_30_DATA, restore->palette[0][i]);
+ }
}
}
@@ -5733,6 +5737,20 @@ RADEONSaveBIOSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
}
}
+void radeon_save_palette_on_demand(ScrnInfoPtr pScrn, int palID)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ RADEONSavePtr save = info->SavedReg;
+
+ if (save->palette_saved[palID] == TRUE)
+ return;
+
+ if (!IS_AVIVO_VARIANT)
+ RADEONSavePalette(pScrn, palID, save);
+
+ save->palette_saved[palID] = TRUE;
+}
+
/* Save everything needed to restore the original VC state */
static void RADEONSave(ScrnInfoPtr pScrn)
{
@@ -5756,12 +5774,9 @@ static void RADEONSave(ScrnInfoPtr pScrn)
* setup in the card at all !!
*/
vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_MODE); /* Save mode only */
-# elif defined(__linux__)
+# else
/* Save only mode * & fonts */
vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_MODE | VGA_SR_FONTS );
-# else
- /* Save mode * & fonts & cmap */
- vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_ALL);
# endif
vgaHWLock(hwp);
}
@@ -5786,7 +5801,7 @@ static void RADEONSave(ScrnInfoPtr pScrn)
RADEONSaveCrtcRegisters(pScrn, save);
RADEONSaveFPRegisters(pScrn, save);
RADEONSaveDACRegisters(pScrn, save);
- RADEONSavePalette(pScrn, save);
+ /* Palette saving is done on demand now */
if (pRADEONEnt->HasCRTC2) {
RADEONSaveCrtc2Registers(pScrn, save);
@@ -5840,6 +5855,7 @@ static void RADEONRestore(ScrnInfoPtr pScrn)
RADEONRestoreMemMapRegisters(pScrn, restore);
RADEONRestoreCommonRegisters(pScrn, restore);
+ RADEONRestorePalette(pScrn, restore);
if (pRADEONEnt->HasCRTC2) {
RADEONRestoreCrtc2Registers(pScrn, restore);
RADEONRestorePLL2Registers(pScrn, restore);
@@ -5869,7 +5885,7 @@ static void RADEONRestore(ScrnInfoPtr pScrn)
* corrupted. This hack solves the problem 99% of the time. A
* correct fix is being worked on.
*/
- usleep(100000);
+ usleep(1000000);
#endif
if (info->ChipFamily < CHIP_FAMILY_R600)
@@ -5879,12 +5895,12 @@ static void RADEONRestore(ScrnInfoPtr pScrn)
if (pRADEONEnt->HasCRTC2 && !info->IsSecondary) {
if (info->crtc2_on && xf86_config->num_crtc > 1) {
crtc = xf86_config->crtc[1];
- crtc->funcs->dpms(crtc, DPMSModeOn);
+ radeon_do_crtc_dpms(crtc, DPMSModeOn);
}
}
if (info->crtc_on) {
crtc = xf86_config->crtc[0];
- crtc->funcs->dpms(crtc, DPMSModeOn);
+ radeon_do_crtc_dpms(crtc, DPMSModeOn);
}
#ifdef WITH_VGAHW
@@ -5896,10 +5912,8 @@ static void RADEONRestore(ScrnInfoPtr pScrn)
* write VGA fonts, will find a better solution in the future
*/
vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE );
-# elif defined(__linux__)
- vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE | VGA_SR_FONTS );
# else
- vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_ALL );
+ vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE | VGA_SR_FONTS );
# endif
vgaHWLock(hwp);
}
@@ -5913,7 +5927,6 @@ static void RADEONRestore(ScrnInfoPtr pScrn)
else if (IS_AVIVO_VARIANT)
avivo_restore_vga_regs(pScrn, restore);
else {
- RADEONRestorePalette(pScrn, restore);
RADEONRestoreDACRegisters(pScrn, restore);
}
#if 0
diff --git a/driver/xf86-video-ati/src/radeon_drm.h b/driver/xf86-video-ati/src/radeon_drm.h
index 49a5f81a5..042e82221 100644
--- a/driver/xf86-video-ati/src/radeon_drm.h
+++ b/driver/xf86-video-ati/src/radeon_drm.h
@@ -800,12 +800,23 @@ struct drm_radeon_gem_create {
uint32_t flags;
};
-#define RADEON_TILING_MACRO 0x1
-#define RADEON_TILING_MICRO 0x2
-#define RADEON_TILING_SWAP_16BIT 0x4
-#define RADEON_TILING_SWAP_32BIT 0x8
-#define RADEON_TILING_SURFACE 0x10 /* this object requires a surface
- * when mapped - i.e. front buffer */
+#define RADEON_TILING_MACRO 0x1
+#define RADEON_TILING_MICRO 0x2
+#define RADEON_TILING_SWAP_16BIT 0x4
+#define RADEON_TILING_SWAP_32BIT 0x8
+/* this object requires a surface when mapped - i.e. front buffer */
+#define RADEON_TILING_SURFACE 0x10
+#define RADEON_TILING_MICRO_SQUARE 0x20
+#define RADEON_TILING_EG_BANKW_SHIFT 8
+#define RADEON_TILING_EG_BANKW_MASK 0xf
+#define RADEON_TILING_EG_BANKH_SHIFT 12
+#define RADEON_TILING_EG_BANKH_MASK 0xf
+#define RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT 16
+#define RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK 0xf
+#define RADEON_TILING_EG_TILE_SPLIT_SHIFT 24
+#define RADEON_TILING_EG_TILE_SPLIT_MASK 0xf
+#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT 28
+#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf
struct drm_radeon_gem_set_tiling {
uint32_t handle;
diff --git a/driver/xf86-video-ati/src/radeon_exa.c b/driver/xf86-video-ati/src/radeon_exa.c
index f3daec045..99a58069e 100644
--- a/driver/xf86-video-ati/src/radeon_exa.c
+++ b/driver/xf86-video-ati/src/radeon_exa.c
@@ -454,9 +454,12 @@ void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height,
RADEONInfoPtr info = RADEONPTR(pScrn);
struct radeon_exa_pixmap_priv *new_priv;
int pitch, base_align;
- uint32_t size;
+ uint32_t size, heighta;
uint32_t tiling = 0;
int cpp = bitsPerPixel / 8;
+#ifdef XF86DRM_MODE
+ struct radeon_surface surface;
+#endif
#ifdef EXA_MIXED_PIXMAPS
if (info->accel_state->exa->flags & EXA_MIXED_PIXMAPS) {
@@ -473,6 +476,9 @@ void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height,
if (usage_hint & RADEON_CREATE_PIXMAP_TILING_MICRO)
tiling |= RADEON_TILING_MICRO;
}
+ if (usage_hint & RADEON_CREATE_PIXMAP_DEPTH)
+ tiling |= RADEON_TILING_MACRO | RADEON_TILING_MICRO;
+
}
/* Small pixmaps must not be macrotiled on R300, hw cannot sample them
@@ -485,17 +491,78 @@ void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height,
tiling &= ~RADEON_TILING_MACRO;
}
- height = RADEON_ALIGN(height, drmmode_get_height_align(pScrn, tiling));
+ heighta = RADEON_ALIGN(height, drmmode_get_height_align(pScrn, tiling));
pitch = RADEON_ALIGN(width, drmmode_get_pitch_align(pScrn, cpp, tiling)) * cpp;
base_align = drmmode_get_base_align(pScrn, cpp, tiling);
- size = RADEON_ALIGN(height * pitch, RADEON_GPU_PAGE_SIZE);
+ size = RADEON_ALIGN(heighta * pitch, RADEON_GPU_PAGE_SIZE);
+ memset(&surface, 0, sizeof(struct radeon_surface));
+
+#ifdef XF86DRM_MODE
+ if (info->ChipFamily >= CHIP_FAMILY_R600 && info->surf_man) {
+ if (width) {
+ surface.npix_x = width;
+ /* need to align height to 8 for old kernel */
+ surface.npix_y = RADEON_ALIGN(height, 8);
+ surface.npix_z = 1;
+ surface.blk_w = 1;
+ surface.blk_h = 1;
+ surface.blk_d = 1;
+ surface.array_size = 1;
+ surface.last_level = 0;
+ surface.bpe = cpp;
+ surface.nsamples = 1;
+ surface.flags = RADEON_SURF_SCANOUT;
+ surface.flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
+ surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE);
+ if ((tiling & RADEON_TILING_MICRO)) {
+ surface.flags = RADEON_SURF_CLR(surface.flags, MODE);
+ surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
+ }
+ if ((tiling & RADEON_TILING_MACRO)) {
+ surface.flags = RADEON_SURF_CLR(surface.flags, MODE);
+ surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
+ }
+ if (usage_hint & RADEON_CREATE_PIXMAP_SZBUFFER) {
+ surface.flags |= RADEON_SURF_ZBUFFER;
+ surface.flags |= RADEON_SURF_SBUFFER;
+ }
+ if (radeon_surface_best(info->surf_man, &surface)) {
+ return NULL;
+ }
+ if (radeon_surface_init(info->surf_man, &surface)) {
+ return NULL;
+ }
+ size = surface.bo_size;
+ base_align = surface.bo_alignment;
+ pitch = surface.level[0].pitch_bytes;
+ tiling = 0;
+ switch (surface.level[0].mode) {
+ case RADEON_SURF_MODE_2D:
+ tiling |= RADEON_TILING_MACRO;
+ tiling |= surface.bankw << RADEON_TILING_EG_BANKW_SHIFT;
+ tiling |= surface.bankh << RADEON_TILING_EG_BANKH_SHIFT;
+ tiling |= surface.mtilea << RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT;
+ tiling |= eg_tile_split(surface.tile_split) << RADEON_TILING_EG_TILE_SPLIT_SHIFT;
+ tiling |= eg_tile_split(surface.stencil_tile_split) << RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT;
+ break;
+ case RADEON_SURF_MODE_1D:
+ tiling |= RADEON_TILING_MICRO;
+ break;
+ default:
+ break;
+ }
+ }
+ }
+#endif
new_priv = calloc(1, sizeof(struct radeon_exa_pixmap_priv));
- if (!new_priv)
+ if (!new_priv) {
return NULL;
+ }
- if (size == 0)
+ if (size == 0) {
return new_priv;
+ }
*new_pitch = pitch;
@@ -510,6 +577,7 @@ void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height,
if (tiling && !radeon_bo_set_tiling(new_priv->bo, tiling, *new_pitch))
new_priv->tiling_flags = tiling;
+ new_priv->surface = surface;
return new_priv;
}
@@ -532,6 +600,15 @@ struct radeon_bo *radeon_get_pixmap_bo(PixmapPtr pPix)
return driver_priv->bo;
}
+#if defined(XF86DRM_MODE)
+struct radeon_surface *radeon_get_pixmap_surface(PixmapPtr pPix)
+{
+ struct radeon_exa_pixmap_priv *driver_priv;
+ driver_priv = exaGetPixmapDriverPrivate(pPix);
+ return &driver_priv->surface;
+}
+#endif
+
uint32_t radeon_get_pixmap_tiling(PixmapPtr pPix)
{
struct radeon_exa_pixmap_priv *driver_priv;
diff --git a/driver/xf86-video-ati/src/radeon_kms.c b/driver/xf86-video-ati/src/radeon_kms.c
index 32065fb96..dda25e900 100644
--- a/driver/xf86-video-ati/src/radeon_kms.c
+++ b/driver/xf86-video-ati/src/radeon_kms.c
@@ -62,6 +62,7 @@ const OptionInfoRec RADEONOptions_KMS[] = {
{ OPTION_ACCEL_DFS, "AccelDFS", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_IGNORE_EDID, "IgnoreEDID", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_COLOR_TILING, "ColorTiling", OPTV_BOOLEAN, {0}, FALSE },
+ { OPTION_COLOR_TILING_2D,"ColorTiling2D", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_RENDER_ACCEL, "RenderAccel", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_SUBPIXEL_ORDER, "SubPixelOrder", OPTV_ANYSTR, {0}, FALSE },
{ OPTION_ACCELMETHOD, "AccelMethod", OPTV_STRING, {0}, FALSE },
@@ -158,6 +159,7 @@ static Bool RADEONCreateScreenResources_KMS(ScreenPtr pScreen)
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
RADEONInfoPtr info = RADEONPTR(pScrn);
PixmapPtr pixmap;
+ struct radeon_surface *surface;
pScreen->CreateScreenResources = info->CreateScreenResources;
if (!(*pScreen->CreateScreenResources)(pScreen))
@@ -181,6 +183,10 @@ static Bool RADEONCreateScreenResources_KMS(ScreenPtr pScreen)
if (info->front_bo) {
PixmapPtr pPix = pScreen->GetScreenPixmap(pScreen);
radeon_set_pixmap_bo(pPix, info->front_bo);
+ surface = radeon_get_pixmap_surface(pPix);
+ if (surface) {
+ *surface = info->front_surface;
+ }
}
}
return TRUE;
@@ -429,7 +435,7 @@ static Bool radeon_open_drm_master(ScrnInfoPtr pScrn)
int err;
if (pRADEONEnt->fd) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
" reusing fd for second head\n");
info->dri2.drm_fd = pRADEONEnt->fd;
@@ -674,11 +680,20 @@ Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags)
if (!RADEONPreInitAccel_KMS(pScrn)) goto fail;
+ info->allowColorTiling2D = FALSE;
+
#ifdef EXA_MIXED_PIXMAPS
/* don't enable tiling if accel is not enabled */
if (!info->r600_shadow_fb) {
- Bool colorTilingDefault = info->ChipFamily >= CHIP_FAMILY_R300 &&
- info->ChipFamily <= CHIP_FAMILY_CAYMAN;
+ Bool colorTilingDefault =
+ xorgGetVersion() >= XORG_VERSION_NUMERIC(1,9,4,901,0) &&
+ info->ChipFamily >= CHIP_FAMILY_R300 &&
+ info->ChipFamily <= CHIP_FAMILY_ARUBA;
+
+ /* 2D color tiling */
+ if (info->ChipFamily >= CHIP_FAMILY_R600) {
+ info->allowColorTiling2D = xf86ReturnOptValBool(info->Options, OPTION_COLOR_TILING_2D, FALSE);
+ }
if (info->ChipFamily >= CHIP_FAMILY_R600) {
/* set default group bytes, overridden by kernel info below */
@@ -931,6 +946,7 @@ Bool RADEONScreenInit_KMS(int scrnIndex, ScreenPtr pScreen,
front_ptr = info->FB;
+ info->surf_man = radeon_surface_manager_new(info->dri->drmFD);
if (!info->bufmgr)
info->bufmgr = radeon_bo_manager_gem_ctor(info->dri->drmFD);
if (!info->bufmgr) {
@@ -1120,6 +1136,8 @@ Bool RADEONScreenInit_KMS(int scrnIndex, ScreenPtr pScreen,
if (serverGeneration == 1)
xf86ShowUnusedOptions(pScrn->scrnIndex, pScrn->options);
+ drmmode_init(pScrn, &info->drmmode);
+
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"RADEONScreenInit finished\n");
@@ -1207,6 +1225,7 @@ static Bool radeon_setup_kernel_mem(ScreenPtr pScreen)
int pitch, base_align;
int total_size_bytes = 0;
uint32_t tiling_flags = 0;
+ struct radeon_surface surface;
if (info->accel_state->exa != NULL) {
xf86DrvMsg(pScreen->myNum, X_ERROR, "Memory map already initialized\n");
@@ -1219,14 +1238,67 @@ static Bool radeon_setup_kernel_mem(ScreenPtr pScreen)
}
if (info->allowColorTiling) {
- if (info->ChipFamily >= CHIP_FAMILY_R600)
- tiling_flags |= RADEON_TILING_MICRO;
- else
+ if (info->ChipFamily >= CHIP_FAMILY_R600) {
+ if (info->allowColorTiling2D) {
+ tiling_flags |= RADEON_TILING_MACRO;
+ } else {
+ tiling_flags |= RADEON_TILING_MICRO;
+ }
+ } else
tiling_flags |= RADEON_TILING_MACRO;
}
pitch = RADEON_ALIGN(pScrn->displayWidth, drmmode_get_pitch_align(pScrn, cpp, tiling_flags)) * cpp;
screen_size = RADEON_ALIGN(pScrn->virtualY, drmmode_get_height_align(pScrn, tiling_flags)) * pitch;
base_align = drmmode_get_base_align(pScrn, cpp, tiling_flags);
+ if (info->ChipFamily >= CHIP_FAMILY_R600) {
+ memset(&surface, 0, sizeof(struct radeon_surface));
+ surface.npix_x = pScrn->displayWidth;
+ surface.npix_y = pScrn->virtualY;
+ surface.npix_z = 1;
+ surface.blk_w = 1;
+ surface.blk_h = 1;
+ surface.blk_d = 1;
+ surface.array_size = 1;
+ surface.last_level = 0;
+ surface.bpe = cpp;
+ surface.nsamples = 1;
+ surface.flags = RADEON_SURF_SCANOUT;
+ surface.flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
+ surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
+ if (tiling_flags & RADEON_TILING_MICRO) {
+ surface.flags = RADEON_SURF_CLR(surface.flags, MODE);
+ surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
+ }
+ if (tiling_flags & RADEON_TILING_MACRO) {
+ surface.flags = RADEON_SURF_CLR(surface.flags, MODE);
+ surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
+ }
+ if (radeon_surface_best(info->surf_man, &surface)) {
+ return FALSE;
+ }
+ if (radeon_surface_init(info->surf_man, &surface)) {
+ return FALSE;
+ }
+ pitch = surface.level[0].pitch_bytes;
+ screen_size = surface.bo_size;
+ base_align = surface.bo_alignment;
+ tiling_flags = 0;
+ switch (surface.level[0].mode) {
+ case RADEON_SURF_MODE_2D:
+ tiling_flags |= RADEON_TILING_MACRO;
+ tiling_flags |= surface.bankw << RADEON_TILING_EG_BANKW_SHIFT;
+ tiling_flags |= surface.bankh << RADEON_TILING_EG_BANKH_SHIFT;
+ tiling_flags |= surface.mtilea << RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT;
+ tiling_flags |= eg_tile_split(surface.tile_split) << RADEON_TILING_EG_TILE_SPLIT_SHIFT;
+ break;
+ case RADEON_SURF_MODE_1D:
+ tiling_flags |= RADEON_TILING_MICRO;
+ break;
+ default:
+ break;
+ }
+ info->front_surface = surface;
+ }
{
int cursor_size = 64 * 4 * 64;
int c;
diff --git a/driver/xf86-video-ati/src/radeon_output.c b/driver/xf86-video-ati/src/radeon_output.c
index ccde346ec..5abd60e2d 100644
--- a/driver/xf86-video-ati/src/radeon_output.c
+++ b/driver/xf86-video-ati/src/radeon_output.c
@@ -3002,9 +3002,9 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn)
info->BiosConnector[i].devices |= ATOM_DEVICE_CRT2_SUPPORT;
if (!radeon_add_encoder(pScrn,
radeon_get_encoder_id_from_supported_device(pScrn,
- ATOM_DEVICE_CRT1_SUPPORT,
+ ATOM_DEVICE_CRT2_SUPPORT,
2),
- ATOM_DEVICE_CRT1_SUPPORT))
+ ATOM_DEVICE_CRT2_SUPPORT))
return FALSE;
info->BiosConnector[i].load_detection = FALSE;
break;
diff --git a/driver/xf86-video-ati/src/radeon_pci_chipset_gen.h b/driver/xf86-video-ati/src/radeon_pci_chipset_gen.h
index 549eaca0d..aef8d897d 100644
--- a/driver/xf86-video-ati/src/radeon_pci_chipset_gen.h
+++ b/driver/xf86-video-ati/src/radeon_pci_chipset_gen.h
@@ -53,6 +53,7 @@ PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_RV250_Ld, PCI_CHIP_RV250_Ld, RES_SHARED_VGA },
{ PCI_CHIP_RV250_Lf, PCI_CHIP_RV250_Lf, RES_SHARED_VGA },
{ PCI_CHIP_RV250_Lg, PCI_CHIP_RV250_Lg, RES_SHARED_VGA },
+ { PCI_CHIP_RV280_4C6E, PCI_CHIP_RV280_4C6E, RES_SHARED_VGA },
{ PCI_CHIP_R300_ND, PCI_CHIP_R300_ND, RES_SHARED_VGA },
{ PCI_CHIP_R300_NE, PCI_CHIP_R300_NE, RES_SHARED_VGA },
{ PCI_CHIP_R300_NF, PCI_CHIP_R300_NF, RES_SHARED_VGA },
@@ -380,6 +381,8 @@ PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_SUMO_9647, PCI_CHIP_SUMO_9647, RES_SHARED_VGA },
{ PCI_CHIP_SUMO_9648, PCI_CHIP_SUMO_9648, RES_SHARED_VGA },
{ PCI_CHIP_SUMO_964A, PCI_CHIP_SUMO_964A, RES_SHARED_VGA },
+ { PCI_CHIP_SUMO_964B, PCI_CHIP_SUMO_964B, RES_SHARED_VGA },
+ { PCI_CHIP_SUMO_964C, PCI_CHIP_SUMO_964C, RES_SHARED_VGA },
{ PCI_CHIP_SUMO_964E, PCI_CHIP_SUMO_964E, RES_SHARED_VGA },
{ PCI_CHIP_SUMO_964F, PCI_CHIP_SUMO_964F, RES_SHARED_VGA },
{ PCI_CHIP_RS880_9710, PCI_CHIP_RS880_9710, RES_SHARED_VGA },
@@ -394,6 +397,8 @@ PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_PALM_9805, PCI_CHIP_PALM_9805, RES_SHARED_VGA },
{ PCI_CHIP_PALM_9806, PCI_CHIP_PALM_9806, RES_SHARED_VGA },
{ PCI_CHIP_PALM_9807, PCI_CHIP_PALM_9807, RES_SHARED_VGA },
+ { PCI_CHIP_PALM_9808, PCI_CHIP_PALM_9808, RES_SHARED_VGA },
+ { PCI_CHIP_PALM_9809, PCI_CHIP_PALM_9809, RES_SHARED_VGA },
{ PCI_CHIP_CYPRESS_6880, PCI_CHIP_CYPRESS_6880, RES_SHARED_VGA },
{ PCI_CHIP_CYPRESS_6888, PCI_CHIP_CYPRESS_6888, RES_SHARED_VGA },
{ PCI_CHIP_CYPRESS_6889, PCI_CHIP_CYPRESS_6889, RES_SHARED_VGA },
@@ -435,6 +440,7 @@ PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_CEDAR_68F2, PCI_CHIP_CEDAR_68F2, RES_SHARED_VGA },
{ PCI_CHIP_CEDAR_68F8, PCI_CHIP_CEDAR_68F8, RES_SHARED_VGA },
{ PCI_CHIP_CEDAR_68F9, PCI_CHIP_CEDAR_68F9, RES_SHARED_VGA },
+ { PCI_CHIP_CEDAR_68FA, PCI_CHIP_CEDAR_68FA, RES_SHARED_VGA },
{ PCI_CHIP_CEDAR_68FE, PCI_CHIP_CEDAR_68FE, RES_SHARED_VGA },
{ PCI_CHIP_CAYMAN_6700, PCI_CHIP_CAYMAN_6700, RES_SHARED_VGA },
{ PCI_CHIP_CAYMAN_6701, PCI_CHIP_CAYMAN_6701, RES_SHARED_VGA },
@@ -475,9 +481,20 @@ PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_TURKS_6748, PCI_CHIP_TURKS_6748, RES_SHARED_VGA },
{ PCI_CHIP_TURKS_6749, PCI_CHIP_TURKS_6749, RES_SHARED_VGA },
{ PCI_CHIP_TURKS_6750, PCI_CHIP_TURKS_6750, RES_SHARED_VGA },
+ { PCI_CHIP_TURKS_6751, PCI_CHIP_TURKS_6751, RES_SHARED_VGA },
{ PCI_CHIP_TURKS_6758, PCI_CHIP_TURKS_6758, RES_SHARED_VGA },
{ PCI_CHIP_TURKS_6759, PCI_CHIP_TURKS_6759, RES_SHARED_VGA },
+ { PCI_CHIP_TURKS_675B, PCI_CHIP_TURKS_675B, RES_SHARED_VGA },
+ { PCI_CHIP_TURKS_675D, PCI_CHIP_TURKS_675D, RES_SHARED_VGA },
{ PCI_CHIP_TURKS_675F, PCI_CHIP_TURKS_675F, RES_SHARED_VGA },
+ { PCI_CHIP_TURKS_6840, PCI_CHIP_TURKS_6840, RES_SHARED_VGA },
+ { PCI_CHIP_TURKS_6841, PCI_CHIP_TURKS_6841, RES_SHARED_VGA },
+ { PCI_CHIP_TURKS_6842, PCI_CHIP_TURKS_6842, RES_SHARED_VGA },
+ { PCI_CHIP_TURKS_6843, PCI_CHIP_TURKS_6843, RES_SHARED_VGA },
+ { PCI_CHIP_TURKS_6849, PCI_CHIP_TURKS_6849, RES_SHARED_VGA },
+ { PCI_CHIP_TURKS_6850, PCI_CHIP_TURKS_6850, RES_SHARED_VGA },
+ { PCI_CHIP_TURKS_6858, PCI_CHIP_TURKS_6858, RES_SHARED_VGA },
+ { PCI_CHIP_TURKS_6859, PCI_CHIP_TURKS_6859, RES_SHARED_VGA },
{ PCI_CHIP_CAICOS_6760, PCI_CHIP_CAICOS_6760, RES_SHARED_VGA },
{ PCI_CHIP_CAICOS_6761, PCI_CHIP_CAICOS_6761, RES_SHARED_VGA },
{ PCI_CHIP_CAICOS_6762, PCI_CHIP_CAICOS_6762, RES_SHARED_VGA },
@@ -488,7 +505,16 @@ PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_CAICOS_6767, PCI_CHIP_CAICOS_6767, RES_SHARED_VGA },
{ PCI_CHIP_CAICOS_6768, PCI_CHIP_CAICOS_6768, RES_SHARED_VGA },
{ PCI_CHIP_CAICOS_6770, PCI_CHIP_CAICOS_6770, RES_SHARED_VGA },
+ { PCI_CHIP_CAICOS_6772, PCI_CHIP_CAICOS_6772, RES_SHARED_VGA },
{ PCI_CHIP_CAICOS_6778, PCI_CHIP_CAICOS_6778, RES_SHARED_VGA },
{ PCI_CHIP_CAICOS_6779, PCI_CHIP_CAICOS_6779, RES_SHARED_VGA },
+ { PCI_CHIP_CAICOS_677B, PCI_CHIP_CAICOS_677B, RES_SHARED_VGA },
+ { PCI_CHIP_ARUBA_9900, PCI_CHIP_ARUBA_9900, RES_SHARED_VGA },
+ { PCI_CHIP_ARUBA_9901, PCI_CHIP_ARUBA_9901, RES_SHARED_VGA },
+ { PCI_CHIP_ARUBA_9903, PCI_CHIP_ARUBA_9903, RES_SHARED_VGA },
+ { PCI_CHIP_ARUBA_9904, PCI_CHIP_ARUBA_9904, RES_SHARED_VGA },
+ { PCI_CHIP_ARUBA_990f, PCI_CHIP_ARUBA_990f, RES_SHARED_VGA },
+ { PCI_CHIP_ARUBA_9990, PCI_CHIP_ARUBA_9990, RES_SHARED_VGA },
+ { PCI_CHIP_ARUBA_9991, PCI_CHIP_ARUBA_9991, RES_SHARED_VGA },
{ -1, -1, RES_UNDEFINED }
};
diff --git a/driver/xf86-video-ati/src/radeon_pci_device_match_gen.h b/driver/xf86-video-ati/src/radeon_pci_device_match_gen.h
index 0739f81d1..681a6b8a5 100644
--- a/driver/xf86-video-ati/src/radeon_pci_device_match_gen.h
+++ b/driver/xf86-video-ati/src/radeon_pci_device_match_gen.h
@@ -53,6 +53,7 @@ static const struct pci_id_match radeon_device_match[] = {
ATI_DEVICE_MATCH( PCI_CHIP_RV250_Ld, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV250_Lf, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV250_Lg, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV280_4C6E, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_R300_ND, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_R300_NE, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_R300_NF, 0 ),
@@ -380,6 +381,8 @@ static const struct pci_id_match radeon_device_match[] = {
ATI_DEVICE_MATCH( PCI_CHIP_SUMO_9647, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_SUMO_9648, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_SUMO_964A, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_SUMO_964B, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_SUMO_964C, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_SUMO_964E, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_SUMO_964F, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RS880_9710, 0 ),
@@ -394,6 +397,8 @@ static const struct pci_id_match radeon_device_match[] = {
ATI_DEVICE_MATCH( PCI_CHIP_PALM_9805, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_PALM_9806, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_PALM_9807, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_PALM_9808, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_PALM_9809, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_6880, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_6888, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_6889, 0 ),
@@ -435,6 +440,7 @@ static const struct pci_id_match radeon_device_match[] = {
ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68F2, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68F8, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68F9, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68FA, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68FE, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_6700, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_6701, 0 ),
@@ -475,9 +481,20 @@ static const struct pci_id_match radeon_device_match[] = {
ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6748, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6749, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6750, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6751, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6758, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6759, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_TURKS_675B, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_TURKS_675D, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_TURKS_675F, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6840, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6841, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6842, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6843, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6849, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6850, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6858, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_TURKS_6859, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6760, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6761, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6762, 0 ),
@@ -488,7 +505,16 @@ static const struct pci_id_match radeon_device_match[] = {
ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6767, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6768, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6770, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6772, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6778, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_6779, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CAICOS_677B, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9900, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9901, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9903, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9904, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_990f, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9990, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_ARUBA_9991, 0 ),
{ 0, 0, 0 }
};
diff --git a/driver/xf86-video-ati/src/radeon_probe.h b/driver/xf86-video-ati/src/radeon_probe.h
index 94f6d7d15..66905022f 100644
--- a/driver/xf86-video-ati/src/radeon_probe.h
+++ b/driver/xf86-video-ati/src/radeon_probe.h
@@ -108,6 +108,7 @@ typedef enum {
CHIP_FAMILY_TURKS,
CHIP_FAMILY_CAICOS,
CHIP_FAMILY_CAYMAN,
+ CHIP_FAMILY_ARUBA,
CHIP_FAMILY_LAST
} RADEONChipFamily;
@@ -663,8 +664,8 @@ typedef struct {
/* Pallet */
Bool palette_valid;
- uint32_t palette[256];
- uint32_t palette2[256];
+ Bool palette_saved[2];
+ uint32_t palette[2][256];
uint32_t disp2_req_cntl1;
uint32_t disp2_req_cntl2;
@@ -750,7 +751,7 @@ typedef struct
void *FB; /* Map of FB region */
int FB_cnt; /* Map of FB region refcount */
int fd; /* for sharing across zaphod heads */
- Bool fd_wakeup_registered; /* fd has already been registered for wakeup handling */
+ unsigned long fd_wakeup_registered; /* server generation for which fd has been registered for wakeup handling */
int dri2_info_cnt;
} RADEONEntRec, *RADEONEntPtr;
diff --git a/driver/xf86-video-ati/src/radeon_textured_video.c b/driver/xf86-video-ati/src/radeon_textured_video.c
index e49575da9..ff2bb9f98 100644
--- a/driver/xf86-video-ati/src/radeon_textured_video.c
+++ b/driver/xf86-video-ati/src/radeon_textured_video.c
@@ -66,6 +66,9 @@ R600CopyToVRAM(ScrnInfoPtr pScrn,
#define IMAGE_MAX_WIDTH_R600 8192
#define IMAGE_MAX_HEIGHT_R600 8192
+#define IMAGE_MAX_WIDTH_EG 16384
+#define IMAGE_MAX_HEIGHT_EG 16384
+
static Bool
RADEONTilingEnabled(ScrnInfoPtr pScrn, PixmapPtr pPix)
{
@@ -554,6 +557,16 @@ static XF86VideoEncodingRec DummyEncodingR600[1] =
}
};
+static XF86VideoEncodingRec DummyEncodingEG[1] =
+{
+ {
+ 0,
+ "XV_IMAGE",
+ IMAGE_MAX_WIDTH_EG, IMAGE_MAX_HEIGHT_EG,
+ {1, 1}
+ }
+};
+
#define NUM_FORMATS 3
static XF86VideoFormatRec Formats[NUM_FORMATS] =
@@ -824,7 +837,9 @@ RADEONSetupImageTexturedVideo(ScreenPtr pScreen)
adapt->flags = 0;
adapt->name = "Radeon Textured Video";
adapt->nEncodings = 1;
- if (IS_R600_3D)
+ if (IS_EVERGREEN_3D)
+ adapt->pEncodings = DummyEncodingEG;
+ else if (IS_R600_3D)
adapt->pEncodings = DummyEncodingR600;
else if (IS_R500_3D)
adapt->pEncodings = DummyEncodingR500;
diff --git a/driver/xf86-video-ati/src/radeon_textured_videofuncs.c b/driver/xf86-video-ati/src/radeon_textured_videofuncs.c
index 84aba6f82..71195530c 100644
--- a/driver/xf86-video-ati/src/radeon_textured_videofuncs.c
+++ b/driver/xf86-video-ati/src/radeon_textured_videofuncs.c
@@ -121,6 +121,8 @@ FUNC_NAME(RADEONPrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
return FALSE;
}
}
+#else
+ (void)src_bo;
#endif
pixel_shift = pPixmap->drawable.bitsPerPixel >> 4;
@@ -435,7 +437,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
((loop_boxes * 3) << RADEON_CP_VC_CNTL_NUM_SHIFT));
while (loop_boxes--) {
- int srcX, srcY, srcw, srch;
+ float srcX, srcY, srcw, srch;
int dstX, dstY, dstw, dsth;
dstX = pBox->x1 + dstxoff;
dstY = pBox->y1 + dstyoff;
@@ -444,13 +446,13 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
srcX = pPriv->src_x;
srcX += ((pBox->x1 - pPriv->drw_x) *
- pPriv->src_w) / pPriv->dst_w;
+ pPriv->src_w) / (float)pPriv->dst_w;
srcY = pPriv->src_y;
srcY += ((pBox->y1 - pPriv->drw_y) *
- pPriv->src_h) / pPriv->dst_h;
+ pPriv->src_h) / (float)pPriv->dst_h;
- srcw = (pPriv->src_w * dstw) / pPriv->dst_w;
- srch = (pPriv->src_h * dsth) / pPriv->dst_h;
+ srcw = (pPriv->src_w * dstw) / (float)pPriv->dst_w;
+ srch = (pPriv->src_h * dsth) / (float)pPriv->dst_h;
if (pPriv->is_planar) {
@@ -491,7 +493,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
RADEON_VF_RADEON_MODE |
((nBox * 3) << RADEON_VF_NUM_VERTICES_SHIFT)));
while (nBox--) {
- int srcX, srcY, srcw, srch;
+ float srcX, srcY, srcw, srch;
int dstX, dstY, dstw, dsth;
dstX = pBox->x1 + dstxoff;
dstY = pBox->y1 + dstyoff;
@@ -500,13 +502,13 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
srcX = pPriv->src_x;
srcX += ((pBox->x1 - pPriv->drw_x) *
- pPriv->src_w) / pPriv->dst_w;
+ pPriv->src_w) / (float)pPriv->dst_w;
srcY = pPriv->src_y;
srcY += ((pBox->y1 - pPriv->drw_y) *
- pPriv->src_h) / pPriv->dst_h;
+ pPriv->src_h) / (float)pPriv->dst_h;
- srcw = (pPriv->src_w * dstw) / pPriv->dst_w;
- srch = (pPriv->src_h * dsth) / pPriv->dst_h;
+ srcw = (pPriv->src_w * dstw) / (float)pPriv->dst_w;
+ srch = (pPriv->src_h * dsth) / (float)pPriv->dst_h;
if (pPriv->is_planar) {
@@ -588,6 +590,8 @@ FUNC_NAME(R200PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
return FALSE;
}
}
+#else
+ (void)src_bo;
#endif
pixel_shift = pPixmap->drawable.bitsPerPixel >> 4;
@@ -1066,7 +1070,7 @@ FUNC_NAME(R200DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
((loop_boxes * 3) << RADEON_CP_VC_CNTL_NUM_SHIFT));
while (loop_boxes--) {
- int srcX, srcY, srcw, srch;
+ float srcX, srcY, srcw, srch;
int dstX, dstY, dstw, dsth;
dstX = pBox->x1 + dstxoff;
dstY = pBox->y1 + dstyoff;
@@ -1075,13 +1079,13 @@ FUNC_NAME(R200DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
srcX = pPriv->src_x;
srcX += ((pBox->x1 - pPriv->drw_x) *
- pPriv->src_w) / pPriv->dst_w;
+ pPriv->src_w) / (float)pPriv->dst_w;
srcY = pPriv->src_y;
srcY += ((pBox->y1 - pPriv->drw_y) *
- pPriv->src_h) / pPriv->dst_h;
+ pPriv->src_h) / (float)pPriv->dst_h;
- srcw = (pPriv->src_w * dstw) / pPriv->dst_w;
- srch = (pPriv->src_h * dsth) / pPriv->dst_h;
+ srcw = (pPriv->src_w * dstw) / (float)pPriv->dst_w;
+ srch = (pPriv->src_h * dsth) / (float)pPriv->dst_h;
if (pPriv->is_planar) {
/*
@@ -1120,7 +1124,7 @@ FUNC_NAME(R200DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
RADEON_VF_PRIM_WALK_DATA |
((nBox * 3) << RADEON_VF_NUM_VERTICES_SHIFT)));
while (nBox--) {
- int srcX, srcY, srcw, srch;
+ float srcX, srcY, srcw, srch;
int dstX, dstY, dstw, dsth;
dstX = pBox->x1 + dstxoff;
dstY = pBox->y1 + dstyoff;
@@ -1129,13 +1133,13 @@ FUNC_NAME(R200DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
srcX = pPriv->src_x;
srcX += ((pBox->x1 - pPriv->drw_x) *
- pPriv->src_w) / pPriv->dst_w;
+ pPriv->src_w) / (float)pPriv->dst_w;
srcY = pPriv->src_y;
srcY += ((pBox->y1 - pPriv->drw_y) *
- pPriv->src_h) / pPriv->dst_h;
+ pPriv->src_h) / (float)pPriv->dst_h;
- srcw = (pPriv->src_w * dstw) / pPriv->dst_w;
- srch = (pPriv->src_h * dsth) / pPriv->dst_h;
+ srcw = (pPriv->src_w * dstw) / (float)pPriv->dst_w;
+ srch = (pPriv->src_h * dsth) / (float)pPriv->dst_h;
if (pPriv->is_planar) {
/*
@@ -1205,6 +1209,8 @@ FUNC_NAME(R300PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
return FALSE;
}
}
+#else
+ (void)src_bo;
#endif
pixel_shift = pPixmap->drawable.bitsPerPixel >> 4;
@@ -2493,7 +2499,7 @@ FUNC_NAME(R300DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
*/
while (nBox--) {
- int srcX, srcY, srcw, srch;
+ float srcX, srcY, srcw, srch;
int dstX, dstY, dstw, dsth;
Bool use_quad = FALSE;
#ifdef ACCEL_CP
@@ -2516,13 +2522,13 @@ FUNC_NAME(R300DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
srcX = pPriv->src_x;
srcX += ((pBox->x1 - pPriv->drw_x) *
- pPriv->src_w) / pPriv->dst_w;
+ pPriv->src_w) / (float)pPriv->dst_w;
srcY = pPriv->src_y;
srcY += ((pBox->y1 - pPriv->drw_y) *
- pPriv->src_h) / pPriv->dst_h;
+ pPriv->src_h) / (float)pPriv->dst_h;
- srcw = (pPriv->src_w * dstw) / pPriv->dst_w;
- srch = (pPriv->src_h * dsth) / pPriv->dst_h;
+ srcw = (pPriv->src_w * dstw) / (float)pPriv->dst_w;
+ srch = (pPriv->src_h * dsth) / (float)pPriv->dst_h;
if (IS_R400_3D) {
if ((dstw+dsth) > 4021)
@@ -2687,6 +2693,8 @@ FUNC_NAME(R500PrepareTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
return FALSE;
}
}
+#else
+ (void)src_bo;
#endif
pixel_shift = pPixmap->drawable.bitsPerPixel >> 4;
@@ -4122,7 +4130,7 @@ FUNC_NAME(R500DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
*/
while (nBox--) {
- int srcX, srcY, srcw, srch;
+ float srcX, srcY, srcw, srch;
int dstX, dstY, dstw, dsth;
#ifdef ACCEL_CP
int draw_size = 3 * pPriv->vtx_count + 4 + 2 + 3;
@@ -4144,13 +4152,13 @@ FUNC_NAME(R500DisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
srcX = pPriv->src_x;
srcX += ((pBox->x1 - pPriv->drw_x) *
- pPriv->src_w) / pPriv->dst_w;
+ pPriv->src_w) / (float)pPriv->dst_w;
srcY = pPriv->src_y;
srcY += ((pBox->y1 - pPriv->drw_y) *
- pPriv->src_h) / pPriv->dst_h;
+ pPriv->src_h) / (float)pPriv->dst_h;
- srcw = (pPriv->src_w * dstw) / pPriv->dst_w;
- srch = (pPriv->src_h * dsth) / pPriv->dst_h;
+ srcw = (pPriv->src_w * dstw) / (float)pPriv->dst_w;
+ srch = (pPriv->src_h * dsth) / (float)pPriv->dst_h;
BEGIN_ACCEL(2);
OUT_ACCEL_REG(R300_SC_SCISSOR0, (((dstX) << R300_SCISSOR_X_SHIFT) |
diff --git a/driver/xf86-video-ati/src/radeon_video.c b/driver/xf86-video-ati/src/radeon_video.c
index 834f92460..0e2c1275c 100644
--- a/driver/xf86-video-ati/src/radeon_video.c
+++ b/driver/xf86-video-ati/src/radeon_video.c
@@ -142,7 +142,7 @@ radeon_pick_best_crtc(ScrnInfoPtr pScrn,
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
int coverage, best_coverage, c;
BoxRec box, crtc_box, cover_box;
- RROutputPtr primary_output;
+ RROutputPtr primary_output = NULL;
xf86CrtcPtr best_crtc = NULL, primary_crtc = NULL;
box.x1 = x1;
@@ -152,7 +152,9 @@ radeon_pick_best_crtc(ScrnInfoPtr pScrn,
best_coverage = 0;
/* Prefer the CRTC of the primary output */
- primary_output = RRFirstOutput(pScrn->pScreen);
+ if (dixPrivateKeyRegistered(rrPrivKey)) {
+ primary_output = RRFirstOutput(pScrn->pScreen);
+ }
if (primary_output && primary_output->crtc)
primary_crtc = primary_output->crtc->devPrivate;
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-29 19:49:11 +0000