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authorJonathan Gray <jsg@cvs.openbsd.org>2022-02-24 02:30:08 +0000
committerJonathan Gray <jsg@cvs.openbsd.org>2022-02-24 02:30:08 +0000
commit1d35364040c0ffa99133522fa5ab3bd6131d8bf7 (patch)
tree0ea3d9ca4ad10692c6477168b67e98cb50ea6bd3 /lib/mesa/include
parentb24b5b9049e889ee4eb39b565bcc8d48bd45ab48 (diff)
Merge Mesa 21.3.7
Diffstat (limited to 'lib/mesa/include')
-rw-r--r--lib/mesa/include/CL/cl_d3d10.h2
-rw-r--r--lib/mesa/include/CL/cl_d3d11.h2
-rw-r--r--lib/mesa/include/CL/cl_dx9_media_sharing.h2
-rw-r--r--lib/mesa/include/CL/opencl.h2
-rw-r--r--lib/mesa/include/EGL/egl.h27
-rw-r--r--lib/mesa/include/EGL/eglext.h90
-rw-r--r--lib/mesa/include/EGL/eglplatform.h2
-rw-r--r--lib/mesa/include/GL/internal/dri_interface.h200
-rw-r--r--lib/mesa/include/GLES3/gl3ext.h2
-rw-r--r--lib/mesa/include/android_stub/apex/window.h210
-rw-r--r--lib/mesa/include/drm-uapi/amdgpu_drm.h18
-rw-r--r--lib/mesa/include/drm-uapi/drm.h260
-rw-r--r--lib/mesa/include/drm-uapi/drm_fourcc.h118
-rw-r--r--lib/mesa/include/drm-uapi/drm_mode.h264
-rw-r--r--lib/mesa/include/drm-uapi/i915_drm.h895
-rw-r--r--lib/mesa/include/pci_ids/i810_pci_ids.h4
-rw-r--r--lib/mesa/include/pci_ids/i965_pci_ids.h2
-rw-r--r--lib/mesa/include/vulkan/vk_platform.h2
-rw-r--r--lib/mesa/include/vulkan/vulkan.h7
-rw-r--r--lib/mesa/include/vulkan/vulkan_beta.h649
20 files changed, 2143 insertions, 615 deletions
diff --git a/lib/mesa/include/CL/cl_d3d10.h b/lib/mesa/include/CL/cl_d3d10.h
index 7016da038..509f07992 100644
--- a/lib/mesa/include/CL/cl_d3d10.h
+++ b/lib/mesa/include/CL/cl_d3d10.h
@@ -26,7 +26,7 @@
* MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.
**********************************************************************************/
-/* $Revision: 1.22 $ on $Date: 2021/09/09 09:59:14 $ */
+/* $Revision: 1.23 $ on $Date: 2022/02/24 02:29:48 $ */
#ifndef __OPENCL_CL_D3D10_H
#define __OPENCL_CL_D3D10_H
diff --git a/lib/mesa/include/CL/cl_d3d11.h b/lib/mesa/include/CL/cl_d3d11.h
index 57f46fa79..128bbf03f 100644
--- a/lib/mesa/include/CL/cl_d3d11.h
+++ b/lib/mesa/include/CL/cl_d3d11.h
@@ -26,7 +26,7 @@
* MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.
**********************************************************************************/
-/* $Revision: 1.22 $ on $Date: 2021/09/09 09:59:14 $ */
+/* $Revision: 1.23 $ on $Date: 2022/02/24 02:29:48 $ */
#ifndef __OPENCL_CL_D3D11_H
#define __OPENCL_CL_D3D11_H
diff --git a/lib/mesa/include/CL/cl_dx9_media_sharing.h b/lib/mesa/include/CL/cl_dx9_media_sharing.h
index f860c4471..e34e8c21c 100644
--- a/lib/mesa/include/CL/cl_dx9_media_sharing.h
+++ b/lib/mesa/include/CL/cl_dx9_media_sharing.h
@@ -26,7 +26,7 @@
* MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.
**********************************************************************************/
-/* $Revision: 1.22 $ on $Date: 2021/09/09 09:59:14 $ */
+/* $Revision: 1.23 $ on $Date: 2022/02/24 02:29:48 $ */
#ifndef __OPENCL_CL_DX9_MEDIA_SHARING_H
#define __OPENCL_CL_DX9_MEDIA_SHARING_H
diff --git a/lib/mesa/include/CL/opencl.h b/lib/mesa/include/CL/opencl.h
index 919351b7b..c61094100 100644
--- a/lib/mesa/include/CL/opencl.h
+++ b/lib/mesa/include/CL/opencl.h
@@ -26,7 +26,7 @@
* MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.
******************************************************************************/
-/* $Revision: 1.22 $ on $Date: 2021/09/09 09:59:14 $ */
+/* $Revision: 1.23 $ on $Date: 2022/02/24 02:29:48 $ */
#ifndef __OPENCL_H
#define __OPENCL_H
diff --git a/lib/mesa/include/EGL/egl.h b/lib/mesa/include/EGL/egl.h
index 959f175d7..9c3254996 100644
--- a/lib/mesa/include/EGL/egl.h
+++ b/lib/mesa/include/EGL/egl.h
@@ -6,34 +6,15 @@ extern "C" {
#endif
/*
-** Copyright (c) 2013-2017 The Khronos Group Inc.
+** Copyright 2013-2020 The Khronos Group Inc.
+** SPDX-License-Identifier: Apache-2.0
**
-** Permission is hereby granted, free of charge, to any person obtaining a
-** copy of this software and/or associated documentation files (the
-** "Materials"), to deal in the Materials without restriction, including
-** without limitation the rights to use, copy, modify, merge, publish,
-** distribute, sublicense, and/or sell copies of the Materials, and to
-** permit persons to whom the Materials are furnished to do so, subject to
-** the following conditions:
-**
-** The above copyright notice and this permission notice shall be included
-** in all copies or substantial portions of the Materials.
-**
-** THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-** MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-** CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-** TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-** MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.
-*/
-/*
** This header is generated from the Khronos EGL XML API Registry.
** The current version of the Registry, generator scripts
** used to make the header, and the header can be found at
** http://www.khronos.org/registry/egl
**
-** Khronos $Git commit SHA1: b5409265f3 $ on $Git commit date: 2020-02-20 08:24:34 -0800 $
+** Khronos $Git commit SHA1: e8baa0bf39 $ on $Git commit date: 2021-04-26 17:56:26 -0600 $
*/
#include <EGL/eglplatform.h>
@@ -42,7 +23,7 @@ extern "C" {
#define EGL_EGL_PROTOTYPES 1
#endif
-/* Generated on date 20200220 */
+/* Generated on date 20210604 */
/* Generated C header for:
* API: egl
diff --git a/lib/mesa/include/EGL/eglext.h b/lib/mesa/include/EGL/eglext.h
index a911e40c9..94dd038c9 100644
--- a/lib/mesa/include/EGL/eglext.h
+++ b/lib/mesa/include/EGL/eglext.h
@@ -6,39 +6,20 @@ extern "C" {
#endif
/*
-** Copyright (c) 2013-2017 The Khronos Group Inc.
+** Copyright 2013-2020 The Khronos Group Inc.
+** SPDX-License-Identifier: Apache-2.0
**
-** Permission is hereby granted, free of charge, to any person obtaining a
-** copy of this software and/or associated documentation files (the
-** "Materials"), to deal in the Materials without restriction, including
-** without limitation the rights to use, copy, modify, merge, publish,
-** distribute, sublicense, and/or sell copies of the Materials, and to
-** permit persons to whom the Materials are furnished to do so, subject to
-** the following conditions:
-**
-** The above copyright notice and this permission notice shall be included
-** in all copies or substantial portions of the Materials.
-**
-** THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-** MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-** CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-** TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-** MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.
-*/
-/*
** This header is generated from the Khronos EGL XML API Registry.
** The current version of the Registry, generator scripts
** used to make the header, and the header can be found at
** http://www.khronos.org/registry/egl
**
-** Khronos $Git commit SHA1: b5409265f3 $ on $Git commit date: 2020-02-20 08:24:34 -0800 $
+** Khronos $Git commit SHA1: dc0b58dca5 $ on $Git commit date: 2021-06-25 01:58:50 +0200 $
*/
#include <EGL/eglplatform.h>
-#define EGL_EGLEXT_VERSION 20200220
+#define EGL_EGLEXT_VERSION 20210629
/* Generated C header for:
* API: egl
@@ -593,6 +574,14 @@ EGLAPI EGLBoolean EGLAPIENTRY eglQuerySurfacePointerANGLE (EGLDisplay dpy, EGLSu
#define EGL_ANGLE_surface_d3d_texture_2d_share_handle 1
#endif /* EGL_ANGLE_surface_d3d_texture_2d_share_handle */
+#ifndef EGL_ANGLE_sync_control_rate
+#define EGL_ANGLE_sync_control_rate 1
+typedef EGLBoolean (EGLAPIENTRYP PFNEGLGETMSCRATEANGLEPROC) (EGLDisplay dpy, EGLSurface surface, EGLint *numerator, EGLint *denominator);
+#ifdef EGL_EGLEXT_PROTOTYPES
+EGLAPI EGLBoolean EGLAPIENTRY eglGetMscRateANGLE (EGLDisplay dpy, EGLSurface surface, EGLint *numerator, EGLint *denominator);
+#endif
+#endif /* EGL_ANGLE_sync_control_rate */
+
#ifndef EGL_ANGLE_window_fixed_size
#define EGL_ANGLE_window_fixed_size 1
#define EGL_FIXED_SIZE_ANGLE 0x3201
@@ -662,6 +651,11 @@ EGLAPI EGLBoolean EGLAPIENTRY eglCompositorSwapPolicyEXT (EGLint external_win_id
#endif
#endif /* EGL_EXT_compositor */
+#ifndef EGL_EXT_config_select_group
+#define EGL_EXT_config_select_group 1
+#define EGL_CONFIG_SELECT_GROUP_EXT 0x34C0
+#endif /* EGL_EXT_config_select_group */
+
#ifndef EGL_EXT_create_context_robustness
#define EGL_EXT_create_context_robustness 1
#define EGL_CONTEXT_OPENGL_ROBUST_ACCESS_EXT 0x30BF
@@ -694,6 +688,11 @@ EGLAPI EGLBoolean EGLAPIENTRY eglQueryDisplayAttribEXT (EGLDisplay dpy, EGLint a
#define EGL_DRM_MASTER_FD_EXT 0x333C
#endif /* EGL_EXT_device_drm */
+#ifndef EGL_EXT_device_drm_render_node
+#define EGL_EXT_device_drm_render_node 1
+#define EGL_DRM_RENDER_NODE_FILE_EXT 0x3377
+#endif /* EGL_EXT_device_drm_render_node */
+
#ifndef EGL_EXT_device_enumeration
#define EGL_EXT_device_enumeration 1
#endif /* EGL_EXT_device_enumeration */
@@ -703,10 +702,26 @@ EGLAPI EGLBoolean EGLAPIENTRY eglQueryDisplayAttribEXT (EGLDisplay dpy, EGLint a
#define EGL_OPENWF_DEVICE_ID_EXT 0x3237
#endif /* EGL_EXT_device_openwf */
+#ifndef EGL_EXT_device_persistent_id
+#define EGL_EXT_device_persistent_id 1
+#define EGL_DEVICE_UUID_EXT 0x335C
+#define EGL_DRIVER_UUID_EXT 0x335D
+#define EGL_DRIVER_NAME_EXT 0x335E
+typedef EGLBoolean (EGLAPIENTRYP PFNEGLQUERYDEVICEBINARYEXTPROC) (EGLDeviceEXT device, EGLint name, EGLint max_size, void *value, EGLint *size);
+#ifdef EGL_EGLEXT_PROTOTYPES
+EGLAPI EGLBoolean EGLAPIENTRY eglQueryDeviceBinaryEXT (EGLDeviceEXT device, EGLint name, EGLint max_size, void *value, EGLint *size);
+#endif
+#endif /* EGL_EXT_device_persistent_id */
+
#ifndef EGL_EXT_device_query
#define EGL_EXT_device_query 1
#endif /* EGL_EXT_device_query */
+#ifndef EGL_EXT_device_query_name
+#define EGL_EXT_device_query_name 1
+#define EGL_RENDERER_EXT 0x335F
+#endif /* EGL_EXT_device_query_name */
+
#ifndef EGL_EXT_gl_colorspace_bt2020_linear
#define EGL_EXT_gl_colorspace_bt2020_linear 1
#define EGL_GL_COLORSPACE_BT2020_LINEAR_EXT 0x333F
@@ -883,11 +898,16 @@ EGLAPI EGLSurface EGLAPIENTRY eglCreatePlatformPixmapSurfaceEXT (EGLDisplay dpy,
#define EGL_PLATFORM_X11_SCREEN_EXT 0x31D6
#endif /* EGL_EXT_platform_x11 */
-#ifndef EGL_MESA_platform_xcb
-#define EGL_MESA_platform_xcb 1
+#ifndef EGL_EXT_platform_xcb
+#define EGL_EXT_platform_xcb 1
#define EGL_PLATFORM_XCB_EXT 0x31DC
#define EGL_PLATFORM_XCB_SCREEN_EXT 0x31DE
-#endif /* EGL_MESA_platform_xcb */
+#endif /* EGL_EXT_platform_xcb */
+
+#ifndef EGL_EXT_present_opaque
+#define EGL_EXT_present_opaque 1
+#define EGL_PRESENT_OPAQUE_EXT 0x31DF
+#endif /* EGL_EXT_present_opaque */
#ifndef EGL_EXT_protected_content
#define EGL_EXT_protected_content 1
@@ -1155,6 +1175,24 @@ EGLAPI EGLBoolean EGLAPIENTRY eglPostSubBufferNV (EGLDisplay dpy, EGLSurface sur
#define EGL_GENERATE_RESET_ON_VIDEO_MEMORY_PURGE_NV 0x334C
#endif /* EGL_NV_robustness_video_memory_purge */
+#ifndef EGL_NV_stream_consumer_eglimage
+#define EGL_NV_stream_consumer_eglimage 1
+#define EGL_STREAM_CONSUMER_IMAGE_NV 0x3373
+#define EGL_STREAM_IMAGE_ADD_NV 0x3374
+#define EGL_STREAM_IMAGE_REMOVE_NV 0x3375
+#define EGL_STREAM_IMAGE_AVAILABLE_NV 0x3376
+typedef EGLBoolean (EGLAPIENTRYP PFNEGLSTREAMIMAGECONSUMERCONNECTNVPROC) (EGLDisplay dpy, EGLStreamKHR stream, EGLint num_modifiers, EGLuint64KHR *modifiers, EGLAttrib *attrib_list);
+typedef EGLint (EGLAPIENTRYP PFNEGLQUERYSTREAMCONSUMEREVENTNVPROC) (EGLDisplay dpy, EGLStreamKHR stream, EGLTime timeout, EGLenum *event, EGLAttrib *aux);
+typedef EGLBoolean (EGLAPIENTRYP PFNEGLSTREAMACQUIREIMAGENVPROC) (EGLDisplay dpy, EGLStreamKHR stream, EGLImage *pImage, EGLSync sync);
+typedef EGLBoolean (EGLAPIENTRYP PFNEGLSTREAMRELEASEIMAGENVPROC) (EGLDisplay dpy, EGLStreamKHR stream, EGLImage image, EGLSync sync);
+#ifdef EGL_EGLEXT_PROTOTYPES
+EGLAPI EGLBoolean EGLAPIENTRY eglStreamImageConsumerConnectNV (EGLDisplay dpy, EGLStreamKHR stream, EGLint num_modifiers, EGLuint64KHR *modifiers, EGLAttrib *attrib_list);
+EGLAPI EGLint EGLAPIENTRY eglQueryStreamConsumerEventNV (EGLDisplay dpy, EGLStreamKHR stream, EGLTime timeout, EGLenum *event, EGLAttrib *aux);
+EGLAPI EGLBoolean EGLAPIENTRY eglStreamAcquireImageNV (EGLDisplay dpy, EGLStreamKHR stream, EGLImage *pImage, EGLSync sync);
+EGLAPI EGLBoolean EGLAPIENTRY eglStreamReleaseImageNV (EGLDisplay dpy, EGLStreamKHR stream, EGLImage image, EGLSync sync);
+#endif
+#endif /* EGL_NV_stream_consumer_eglimage */
+
#ifndef EGL_NV_stream_consumer_gltexture_yuv
#define EGL_NV_stream_consumer_gltexture_yuv 1
#define EGL_YUV_PLANE0_TEXTURE_UNIT_NV 0x332C
diff --git a/lib/mesa/include/EGL/eglplatform.h b/lib/mesa/include/EGL/eglplatform.h
index befa50b9f..67d6c1f4e 100644
--- a/lib/mesa/include/EGL/eglplatform.h
+++ b/lib/mesa/include/EGL/eglplatform.h
@@ -25,7 +25,7 @@
*/
/* Platform-specific types and definitions for egl.h
- * $Revision: 1.22 $ on $Date: 2021/09/09 09:59:14 $
+ * $Revision: 1.23 $ on $Date: 2022/02/24 02:29:48 $
*
* Adopters may modify khrplatform.h and this file to suit their platform.
* You are encouraged to submit all modifications to the Khronos group so that
diff --git a/lib/mesa/include/GL/internal/dri_interface.h b/lib/mesa/include/GL/internal/dri_interface.h
index 9b85e67ce..49ea14f3c 100644
--- a/lib/mesa/include/GL/internal/dri_interface.h
+++ b/lib/mesa/include/GL/internal/dri_interface.h
@@ -48,8 +48,6 @@ typedef unsigned int drm_drawable_t;
typedef struct drm_clip_rect drm_clip_rect_t;
#endif
-#include <GL/gl.h>
-
#include <stdint.h>
/**
@@ -154,32 +152,6 @@ struct __DRIswapControlExtensionRec {
};
/**
- * Used by drivers that implement the GLX_MESA_swap_frame_usage extension.
- */
-#define __DRI_FRAME_TRACKING "DRI_FrameTracking"
-#define __DRI_FRAME_TRACKING_VERSION 1
-struct __DRIframeTrackingExtensionRec {
- __DRIextension base;
-
- /**
- * Enable or disable frame usage tracking.
- *
- * \since Internal API version 20030317.
- */
- int (*frameTracking)(__DRIdrawable *drawable, GLboolean enable);
-
- /**
- * Retrieve frame usage information.
- *
- * \since Internal API version 20030317.
- */
- int (*queryFrameTracking)(__DRIdrawable *drawable,
- int64_t * sbc, int64_t * missedFrames,
- float * lastMissedUsage, float * usage);
-};
-
-
-/**
* Used by drivers that implement the GLX_SGI_video_sync extension.
*/
#define __DRI_MEDIA_STREAM_COUNTER "DRI_MediaStreamCounter"
@@ -205,24 +177,6 @@ struct __DRImediaStreamCounterExtensionRec {
int64_t *msc);
};
-
-#define __DRI_TEX_OFFSET "DRI_TexOffset"
-#define __DRI_TEX_OFFSET_VERSION 1
-struct __DRItexOffsetExtensionRec {
- __DRIextension base;
-
- /**
- * Method to override base texture image with a driver specific 'offset'.
- * The depth passed in allows e.g. to ignore the alpha channel of texture
- * images where the non-alpha components don't occupy a whole texel.
- *
- * For GLX_EXT_texture_from_pixmap with AIGLX.
- */
- void (*setTexOffset)(__DRIcontext *pDRICtx, GLint texname,
- unsigned long long offset, GLint depth, GLuint pitch);
-};
-
-
/* Valid values for format in the setTexBuffer2 function below. These
* values match the GLX tokens for compatibility reasons, but we
* define them here since the DRI interface can't depend on GLX. */
@@ -243,7 +197,7 @@ struct __DRItexBufferExtensionRec {
* setTexBuffer2 in version 2 of this interface
*/
void (*setTexBuffer)(__DRIcontext *pDRICtx,
- GLint target,
+ int target,
__DRIdrawable *pDraw);
/**
@@ -255,8 +209,8 @@ struct __DRItexBufferExtensionRec {
* \since 2
*/
void (*setTexBuffer2)(__DRIcontext *pDRICtx,
- GLint target,
- GLint format,
+ int target,
+ int format,
__DRIdrawable *pDraw);
/**
* Method to release texture buffer in case some special platform
@@ -267,7 +221,7 @@ struct __DRItexBufferExtensionRec {
* \since 3
*/
void (*releaseTexBuffer)(__DRIcontext *pDRICtx,
- GLint target,
+ int target,
__DRIdrawable *pDraw);
};
@@ -410,8 +364,8 @@ struct __DRI2fenceExtensionRec {
* \param flags a combination of __DRI2_FENCE_FLAG_xxx flags
* \param timeout the timeout in ns or __DRI2_FENCE_TIMEOUT_INFINITE
*/
- GLboolean (*client_wait_sync)(__DRIcontext *ctx, void *fence,
- unsigned flags, uint64_t timeout);
+ unsigned char (*client_wait_sync)(__DRIcontext *ctx, void *fence,
+ unsigned flags, uint64_t timeout);
/**
* This function enqueues a wait command into the command stream of
@@ -549,28 +503,6 @@ typedef struct __DRIdamageExtensionRec __DRIdamageExtension;
typedef struct __DRIloaderExtensionRec __DRIloaderExtension;
typedef struct __DRIswrastLoaderExtensionRec __DRIswrastLoaderExtension;
-
-/**
- * Callback to getDrawableInfo protocol
- */
-#define __DRI_GET_DRAWABLE_INFO "DRI_GetDrawableInfo"
-#define __DRI_GET_DRAWABLE_INFO_VERSION 1
-struct __DRIgetDrawableInfoExtensionRec {
- __DRIextension base;
-
- /**
- * This function is used to get information about the position, size, and
- * clip rects of a drawable.
- */
- GLboolean (* getDrawableInfo) ( __DRIdrawable *drawable,
- unsigned int * index, unsigned int * stamp,
- int * x, int * y, int * width, int * height,
- int * numClipRects, drm_clip_rect_t ** pClipRects,
- int * backX, int * backY,
- int * numBackClipRects, drm_clip_rect_t ** pBackClipRects,
- void *loaderPrivate);
-};
-
/**
* Callback to get system time for media stream counter extensions.
*/
@@ -591,7 +523,7 @@ struct __DRIsystemTimeExtensionRec {
* the rate of the "media stream counter". In practical terms, this is
* the frame refresh rate of the display.
*/
- GLboolean (*getMSCRate)(__DRIdrawable *draw,
+ unsigned char (*getMSCRate)(__DRIdrawable *draw,
int32_t * numerator, int32_t * denominator,
void *loaderPrivate);
};
@@ -622,7 +554,7 @@ struct __DRIdamageExtensionRec {
void (*reportDamage)(__DRIdrawable *draw,
int x, int y,
drm_clip_rect_t *rects, int num_rects,
- GLboolean front_buffer,
+ unsigned char front_buffer,
void *loaderPrivate);
};
@@ -721,9 +653,9 @@ struct __DRIswrastLoaderExtensionRec {
*
* \since 6
*/
- GLboolean (*getImageShm2)(__DRIdrawable *readable,
- int x, int y, int width, int height,
- int shmid, void *loaderPrivate);
+ unsigned char (*getImageShm2)(__DRIdrawable *readable,
+ int x, int y, int width, int height,
+ int shmid, void *loaderPrivate);
};
/**
@@ -1203,50 +1135,27 @@ struct __DRIdri2LoaderExtensionRec {
#define __DRI_CTX_ATTRIB_MAJOR_VERSION 0
#define __DRI_CTX_ATTRIB_MINOR_VERSION 1
-#define __DRI_CTX_ATTRIB_FLAGS 2
-
-/**
- * \requires __DRI2_ROBUSTNESS.
- */
-#define __DRI_CTX_ATTRIB_RESET_STRATEGY 3
+#define __DRI_CTX_ATTRIB_FLAGS 2
#define __DRI_CTX_FLAG_DEBUG 0x00000001
#define __DRI_CTX_FLAG_FORWARD_COMPATIBLE 0x00000002
-
-/**
- * \requires __DRI2_ROBUSTNESS.
- */
#define __DRI_CTX_FLAG_ROBUST_BUFFER_ACCESS 0x00000004
-
-/**
- * \requires __DRI2_NO_ERROR.
- *
- */
#define __DRI_CTX_FLAG_NO_ERROR 0x00000008
-/**
- * \name Context reset strategies.
- */
-/*@{*/
+#define __DRI_CTX_ATTRIB_RESET_STRATEGY 3
#define __DRI_CTX_RESET_NO_NOTIFICATION 0
#define __DRI_CTX_RESET_LOSE_CONTEXT 1
-/*@}*/
#define __DRI_CTX_ATTRIB_PRIORITY 4
-
#define __DRI_CTX_PRIORITY_LOW 0
#define __DRI_CTX_PRIORITY_MEDIUM 1
#define __DRI_CTX_PRIORITY_HIGH 2
-/**
- * \name Context release behaviors.
- */
-/*@{*/
#define __DRI_CTX_ATTRIB_RELEASE_BEHAVIOR 5
-
#define __DRI_CTX_RELEASE_BEHAVIOR_NONE 0
#define __DRI_CTX_RELEASE_BEHAVIOR_FLUSH 1
-/*@}*/
+
+#define __DRI_CTX_NUM_ATTRIBS 6
/**
* \name Reasons that __DRIdri2Extension::createContextAttribs might fail
@@ -1328,7 +1237,7 @@ struct __DRIdri2ExtensionRec {
* extensions.
*/
#define __DRI_IMAGE "DRI_IMAGE"
-#define __DRI_IMAGE_VERSION 18
+#define __DRI_IMAGE_VERSION 19
/**
* These formats correspond to the similarly named MESA_FORMAT_*
@@ -1366,6 +1275,7 @@ struct __DRIdri2ExtensionRec {
#define __DRI_IMAGE_FORMAT_XBGR16161616F 0x1014
#define __DRI_IMAGE_FORMAT_ABGR16161616F 0x1015
#define __DRI_IMAGE_FORMAT_SXRGB8 0x1016
+#define __DRI_IMAGE_FORMAT_ABGR16161616 0x1017
#define __DRI_IMAGE_USE_SHARE 0x0001
#define __DRI_IMAGE_USE_SCANOUT 0x0002
@@ -1395,11 +1305,12 @@ struct __DRIdri2ExtensionRec {
#define __DRI_IMAGE_FOURCC_SARGB8888 0x83324258
#define __DRI_IMAGE_FOURCC_SABGR8888 0x84324258
#define __DRI_IMAGE_FOURCC_SXRGB8888 0x85324258
+#define __DRI_IMAGE_FOURCC_RGBA16161616 0x38344152 /* fourcc_code('R', 'A', '4', '8' ) */
/**
* Queryable on images created by createImageFromNames.
*
- * RGB and RGBA are may be usable directly as images but its still
+ * RGB and RGBA might be usable directly as images, but it's still
* recommended to call fromPlanar with plane == 0.
*
* Y_U_V, Y_UV,Y_XUXV and Y_UXVX all requires call to fromPlanar to create
@@ -1530,7 +1441,7 @@ struct __DRIimageExtensionRec {
unsigned int use,
void *loaderPrivate);
- GLboolean (*queryImage)(__DRIimage *image, int attrib, int *value);
+ unsigned char (*queryImage)(__DRIimage *image, int attrib, int *value);
/**
* The new __DRIimage will share the content with the old one, see dup(2).
@@ -1542,7 +1453,7 @@ struct __DRIimageExtensionRec {
*
* \since 2
*/
- GLboolean (*validateUsage)(__DRIimage *image, unsigned int use);
+ unsigned char (*validateUsage)(__DRIimage *image, unsigned int use);
/**
* Unlike createImageFromName __DRI_IMAGE_FORMAT is not used but instead
@@ -1723,8 +1634,8 @@ struct __DRIimageExtensionRec {
*
* \since 15
*/
- GLboolean (*queryDmaBufFormats)(__DRIscreen *screen, int max,
- int *formats, int *count);
+ unsigned char (*queryDmaBufFormats)(__DRIscreen *screen, int max,
+ int *formats, int *count);
/*
* dmabuf format modifier query for a given format to support
@@ -1745,10 +1656,10 @@ struct __DRIimageExtensionRec {
*
* \since 15
*/
- GLboolean (*queryDmaBufModifiers)(__DRIscreen *screen, int fourcc,
- int max, uint64_t *modifiers,
- unsigned int *external_only,
- int *count);
+ unsigned char (*queryDmaBufModifiers)(__DRIscreen *screen, int fourcc,
+ int max, uint64_t *modifiers,
+ unsigned int *external_only,
+ int *count);
/**
* dmabuf format modifier attribute query for a given format and modifier.
@@ -1764,9 +1675,11 @@ struct __DRIimageExtensionRec {
*
* \since 16
*/
- GLboolean (*queryDmaBufFormatModifierAttribs)(__DRIscreen *screen,
- uint32_t fourcc, uint64_t modifier,
- int attrib, uint64_t *value);
+ unsigned char (*queryDmaBufFormatModifierAttribs)(__DRIscreen *screen,
+ uint32_t fourcc,
+ uint64_t modifier,
+ int attrib,
+ uint64_t *value);
/**
* Create a DRI image from the given renderbuffer.
@@ -1803,6 +1716,28 @@ struct __DRIimageExtensionRec {
uint32_t flags,
unsigned *error,
void *loaderPrivate);
+
+ /**
+ * Creates an image with implementation's favorite modifiers and the
+ * provided usage flags.
+ *
+ * This acts like createImageWithModifiers except usage is also specified.
+ *
+ * The created image should be destroyed with destroyImage().
+ *
+ * Returns the new DRIimage. The chosen modifier can be obtained later on
+ * and passed back to things like the kernel's AddFB2 interface.
+ *
+ * \sa __DRIimageRec::createImage
+ *
+ * \since 19
+ */
+ __DRIimage *(*createImageWithModifiers2)(__DRIscreen *screen,
+ int width, int height, int format,
+ const uint64_t *modifiers,
+ const unsigned int modifier_count,
+ unsigned int use,
+ void *loaderPrivate);
};
@@ -1816,14 +1751,36 @@ struct __DRIimageExtensionRec {
* with new lookup functions.
*/
#define __DRI_IMAGE_LOOKUP "DRI_IMAGE_LOOKUP"
-#define __DRI_IMAGE_LOOKUP_VERSION 1
+#define __DRI_IMAGE_LOOKUP_VERSION 2
typedef struct __DRIimageLookupExtensionRec __DRIimageLookupExtension;
struct __DRIimageLookupExtensionRec {
__DRIextension base;
+ /**
+ * Lookup EGLImage without validated. Equivalent to call
+ * validateEGLImage() then lookupEGLImageValidated().
+ *
+ * \since 1
+ */
__DRIimage *(*lookupEGLImage)(__DRIscreen *screen, void *image,
void *loaderPrivate);
+
+ /**
+ * Check if EGLImage is associated with the EGL display before lookup with
+ * lookupEGLImageValidated(). It will hold EGLDisplay.Mutex, so is separated
+ * out from lookupEGLImage() to avoid deadlock.
+ *
+ * \since 2
+ */
+ unsigned char (*validateEGLImage)(void *image, void *loaderPrivate);
+
+ /**
+ * Lookup EGLImage after validateEGLImage(). No lock in this function.
+ *
+ * \since 2
+ */
+ __DRIimage *(*lookupEGLImageValidated)(void *image, void *loaderPrivate);
};
/**
@@ -1968,6 +1925,7 @@ typedef struct __DRIDriverVtableExtensionRec {
#define __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_HIGH (1 << 2)
#define __DRI2_RENDERER_HAS_PROTECTED_CONTENT 0x000e
+#define __DRI2_RENDERER_PREFER_BACK_BUFFER_REUSE 0x000f
typedef struct __DRI2rendererQueryExtensionRec __DRI2rendererQueryExtension;
struct __DRI2rendererQueryExtensionRec {
@@ -2177,7 +2135,7 @@ struct __DRIbackgroundCallableExtensionRec {
* the context was created. This can be used by the loader to identify
* which context any callbacks are associated with.
*/
- GLboolean (*isThreadSafe)(void *loaderPrivate);
+ unsigned char (*isThreadSafe)(void *loaderPrivate);
};
/**
diff --git a/lib/mesa/include/GLES3/gl3ext.h b/lib/mesa/include/GLES3/gl3ext.h
index e2a511b04..49b62f16e 100644
--- a/lib/mesa/include/GLES3/gl3ext.h
+++ b/lib/mesa/include/GLES3/gl3ext.h
@@ -1,7 +1,7 @@
#ifndef __gl3ext_h_
#define __gl3ext_h_
-/* $Revision: 1.22 $ on $Date: 2021/09/09 09:59:14 $ */
+/* $Revision: 1.23 $ on $Date: 2022/02/24 02:29:48 $ */
/*
* This document is licensed under the SGI Free Software B License Version
diff --git a/lib/mesa/include/android_stub/apex/window.h b/lib/mesa/include/android_stub/apex/window.h
deleted file mode 100644
index 2d1354cdf..000000000
--- a/lib/mesa/include/android_stub/apex/window.h
+++ /dev/null
@@ -1,210 +0,0 @@
-/*
- * Copyright 2019 The Android Open Source Project
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#pragma once
-
-#include <nativebase/nativebase.h>
-#include <stdarg.h>
-
-// apex is a superset of the NDK
-#include <android/native_window.h>
-
-__BEGIN_DECLS
-
-/*
- * perform bits that can be used with ANativeWindow_perform()
- *
- * This is only to support the intercepting methods below - these should notbe
- * used directly otherwise.
- */
-enum ANativeWindowPerform {
- // clang-format off
- ANATIVEWINDOW_PERFORM_SET_USAGE = 0,
- ANATIVEWINDOW_PERFORM_SET_BUFFERS_GEOMETRY = 5,
- ANATIVEWINDOW_PERFORM_SET_BUFFERS_FORMAT = 9,
- ANATIVEWINDOW_PERFORM_SET_USAGE64 = 30,
- // clang-format on
-};
-
-/**
- * Prototype of the function that an ANativeWindow implementation would call
- * when ANativeWindow_cancelBuffer is called.
- */
-typedef int (*ANativeWindow_cancelBufferFn)(ANativeWindow* window, ANativeWindowBuffer* buffer,
- int fenceFd);
-
-/**
- * Prototype of the function that intercepts an invocation of
- * ANativeWindow_cancelBufferFn, along with a data pointer that's passed by the
- * caller who set the interceptor, as well as arguments that would be
- * passed to ANativeWindow_cancelBufferFn if it were to be called.
- */
-typedef int (*ANativeWindow_cancelBufferInterceptor)(ANativeWindow* window,
- ANativeWindow_cancelBufferFn cancelBuffer,
- void* data, ANativeWindowBuffer* buffer,
- int fenceFd);
-
-/**
- * Prototype of the function that an ANativeWindow implementation would call
- * when ANativeWindow_dequeueBuffer is called.
- */
-typedef int (*ANativeWindow_dequeueBufferFn)(ANativeWindow* window, ANativeWindowBuffer** buffer,
- int* fenceFd);
-
-/**
- * Prototype of the function that intercepts an invocation of
- * ANativeWindow_dequeueBufferFn, along with a data pointer that's passed by the
- * caller who set the interceptor, as well as arguments that would be
- * passed to ANativeWindow_dequeueBufferFn if it were to be called.
- */
-typedef int (*ANativeWindow_dequeueBufferInterceptor)(ANativeWindow* window,
- ANativeWindow_dequeueBufferFn dequeueBuffer,
- void* data, ANativeWindowBuffer** buffer,
- int* fenceFd);
-
-/**
- * Prototype of the function that an ANativeWindow implementation would call
- * when ANativeWindow_perform is called.
- */
-typedef int (*ANativeWindow_performFn)(ANativeWindow* window, int operation, va_list args);
-
-/**
- * Prototype of the function that intercepts an invocation of
- * ANativeWindow_performFn, along with a data pointer that's passed by the
- * caller who set the interceptor, as well as arguments that would be
- * passed to ANativeWindow_performFn if it were to be called.
- */
-typedef int (*ANativeWindow_performInterceptor)(ANativeWindow* window,
- ANativeWindow_performFn perform, void* data,
- int operation, va_list args);
-
-/**
- * Prototype of the function that an ANativeWindow implementation would call
- * when ANativeWindow_queueBuffer is called.
- */
-typedef int (*ANativeWindow_queueBufferFn)(ANativeWindow* window, ANativeWindowBuffer* buffer,
- int fenceFd);
-
-/**
- * Prototype of the function that intercepts an invocation of
- * ANativeWindow_queueBufferFn, along with a data pointer that's passed by the
- * caller who set the interceptor, as well as arguments that would be
- * passed to ANativeWindow_queueBufferFn if it were to be called.
- */
-typedef int (*ANativeWindow_queueBufferInterceptor)(ANativeWindow* window,
- ANativeWindow_queueBufferFn queueBuffer,
- void* data, ANativeWindowBuffer* buffer,
- int fenceFd);
-
-/**
- * Registers an interceptor for ANativeWindow_cancelBuffer. Instead of calling
- * the underlying cancelBuffer function, instead the provided interceptor is
- * called, which may optionally call the underlying cancelBuffer function. An
- * optional data pointer is also provided to side-channel additional arguments.
- *
- * Note that usage of this should only be used for specialized use-cases by
- * either the system partition or to Mainline modules. This should never be
- * exposed to NDK or LL-NDK.
- *
- * Returns NO_ERROR on success, -errno if registration failed.
- */
-int ANativeWindow_setCancelBufferInterceptor(ANativeWindow* window,
- ANativeWindow_cancelBufferInterceptor interceptor,
- void* data);
-
-/**
- * Registers an interceptor for ANativeWindow_dequeueBuffer. Instead of calling
- * the underlying dequeueBuffer function, instead the provided interceptor is
- * called, which may optionally call the underlying dequeueBuffer function. An
- * optional data pointer is also provided to side-channel additional arguments.
- *
- * Note that usage of this should only be used for specialized use-cases by
- * either the system partition or to Mainline modules. This should never be
- * exposed to NDK or LL-NDK.
- *
- * Returns NO_ERROR on success, -errno if registration failed.
- */
-int ANativeWindow_setDequeueBufferInterceptor(ANativeWindow* window,
- ANativeWindow_dequeueBufferInterceptor interceptor,
- void* data);
-/**
- * Registers an interceptor for ANativeWindow_perform. Instead of calling
- * the underlying perform function, instead the provided interceptor is
- * called, which may optionally call the underlying perform function. An
- * optional data pointer is also provided to side-channel additional arguments.
- *
- * Note that usage of this should only be used for specialized use-cases by
- * either the system partition or to Mainline modules. This should never be
- * exposed to NDK or LL-NDK.
- *
- * Returns NO_ERROR on success, -errno if registration failed.
- */
-int ANativeWindow_setPerformInterceptor(ANativeWindow* window,
- ANativeWindow_performInterceptor interceptor, void* data);
-/**
- * Registers an interceptor for ANativeWindow_queueBuffer. Instead of calling
- * the underlying queueBuffer function, instead the provided interceptor is
- * called, which may optionally call the underlying queueBuffer function. An
- * optional data pointer is also provided to side-channel additional arguments.
- *
- * Note that usage of this should only be used for specialized use-cases by
- * either the system partition or to Mainline modules. This should never be
- * exposed to NDK or LL-NDK.
- *
- * Returns NO_ERROR on success, -errno if registration failed.
- */
-int ANativeWindow_setQueueBufferInterceptor(ANativeWindow* window,
- ANativeWindow_queueBufferInterceptor interceptor,
- void* data);
-
-/**
- * Retrieves how long it took for the last time a buffer was dequeued.
- *
- * \return the dequeue duration in nanoseconds
- */
-int64_t ANativeWindow_getLastDequeueDuration(ANativeWindow* window);
-
-/**
- * Retrieves how long it took for the last time a buffer was queued.
- *
- * \return the queue duration in nanoseconds
- */
-int64_t ANativeWindow_getLastQueueDuration(ANativeWindow* window);
-
-/**
- * Retrieves the system time in nanoseconds when the last time a buffer
- * started to be dequeued.
- *
- * \return the start time in nanoseconds
- */
-int64_t ANativeWindow_getLastDequeueStartTime(ANativeWindow* window);
-
-/**
- * Sets a timeout in nanoseconds for dequeue calls. All subsequent dequeue calls
- * made by the window will return -ETIMEDOUT after the timeout if the dequeue
- * takes too long.
- *
- * If the provided timeout is negative, hen this removes the previously configured
- * timeout. The window then behaves as if ANativeWindow_setDequeueTimeout was
- * never called.
- *
- * \return NO_ERROR on success
- * \return BAD_VALUE if the dequeue timeout was unabled to be updated, as
- * updating the dequeue timeout may change internals of the underlying window.
- */
-int ANativeWindow_setDequeueTimeout(ANativeWindow* window, int64_t timeout);
-
-__END_DECLS
diff --git a/lib/mesa/include/drm-uapi/amdgpu_drm.h b/lib/mesa/include/drm-uapi/amdgpu_drm.h
index 728566542..0cbd1540a 100644
--- a/lib/mesa/include/drm-uapi/amdgpu_drm.h
+++ b/lib/mesa/include/drm-uapi/amdgpu_drm.h
@@ -116,8 +116,6 @@ extern "C" {
#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2)
/* Flag that the memory should be in VRAM and cleared */
#define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3)
-/* Flag that create shadow bo(GTT) while allocating vram bo */
-#define AMDGPU_GEM_CREATE_SHADOW (1 << 4)
/* Flag that allocating the BO should use linear VRAM */
#define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5)
/* Flag that BO is always valid in this VM */
@@ -138,6 +136,10 @@ extern "C" {
* accessing it with various hw blocks
*/
#define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10)
+/* Flag that BO will be used only in preemptible context, which does
+ * not require GTT memory accounting
+ */
+#define AMDGPU_GEM_CREATE_PREEMPTIBLE (1 << 11)
struct drm_amdgpu_gem_create_in {
/** the requested memory size */
@@ -755,6 +757,8 @@ struct drm_amdgpu_cs_chunk_data {
#define AMDGPU_INFO_VBIOS_SIZE 0x1
/* Subquery id: Query vbios image */
#define AMDGPU_INFO_VBIOS_IMAGE 0x2
+ /* Subquery id: Query vbios info */
+ #define AMDGPU_INFO_VBIOS_INFO 0x3
/* Query UVD handles */
#define AMDGPU_INFO_NUM_HANDLES 0x1C
/* Query sensor related information */
@@ -948,6 +952,15 @@ struct drm_amdgpu_info_firmware {
__u32 feature;
};
+struct drm_amdgpu_info_vbios {
+ __u8 name[64];
+ __u8 vbios_pn[64];
+ __u32 version;
+ __u32 pad;
+ __u8 vbios_ver_str[32];
+ __u8 date[32];
+};
+
#define AMDGPU_VRAM_TYPE_UNKNOWN 0
#define AMDGPU_VRAM_TYPE_GDDR1 1
#define AMDGPU_VRAM_TYPE_DDR2 2
@@ -1121,6 +1134,7 @@ struct drm_amdgpu_info_video_caps {
#define AMDGPU_FAMILY_RV 142 /* Raven */
#define AMDGPU_FAMILY_NV 143 /* Navi10 */
#define AMDGPU_FAMILY_VGH 144 /* Van Gogh */
+#define AMDGPU_FAMILY_YC 146 /* Yellow Carp */
#if defined(__cplusplus)
}
diff --git a/lib/mesa/include/drm-uapi/drm.h b/lib/mesa/include/drm-uapi/drm.h
index c7fd2a35f..5e54c3aa4 100644
--- a/lib/mesa/include/drm-uapi/drm.h
+++ b/lib/mesa/include/drm-uapi/drm.h
@@ -1,11 +1,10 @@
-/**
- * \file drm.h
+/*
* Header for the Direct Rendering Manager
*
- * \author Rickard E. (Rik) Faith <faith@valinux.com>
+ * Author: Rickard E. (Rik) Faith <faith@valinux.com>
*
- * \par Acknowledgments:
- * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg.
+ * Acknowledgments:
+ * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic cmpxchg.
*/
/*
@@ -79,7 +78,7 @@ typedef unsigned int drm_context_t;
typedef unsigned int drm_drawable_t;
typedef unsigned int drm_magic_t;
-/**
+/*
* Cliprect.
*
* \warning: If you change this structure, make sure you change
@@ -95,7 +94,7 @@ struct drm_clip_rect {
unsigned short y2;
};
-/**
+/*
* Drawable information.
*/
struct drm_drawable_info {
@@ -103,7 +102,7 @@ struct drm_drawable_info {
struct drm_clip_rect *rects;
};
-/**
+/*
* Texture region,
*/
struct drm_tex_region {
@@ -114,7 +113,7 @@ struct drm_tex_region {
unsigned int age;
};
-/**
+/*
* Hardware lock.
*
* The lock structure is a simple cache-line aligned integer. To avoid
@@ -126,7 +125,7 @@ struct drm_hw_lock {
char padding[60]; /**< Pad to cache line */
};
-/**
+/*
* DRM_IOCTL_VERSION ioctl argument type.
*
* \sa drmGetVersion().
@@ -143,7 +142,7 @@ struct drm_version {
char *desc; /**< User-space buffer to hold desc */
};
-/**
+/*
* DRM_IOCTL_GET_UNIQUE ioctl argument type.
*
* \sa drmGetBusid() and drmSetBusId().
@@ -162,7 +161,7 @@ struct drm_block {
int unused;
};
-/**
+/*
* DRM_IOCTL_CONTROL ioctl argument type.
*
* \sa drmCtlInstHandler() and drmCtlUninstHandler().
@@ -177,7 +176,7 @@ struct drm_control {
int irq;
};
-/**
+/*
* Type of memory to map.
*/
enum drm_map_type {
@@ -189,7 +188,7 @@ enum drm_map_type {
_DRM_CONSISTENT = 5 /**< Consistent memory for PCI DMA */
};
-/**
+/*
* Memory mapping flags.
*/
enum drm_map_flags {
@@ -208,7 +207,7 @@ struct drm_ctx_priv_map {
void *handle; /**< Handle of map */
};
-/**
+/*
* DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
* argument type.
*
@@ -225,7 +224,7 @@ struct drm_map {
/* Private data */
};
-/**
+/*
* DRM_IOCTL_GET_CLIENT ioctl argument type.
*/
struct drm_client {
@@ -257,7 +256,7 @@ enum drm_stat_type {
/* Add to the *END* of the list */
};
-/**
+/*
* DRM_IOCTL_GET_STATS ioctl argument type.
*/
struct drm_stats {
@@ -268,7 +267,7 @@ struct drm_stats {
} data[15];
};
-/**
+/*
* Hardware locking flags.
*/
enum drm_lock_flags {
@@ -283,7 +282,7 @@ enum drm_lock_flags {
_DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */
};
-/**
+/*
* DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
*
* \sa drmGetLock() and drmUnlock().
@@ -293,7 +292,7 @@ struct drm_lock {
enum drm_lock_flags flags;
};
-/**
+/*
* DMA flags
*
* \warning
@@ -322,7 +321,7 @@ enum drm_dma_flags {
_DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */
};
-/**
+/*
* DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
*
* \sa drmAddBufs().
@@ -345,7 +344,7 @@ struct drm_buf_desc {
*/
};
-/**
+/*
* DRM_IOCTL_INFO_BUFS ioctl argument type.
*/
struct drm_buf_info {
@@ -353,7 +352,7 @@ struct drm_buf_info {
struct drm_buf_desc *list;
};
-/**
+/*
* DRM_IOCTL_FREE_BUFS ioctl argument type.
*/
struct drm_buf_free {
@@ -361,7 +360,7 @@ struct drm_buf_free {
int *list;
};
-/**
+/*
* Buffer information
*
* \sa drm_buf_map.
@@ -373,7 +372,7 @@ struct drm_buf_pub {
void *address; /**< Address of buffer */
};
-/**
+/*
* DRM_IOCTL_MAP_BUFS ioctl argument type.
*/
struct drm_buf_map {
@@ -386,7 +385,7 @@ struct drm_buf_map {
struct drm_buf_pub *list; /**< Buffer information */
};
-/**
+/*
* DRM_IOCTL_DMA ioctl argument type.
*
* Indices here refer to the offset into the buffer list in drm_buf_get.
@@ -411,7 +410,7 @@ enum drm_ctx_flags {
_DRM_CONTEXT_2DONLY = 0x02
};
-/**
+/*
* DRM_IOCTL_ADD_CTX ioctl argument type.
*
* \sa drmCreateContext() and drmDestroyContext().
@@ -421,7 +420,7 @@ struct drm_ctx {
enum drm_ctx_flags flags;
};
-/**
+/*
* DRM_IOCTL_RES_CTX ioctl argument type.
*/
struct drm_ctx_res {
@@ -429,14 +428,14 @@ struct drm_ctx_res {
struct drm_ctx *contexts;
};
-/**
+/*
* DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
*/
struct drm_draw {
drm_drawable_t handle;
};
-/**
+/*
* DRM_IOCTL_UPDATE_DRAW ioctl argument type.
*/
typedef enum {
@@ -450,14 +449,14 @@ struct drm_update_draw {
unsigned long long data;
};
-/**
+/*
* DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
*/
struct drm_auth {
drm_magic_t magic;
};
-/**
+/*
* DRM_IOCTL_IRQ_BUSID ioctl argument type.
*
* \sa drmGetInterruptFromBusID().
@@ -499,7 +498,7 @@ struct drm_wait_vblank_reply {
long tval_usec;
};
-/**
+/*
* DRM_IOCTL_WAIT_VBLANK ioctl argument type.
*
* \sa drmWaitVBlank().
@@ -512,7 +511,7 @@ union drm_wait_vblank {
#define _DRM_PRE_MODESET 1
#define _DRM_POST_MODESET 2
-/**
+/*
* DRM_IOCTL_MODESET_CTL ioctl argument type
*
* \sa drmModesetCtl().
@@ -522,7 +521,7 @@ struct drm_modeset_ctl {
__u32 cmd;
};
-/**
+/*
* DRM_IOCTL_AGP_ENABLE ioctl argument type.
*
* \sa drmAgpEnable().
@@ -531,7 +530,7 @@ struct drm_agp_mode {
unsigned long mode; /**< AGP mode */
};
-/**
+/*
* DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
*
* \sa drmAgpAlloc() and drmAgpFree().
@@ -543,7 +542,7 @@ struct drm_agp_buffer {
unsigned long physical; /**< Physical used by i810 */
};
-/**
+/*
* DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
*
* \sa drmAgpBind() and drmAgpUnbind().
@@ -553,7 +552,7 @@ struct drm_agp_binding {
unsigned long offset; /**< In bytes -- will round to page boundary */
};
-/**
+/*
* DRM_IOCTL_AGP_INFO ioctl argument type.
*
* \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
@@ -574,7 +573,7 @@ struct drm_agp_info {
unsigned short id_device;
};
-/**
+/*
* DRM_IOCTL_SG_ALLOC ioctl argument type.
*/
struct drm_scatter_gather {
@@ -582,7 +581,7 @@ struct drm_scatter_gather {
unsigned long handle; /**< Used for mapping / unmapping */
};
-/**
+/*
* DRM_IOCTL_SET_VERSION ioctl argument type.
*/
struct drm_set_version {
@@ -592,14 +591,14 @@ struct drm_set_version {
int drm_dd_minor;
};
-/** DRM_IOCTL_GEM_CLOSE ioctl argument type */
+/* DRM_IOCTL_GEM_CLOSE ioctl argument type */
struct drm_gem_close {
/** Handle of the object to be closed. */
__u32 handle;
__u32 pad;
};
-/** DRM_IOCTL_GEM_FLINK ioctl argument type */
+/* DRM_IOCTL_GEM_FLINK ioctl argument type */
struct drm_gem_flink {
/** Handle for the object being named */
__u32 handle;
@@ -608,7 +607,7 @@ struct drm_gem_flink {
__u32 name;
};
-/** DRM_IOCTL_GEM_OPEN ioctl argument type */
+/* DRM_IOCTL_GEM_OPEN ioctl argument type */
struct drm_gem_open {
/** Name of object being opened */
__u32 name;
@@ -620,33 +619,150 @@ struct drm_gem_open {
__u64 size;
};
+/**
+ * DRM_CAP_DUMB_BUFFER
+ *
+ * If set to 1, the driver supports creating dumb buffers via the
+ * &DRM_IOCTL_MODE_CREATE_DUMB ioctl.
+ */
#define DRM_CAP_DUMB_BUFFER 0x1
+/**
+ * DRM_CAP_VBLANK_HIGH_CRTC
+ *
+ * If set to 1, the kernel supports specifying a :ref:`CRTC index<crtc_index>`
+ * in the high bits of &drm_wait_vblank_request.type.
+ *
+ * Starting kernel version 2.6.39, this capability is always set to 1.
+ */
#define DRM_CAP_VBLANK_HIGH_CRTC 0x2
+/**
+ * DRM_CAP_DUMB_PREFERRED_DEPTH
+ *
+ * The preferred bit depth for dumb buffers.
+ *
+ * The bit depth is the number of bits used to indicate the color of a single
+ * pixel excluding any padding. This is different from the number of bits per
+ * pixel. For instance, XRGB8888 has a bit depth of 24 but has 32 bits per
+ * pixel.
+ *
+ * Note that this preference only applies to dumb buffers, it's irrelevant for
+ * other types of buffers.
+ */
#define DRM_CAP_DUMB_PREFERRED_DEPTH 0x3
+/**
+ * DRM_CAP_DUMB_PREFER_SHADOW
+ *
+ * If set to 1, the driver prefers userspace to render to a shadow buffer
+ * instead of directly rendering to a dumb buffer. For best speed, userspace
+ * should do streaming ordered memory copies into the dumb buffer and never
+ * read from it.
+ *
+ * Note that this preference only applies to dumb buffers, it's irrelevant for
+ * other types of buffers.
+ */
#define DRM_CAP_DUMB_PREFER_SHADOW 0x4
+/**
+ * DRM_CAP_PRIME
+ *
+ * Bitfield of supported PRIME sharing capabilities. See &DRM_PRIME_CAP_IMPORT
+ * and &DRM_PRIME_CAP_EXPORT.
+ *
+ * PRIME buffers are exposed as dma-buf file descriptors. See
+ * Documentation/gpu/drm-mm.rst, section "PRIME Buffer Sharing".
+ */
#define DRM_CAP_PRIME 0x5
+/**
+ * DRM_PRIME_CAP_IMPORT
+ *
+ * If this bit is set in &DRM_CAP_PRIME, the driver supports importing PRIME
+ * buffers via the &DRM_IOCTL_PRIME_FD_TO_HANDLE ioctl.
+ */
#define DRM_PRIME_CAP_IMPORT 0x1
+/**
+ * DRM_PRIME_CAP_EXPORT
+ *
+ * If this bit is set in &DRM_CAP_PRIME, the driver supports exporting PRIME
+ * buffers via the &DRM_IOCTL_PRIME_HANDLE_TO_FD ioctl.
+ */
#define DRM_PRIME_CAP_EXPORT 0x2
+/**
+ * DRM_CAP_TIMESTAMP_MONOTONIC
+ *
+ * If set to 0, the kernel will report timestamps with ``CLOCK_REALTIME`` in
+ * struct drm_event_vblank. If set to 1, the kernel will report timestamps with
+ * ``CLOCK_MONOTONIC``. See ``clock_gettime(2)`` for the definition of these
+ * clocks.
+ *
+ * Starting from kernel version 2.6.39, the default value for this capability
+ * is 1. Starting kernel version 4.15, this capability is always set to 1.
+ */
#define DRM_CAP_TIMESTAMP_MONOTONIC 0x6
+/**
+ * DRM_CAP_ASYNC_PAGE_FLIP
+ *
+ * If set to 1, the driver supports &DRM_MODE_PAGE_FLIP_ASYNC.
+ */
#define DRM_CAP_ASYNC_PAGE_FLIP 0x7
-/*
- * The CURSOR_WIDTH and CURSOR_HEIGHT capabilities return a valid widthxheight
- * combination for the hardware cursor. The intention is that a hardware
- * agnostic userspace can query a cursor plane size to use.
+/**
+ * DRM_CAP_CURSOR_WIDTH
+ *
+ * The ``CURSOR_WIDTH`` and ``CURSOR_HEIGHT`` capabilities return a valid
+ * width x height combination for the hardware cursor. The intention is that a
+ * hardware agnostic userspace can query a cursor plane size to use.
*
* Note that the cross-driver contract is to merely return a valid size;
* drivers are free to attach another meaning on top, eg. i915 returns the
* maximum plane size.
*/
#define DRM_CAP_CURSOR_WIDTH 0x8
+/**
+ * DRM_CAP_CURSOR_HEIGHT
+ *
+ * See &DRM_CAP_CURSOR_WIDTH.
+ */
#define DRM_CAP_CURSOR_HEIGHT 0x9
+/**
+ * DRM_CAP_ADDFB2_MODIFIERS
+ *
+ * If set to 1, the driver supports supplying modifiers in the
+ * &DRM_IOCTL_MODE_ADDFB2 ioctl.
+ */
#define DRM_CAP_ADDFB2_MODIFIERS 0x10
+/**
+ * DRM_CAP_PAGE_FLIP_TARGET
+ *
+ * If set to 1, the driver supports the &DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE and
+ * &DRM_MODE_PAGE_FLIP_TARGET_RELATIVE flags in
+ * &drm_mode_crtc_page_flip_target.flags for the &DRM_IOCTL_MODE_PAGE_FLIP
+ * ioctl.
+ */
#define DRM_CAP_PAGE_FLIP_TARGET 0x11
+/**
+ * DRM_CAP_CRTC_IN_VBLANK_EVENT
+ *
+ * If set to 1, the kernel supports reporting the CRTC ID in
+ * &drm_event_vblank.crtc_id for the &DRM_EVENT_VBLANK and
+ * &DRM_EVENT_FLIP_COMPLETE events.
+ *
+ * Starting kernel version 4.12, this capability is always set to 1.
+ */
#define DRM_CAP_CRTC_IN_VBLANK_EVENT 0x12
+/**
+ * DRM_CAP_SYNCOBJ
+ *
+ * If set to 1, the driver supports sync objects. See
+ * Documentation/gpu/drm-mm.rst, section "DRM Sync Objects".
+ */
#define DRM_CAP_SYNCOBJ 0x13
+/**
+ * DRM_CAP_SYNCOBJ_TIMELINE
+ *
+ * If set to 1, the driver supports timeline operations on sync objects. See
+ * Documentation/gpu/drm-mm.rst, section "DRM Sync Objects".
+ */
#define DRM_CAP_SYNCOBJ_TIMELINE 0x14
-/** DRM_IOCTL_GET_CAP ioctl argument type */
+/* DRM_IOCTL_GET_CAP ioctl argument type */
struct drm_get_cap {
__u64 capability;
__u64 value;
@@ -655,9 +771,12 @@ struct drm_get_cap {
/**
* DRM_CLIENT_CAP_STEREO_3D
*
- * if set to 1, the DRM core will expose the stereo 3D capabilities of the
+ * If set to 1, the DRM core will expose the stereo 3D capabilities of the
* monitor by advertising the supported 3D layouts in the flags of struct
- * drm_mode_modeinfo.
+ * drm_mode_modeinfo. See ``DRM_MODE_FLAG_3D_*``.
+ *
+ * This capability is always supported for all drivers starting from kernel
+ * version 3.13.
*/
#define DRM_CLIENT_CAP_STEREO_3D 1
@@ -666,13 +785,25 @@ struct drm_get_cap {
*
* If set to 1, the DRM core will expose all planes (overlay, primary, and
* cursor) to userspace.
+ *
+ * This capability has been introduced in kernel version 3.15. Starting from
+ * kernel version 3.17, this capability is always supported for all drivers.
*/
#define DRM_CLIENT_CAP_UNIVERSAL_PLANES 2
/**
* DRM_CLIENT_CAP_ATOMIC
*
- * If set to 1, the DRM core will expose atomic properties to userspace
+ * If set to 1, the DRM core will expose atomic properties to userspace. This
+ * implicitly enables &DRM_CLIENT_CAP_UNIVERSAL_PLANES and
+ * &DRM_CLIENT_CAP_ASPECT_RATIO.
+ *
+ * If the driver doesn't support atomic mode-setting, enabling this capability
+ * will fail with -EOPNOTSUPP.
+ *
+ * This capability has been introduced in kernel version 4.0. Starting from
+ * kernel version 4.2, this capability is always supported for atomic-capable
+ * drivers.
*/
#define DRM_CLIENT_CAP_ATOMIC 3
@@ -680,6 +811,10 @@ struct drm_get_cap {
* DRM_CLIENT_CAP_ASPECT_RATIO
*
* If set to 1, the DRM core will provide aspect ratio information in modes.
+ * See ``DRM_MODE_FLAG_PIC_AR_*``.
+ *
+ * This capability is always supported for all drivers starting from kernel
+ * version 4.18.
*/
#define DRM_CLIENT_CAP_ASPECT_RATIO 4
@@ -687,12 +822,15 @@ struct drm_get_cap {
* DRM_CLIENT_CAP_WRITEBACK_CONNECTORS
*
* If set to 1, the DRM core will expose special connectors to be used for
- * writing back to memory the scene setup in the commit. Depends on client
- * also supporting DRM_CLIENT_CAP_ATOMIC
+ * writing back to memory the scene setup in the commit. The client must enable
+ * &DRM_CLIENT_CAP_ATOMIC first.
+ *
+ * This capability is always supported for atomic-capable drivers starting from
+ * kernel version 4.19.
*/
#define DRM_CLIENT_CAP_WRITEBACK_CONNECTORS 5
-/** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */
+/* DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */
struct drm_set_client_cap {
__u64 capability;
__u64 value;
@@ -906,6 +1044,16 @@ extern "C" {
#define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob)
#define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd)
#define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd)
+/**
+ * DRM_IOCTL_MODE_RMFB - Remove a framebuffer.
+ *
+ * This removes a framebuffer previously added via ADDFB/ADDFB2. The IOCTL
+ * argument is a framebuffer object ID.
+ *
+ * Warning: removing a framebuffer currently in-use on an enabled plane will
+ * disable that plane. The CRTC the plane is linked to may also be disabled
+ * (depending on driver capabilities).
+ */
#define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, unsigned int)
#define DRM_IOCTL_MODE_PAGE_FLIP DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip)
#define DRM_IOCTL_MODE_DIRTYFB DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd)
@@ -944,7 +1092,7 @@ extern "C" {
#define DRM_IOCTL_MODE_GETFB2 DRM_IOWR(0xCE, struct drm_mode_fb_cmd2)
-/**
+/*
* Device specific ioctls should only be in their respective headers
* The device specific ioctl range is from 0x40 to 0x9f.
* Generic IOCTLS restart at 0xA0.
@@ -955,7 +1103,7 @@ extern "C" {
#define DRM_COMMAND_BASE 0x40
#define DRM_COMMAND_END 0xA0
-/**
+/*
* Header for events written back to userspace on the drm fd. The
* type defines the type of event, the length specifies the total
* length of the event (including the header), and user_data is
diff --git a/lib/mesa/include/drm-uapi/drm_fourcc.h b/lib/mesa/include/drm-uapi/drm_fourcc.h
index f76de49c7..957c7be29 100644
--- a/lib/mesa/include/drm-uapi/drm_fourcc.h
+++ b/lib/mesa/include/drm-uapi/drm_fourcc.h
@@ -168,6 +168,13 @@ extern "C" {
#define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
#define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
+/* 64 bpp RGB */
+#define DRM_FORMAT_XRGB16161616 fourcc_code('X', 'R', '4', '8') /* [63:0] x:R:G:B 16:16:16:16 little endian */
+#define DRM_FORMAT_XBGR16161616 fourcc_code('X', 'B', '4', '8') /* [63:0] x:B:G:R 16:16:16:16 little endian */
+
+#define DRM_FORMAT_ARGB16161616 fourcc_code('A', 'R', '4', '8') /* [63:0] A:R:G:B 16:16:16:16 little endian */
+#define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */
+
/*
* Floating point 64bpp RGB
* IEEE 754-2008 binary16 half-precision float
@@ -729,7 +736,7 @@ extern "C" {
* which corresponds to the "generic" kind used for simple single-sample
* uncompressed color formats on Fermi - Volta GPUs.
*/
-static inline __u64
+static __inline__ __u64
drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
{
if (!(modifier & 0x10) || (modifier & (0xff << 12)))
@@ -893,9 +900,9 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
/*
* The top 4 bits (out of the 56 bits alloted for specifying vendor specific
- * modifiers) denote the category for modifiers. Currently we have only two
- * categories of modifiers ie AFBC and MISC. We can have a maximum of sixteen
- * different categories.
+ * modifiers) denote the category for modifiers. Currently we have three
+ * categories of modifiers ie AFBC, MISC and AFRC. We can have a maximum of
+ * sixteen different categories.
*/
#define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \
fourcc_mod_code(ARM, ((__u64)(__type) << 52) | ((__val) & 0x000fffffffffffffULL))
@@ -1011,6 +1018,109 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
#define AFBC_FORMAT_MOD_USM (1ULL << 12)
/*
+ * Arm Fixed-Rate Compression (AFRC) modifiers
+ *
+ * AFRC is a proprietary fixed rate image compression protocol and format,
+ * designed to provide guaranteed bandwidth and memory footprint
+ * reductions in graphics and media use-cases.
+ *
+ * AFRC buffers consist of one or more planes, with the same components
+ * and meaning as an uncompressed buffer using the same pixel format.
+ *
+ * Within each plane, the pixel/luma/chroma values are grouped into
+ * "coding unit" blocks which are individually compressed to a
+ * fixed size (in bytes). All coding units within a given plane of a buffer
+ * store the same number of values, and have the same compressed size.
+ *
+ * The coding unit size is configurable, allowing different rates of compression.
+ *
+ * The start of each AFRC buffer plane must be aligned to an alignment granule which
+ * depends on the coding unit size.
+ *
+ * Coding Unit Size Plane Alignment
+ * ---------------- ---------------
+ * 16 bytes 1024 bytes
+ * 24 bytes 512 bytes
+ * 32 bytes 2048 bytes
+ *
+ * Coding units are grouped into paging tiles. AFRC buffer dimensions must be aligned
+ * to a multiple of the paging tile dimensions.
+ * The dimensions of each paging tile depend on whether the buffer is optimised for
+ * scanline (SCAN layout) or rotated (ROT layout) access.
+ *
+ * Layout Paging Tile Width Paging Tile Height
+ * ------ ----------------- ------------------
+ * SCAN 16 coding units 4 coding units
+ * ROT 8 coding units 8 coding units
+ *
+ * The dimensions of each coding unit depend on the number of components
+ * in the compressed plane and whether the buffer is optimised for
+ * scanline (SCAN layout) or rotated (ROT layout) access.
+ *
+ * Number of Components in Plane Layout Coding Unit Width Coding Unit Height
+ * ----------------------------- --------- ----------------- ------------------
+ * 1 SCAN 16 samples 4 samples
+ * Example: 16x4 luma samples in a 'Y' plane
+ * 16x4 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
+ * ----------------------------- --------- ----------------- ------------------
+ * 1 ROT 8 samples 8 samples
+ * Example: 8x8 luma samples in a 'Y' plane
+ * 8x8 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
+ * ----------------------------- --------- ----------------- ------------------
+ * 2 DONT CARE 8 samples 4 samples
+ * Example: 8x4 chroma pairs in the 'UV' plane of a semi-planar YUV buffer
+ * ----------------------------- --------- ----------------- ------------------
+ * 3 DONT CARE 4 samples 4 samples
+ * Example: 4x4 pixels in an RGB buffer without alpha
+ * ----------------------------- --------- ----------------- ------------------
+ * 4 DONT CARE 4 samples 4 samples
+ * Example: 4x4 pixels in an RGB buffer with alpha
+ */
+
+#define DRM_FORMAT_MOD_ARM_TYPE_AFRC 0x02
+
+#define DRM_FORMAT_MOD_ARM_AFRC(__afrc_mode) \
+ DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFRC, __afrc_mode)
+
+/*
+ * AFRC coding unit size modifier.
+ *
+ * Indicates the number of bytes used to store each compressed coding unit for
+ * one or more planes in an AFRC encoded buffer. The coding unit size for chrominance
+ * is the same for both Cb and Cr, which may be stored in separate planes.
+ *
+ * AFRC_FORMAT_MOD_CU_SIZE_P0 indicates the number of bytes used to store
+ * each compressed coding unit in the first plane of the buffer. For RGBA buffers
+ * this is the only plane, while for semi-planar and fully-planar YUV buffers,
+ * this corresponds to the luma plane.
+ *
+ * AFRC_FORMAT_MOD_CU_SIZE_P12 indicates the number of bytes used to store
+ * each compressed coding unit in the second and third planes in the buffer.
+ * For semi-planar and fully-planar YUV buffers, this corresponds to the chroma plane(s).
+ *
+ * For single-plane buffers, AFRC_FORMAT_MOD_CU_SIZE_P0 must be specified
+ * and AFRC_FORMAT_MOD_CU_SIZE_P12 must be zero.
+ * For semi-planar and fully-planar buffers, both AFRC_FORMAT_MOD_CU_SIZE_P0 and
+ * AFRC_FORMAT_MOD_CU_SIZE_P12 must be specified.
+ */
+#define AFRC_FORMAT_MOD_CU_SIZE_MASK 0xf
+#define AFRC_FORMAT_MOD_CU_SIZE_16 (1ULL)
+#define AFRC_FORMAT_MOD_CU_SIZE_24 (2ULL)
+#define AFRC_FORMAT_MOD_CU_SIZE_32 (3ULL)
+
+#define AFRC_FORMAT_MOD_CU_SIZE_P0(__afrc_cu_size) (__afrc_cu_size)
+#define AFRC_FORMAT_MOD_CU_SIZE_P12(__afrc_cu_size) ((__afrc_cu_size) << 4)
+
+/*
+ * AFRC scanline memory layout.
+ *
+ * Indicates if the buffer uses the scanline-optimised layout
+ * for an AFRC encoded buffer, otherwise, it uses the rotation-optimised layout.
+ * The memory layout is the same for all planes.
+ */
+#define AFRC_FORMAT_MOD_LAYOUT_SCAN (1ULL << 8)
+
+/*
* Arm 16x16 Block U-Interleaved modifier
*
* This is used by Arm Mali Utgard and Midgard GPUs. It divides the image
diff --git a/lib/mesa/include/drm-uapi/drm_mode.h b/lib/mesa/include/drm-uapi/drm_mode.h
index 863eda048..90c55383f 100644
--- a/lib/mesa/include/drm-uapi/drm_mode.h
+++ b/lib/mesa/include/drm-uapi/drm_mode.h
@@ -218,6 +218,27 @@ extern "C" {
#define DRM_MODE_CONTENT_PROTECTION_DESIRED 1
#define DRM_MODE_CONTENT_PROTECTION_ENABLED 2
+/**
+ * struct drm_mode_modeinfo - Display mode information.
+ * @clock: pixel clock in kHz
+ * @hdisplay: horizontal display size
+ * @hsync_start: horizontal sync start
+ * @hsync_end: horizontal sync end
+ * @htotal: horizontal total size
+ * @hskew: horizontal skew
+ * @vdisplay: vertical display size
+ * @vsync_start: vertical sync start
+ * @vsync_end: vertical sync end
+ * @vtotal: vertical total size
+ * @vscan: vertical scan
+ * @vrefresh: approximate vertical refresh rate in Hz
+ * @flags: bitmask of misc. flags, see DRM_MODE_FLAG_* defines
+ * @type: bitmask of type flags, see DRM_MODE_TYPE_* defines
+ * @name: string describing the mode resolution
+ *
+ * This is the user-space API display mode information structure. For the
+ * kernel version see struct drm_display_mode.
+ */
struct drm_mode_modeinfo {
__u32 clock;
__u16 hdisplay;
@@ -291,16 +312,48 @@ struct drm_mode_set_plane {
__u32 src_w;
};
+/**
+ * struct drm_mode_get_plane - Get plane metadata.
+ *
+ * Userspace can perform a GETPLANE ioctl to retrieve information about a
+ * plane.
+ *
+ * To retrieve the number of formats supported, set @count_format_types to zero
+ * and call the ioctl. @count_format_types will be updated with the value.
+ *
+ * To retrieve these formats, allocate an array with the memory needed to store
+ * @count_format_types formats. Point @format_type_ptr to this array and call
+ * the ioctl again (with @count_format_types still set to the value returned in
+ * the first ioctl call).
+ */
struct drm_mode_get_plane {
+ /**
+ * @plane_id: Object ID of the plane whose information should be
+ * retrieved. Set by caller.
+ */
__u32 plane_id;
+ /** @crtc_id: Object ID of the current CRTC. */
__u32 crtc_id;
+ /** @fb_id: Object ID of the current fb. */
__u32 fb_id;
+ /**
+ * @possible_crtcs: Bitmask of CRTC's compatible with the plane. CRTC's
+ * are created and they receive an index, which corresponds to their
+ * position in the bitmask. Bit N corresponds to
+ * :ref:`CRTC index<crtc_index>` N.
+ */
__u32 possible_crtcs;
+ /** @gamma_size: Never used. */
__u32 gamma_size;
+ /** @count_format_types: Number of formats. */
__u32 count_format_types;
+ /**
+ * @format_type_ptr: Pointer to ``__u32`` array of formats that are
+ * supported by the plane. These formats do not require modifiers.
+ */
__u64 format_type_ptr;
};
@@ -367,28 +420,95 @@ enum drm_mode_subconnector {
#define DRM_MODE_CONNECTOR_DPI 17
#define DRM_MODE_CONNECTOR_WRITEBACK 18
#define DRM_MODE_CONNECTOR_SPI 19
+#define DRM_MODE_CONNECTOR_USB 20
+/**
+ * struct drm_mode_get_connector - Get connector metadata.
+ *
+ * User-space can perform a GETCONNECTOR ioctl to retrieve information about a
+ * connector. User-space is expected to retrieve encoders, modes and properties
+ * by performing this ioctl at least twice: the first time to retrieve the
+ * number of elements, the second time to retrieve the elements themselves.
+ *
+ * To retrieve the number of elements, set @count_props and @count_encoders to
+ * zero, set @count_modes to 1, and set @modes_ptr to a temporary struct
+ * drm_mode_modeinfo element.
+ *
+ * To retrieve the elements, allocate arrays for @encoders_ptr, @modes_ptr,
+ * @props_ptr and @prop_values_ptr, then set @count_modes, @count_props and
+ * @count_encoders to their capacity.
+ *
+ * Performing the ioctl only twice may be racy: the number of elements may have
+ * changed with a hotplug event in-between the two ioctls. User-space is
+ * expected to retry the last ioctl until the number of elements stabilizes.
+ * The kernel won't fill any array which doesn't have the expected length.
+ *
+ * **Force-probing a connector**
+ *
+ * If the @count_modes field is set to zero and the DRM client is the current
+ * DRM master, the kernel will perform a forced probe on the connector to
+ * refresh the connector status, modes and EDID. A forced-probe can be slow,
+ * might cause flickering and the ioctl will block.
+ *
+ * User-space needs to force-probe connectors to ensure their metadata is
+ * up-to-date at startup and after receiving a hot-plug event. User-space
+ * may perform a forced-probe when the user explicitly requests it. User-space
+ * shouldn't perform a forced-probe in other situations.
+ */
struct drm_mode_get_connector {
-
+ /** @encoders_ptr: Pointer to ``__u32`` array of object IDs. */
__u64 encoders_ptr;
+ /** @modes_ptr: Pointer to struct drm_mode_modeinfo array. */
__u64 modes_ptr;
+ /** @props_ptr: Pointer to ``__u32`` array of property IDs. */
__u64 props_ptr;
+ /** @prop_values_ptr: Pointer to ``__u64`` array of property values. */
__u64 prop_values_ptr;
+ /** @count_modes: Number of modes. */
__u32 count_modes;
+ /** @count_props: Number of properties. */
__u32 count_props;
+ /** @count_encoders: Number of encoders. */
__u32 count_encoders;
- __u32 encoder_id; /**< Current Encoder */
- __u32 connector_id; /**< Id */
+ /** @encoder_id: Object ID of the current encoder. */
+ __u32 encoder_id;
+ /** @connector_id: Object ID of the connector. */
+ __u32 connector_id;
+ /**
+ * @connector_type: Type of the connector.
+ *
+ * See DRM_MODE_CONNECTOR_* defines.
+ */
__u32 connector_type;
+ /**
+ * @connector_type_id: Type-specific connector number.
+ *
+ * This is not an object ID. This is a per-type connector number. Each
+ * (type, type_id) combination is unique across all connectors of a DRM
+ * device.
+ */
__u32 connector_type_id;
+ /**
+ * @connection: Status of the connector.
+ *
+ * See enum drm_connector_status.
+ */
__u32 connection;
- __u32 mm_width; /**< width in millimeters */
- __u32 mm_height; /**< height in millimeters */
+ /** @mm_width: Width of the connected sink in millimeters. */
+ __u32 mm_width;
+ /** @mm_height: Height of the connected sink in millimeters. */
+ __u32 mm_height;
+ /**
+ * @subpixel: Subpixel order of the connected sink.
+ *
+ * See enum subpixel_order.
+ */
__u32 subpixel;
+ /** @pad: Padding, must be zero. */
__u32 pad;
};
@@ -421,22 +541,74 @@ struct drm_mode_get_connector {
*/
#define DRM_MODE_PROP_ATOMIC 0x80000000
+/**
+ * struct drm_mode_property_enum - Description for an enum/bitfield entry.
+ * @value: numeric value for this enum entry.
+ * @name: symbolic name for this enum entry.
+ *
+ * See struct drm_property_enum for details.
+ */
struct drm_mode_property_enum {
__u64 value;
char name[DRM_PROP_NAME_LEN];
};
+/**
+ * struct drm_mode_get_property - Get property metadata.
+ *
+ * User-space can perform a GETPROPERTY ioctl to retrieve information about a
+ * property. The same property may be attached to multiple objects, see
+ * "Modeset Base Object Abstraction".
+ *
+ * The meaning of the @values_ptr field changes depending on the property type.
+ * See &drm_property.flags for more details.
+ *
+ * The @enum_blob_ptr and @count_enum_blobs fields are only meaningful when the
+ * property has the type &DRM_MODE_PROP_ENUM or &DRM_MODE_PROP_BITMASK. For
+ * backwards compatibility, the kernel will always set @count_enum_blobs to
+ * zero when the property has the type &DRM_MODE_PROP_BLOB. User-space must
+ * ignore these two fields if the property has a different type.
+ *
+ * User-space is expected to retrieve values and enums by performing this ioctl
+ * at least twice: the first time to retrieve the number of elements, the
+ * second time to retrieve the elements themselves.
+ *
+ * To retrieve the number of elements, set @count_values and @count_enum_blobs
+ * to zero, then call the ioctl. @count_values will be updated with the number
+ * of elements. If the property has the type &DRM_MODE_PROP_ENUM or
+ * &DRM_MODE_PROP_BITMASK, @count_enum_blobs will be updated as well.
+ *
+ * To retrieve the elements themselves, allocate an array for @values_ptr and
+ * set @count_values to its capacity. If the property has the type
+ * &DRM_MODE_PROP_ENUM or &DRM_MODE_PROP_BITMASK, allocate an array for
+ * @enum_blob_ptr and set @count_enum_blobs to its capacity. Calling the ioctl
+ * again will fill the arrays.
+ */
struct drm_mode_get_property {
- __u64 values_ptr; /* values and blob lengths */
- __u64 enum_blob_ptr; /* enum and blob id ptrs */
+ /** @values_ptr: Pointer to a ``__u64`` array. */
+ __u64 values_ptr;
+ /** @enum_blob_ptr: Pointer to a struct drm_mode_property_enum array. */
+ __u64 enum_blob_ptr;
+ /**
+ * @prop_id: Object ID of the property which should be retrieved. Set
+ * by the caller.
+ */
__u32 prop_id;
+ /**
+ * @flags: ``DRM_MODE_PROP_*`` bitfield. See &drm_property.flags for
+ * a definition of the flags.
+ */
__u32 flags;
+ /**
+ * @name: Symbolic property name. User-space should use this field to
+ * recognize properties.
+ */
char name[DRM_PROP_NAME_LEN];
+ /** @count_values: Number of elements in @values_ptr. */
__u32 count_values;
- /* This is only used to count enum values, not blobs. The _blobs is
- * simply because of a historical reason, i.e. backwards compat. */
+ /** @count_enum_blobs: Number of elements in @enum_blob_ptr. */
__u32 count_enum_blobs;
};
@@ -904,26 +1076,31 @@ struct drm_format_modifier {
};
/**
- * struct drm_mode_create_blob - Create New block property
- * @data: Pointer to data to copy.
- * @length: Length of data to copy.
- * @blob_id: new property ID.
+ * struct drm_mode_create_blob - Create New blob property
+ *
* Create a new 'blob' data property, copying length bytes from data pointer,
* and returning new blob ID.
*/
struct drm_mode_create_blob {
- /** Pointer to data to copy. */
+ /** @data: Pointer to data to copy. */
__u64 data;
- /** Length of data to copy. */
+ /** @length: Length of data to copy. */
__u32 length;
- /** Return: new property ID. */
+ /** @blob_id: Return: new property ID. */
__u32 blob_id;
};
/**
* struct drm_mode_destroy_blob - Destroy user blob
* @blob_id: blob_id to destroy
+ *
* Destroy a user-created blob property.
+ *
+ * User-space can release blobs as soon as they do not need to refer to them by
+ * their blob object ID. For instance, if you are using a MODE_ID blob in an
+ * atomic commit and you will not make another commit re-using the same ID, you
+ * can destroy the blob as soon as the commit has been issued, without waiting
+ * for it to complete.
*/
struct drm_mode_destroy_blob {
__u32 blob_id;
@@ -931,36 +1108,32 @@ struct drm_mode_destroy_blob {
/**
* struct drm_mode_create_lease - Create lease
- * @object_ids: Pointer to array of object ids.
- * @object_count: Number of object ids.
- * @flags: flags for new FD.
- * @lessee_id: unique identifier for lessee.
- * @fd: file descriptor to new drm_master file.
+ *
* Lease mode resources, creating another drm_master.
*/
struct drm_mode_create_lease {
- /** Pointer to array of object ids (__u32) */
+ /** @object_ids: Pointer to array of object ids (__u32) */
__u64 object_ids;
- /** Number of object ids */
+ /** @object_count: Number of object ids */
__u32 object_count;
- /** flags for new FD (O_CLOEXEC, etc) */
+ /** @flags: flags for new FD (O_CLOEXEC, etc) */
__u32 flags;
- /** Return: unique identifier for lessee. */
+ /** @lessee_id: Return: unique identifier for lessee. */
__u32 lessee_id;
- /** Return: file descriptor to new drm_master file */
+ /** @fd: Return: file descriptor to new drm_master file */
__u32 fd;
};
/**
* struct drm_mode_list_lessees - List lessees
- * @count_lessees: Number of lessees.
- * @pad: pad.
- * @lessees_ptr: Pointer to lessess.
- * List lesses from a drm_master
+ *
+ * List lesses from a drm_master.
*/
struct drm_mode_list_lessees {
- /** Number of lessees.
+ /**
+ * @count_lessees: Number of lessees.
+ *
* On input, provides length of the array.
* On output, provides total number. No
* more than the input number will be written
@@ -968,23 +1141,26 @@ struct drm_mode_list_lessees {
* the size and then the data.
*/
__u32 count_lessees;
+ /** @pad: Padding. */
__u32 pad;
- /** Pointer to lessees.
- * pointer to __u64 array of lessee ids
+ /**
+ * @lessees_ptr: Pointer to lessees.
+ *
+ * Pointer to __u64 array of lessee ids
*/
__u64 lessees_ptr;
};
/**
* struct drm_mode_get_lease - Get Lease
- * @count_objects: Number of leased objects.
- * @pad: pad.
- * @objects_ptr: Pointer to objects.
- * Get leased objects
+ *
+ * Get leased objects.
*/
struct drm_mode_get_lease {
- /** Number of leased objects.
+ /**
+ * @count_objects: Number of leased objects.
+ *
* On input, provides length of the array.
* On output, provides total number. No
* more than the input number will be written
@@ -992,22 +1168,22 @@ struct drm_mode_get_lease {
* the size and then the data.
*/
__u32 count_objects;
+ /** @pad: Padding. */
__u32 pad;
- /** Pointer to objects.
- * pointer to __u32 array of object ids
+ /**
+ * @objects_ptr: Pointer to objects.
+ *
+ * Pointer to __u32 array of object ids.
*/
__u64 objects_ptr;
};
/**
* struct drm_mode_revoke_lease - Revoke lease
- * @lessee_id: Unique ID of lessee.
- * Revoke lease
*/
struct drm_mode_revoke_lease {
- /** Unique ID of lessee
- */
+ /** @lessee_id: Unique ID of lessee */
__u32 lessee_id;
};
diff --git a/lib/mesa/include/drm-uapi/i915_drm.h b/lib/mesa/include/drm-uapi/i915_drm.h
index ef696d1a5..c788a1ab4 100644
--- a/lib/mesa/include/drm-uapi/i915_drm.h
+++ b/lib/mesa/include/drm-uapi/i915_drm.h
@@ -62,8 +62,8 @@ extern "C" {
#define I915_ERROR_UEVENT "ERROR"
#define I915_RESET_UEVENT "RESET"
-/*
- * i915_user_extension: Base class for defining a chain of extensions
+/**
+ * struct i915_user_extension - Base class for defining a chain of extensions
*
* Many interfaces need to grow over time. In most cases we can simply
* extend the struct and have userspace pass in more data. Another option,
@@ -76,12 +76,58 @@ extern "C" {
* increasing complexity, and for large parts of that interface to be
* entirely optional. The downside is more pointer chasing; chasing across
* the boundary with pointers encapsulated inside u64.
+ *
+ * Example chaining:
+ *
+ * .. code-block:: C
+ *
+ * struct i915_user_extension ext3 {
+ * .next_extension = 0, // end
+ * .name = ...,
+ * };
+ * struct i915_user_extension ext2 {
+ * .next_extension = (uintptr_t)&ext3,
+ * .name = ...,
+ * };
+ * struct i915_user_extension ext1 {
+ * .next_extension = (uintptr_t)&ext2,
+ * .name = ...,
+ * };
+ *
+ * Typically the struct i915_user_extension would be embedded in some uAPI
+ * struct, and in this case we would feed it the head of the chain(i.e ext1),
+ * which would then apply all of the above extensions.
+ *
*/
struct i915_user_extension {
+ /**
+ * @next_extension:
+ *
+ * Pointer to the next struct i915_user_extension, or zero if the end.
+ */
__u64 next_extension;
+ /**
+ * @name: Name of the extension.
+ *
+ * Note that the name here is just some integer.
+ *
+ * Also note that the name space for this is not global for the whole
+ * driver, but rather its scope/meaning is limited to the specific piece
+ * of uAPI which has embedded the struct i915_user_extension.
+ */
__u32 name;
- __u32 flags; /* All undefined bits must be zero. */
- __u32 rsvd[4]; /* Reserved for future use; must be zero. */
+ /**
+ * @flags: MBZ
+ *
+ * All undefined bits must be zero.
+ */
+ __u32 flags;
+ /**
+ * @rsvd: MBZ
+ *
+ * Reserved for future use; must be zero.
+ */
+ __u32 rsvd[4];
};
/*
@@ -177,8 +223,9 @@ enum drm_i915_pmu_engine_sample {
#define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1)
#define I915_PMU_INTERRUPTS __I915_PMU_OTHER(2)
#define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3)
+#define I915_PMU_SOFTWARE_GT_AWAKE_TIME __I915_PMU_OTHER(4)
-#define I915_PMU_LAST I915_PMU_RC6_RESIDENCY
+#define I915_PMU_LAST /* Deprecated - do not use */ I915_PMU_RC6_RESIDENCY
/* Each region is a minimum of 16k, and there are at most 255 of them.
*/
@@ -359,6 +406,7 @@ typedef struct _drm_i915_sarea {
#define DRM_I915_QUERY 0x39
#define DRM_I915_GEM_VM_CREATE 0x3a
#define DRM_I915_GEM_VM_DESTROY 0x3b
+#define DRM_I915_GEM_CREATE_EXT 0x3c
/* Must be kept compact -- no holes */
#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
@@ -391,6 +439,7 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
+#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE_EXT, struct drm_i915_gem_create_ext)
#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
@@ -523,6 +572,15 @@ typedef struct drm_i915_irq_wait {
#define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2)
#define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3)
#define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4)
+/*
+ * Indicates the 2k user priority levels are statically mapped into 3 buckets as
+ * follows:
+ *
+ * -1k to -1 Low priority
+ * 0 Normal priority
+ * 1 to 1k Highest priority
+ */
+#define I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP (1ul << 5)
#define I915_PARAM_HUC_STATUS 42
@@ -625,6 +683,9 @@ typedef struct drm_i915_irq_wait {
*/
#define I915_PARAM_HAS_EXEC_TIMELINE_FENCES 55
+/* Query if the kernel supports the I915_USERPTR_PROBE flag. */
+#define I915_PARAM_HAS_USERPTR_PROBE 56
+
/* Must be kept compact -- no holes and well documented */
typedef struct drm_i915_getparam {
@@ -800,45 +861,113 @@ struct drm_i915_gem_mmap_gtt {
__u64 offset;
};
+/**
+ * struct drm_i915_gem_mmap_offset - Retrieve an offset so we can mmap this buffer object.
+ *
+ * This struct is passed as argument to the `DRM_IOCTL_I915_GEM_MMAP_OFFSET` ioctl,
+ * and is used to retrieve the fake offset to mmap an object specified by &handle.
+ *
+ * The legacy way of using `DRM_IOCTL_I915_GEM_MMAP` is removed on gen12+.
+ * `DRM_IOCTL_I915_GEM_MMAP_GTT` is an older supported alias to this struct, but will behave
+ * as setting the &extensions to 0, and &flags to `I915_MMAP_OFFSET_GTT`.
+ */
struct drm_i915_gem_mmap_offset {
- /** Handle for the object being mapped. */
+ /** @handle: Handle for the object being mapped. */
__u32 handle;
+ /** @pad: Must be zero */
__u32 pad;
/**
- * Fake offset to use for subsequent mmap call
+ * @offset: The fake offset to use for subsequent mmap call
*
* This is a fixed-size type for 32/64 compatibility.
*/
__u64 offset;
/**
- * Flags for extended behaviour.
+ * @flags: Flags for extended behaviour.
+ *
+ * It is mandatory that one of the `MMAP_OFFSET` types
+ * should be included:
*
- * It is mandatory that one of the MMAP_OFFSET types
- * (GTT, WC, WB, UC, etc) should be included.
+ * - `I915_MMAP_OFFSET_GTT`: Use mmap with the object bound to GTT. (Write-Combined)
+ * - `I915_MMAP_OFFSET_WC`: Use Write-Combined caching.
+ * - `I915_MMAP_OFFSET_WB`: Use Write-Back caching.
+ * - `I915_MMAP_OFFSET_FIXED`: Use object placement to determine caching.
+ *
+ * On devices with local memory `I915_MMAP_OFFSET_FIXED` is the only valid
+ * type. On devices without local memory, this caching mode is invalid.
+ *
+ * As caching mode when specifying `I915_MMAP_OFFSET_FIXED`, WC or WB will
+ * be used, depending on the object placement on creation. WB will be used
+ * when the object can only exist in system memory, WC otherwise.
*/
__u64 flags;
-#define I915_MMAP_OFFSET_GTT 0
-#define I915_MMAP_OFFSET_WC 1
-#define I915_MMAP_OFFSET_WB 2
-#define I915_MMAP_OFFSET_UC 3
- /*
- * Zero-terminated chain of extensions.
+#define I915_MMAP_OFFSET_GTT 0
+#define I915_MMAP_OFFSET_WC 1
+#define I915_MMAP_OFFSET_WB 2
+#define I915_MMAP_OFFSET_UC 3
+#define I915_MMAP_OFFSET_FIXED 4
+
+ /**
+ * @extensions: Zero-terminated chain of extensions.
*
* No current extensions defined; mbz.
*/
__u64 extensions;
};
+/**
+ * struct drm_i915_gem_set_domain - Adjust the objects write or read domain, in
+ * preparation for accessing the pages via some CPU domain.
+ *
+ * Specifying a new write or read domain will flush the object out of the
+ * previous domain(if required), before then updating the objects domain
+ * tracking with the new domain.
+ *
+ * Note this might involve waiting for the object first if it is still active on
+ * the GPU.
+ *
+ * Supported values for @read_domains and @write_domain:
+ *
+ * - I915_GEM_DOMAIN_WC: Uncached write-combined domain
+ * - I915_GEM_DOMAIN_CPU: CPU cache domain
+ * - I915_GEM_DOMAIN_GTT: Mappable aperture domain
+ *
+ * All other domains are rejected.
+ *
+ * Note that for discrete, starting from DG1, this is no longer supported, and
+ * is instead rejected. On such platforms the CPU domain is effectively static,
+ * where we also only support a single &drm_i915_gem_mmap_offset cache mode,
+ * which can't be set explicitly and instead depends on the object placements,
+ * as per the below.
+ *
+ * Implicit caching rules, starting from DG1:
+ *
+ * - If any of the object placements (see &drm_i915_gem_create_ext_memory_regions)
+ * contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and
+ * mapped as write-combined only.
+ *
+ * - Everything else is always allocated and mapped as write-back, with the
+ * guarantee that everything is also coherent with the GPU.
+ *
+ * Note that this is likely to change in the future again, where we might need
+ * more flexibility on future devices, so making this all explicit as part of a
+ * new &drm_i915_gem_create_ext extension is probable.
+ */
struct drm_i915_gem_set_domain {
- /** Handle for the object */
+ /** @handle: Handle for the object. */
__u32 handle;
- /** New read domains */
+ /** @read_domains: New read domains. */
__u32 read_domains;
- /** New write domain */
+ /**
+ * @write_domain: New write domain.
+ *
+ * Note that having something in the write domain implies it's in the
+ * read domain, and only that read domain.
+ */
__u32 write_domain;
};
@@ -942,6 +1071,7 @@ struct drm_i915_gem_exec_object {
__u64 offset;
};
+/* DRM_IOCTL_I915_GEM_EXECBUFFER was removed in Linux 5.13 */
struct drm_i915_gem_execbuffer {
/**
* List of buffers to be validated with their relocations to be
@@ -1052,12 +1182,12 @@ struct drm_i915_gem_exec_fence {
__u32 flags;
};
-/**
+/*
* See drm_i915_gem_execbuffer_ext_timeline_fences.
*/
#define DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES 0
-/**
+/*
* This structure describes an array of drm_syncobj and associated points for
* timeline variants of drm_syncobj. It is invalid to append this structure to
* the execbuf if I915_EXEC_FENCE_ARRAY is set.
@@ -1298,12 +1428,11 @@ struct drm_i915_gem_busy {
* reading from the object simultaneously.
*
* The value of each engine class is the same as specified in the
- * I915_CONTEXT_SET_ENGINES parameter and via perf, i.e.
+ * I915_CONTEXT_PARAM_ENGINES context parameter and via perf, i.e.
* I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc.
- * reported as active itself. Some hardware may have parallel
- * execution engines, e.g. multiple media engines, which are
- * mapped to the same class identifier and so are not separately
- * reported for busyness.
+ * Some hardware may have parallel execution engines, e.g. multiple
+ * media engines, which are mapped to the same class identifier and so
+ * are not separately reported for busyness.
*
* Caveat emptor:
* Only the boolean result of this query is reliable; that is whether
@@ -1314,43 +1443,79 @@ struct drm_i915_gem_busy {
};
/**
- * I915_CACHING_NONE
- *
- * GPU access is not coherent with cpu caches. Default for machines without an
- * LLC.
- */
-#define I915_CACHING_NONE 0
-/**
- * I915_CACHING_CACHED
- *
- * GPU access is coherent with cpu caches and furthermore the data is cached in
- * last-level caches shared between cpu cores and the gpu GT. Default on
- * machines with HAS_LLC.
+ * struct drm_i915_gem_caching - Set or get the caching for given object
+ * handle.
+ *
+ * Allow userspace to control the GTT caching bits for a given object when the
+ * object is later mapped through the ppGTT(or GGTT on older platforms lacking
+ * ppGTT support, or if the object is used for scanout). Note that this might
+ * require unbinding the object from the GTT first, if its current caching value
+ * doesn't match.
+ *
+ * Note that this all changes on discrete platforms, starting from DG1, the
+ * set/get caching is no longer supported, and is now rejected. Instead the CPU
+ * caching attributes(WB vs WC) will become an immutable creation time property
+ * for the object, along with the GTT caching level. For now we don't expose any
+ * new uAPI for this, instead on DG1 this is all implicit, although this largely
+ * shouldn't matter since DG1 is coherent by default(without any way of
+ * controlling it).
+ *
+ * Implicit caching rules, starting from DG1:
+ *
+ * - If any of the object placements (see &drm_i915_gem_create_ext_memory_regions)
+ * contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and
+ * mapped as write-combined only.
+ *
+ * - Everything else is always allocated and mapped as write-back, with the
+ * guarantee that everything is also coherent with the GPU.
+ *
+ * Note that this is likely to change in the future again, where we might need
+ * more flexibility on future devices, so making this all explicit as part of a
+ * new &drm_i915_gem_create_ext extension is probable.
+ *
+ * Side note: Part of the reason for this is that changing the at-allocation-time CPU
+ * caching attributes for the pages might be required(and is expensive) if we
+ * need to then CPU map the pages later with different caching attributes. This
+ * inconsistent caching behaviour, while supported on x86, is not universally
+ * supported on other architectures. So for simplicity we opt for setting
+ * everything at creation time, whilst also making it immutable, on discrete
+ * platforms.
*/
-#define I915_CACHING_CACHED 1
-/**
- * I915_CACHING_DISPLAY
- *
- * Special GPU caching mode which is coherent with the scanout engines.
- * Transparently falls back to I915_CACHING_NONE on platforms where no special
- * cache mode (like write-through or gfdt flushing) is available. The kernel
- * automatically sets this mode when using a buffer as a scanout target.
- * Userspace can manually set this mode to avoid a costly stall and clflush in
- * the hotpath of drawing the first frame.
- */
-#define I915_CACHING_DISPLAY 2
-
struct drm_i915_gem_caching {
/**
- * Handle of the buffer to set/get the caching level of. */
+ * @handle: Handle of the buffer to set/get the caching level.
+ */
__u32 handle;
/**
- * Cacheing level to apply or return value
+ * @caching: The GTT caching level to apply or possible return value.
+ *
+ * The supported @caching values:
+ *
+ * I915_CACHING_NONE:
*
- * bits0-15 are for generic caching control (i.e. the above defined
- * values). bits16-31 are reserved for platform-specific variations
- * (e.g. l3$ caching on gen7). */
+ * GPU access is not coherent with CPU caches. Default for machines
+ * without an LLC. This means manual flushing might be needed, if we
+ * want GPU access to be coherent.
+ *
+ * I915_CACHING_CACHED:
+ *
+ * GPU access is coherent with CPU caches and furthermore the data is
+ * cached in last-level caches shared between CPU cores and the GPU GT.
+ *
+ * I915_CACHING_DISPLAY:
+ *
+ * Special GPU caching mode which is coherent with the scanout engines.
+ * Transparently falls back to I915_CACHING_NONE on platforms where no
+ * special cache mode (like write-through or gfdt flushing) is
+ * available. The kernel automatically sets this mode when using a
+ * buffer as a scanout target. Userspace can manually set this mode to
+ * avoid a costly stall and clflush in the hotpath of drawing the first
+ * frame.
+ */
+#define I915_CACHING_NONE 0
+#define I915_CACHING_CACHED 1
+#define I915_CACHING_DISPLAY 2
__u32 caching;
};
@@ -1589,6 +1754,10 @@ struct drm_i915_gem_context_param {
__u32 size;
__u64 param;
#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
+/* I915_CONTEXT_PARAM_NO_ZEROMAP has been removed. On the off chance
+ * someone somewhere has attempted to use it, never re-use this context
+ * param number.
+ */
#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
#define I915_CONTEXT_PARAM_GTT_SIZE 0x3
#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4
@@ -1673,24 +1842,8 @@ struct drm_i915_gem_context_param {
*/
#define I915_CONTEXT_PARAM_PERSISTENCE 0xb
-/*
- * I915_CONTEXT_PARAM_RINGSIZE:
- *
- * Sets the size of the CS ringbuffer to use for logical ring contexts. This
- * applies a limit of how many batches can be queued to HW before the caller
- * is blocked due to lack of space for more commands.
- *
- * Only reliably possible to be set prior to first use, i.e. during
- * construction. At any later point, the current execution must be flushed as
- * the ring can only be changed while the context is idle. Note, the ringsize
- * can be specified as a constructor property, see
- * I915_CONTEXT_CREATE_EXT_SETPARAM, but can also be set later if required.
- *
- * Only applies to the current set of engine and lost when those engines
- * are replaced by a new mapping (see I915_CONTEXT_PARAM_ENGINES).
- *
- * Must be between 4 - 512 KiB, in intervals of page size [4 KiB].
- * Default is 16 KiB.
+/* This API has been removed. On the off chance someone somewhere has
+ * attempted to use it, never re-use this context param number.
*/
#define I915_CONTEXT_PARAM_RINGSIZE 0xc
/* Must be kept compact -- no holes and well documented */
@@ -1698,7 +1851,7 @@ struct drm_i915_gem_context_param {
__u64 value;
};
-/**
+/*
* Context SSEU programming
*
* It may be necessary for either functional or performance reason to configure
@@ -1757,6 +1910,69 @@ struct drm_i915_gem_context_param_sseu {
__u32 rsvd;
};
+/**
+ * DOC: Virtual Engine uAPI
+ *
+ * Virtual engine is a concept where userspace is able to configure a set of
+ * physical engines, submit a batch buffer, and let the driver execute it on any
+ * engine from the set as it sees fit.
+ *
+ * This is primarily useful on parts which have multiple instances of a same
+ * class engine, like for example GT3+ Skylake parts with their two VCS engines.
+ *
+ * For instance userspace can enumerate all engines of a certain class using the
+ * previously described `Engine Discovery uAPI`_. After that userspace can
+ * create a GEM context with a placeholder slot for the virtual engine (using
+ * `I915_ENGINE_CLASS_INVALID` and `I915_ENGINE_CLASS_INVALID_NONE` for class
+ * and instance respectively) and finally using the
+ * `I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE` extension place a virtual engine in
+ * the same reserved slot.
+ *
+ * Example of creating a virtual engine and submitting a batch buffer to it:
+ *
+ * .. code-block:: C
+ *
+ * I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(virtual, 2) = {
+ * .base.name = I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE,
+ * .engine_index = 0, // Place this virtual engine into engine map slot 0
+ * .num_siblings = 2,
+ * .engines = { { I915_ENGINE_CLASS_VIDEO, 0 },
+ * { I915_ENGINE_CLASS_VIDEO, 1 }, },
+ * };
+ * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = {
+ * .engines = { { I915_ENGINE_CLASS_INVALID,
+ * I915_ENGINE_CLASS_INVALID_NONE } },
+ * .extensions = to_user_pointer(&virtual), // Chains after load_balance extension
+ * };
+ * struct drm_i915_gem_context_create_ext_setparam p_engines = {
+ * .base = {
+ * .name = I915_CONTEXT_CREATE_EXT_SETPARAM,
+ * },
+ * .param = {
+ * .param = I915_CONTEXT_PARAM_ENGINES,
+ * .value = to_user_pointer(&engines),
+ * .size = sizeof(engines),
+ * },
+ * };
+ * struct drm_i915_gem_context_create_ext create = {
+ * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
+ * .extensions = to_user_pointer(&p_engines);
+ * };
+ *
+ * ctx_id = gem_context_create_ext(drm_fd, &create);
+ *
+ * // Now we have created a GEM context with its engine map containing a
+ * // single virtual engine. Submissions to this slot can go either to
+ * // vcs0 or vcs1, depending on the load balancing algorithm used inside
+ * // the driver. The load balancing is dynamic from one batch buffer to
+ * // another and transparent to userspace.
+ *
+ * ...
+ * execbuf.rsvd1 = ctx_id;
+ * execbuf.flags = 0; // Submits to index 0 which is the virtual engine
+ * gem_execbuf(drm_fd, &execbuf);
+ */
+
/*
* i915_context_engines_load_balance:
*
@@ -1833,6 +2049,61 @@ struct i915_context_engines_bond {
struct i915_engine_class_instance engines[N__]; \
} __attribute__((packed)) name__
+/**
+ * DOC: Context Engine Map uAPI
+ *
+ * Context engine map is a new way of addressing engines when submitting batch-
+ * buffers, replacing the existing way of using identifiers like `I915_EXEC_BLT`
+ * inside the flags field of `struct drm_i915_gem_execbuffer2`.
+ *
+ * To use it created GEM contexts need to be configured with a list of engines
+ * the user is intending to submit to. This is accomplished using the
+ * `I915_CONTEXT_PARAM_ENGINES` parameter and `struct
+ * i915_context_param_engines`.
+ *
+ * For such contexts the `I915_EXEC_RING_MASK` field becomes an index into the
+ * configured map.
+ *
+ * Example of creating such context and submitting against it:
+ *
+ * .. code-block:: C
+ *
+ * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 2) = {
+ * .engines = { { I915_ENGINE_CLASS_RENDER, 0 },
+ * { I915_ENGINE_CLASS_COPY, 0 } }
+ * };
+ * struct drm_i915_gem_context_create_ext_setparam p_engines = {
+ * .base = {
+ * .name = I915_CONTEXT_CREATE_EXT_SETPARAM,
+ * },
+ * .param = {
+ * .param = I915_CONTEXT_PARAM_ENGINES,
+ * .value = to_user_pointer(&engines),
+ * .size = sizeof(engines),
+ * },
+ * };
+ * struct drm_i915_gem_context_create_ext create = {
+ * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
+ * .extensions = to_user_pointer(&p_engines);
+ * };
+ *
+ * ctx_id = gem_context_create_ext(drm_fd, &create);
+ *
+ * // We have now created a GEM context with two engines in the map:
+ * // Index 0 points to rcs0 while index 1 points to bcs0. Other engines
+ * // will not be accessible from this context.
+ *
+ * ...
+ * execbuf.rsvd1 = ctx_id;
+ * execbuf.flags = 0; // Submits to index 0, which is rcs0 for this context
+ * gem_execbuf(drm_fd, &execbuf);
+ *
+ * ...
+ * execbuf.rsvd1 = ctx_id;
+ * execbuf.flags = 1; // Submits to index 0, which is bcs0 for this context
+ * gem_execbuf(drm_fd, &execbuf);
+ */
+
struct i915_context_param_engines {
__u64 extensions; /* linked chain of extension blocks, 0 terminates */
#define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */
@@ -1851,20 +2122,10 @@ struct drm_i915_gem_context_create_ext_setparam {
struct drm_i915_gem_context_param param;
};
-struct drm_i915_gem_context_create_ext_clone {
+/* This API has been removed. On the off chance someone somewhere has
+ * attempted to use it, never re-use this extension number.
+ */
#define I915_CONTEXT_CREATE_EXT_CLONE 1
- struct i915_user_extension base;
- __u32 clone_id;
- __u32 flags;
-#define I915_CONTEXT_CLONE_ENGINES (1u << 0)
-#define I915_CONTEXT_CLONE_FLAGS (1u << 1)
-#define I915_CONTEXT_CLONE_SCHEDATTR (1u << 2)
-#define I915_CONTEXT_CLONE_SSEU (1u << 3)
-#define I915_CONTEXT_CLONE_TIMELINE (1u << 4)
-#define I915_CONTEXT_CLONE_VM (1u << 5)
-#define I915_CONTEXT_CLONE_UNKNOWN -(I915_CONTEXT_CLONE_VM << 1)
- __u64 rsvd;
-};
struct drm_i915_gem_context_destroy {
__u32 ctx_id;
@@ -1936,14 +2197,69 @@ struct drm_i915_reset_stats {
__u32 pad;
};
+/**
+ * struct drm_i915_gem_userptr - Create GEM object from user allocated memory.
+ *
+ * Userptr objects have several restrictions on what ioctls can be used with the
+ * object handle.
+ */
struct drm_i915_gem_userptr {
+ /**
+ * @user_ptr: The pointer to the allocated memory.
+ *
+ * Needs to be aligned to PAGE_SIZE.
+ */
__u64 user_ptr;
+
+ /**
+ * @user_size:
+ *
+ * The size in bytes for the allocated memory. This will also become the
+ * object size.
+ *
+ * Needs to be aligned to PAGE_SIZE, and should be at least PAGE_SIZE,
+ * or larger.
+ */
__u64 user_size;
+
+ /**
+ * @flags:
+ *
+ * Supported flags:
+ *
+ * I915_USERPTR_READ_ONLY:
+ *
+ * Mark the object as readonly, this also means GPU access can only be
+ * readonly. This is only supported on HW which supports readonly access
+ * through the GTT. If the HW can't support readonly access, an error is
+ * returned.
+ *
+ * I915_USERPTR_PROBE:
+ *
+ * Probe the provided @user_ptr range and validate that the @user_ptr is
+ * indeed pointing to normal memory and that the range is also valid.
+ * For example if some garbage address is given to the kernel, then this
+ * should complain.
+ *
+ * Returns -EFAULT if the probe failed.
+ *
+ * Note that this doesn't populate the backing pages, and also doesn't
+ * guarantee that the object will remain valid when the object is
+ * eventually used.
+ *
+ * The kernel supports this feature if I915_PARAM_HAS_USERPTR_PROBE
+ * returns a non-zero value.
+ *
+ * I915_USERPTR_UNSYNCHRONIZED:
+ *
+ * NOT USED. Setting this flag will result in an error.
+ */
__u32 flags;
#define I915_USERPTR_READ_ONLY 0x1
+#define I915_USERPTR_PROBE 0x2
#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
/**
- * Returned handle for the object.
+ * @handle: Returned handle for the object.
*
* Object handles are nonzero.
*/
@@ -2065,7 +2381,7 @@ struct drm_i915_perf_open_param {
__u64 properties_ptr;
};
-/**
+/*
* Enable data capture for a stream that was either opened in a disabled state
* via I915_PERF_FLAG_DISABLED or was later disabled via
* I915_PERF_IOCTL_DISABLE.
@@ -2079,7 +2395,7 @@ struct drm_i915_perf_open_param {
*/
#define I915_PERF_IOCTL_ENABLE _IO('i', 0x0)
-/**
+/*
* Disable data capture for a stream.
*
* It is an error to try and read a stream that is disabled.
@@ -2088,7 +2404,7 @@ struct drm_i915_perf_open_param {
*/
#define I915_PERF_IOCTL_DISABLE _IO('i', 0x1)
-/**
+/*
* Change metrics_set captured by a stream.
*
* If the stream is bound to a specific context, the configuration change
@@ -2101,7 +2417,7 @@ struct drm_i915_perf_open_param {
*/
#define I915_PERF_IOCTL_CONFIG _IO('i', 0x2)
-/**
+/*
* Common to all i915 perf records
*/
struct drm_i915_perf_record_header {
@@ -2149,7 +2465,7 @@ enum drm_i915_perf_record_type {
DRM_I915_PERF_RECORD_MAX /* non-ABI */
};
-/**
+/*
* Structure to upload perf dynamic configuration into the kernel.
*/
struct drm_i915_perf_oa_config {
@@ -2170,53 +2486,95 @@ struct drm_i915_perf_oa_config {
__u64 flex_regs_ptr;
};
+/**
+ * struct drm_i915_query_item - An individual query for the kernel to process.
+ *
+ * The behaviour is determined by the @query_id. Note that exactly what
+ * @data_ptr is also depends on the specific @query_id.
+ */
struct drm_i915_query_item {
+ /** @query_id: The id for this query */
__u64 query_id;
#define DRM_I915_QUERY_TOPOLOGY_INFO 1
#define DRM_I915_QUERY_ENGINE_INFO 2
#define DRM_I915_QUERY_PERF_CONFIG 3
+#define DRM_I915_QUERY_MEMORY_REGIONS 4
/* Must be kept compact -- no holes and well documented */
- /*
+ /**
+ * @length:
+ *
* When set to zero by userspace, this is filled with the size of the
- * data to be written at the data_ptr pointer. The kernel sets this
+ * data to be written at the @data_ptr pointer. The kernel sets this
* value to a negative value to signal an error on a particular query
* item.
*/
__s32 length;
- /*
+ /**
+ * @flags:
+ *
* When query_id == DRM_I915_QUERY_TOPOLOGY_INFO, must be 0.
*
* When query_id == DRM_I915_QUERY_PERF_CONFIG, must be one of the
- * following :
- * - DRM_I915_QUERY_PERF_CONFIG_LIST
- * - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
- * - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
+ * following:
+ *
+ * - DRM_I915_QUERY_PERF_CONFIG_LIST
+ * - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
+ * - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
*/
__u32 flags;
#define DRM_I915_QUERY_PERF_CONFIG_LIST 1
#define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 2
#define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID 3
- /*
- * Data will be written at the location pointed by data_ptr when the
- * value of length matches the length of the data to be written by the
+ /**
+ * @data_ptr:
+ *
+ * Data will be written at the location pointed by @data_ptr when the
+ * value of @length matches the length of the data to be written by the
* kernel.
*/
__u64 data_ptr;
};
+/**
+ * struct drm_i915_query - Supply an array of struct drm_i915_query_item for the
+ * kernel to fill out.
+ *
+ * Note that this is generally a two step process for each struct
+ * drm_i915_query_item in the array:
+ *
+ * 1. Call the DRM_IOCTL_I915_QUERY, giving it our array of struct
+ * drm_i915_query_item, with &drm_i915_query_item.length set to zero. The
+ * kernel will then fill in the size, in bytes, which tells userspace how
+ * memory it needs to allocate for the blob(say for an array of properties).
+ *
+ * 2. Next we call DRM_IOCTL_I915_QUERY again, this time with the
+ * &drm_i915_query_item.data_ptr equal to our newly allocated blob. Note that
+ * the &drm_i915_query_item.length should still be the same as what the
+ * kernel previously set. At this point the kernel can fill in the blob.
+ *
+ * Note that for some query items it can make sense for userspace to just pass
+ * in a buffer/blob equal to or larger than the required size. In this case only
+ * a single ioctl call is needed. For some smaller query items this can work
+ * quite well.
+ *
+ */
struct drm_i915_query {
+ /** @num_items: The number of elements in the @items_ptr array */
__u32 num_items;
- /*
- * Unused for now. Must be cleared to zero.
+ /**
+ * @flags: Unused for now. Must be cleared to zero.
*/
__u32 flags;
- /*
- * This points to an array of num_items drm_i915_query_item structures.
+ /**
+ * @items_ptr:
+ *
+ * Pointer to an array of struct drm_i915_query_item. The number of
+ * array elements is @num_items.
*/
__u64 items_ptr;
};
@@ -2285,26 +2643,96 @@ struct drm_i915_query_topology_info {
};
/**
+ * DOC: Engine Discovery uAPI
+ *
+ * Engine discovery uAPI is a way of enumerating physical engines present in a
+ * GPU associated with an open i915 DRM file descriptor. This supersedes the old
+ * way of using `DRM_IOCTL_I915_GETPARAM` and engine identifiers like
+ * `I915_PARAM_HAS_BLT`.
+ *
+ * The need for this interface came starting with Icelake and newer GPUs, which
+ * started to establish a pattern of having multiple engines of a same class,
+ * where not all instances were always completely functionally equivalent.
+ *
+ * Entry point for this uapi is `DRM_IOCTL_I915_QUERY` with the
+ * `DRM_I915_QUERY_ENGINE_INFO` as the queried item id.
+ *
+ * Example for getting the list of engines:
+ *
+ * .. code-block:: C
+ *
+ * struct drm_i915_query_engine_info *info;
+ * struct drm_i915_query_item item = {
+ * .query_id = DRM_I915_QUERY_ENGINE_INFO;
+ * };
+ * struct drm_i915_query query = {
+ * .num_items = 1,
+ * .items_ptr = (uintptr_t)&item,
+ * };
+ * int err, i;
+ *
+ * // First query the size of the blob we need, this needs to be large
+ * // enough to hold our array of engines. The kernel will fill out the
+ * // item.length for us, which is the number of bytes we need.
+ * //
+ * // Alternatively a large buffer can be allocated straight away enabling
+ * // querying in one pass, in which case item.length should contain the
+ * // length of the provided buffer.
+ * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
+ * if (err) ...
+ *
+ * info = calloc(1, item.length);
+ * // Now that we allocated the required number of bytes, we call the ioctl
+ * // again, this time with the data_ptr pointing to our newly allocated
+ * // blob, which the kernel can then populate with info on all engines.
+ * item.data_ptr = (uintptr_t)&info,
+ *
+ * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
+ * if (err) ...
+ *
+ * // We can now access each engine in the array
+ * for (i = 0; i < info->num_engines; i++) {
+ * struct drm_i915_engine_info einfo = info->engines[i];
+ * u16 class = einfo.engine.class;
+ * u16 instance = einfo.engine.instance;
+ * ....
+ * }
+ *
+ * free(info);
+ *
+ * Each of the enumerated engines, apart from being defined by its class and
+ * instance (see `struct i915_engine_class_instance`), also can have flags and
+ * capabilities defined as documented in i915_drm.h.
+ *
+ * For instance video engines which support HEVC encoding will have the
+ * `I915_VIDEO_CLASS_CAPABILITY_HEVC` capability bit set.
+ *
+ * Engine discovery only fully comes to its own when combined with the new way
+ * of addressing engines when submitting batch buffers using contexts with
+ * engine maps configured.
+ */
+
+/**
* struct drm_i915_engine_info
*
* Describes one engine and it's capabilities as known to the driver.
*/
struct drm_i915_engine_info {
- /** Engine class and instance. */
+ /** @engine: Engine class and instance. */
struct i915_engine_class_instance engine;
- /** Reserved field. */
+ /** @rsvd0: Reserved field. */
__u32 rsvd0;
- /** Engine flags. */
+ /** @flags: Engine flags. */
__u64 flags;
- /** Capabilities of this engine. */
+ /** @capabilities: Capabilities of this engine. */
__u64 capabilities;
#define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0)
#define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1)
- /** Reserved fields. */
+ /** @rsvd1: Reserved fields. */
__u64 rsvd1[4];
};
@@ -2315,13 +2743,13 @@ struct drm_i915_engine_info {
* an array of struct drm_i915_engine_info structures.
*/
struct drm_i915_query_engine_info {
- /** Number of struct drm_i915_engine_info structs following. */
+ /** @num_engines: Number of struct drm_i915_engine_info structs following. */
__u32 num_engines;
- /** MBZ */
+ /** @rsvd: MBZ */
__u32 rsvd[3];
- /** Marker for drm_i915_engine_info structures. */
+ /** @engines: Marker for drm_i915_engine_info structures. */
struct drm_i915_engine_info engines[];
};
@@ -2375,6 +2803,241 @@ struct drm_i915_query_perf_config {
__u8 data[];
};
+/**
+ * enum drm_i915_gem_memory_class - Supported memory classes
+ */
+enum drm_i915_gem_memory_class {
+ /** @I915_MEMORY_CLASS_SYSTEM: System memory */
+ I915_MEMORY_CLASS_SYSTEM = 0,
+ /** @I915_MEMORY_CLASS_DEVICE: Device local-memory */
+ I915_MEMORY_CLASS_DEVICE,
+};
+
+/**
+ * struct drm_i915_gem_memory_class_instance - Identify particular memory region
+ */
+struct drm_i915_gem_memory_class_instance {
+ /** @memory_class: See enum drm_i915_gem_memory_class */
+ __u16 memory_class;
+
+ /** @memory_instance: Which instance */
+ __u16 memory_instance;
+};
+
+/**
+ * struct drm_i915_memory_region_info - Describes one region as known to the
+ * driver.
+ *
+ * Note that we reserve some stuff here for potential future work. As an example
+ * we might want expose the capabilities for a given region, which could include
+ * things like if the region is CPU mappable/accessible, what are the supported
+ * mapping types etc.
+ *
+ * Note that to extend struct drm_i915_memory_region_info and struct
+ * drm_i915_query_memory_regions in the future the plan is to do the following:
+ *
+ * .. code-block:: C
+ *
+ * struct drm_i915_memory_region_info {
+ * struct drm_i915_gem_memory_class_instance region;
+ * union {
+ * __u32 rsvd0;
+ * __u32 new_thing1;
+ * };
+ * ...
+ * union {
+ * __u64 rsvd1[8];
+ * struct {
+ * __u64 new_thing2;
+ * __u64 new_thing3;
+ * ...
+ * };
+ * };
+ * };
+ *
+ * With this things should remain source compatible between versions for
+ * userspace, even as we add new fields.
+ *
+ * Note this is using both struct drm_i915_query_item and struct drm_i915_query.
+ * For this new query we are adding the new query id DRM_I915_QUERY_MEMORY_REGIONS
+ * at &drm_i915_query_item.query_id.
+ */
+struct drm_i915_memory_region_info {
+ /** @region: The class:instance pair encoding */
+ struct drm_i915_gem_memory_class_instance region;
+
+ /** @rsvd0: MBZ */
+ __u32 rsvd0;
+
+ /** @probed_size: Memory probed by the driver (-1 = unknown) */
+ __u64 probed_size;
+
+ /** @unallocated_size: Estimate of memory remaining (-1 = unknown) */
+ __u64 unallocated_size;
+
+ /** @rsvd1: MBZ */
+ __u64 rsvd1[8];
+};
+
+/**
+ * struct drm_i915_query_memory_regions
+ *
+ * The region info query enumerates all regions known to the driver by filling
+ * in an array of struct drm_i915_memory_region_info structures.
+ *
+ * Example for getting the list of supported regions:
+ *
+ * .. code-block:: C
+ *
+ * struct drm_i915_query_memory_regions *info;
+ * struct drm_i915_query_item item = {
+ * .query_id = DRM_I915_QUERY_MEMORY_REGIONS;
+ * };
+ * struct drm_i915_query query = {
+ * .num_items = 1,
+ * .items_ptr = (uintptr_t)&item,
+ * };
+ * int err, i;
+ *
+ * // First query the size of the blob we need, this needs to be large
+ * // enough to hold our array of regions. The kernel will fill out the
+ * // item.length for us, which is the number of bytes we need.
+ * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
+ * if (err) ...
+ *
+ * info = calloc(1, item.length);
+ * // Now that we allocated the required number of bytes, we call the ioctl
+ * // again, this time with the data_ptr pointing to our newly allocated
+ * // blob, which the kernel can then populate with the all the region info.
+ * item.data_ptr = (uintptr_t)&info,
+ *
+ * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
+ * if (err) ...
+ *
+ * // We can now access each region in the array
+ * for (i = 0; i < info->num_regions; i++) {
+ * struct drm_i915_memory_region_info mr = info->regions[i];
+ * u16 class = mr.region.class;
+ * u16 instance = mr.region.instance;
+ *
+ * ....
+ * }
+ *
+ * free(info);
+ */
+struct drm_i915_query_memory_regions {
+ /** @num_regions: Number of supported regions */
+ __u32 num_regions;
+
+ /** @rsvd: MBZ */
+ __u32 rsvd[3];
+
+ /** @regions: Info about each supported region */
+ struct drm_i915_memory_region_info regions[];
+};
+
+/**
+ * struct drm_i915_gem_create_ext - Existing gem_create behaviour, with added
+ * extension support using struct i915_user_extension.
+ *
+ * Note that in the future we want to have our buffer flags here, at least for
+ * the stuff that is immutable. Previously we would have two ioctls, one to
+ * create the object with gem_create, and another to apply various parameters,
+ * however this creates some ambiguity for the params which are considered
+ * immutable. Also in general we're phasing out the various SET/GET ioctls.
+ */
+struct drm_i915_gem_create_ext {
+ /**
+ * @size: Requested size for the object.
+ *
+ * The (page-aligned) allocated size for the object will be returned.
+ *
+ * Note that for some devices we have might have further minimum
+ * page-size restrictions(larger than 4K), like for device local-memory.
+ * However in general the final size here should always reflect any
+ * rounding up, if for example using the I915_GEM_CREATE_EXT_MEMORY_REGIONS
+ * extension to place the object in device local-memory.
+ */
+ __u64 size;
+ /**
+ * @handle: Returned handle for the object.
+ *
+ * Object handles are nonzero.
+ */
+ __u32 handle;
+ /** @flags: MBZ */
+ __u32 flags;
+ /**
+ * @extensions: The chain of extensions to apply to this object.
+ *
+ * This will be useful in the future when we need to support several
+ * different extensions, and we need to apply more than one when
+ * creating the object. See struct i915_user_extension.
+ *
+ * If we don't supply any extensions then we get the same old gem_create
+ * behaviour.
+ *
+ * For I915_GEM_CREATE_EXT_MEMORY_REGIONS usage see
+ * struct drm_i915_gem_create_ext_memory_regions.
+ */
+#define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0
+ __u64 extensions;
+};
+
+/**
+ * struct drm_i915_gem_create_ext_memory_regions - The
+ * I915_GEM_CREATE_EXT_MEMORY_REGIONS extension.
+ *
+ * Set the object with the desired set of placements/regions in priority
+ * order. Each entry must be unique and supported by the device.
+ *
+ * This is provided as an array of struct drm_i915_gem_memory_class_instance, or
+ * an equivalent layout of class:instance pair encodings. See struct
+ * drm_i915_query_memory_regions and DRM_I915_QUERY_MEMORY_REGIONS for how to
+ * query the supported regions for a device.
+ *
+ * As an example, on discrete devices, if we wish to set the placement as
+ * device local-memory we can do something like:
+ *
+ * .. code-block:: C
+ *
+ * struct drm_i915_gem_memory_class_instance region_lmem = {
+ * .memory_class = I915_MEMORY_CLASS_DEVICE,
+ * .memory_instance = 0,
+ * };
+ * struct drm_i915_gem_create_ext_memory_regions regions = {
+ * .base = { .name = I915_GEM_CREATE_EXT_MEMORY_REGIONS },
+ * .regions = (uintptr_t)&region_lmem,
+ * .num_regions = 1,
+ * };
+ * struct drm_i915_gem_create_ext create_ext = {
+ * .size = 16 * PAGE_SIZE,
+ * .extensions = (uintptr_t)&regions,
+ * };
+ *
+ * int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext);
+ * if (err) ...
+ *
+ * At which point we get the object handle in &drm_i915_gem_create_ext.handle,
+ * along with the final object size in &drm_i915_gem_create_ext.size, which
+ * should account for any rounding up, if required.
+ */
+struct drm_i915_gem_create_ext_memory_regions {
+ /** @base: Extension link. See struct i915_user_extension. */
+ struct i915_user_extension base;
+
+ /** @pad: MBZ */
+ __u32 pad;
+ /** @num_regions: Number of elements in the @regions array. */
+ __u32 num_regions;
+ /**
+ * @regions: The regions/placements array.
+ *
+ * An array of struct drm_i915_gem_memory_class_instance.
+ */
+ __u64 regions;
+};
+
#if defined(__cplusplus)
}
#endif
diff --git a/lib/mesa/include/pci_ids/i810_pci_ids.h b/lib/mesa/include/pci_ids/i810_pci_ids.h
deleted file mode 100644
index 7f681925d..000000000
--- a/lib/mesa/include/pci_ids/i810_pci_ids.h
+++ /dev/null
@@ -1,4 +0,0 @@
-CHIPSET(0x7121, I810, i8xx)
-CHIPSET(0x7123, I810_DC100, i8xx)
-CHIPSET(0x7125, I810_E, i8xx)
-CHIPSET(0x1132, I815, i8xx)
diff --git a/lib/mesa/include/pci_ids/i965_pci_ids.h b/lib/mesa/include/pci_ids/i965_pci_ids.h
index 7dfd550ec..6c0cb4692 100644
--- a/lib/mesa/include/pci_ids/i965_pci_ids.h
+++ b/lib/mesa/include/pci_ids/i965_pci_ids.h
@@ -1,3 +1,4 @@
+#ifndef PREFER_CROCUS
CHIPSET(0x29A2, i965, "BW", "Intel(R) 965G")
CHIPSET(0x2992, i965, "BW", "Intel(R) 965Q")
CHIPSET(0x2982, i965, "BW", "Intel(R) 965G")
@@ -102,6 +103,7 @@ CHIPSET(0x22B0, chv, "CHV", "Intel(R) HD Graphics")
CHIPSET(0x22B1, chv, "BSW", "Intel(R) HD Graphics XXX") /* Overridden in brw_get_renderer_string */
CHIPSET(0x22B2, chv, "CHV", "Intel(R) HD Graphics")
CHIPSET(0x22B3, chv, "CHV", "Intel(R) HD Graphics")
+#endif
#ifndef PREFER_IRIS
CHIPSET(0x1602, bdw_gt1, "BDW GT1", "Intel(R) HD Graphics")
diff --git a/lib/mesa/include/vulkan/vk_platform.h b/lib/mesa/include/vulkan/vk_platform.h
index 71858453f..18b913abc 100644
--- a/lib/mesa/include/vulkan/vk_platform.h
+++ b/lib/mesa/include/vulkan/vk_platform.h
@@ -2,7 +2,7 @@
// File: vk_platform.h
//
/*
-** Copyright (c) 2014-2020 The Khronos Group Inc.
+** Copyright 2014-2021 The Khronos Group Inc.
**
** SPDX-License-Identifier: Apache-2.0
*/
diff --git a/lib/mesa/include/vulkan/vulkan.h b/lib/mesa/include/vulkan/vulkan.h
index b7716ec8e..3f7cdba58 100644
--- a/lib/mesa/include/vulkan/vulkan.h
+++ b/lib/mesa/include/vulkan/vulkan.h
@@ -2,7 +2,7 @@
#define VULKAN_H_ 1
/*
-** Copyright (c) 2015-2020 The Khronos Group Inc.
+** Copyright 2015-2021 The Khronos Group Inc.
**
** SPDX-License-Identifier: Apache-2.0
*/
@@ -80,6 +80,11 @@
#endif
+#ifdef VK_USE_PLATFORM_SCREEN_QNX
+#include <screen/screen.h>
+#include "vulkan_screen.h"
+#endif
+
#ifdef VK_ENABLE_BETA_EXTENSIONS
#include "vulkan_beta.h"
#endif
diff --git a/lib/mesa/include/vulkan/vulkan_beta.h b/lib/mesa/include/vulkan/vulkan_beta.h
index 23513b327..2fedade6b 100644
--- a/lib/mesa/include/vulkan/vulkan_beta.h
+++ b/lib/mesa/include/vulkan/vulkan_beta.h
@@ -2,7 +2,7 @@
#define VULKAN_BETA_H_ 1
/*
-** Copyright (c) 2015-2020 The Khronos Group Inc.
+** Copyright 2015-2021 The Khronos Group Inc.
**
** SPDX-License-Identifier: Apache-2.0
*/
@@ -19,6 +19,324 @@ extern "C" {
+#define VK_KHR_video_queue 1
+VK_DEFINE_NON_DISPATCHABLE_HANDLE(VkVideoSessionKHR)
+VK_DEFINE_NON_DISPATCHABLE_HANDLE(VkVideoSessionParametersKHR)
+#define VK_KHR_VIDEO_QUEUE_SPEC_VERSION 2
+#define VK_KHR_VIDEO_QUEUE_EXTENSION_NAME "VK_KHR_video_queue"
+
+typedef enum VkQueryResultStatusKHR {
+ VK_QUERY_RESULT_STATUS_ERROR_KHR = -1,
+ VK_QUERY_RESULT_STATUS_NOT_READY_KHR = 0,
+ VK_QUERY_RESULT_STATUS_COMPLETE_KHR = 1,
+ VK_QUERY_RESULT_STATUS_MAX_ENUM_KHR = 0x7FFFFFFF
+} VkQueryResultStatusKHR;
+
+typedef enum VkVideoCodecOperationFlagBitsKHR {
+ VK_VIDEO_CODEC_OPERATION_INVALID_BIT_KHR = 0,
+#ifdef VK_ENABLE_BETA_EXTENSIONS
+ VK_VIDEO_CODEC_OPERATION_ENCODE_H264_BIT_EXT = 0x00010000,
+#endif
+#ifdef VK_ENABLE_BETA_EXTENSIONS
+ VK_VIDEO_CODEC_OPERATION_DECODE_H264_BIT_EXT = 0x00000001,
+#endif
+#ifdef VK_ENABLE_BETA_EXTENSIONS
+ VK_VIDEO_CODEC_OPERATION_DECODE_H265_BIT_EXT = 0x00000002,
+#endif
+ VK_VIDEO_CODEC_OPERATION_FLAG_BITS_MAX_ENUM_KHR = 0x7FFFFFFF
+} VkVideoCodecOperationFlagBitsKHR;
+typedef VkFlags VkVideoCodecOperationFlagsKHR;
+
+typedef enum VkVideoChromaSubsamplingFlagBitsKHR {
+ VK_VIDEO_CHROMA_SUBSAMPLING_INVALID_BIT_KHR = 0,
+ VK_VIDEO_CHROMA_SUBSAMPLING_MONOCHROME_BIT_KHR = 0x00000001,
+ VK_VIDEO_CHROMA_SUBSAMPLING_420_BIT_KHR = 0x00000002,
+ VK_VIDEO_CHROMA_SUBSAMPLING_422_BIT_KHR = 0x00000004,
+ VK_VIDEO_CHROMA_SUBSAMPLING_444_BIT_KHR = 0x00000008,
+ VK_VIDEO_CHROMA_SUBSAMPLING_FLAG_BITS_MAX_ENUM_KHR = 0x7FFFFFFF
+} VkVideoChromaSubsamplingFlagBitsKHR;
+typedef VkFlags VkVideoChromaSubsamplingFlagsKHR;
+
+typedef enum VkVideoComponentBitDepthFlagBitsKHR {
+ VK_VIDEO_COMPONENT_BIT_DEPTH_INVALID_KHR = 0,
+ VK_VIDEO_COMPONENT_BIT_DEPTH_8_BIT_KHR = 0x00000001,
+ VK_VIDEO_COMPONENT_BIT_DEPTH_10_BIT_KHR = 0x00000004,
+ VK_VIDEO_COMPONENT_BIT_DEPTH_12_BIT_KHR = 0x00000010,
+ VK_VIDEO_COMPONENT_BIT_DEPTH_FLAG_BITS_MAX_ENUM_KHR = 0x7FFFFFFF
+} VkVideoComponentBitDepthFlagBitsKHR;
+typedef VkFlags VkVideoComponentBitDepthFlagsKHR;
+
+typedef enum VkVideoCapabilityFlagBitsKHR {
+ VK_VIDEO_CAPABILITY_PROTECTED_CONTENT_BIT_KHR = 0x00000001,
+ VK_VIDEO_CAPABILITY_SEPARATE_REFERENCE_IMAGES_BIT_KHR = 0x00000002,
+ VK_VIDEO_CAPABILITY_FLAG_BITS_MAX_ENUM_KHR = 0x7FFFFFFF
+} VkVideoCapabilityFlagBitsKHR;
+typedef VkFlags VkVideoCapabilityFlagsKHR;
+
+typedef enum VkVideoSessionCreateFlagBitsKHR {
+ VK_VIDEO_SESSION_CREATE_DEFAULT_KHR = 0,
+ VK_VIDEO_SESSION_CREATE_PROTECTED_CONTENT_BIT_KHR = 0x00000001,
+ VK_VIDEO_SESSION_CREATE_FLAG_BITS_MAX_ENUM_KHR = 0x7FFFFFFF
+} VkVideoSessionCreateFlagBitsKHR;
+typedef VkFlags VkVideoSessionCreateFlagsKHR;
+typedef VkFlags VkVideoBeginCodingFlagsKHR;
+typedef VkFlags VkVideoEndCodingFlagsKHR;
+
+typedef enum VkVideoCodingControlFlagBitsKHR {
+ VK_VIDEO_CODING_CONTROL_DEFAULT_KHR = 0,
+ VK_VIDEO_CODING_CONTROL_RESET_BIT_KHR = 0x00000001,
+ VK_VIDEO_CODING_CONTROL_FLAG_BITS_MAX_ENUM_KHR = 0x7FFFFFFF
+} VkVideoCodingControlFlagBitsKHR;
+typedef VkFlags VkVideoCodingControlFlagsKHR;
+
+typedef enum VkVideoCodingQualityPresetFlagBitsKHR {
+ VK_VIDEO_CODING_QUALITY_PRESET_NORMAL_BIT_KHR = 0x00000001,
+ VK_VIDEO_CODING_QUALITY_PRESET_POWER_BIT_KHR = 0x00000002,
+ VK_VIDEO_CODING_QUALITY_PRESET_QUALITY_BIT_KHR = 0x00000004,
+ VK_VIDEO_CODING_QUALITY_PRESET_FLAG_BITS_MAX_ENUM_KHR = 0x7FFFFFFF
+} VkVideoCodingQualityPresetFlagBitsKHR;
+typedef VkFlags VkVideoCodingQualityPresetFlagsKHR;
+typedef struct VkVideoQueueFamilyProperties2KHR {
+ VkStructureType sType;
+ void* pNext;
+ VkVideoCodecOperationFlagsKHR videoCodecOperations;
+} VkVideoQueueFamilyProperties2KHR;
+
+typedef struct VkVideoProfileKHR {
+ VkStructureType sType;
+ void* pNext;
+ VkVideoCodecOperationFlagBitsKHR videoCodecOperation;
+ VkVideoChromaSubsamplingFlagsKHR chromaSubsampling;
+ VkVideoComponentBitDepthFlagsKHR lumaBitDepth;
+ VkVideoComponentBitDepthFlagsKHR chromaBitDepth;
+} VkVideoProfileKHR;
+
+typedef struct VkVideoProfilesKHR {
+ VkStructureType sType;
+ void* pNext;
+ uint32_t profileCount;
+ const VkVideoProfileKHR* pProfiles;
+} VkVideoProfilesKHR;
+
+typedef struct VkVideoCapabilitiesKHR {
+ VkStructureType sType;
+ void* pNext;
+ VkVideoCapabilityFlagsKHR capabilityFlags;
+ VkDeviceSize minBitstreamBufferOffsetAlignment;
+ VkDeviceSize minBitstreamBufferSizeAlignment;
+ VkExtent2D videoPictureExtentGranularity;
+ VkExtent2D minExtent;
+ VkExtent2D maxExtent;
+ uint32_t maxReferencePicturesSlotsCount;
+ uint32_t maxReferencePicturesActiveCount;
+} VkVideoCapabilitiesKHR;
+
+typedef struct VkPhysicalDeviceVideoFormatInfoKHR {
+ VkStructureType sType;
+ void* pNext;
+ VkImageUsageFlags imageUsage;
+ const VkVideoProfilesKHR* pVideoProfiles;
+} VkPhysicalDeviceVideoFormatInfoKHR;
+
+typedef struct VkVideoFormatPropertiesKHR {
+ VkStructureType sType;
+ void* pNext;
+ VkFormat format;
+} VkVideoFormatPropertiesKHR;
+
+typedef struct VkVideoPictureResourceKHR {
+ VkStructureType sType;
+ const void* pNext;
+ VkOffset2D codedOffset;
+ VkExtent2D codedExtent;
+ uint32_t baseArrayLayer;
+ VkImageView imageViewBinding;
+} VkVideoPictureResourceKHR;
+
+typedef struct VkVideoReferenceSlotKHR {
+ VkStructureType sType;
+ const void* pNext;
+ int8_t slotIndex;
+ const VkVideoPictureResourceKHR* pPictureResource;
+} VkVideoReferenceSlotKHR;
+
+typedef struct VkVideoGetMemoryPropertiesKHR {
+ VkStructureType sType;
+ const void* pNext;
+ uint32_t memoryBindIndex;
+ VkMemoryRequirements2* pMemoryRequirements;
+} VkVideoGetMemoryPropertiesKHR;
+
+typedef struct VkVideoBindMemoryKHR {
+ VkStructureType sType;
+ const void* pNext;
+ uint32_t memoryBindIndex;
+ VkDeviceMemory memory;
+ VkDeviceSize memoryOffset;
+ VkDeviceSize memorySize;
+} VkVideoBindMemoryKHR;
+
+typedef struct VkVideoSessionCreateInfoKHR {
+ VkStructureType sType;
+ const void* pNext;
+ uint32_t queueFamilyIndex;
+ VkVideoSessionCreateFlagsKHR flags;
+ const VkVideoProfileKHR* pVideoProfile;
+ VkFormat pictureFormat;
+ VkExtent2D maxCodedExtent;
+ VkFormat referencePicturesFormat;
+ uint32_t maxReferencePicturesSlotsCount;
+ uint32_t maxReferencePicturesActiveCount;
+} VkVideoSessionCreateInfoKHR;
+
+typedef struct VkVideoSessionParametersCreateInfoKHR {
+ VkStructureType sType;
+ const void* pNext;
+ VkVideoSessionParametersKHR videoSessionParametersTemplate;
+ VkVideoSessionKHR videoSession;
+} VkVideoSessionParametersCreateInfoKHR;
+
+typedef struct VkVideoSessionParametersUpdateInfoKHR {
+ VkStructureType sType;
+ const void* pNext;
+ uint32_t updateSequenceCount;
+} VkVideoSessionParametersUpdateInfoKHR;
+
+typedef struct VkVideoBeginCodingInfoKHR {
+ VkStructureType sType;
+ const void* pNext;
+ VkVideoBeginCodingFlagsKHR flags;
+ VkVideoCodingQualityPresetFlagsKHR codecQualityPreset;
+ VkVideoSessionKHR videoSession;
+ VkVideoSessionParametersKHR videoSessionParameters;
+ uint32_t referenceSlotCount;
+ const VkVideoReferenceSlotKHR* pReferenceSlots;
+} VkVideoBeginCodingInfoKHR;
+
+typedef struct VkVideoEndCodingInfoKHR {
+ VkStructureType sType;
+ const void* pNext;
+ VkVideoEndCodingFlagsKHR flags;
+} VkVideoEndCodingInfoKHR;
+
+typedef struct VkVideoCodingControlInfoKHR {
+ VkStructureType sType;
+ const void* pNext;
+ VkVideoCodingControlFlagsKHR flags;
+} VkVideoCodingControlInfoKHR;
+
+typedef VkResult (VKAPI_PTR *PFN_vkGetPhysicalDeviceVideoCapabilitiesKHR)(VkPhysicalDevice physicalDevice, const VkVideoProfileKHR* pVideoProfile, VkVideoCapabilitiesKHR* pCapabilities);
+typedef VkResult (VKAPI_PTR *PFN_vkGetPhysicalDeviceVideoFormatPropertiesKHR)(VkPhysicalDevice physicalDevice, const VkPhysicalDeviceVideoFormatInfoKHR* pVideoFormatInfo, uint32_t* pVideoFormatPropertyCount, VkVideoFormatPropertiesKHR* pVideoFormatProperties);
+typedef VkResult (VKAPI_PTR *PFN_vkCreateVideoSessionKHR)(VkDevice device, const VkVideoSessionCreateInfoKHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkVideoSessionKHR* pVideoSession);
+typedef void (VKAPI_PTR *PFN_vkDestroyVideoSessionKHR)(VkDevice device, VkVideoSessionKHR videoSession, const VkAllocationCallbacks* pAllocator);
+typedef VkResult (VKAPI_PTR *PFN_vkGetVideoSessionMemoryRequirementsKHR)(VkDevice device, VkVideoSessionKHR videoSession, uint32_t* pVideoSessionMemoryRequirementsCount, VkVideoGetMemoryPropertiesKHR* pVideoSessionMemoryRequirements);
+typedef VkResult (VKAPI_PTR *PFN_vkBindVideoSessionMemoryKHR)(VkDevice device, VkVideoSessionKHR videoSession, uint32_t videoSessionBindMemoryCount, const VkVideoBindMemoryKHR* pVideoSessionBindMemories);
+typedef VkResult (VKAPI_PTR *PFN_vkCreateVideoSessionParametersKHR)(VkDevice device, const VkVideoSessionParametersCreateInfoKHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkVideoSessionParametersKHR* pVideoSessionParameters);
+typedef VkResult (VKAPI_PTR *PFN_vkUpdateVideoSessionParametersKHR)(VkDevice device, VkVideoSessionParametersKHR videoSessionParameters, const VkVideoSessionParametersUpdateInfoKHR* pUpdateInfo);
+typedef void (VKAPI_PTR *PFN_vkDestroyVideoSessionParametersKHR)(VkDevice device, VkVideoSessionParametersKHR videoSessionParameters, const VkAllocationCallbacks* pAllocator);
+typedef void (VKAPI_PTR *PFN_vkCmdBeginVideoCodingKHR)(VkCommandBuffer commandBuffer, const VkVideoBeginCodingInfoKHR* pBeginInfo);
+typedef void (VKAPI_PTR *PFN_vkCmdEndVideoCodingKHR)(VkCommandBuffer commandBuffer, const VkVideoEndCodingInfoKHR* pEndCodingInfo);
+typedef void (VKAPI_PTR *PFN_vkCmdControlVideoCodingKHR)(VkCommandBuffer commandBuffer, const VkVideoCodingControlInfoKHR* pCodingControlInfo);
+
+#ifndef VK_NO_PROTOTYPES
+VKAPI_ATTR VkResult VKAPI_CALL vkGetPhysicalDeviceVideoCapabilitiesKHR(
+ VkPhysicalDevice physicalDevice,
+ const VkVideoProfileKHR* pVideoProfile,
+ VkVideoCapabilitiesKHR* pCapabilities);
+
+VKAPI_ATTR VkResult VKAPI_CALL vkGetPhysicalDeviceVideoFormatPropertiesKHR(
+ VkPhysicalDevice physicalDevice,
+ const VkPhysicalDeviceVideoFormatInfoKHR* pVideoFormatInfo,
+ uint32_t* pVideoFormatPropertyCount,
+ VkVideoFormatPropertiesKHR* pVideoFormatProperties);
+
+VKAPI_ATTR VkResult VKAPI_CALL vkCreateVideoSessionKHR(
+ VkDevice device,
+ const VkVideoSessionCreateInfoKHR* pCreateInfo,
+ const VkAllocationCallbacks* pAllocator,
+ VkVideoSessionKHR* pVideoSession);
+
+VKAPI_ATTR void VKAPI_CALL vkDestroyVideoSessionKHR(
+ VkDevice device,
+ VkVideoSessionKHR videoSession,
+ const VkAllocationCallbacks* pAllocator);
+
+VKAPI_ATTR VkResult VKAPI_CALL vkGetVideoSessionMemoryRequirementsKHR(
+ VkDevice device,
+ VkVideoSessionKHR videoSession,
+ uint32_t* pVideoSessionMemoryRequirementsCount,
+ VkVideoGetMemoryPropertiesKHR* pVideoSessionMemoryRequirements);
+
+VKAPI_ATTR VkResult VKAPI_CALL vkBindVideoSessionMemoryKHR(
+ VkDevice device,
+ VkVideoSessionKHR videoSession,
+ uint32_t videoSessionBindMemoryCount,
+ const VkVideoBindMemoryKHR* pVideoSessionBindMemories);
+
+VKAPI_ATTR VkResult VKAPI_CALL vkCreateVideoSessionParametersKHR(
+ VkDevice device,
+ const VkVideoSessionParametersCreateInfoKHR* pCreateInfo,
+ const VkAllocationCallbacks* pAllocator,
+ VkVideoSessionParametersKHR* pVideoSessionParameters);
+
+VKAPI_ATTR VkResult VKAPI_CALL vkUpdateVideoSessionParametersKHR(
+ VkDevice device,
+ VkVideoSessionParametersKHR videoSessionParameters,
+ const VkVideoSessionParametersUpdateInfoKHR* pUpdateInfo);
+
+VKAPI_ATTR void VKAPI_CALL vkDestroyVideoSessionParametersKHR(
+ VkDevice device,
+ VkVideoSessionParametersKHR videoSessionParameters,
+ const VkAllocationCallbacks* pAllocator);
+
+VKAPI_ATTR void VKAPI_CALL vkCmdBeginVideoCodingKHR(
+ VkCommandBuffer commandBuffer,
+ const VkVideoBeginCodingInfoKHR* pBeginInfo);
+
+VKAPI_ATTR void VKAPI_CALL vkCmdEndVideoCodingKHR(
+ VkCommandBuffer commandBuffer,
+ const VkVideoEndCodingInfoKHR* pEndCodingInfo);
+
+VKAPI_ATTR void VKAPI_CALL vkCmdControlVideoCodingKHR(
+ VkCommandBuffer commandBuffer,
+ const VkVideoCodingControlInfoKHR* pCodingControlInfo);
+#endif
+
+
+#define VK_KHR_video_decode_queue 1
+#define VK_KHR_VIDEO_DECODE_QUEUE_SPEC_VERSION 2
+#define VK_KHR_VIDEO_DECODE_QUEUE_EXTENSION_NAME "VK_KHR_video_decode_queue"
+
+typedef enum VkVideoDecodeFlagBitsKHR {
+ VK_VIDEO_DECODE_DEFAULT_KHR = 0,
+ VK_VIDEO_DECODE_RESERVED_0_BIT_KHR = 0x00000001,
+ VK_VIDEO_DECODE_FLAG_BITS_MAX_ENUM_KHR = 0x7FFFFFFF
+} VkVideoDecodeFlagBitsKHR;
+typedef VkFlags VkVideoDecodeFlagsKHR;
+typedef struct VkVideoDecodeInfoKHR {
+ VkStructureType sType;
+ const void* pNext;
+ VkVideoDecodeFlagsKHR flags;
+ VkOffset2D codedOffset;
+ VkExtent2D codedExtent;
+ VkBuffer srcBuffer;
+ VkDeviceSize srcBufferOffset;
+ VkDeviceSize srcBufferRange;
+ VkVideoPictureResourceKHR dstPictureResource;
+ const VkVideoReferenceSlotKHR* pSetupReferenceSlot;
+ uint32_t referenceSlotCount;
+ const VkVideoReferenceSlotKHR* pReferenceSlots;
+} VkVideoDecodeInfoKHR;
+
+typedef void (VKAPI_PTR *PFN_vkCmdDecodeVideoKHR)(VkCommandBuffer commandBuffer, const VkVideoDecodeInfoKHR* pFrameInfo);
+
+#ifndef VK_NO_PROTOTYPES
+VKAPI_ATTR void VKAPI_CALL vkCmdDecodeVideoKHR(
+ VkCommandBuffer commandBuffer,
+ const VkVideoDecodeInfoKHR* pFrameInfo);
+#endif
+
+
#define VK_KHR_portability_subset 1
#define VK_KHR_PORTABILITY_SUBSET_SPEC_VERSION 1
#define VK_KHR_PORTABILITY_SUBSET_EXTENSION_NAME "VK_KHR_portability_subset"
@@ -49,6 +367,335 @@ typedef struct VkPhysicalDevicePortabilitySubsetPropertiesKHR {
} VkPhysicalDevicePortabilitySubsetPropertiesKHR;
+
+#define VK_KHR_video_encode_queue 1
+#define VK_KHR_VIDEO_ENCODE_QUEUE_SPEC_VERSION 3
+#define VK_KHR_VIDEO_ENCODE_QUEUE_EXTENSION_NAME "VK_KHR_video_encode_queue"
+
+typedef enum VkVideoEncodeFlagBitsKHR {
+ VK_VIDEO_ENCODE_DEFAULT_KHR = 0,
+ VK_VIDEO_ENCODE_RESERVED_0_BIT_KHR = 0x00000001,
+ VK_VIDEO_ENCODE_FLAG_BITS_MAX_ENUM_KHR = 0x7FFFFFFF
+} VkVideoEncodeFlagBitsKHR;
+typedef VkFlags VkVideoEncodeFlagsKHR;
+
+typedef enum VkVideoEncodeRateControlFlagBitsKHR {
+ VK_VIDEO_ENCODE_RATE_CONTROL_DEFAULT_KHR = 0,
+ VK_VIDEO_ENCODE_RATE_CONTROL_RESET_BIT_KHR = 0x00000001,
+ VK_VIDEO_ENCODE_RATE_CONTROL_FLAG_BITS_MAX_ENUM_KHR = 0x7FFFFFFF
+} VkVideoEncodeRateControlFlagBitsKHR;
+typedef VkFlags VkVideoEncodeRateControlFlagsKHR;
+
+typedef enum VkVideoEncodeRateControlModeFlagBitsKHR {
+ VK_VIDEO_ENCODE_RATE_CONTROL_MODE_NONE_BIT_KHR = 0,
+ VK_VIDEO_ENCODE_RATE_CONTROL_MODE_CBR_BIT_KHR = 1,
+ VK_VIDEO_ENCODE_RATE_CONTROL_MODE_VBR_BIT_KHR = 2,
+ VK_VIDEO_ENCODE_RATE_CONTROL_MODE_FLAG_BITS_MAX_ENUM_KHR = 0x7FFFFFFF
+} VkVideoEncodeRateControlModeFlagBitsKHR;
+typedef VkFlags VkVideoEncodeRateControlModeFlagsKHR;
+typedef struct VkVideoEncodeInfoKHR {
+ VkStructureType sType;
+ const void* pNext;
+ VkVideoEncodeFlagsKHR flags;
+ uint32_t qualityLevel;
+ VkExtent2D codedExtent;
+ VkBuffer dstBitstreamBuffer;
+ VkDeviceSize dstBitstreamBufferOffset;
+ VkDeviceSize dstBitstreamBufferMaxRange;
+ VkVideoPictureResourceKHR srcPictureResource;
+ const VkVideoReferenceSlotKHR* pSetupReferenceSlot;
+ uint32_t referenceSlotCount;
+ const VkVideoReferenceSlotKHR* pReferenceSlots;
+} VkVideoEncodeInfoKHR;
+
+typedef struct VkVideoEncodeRateControlInfoKHR {
+ VkStructureType sType;
+ const void* pNext;
+ VkVideoEncodeRateControlFlagsKHR flags;
+ VkVideoEncodeRateControlModeFlagBitsKHR rateControlMode;
+ uint32_t averageBitrate;
+ uint16_t peakToAverageBitrateRatio;
+ uint16_t frameRateNumerator;
+ uint16_t frameRateDenominator;
+ uint32_t virtualBufferSizeInMs;
+} VkVideoEncodeRateControlInfoKHR;
+
+typedef void (VKAPI_PTR *PFN_vkCmdEncodeVideoKHR)(VkCommandBuffer commandBuffer, const VkVideoEncodeInfoKHR* pEncodeInfo);
+
+#ifndef VK_NO_PROTOTYPES
+VKAPI_ATTR void VKAPI_CALL vkCmdEncodeVideoKHR(
+ VkCommandBuffer commandBuffer,
+ const VkVideoEncodeInfoKHR* pEncodeInfo);
+#endif
+
+
+#define VK_EXT_video_encode_h264 1
+#include "vk_video/vulkan_video_codec_h264std.h"
+#include "vk_video/vulkan_video_codec_h264std_encode.h"
+#define VK_EXT_VIDEO_ENCODE_H264_SPEC_VERSION 2
+#define VK_EXT_VIDEO_ENCODE_H264_EXTENSION_NAME "VK_EXT_video_encode_h264"
+
+typedef enum VkVideoEncodeH264CapabilityFlagBitsEXT {
+ VK_VIDEO_ENCODE_H264_CAPABILITY_CABAC_BIT_EXT = 0x00000001,
+ VK_VIDEO_ENCODE_H264_CAPABILITY_CAVLC_BIT_EXT = 0x00000002,
+ VK_VIDEO_ENCODE_H264_CAPABILITY_WEIGHTED_BI_PRED_IMPLICIT_BIT_EXT = 0x00000004,
+ VK_VIDEO_ENCODE_H264_CAPABILITY_TRANSFORM_8X8_BIT_EXT = 0x00000008,
+ VK_VIDEO_ENCODE_H264_CAPABILITY_CHROMA_QP_OFFSET_BIT_EXT = 0x00000010,
+ VK_VIDEO_ENCODE_H264_CAPABILITY_SECOND_CHROMA_QP_OFFSET_BIT_EXT = 0x00000020,
+ VK_VIDEO_ENCODE_H264_CAPABILITY_DEBLOCKING_FILTER_DISABLED_BIT_EXT = 0x00000040,
+ VK_VIDEO_ENCODE_H264_CAPABILITY_DEBLOCKING_FILTER_ENABLED_BIT_EXT = 0x00000080,
+ VK_VIDEO_ENCODE_H264_CAPABILITY_DEBLOCKING_FILTER_PARTIAL_BIT_EXT = 0x00000100,
+ VK_VIDEO_ENCODE_H264_CAPABILITY_MULTIPLE_SLICE_PER_FRAME_BIT_EXT = 0x00000200,
+ VK_VIDEO_ENCODE_H264_CAPABILITY_EVENLY_DISTRIBUTED_SLICE_SIZE_BIT_EXT = 0x00000400,
+ VK_VIDEO_ENCODE_H264_CAPABILITY_FLAG_BITS_MAX_ENUM_EXT = 0x7FFFFFFF
+} VkVideoEncodeH264CapabilityFlagBitsEXT;
+typedef VkFlags VkVideoEncodeH264CapabilityFlagsEXT;
+
+typedef enum VkVideoEncodeH264InputModeFlagBitsEXT {
+ VK_VIDEO_ENCODE_H264_INPUT_MODE_FRAME_BIT_EXT = 0x00000001,
+ VK_VIDEO_ENCODE_H264_INPUT_MODE_SLICE_BIT_EXT = 0x00000002,
+ VK_VIDEO_ENCODE_H264_INPUT_MODE_NON_VCL_BIT_EXT = 0x00000004,
+ VK_VIDEO_ENCODE_H264_INPUT_MODE_FLAG_BITS_MAX_ENUM_EXT = 0x7FFFFFFF
+} VkVideoEncodeH264InputModeFlagBitsEXT;
+typedef VkFlags VkVideoEncodeH264InputModeFlagsEXT;
+
+typedef enum VkVideoEncodeH264OutputModeFlagBitsEXT {
+ VK_VIDEO_ENCODE_H264_OUTPUT_MODE_FRAME_BIT_EXT = 0x00000001,
+ VK_VIDEO_ENCODE_H264_OUTPUT_MODE_SLICE_BIT_EXT = 0x00000002,
+ VK_VIDEO_ENCODE_H264_OUTPUT_MODE_NON_VCL_BIT_EXT = 0x00000004,
+ VK_VIDEO_ENCODE_H264_OUTPUT_MODE_FLAG_BITS_MAX_ENUM_EXT = 0x7FFFFFFF
+} VkVideoEncodeH264OutputModeFlagBitsEXT;
+typedef VkFlags VkVideoEncodeH264OutputModeFlagsEXT;
+
+typedef enum VkVideoEncodeH264CreateFlagBitsEXT {
+ VK_VIDEO_ENCODE_H264_CREATE_DEFAULT_EXT = 0,
+ VK_VIDEO_ENCODE_H264_CREATE_RESERVED_0_BIT_EXT = 0x00000001,
+ VK_VIDEO_ENCODE_H264_CREATE_FLAG_BITS_MAX_ENUM_EXT = 0x7FFFFFFF
+} VkVideoEncodeH264CreateFlagBitsEXT;
+typedef VkFlags VkVideoEncodeH264CreateFlagsEXT;
+typedef struct VkVideoEncodeH264CapabilitiesEXT {
+ VkStructureType sType;
+ const void* pNext;
+ VkVideoEncodeH264CapabilityFlagsEXT flags;
+ VkVideoEncodeH264InputModeFlagsEXT inputModeFlags;
+ VkVideoEncodeH264OutputModeFlagsEXT outputModeFlags;
+ VkExtent2D minPictureSizeInMbs;
+ VkExtent2D maxPictureSizeInMbs;
+ VkExtent2D inputImageDataAlignment;
+ uint8_t maxNumL0ReferenceForP;
+ uint8_t maxNumL0ReferenceForB;
+ uint8_t maxNumL1Reference;
+ uint8_t qualityLevelCount;
+ VkExtensionProperties stdExtensionVersion;
+} VkVideoEncodeH264CapabilitiesEXT;
+
+typedef struct VkVideoEncodeH264SessionCreateInfoEXT {
+ VkStructureType sType;
+ const void* pNext;
+ VkVideoEncodeH264CreateFlagsEXT flags;
+ VkExtent2D maxPictureSizeInMbs;
+ const VkExtensionProperties* pStdExtensionVersion;
+} VkVideoEncodeH264SessionCreateInfoEXT;
+
+typedef struct VkVideoEncodeH264SessionParametersAddInfoEXT {
+ VkStructureType sType;
+ const void* pNext;
+ uint32_t spsStdCount;
+ const StdVideoH264SequenceParameterSet* pSpsStd;
+ uint32_t ppsStdCount;
+ const StdVideoH264PictureParameterSet* pPpsStd;
+} VkVideoEncodeH264SessionParametersAddInfoEXT;
+
+typedef struct VkVideoEncodeH264SessionParametersCreateInfoEXT {
+ VkStructureType sType;
+ const void* pNext;
+ uint32_t maxSpsStdCount;
+ uint32_t maxPpsStdCount;
+ const VkVideoEncodeH264SessionParametersAddInfoEXT* pParametersAddInfo;
+} VkVideoEncodeH264SessionParametersCreateInfoEXT;
+
+typedef struct VkVideoEncodeH264DpbSlotInfoEXT {
+ VkStructureType sType;
+ const void* pNext;
+ int8_t slotIndex;
+ const StdVideoEncodeH264PictureInfo* pStdPictureInfo;
+} VkVideoEncodeH264DpbSlotInfoEXT;
+
+typedef struct VkVideoEncodeH264NaluSliceEXT {
+ VkStructureType sType;
+ const void* pNext;
+ const StdVideoEncodeH264SliceHeader* pSliceHeaderStd;
+ uint32_t mbCount;
+ uint8_t refFinalList0EntryCount;
+ const VkVideoEncodeH264DpbSlotInfoEXT* pRefFinalList0Entries;
+ uint8_t refFinalList1EntryCount;
+ const VkVideoEncodeH264DpbSlotInfoEXT* pRefFinalList1Entries;
+ uint32_t precedingNaluBytes;
+ uint8_t minQp;
+ uint8_t maxQp;
+} VkVideoEncodeH264NaluSliceEXT;
+
+typedef struct VkVideoEncodeH264VclFrameInfoEXT {
+ VkStructureType sType;
+ const void* pNext;
+ uint8_t refDefaultFinalList0EntryCount;
+ const VkVideoEncodeH264DpbSlotInfoEXT* pRefDefaultFinalList0Entries;
+ uint8_t refDefaultFinalList1EntryCount;
+ const VkVideoEncodeH264DpbSlotInfoEXT* pRefDefaultFinalList1Entries;
+ uint32_t naluSliceEntryCount;
+ const VkVideoEncodeH264NaluSliceEXT* pNaluSliceEntries;
+ const VkVideoEncodeH264DpbSlotInfoEXT* pCurrentPictureInfo;
+} VkVideoEncodeH264VclFrameInfoEXT;
+
+typedef struct VkVideoEncodeH264EmitPictureParametersEXT {
+ VkStructureType sType;
+ const void* pNext;
+ uint8_t spsId;
+ VkBool32 emitSpsEnable;
+ uint32_t ppsIdEntryCount;
+ const uint8_t* ppsIdEntries;
+} VkVideoEncodeH264EmitPictureParametersEXT;
+
+typedef struct VkVideoEncodeH264ProfileEXT {
+ VkStructureType sType;
+ const void* pNext;
+ StdVideoH264ProfileIdc stdProfileIdc;
+} VkVideoEncodeH264ProfileEXT;
+
+
+
+#define VK_EXT_video_decode_h264 1
+#include "vk_video/vulkan_video_codec_h264std_decode.h"
+#define VK_EXT_VIDEO_DECODE_H264_SPEC_VERSION 3
+#define VK_EXT_VIDEO_DECODE_H264_EXTENSION_NAME "VK_EXT_video_decode_h264"
+
+typedef enum VkVideoDecodeH264PictureLayoutFlagBitsEXT {
+ VK_VIDEO_DECODE_H264_PICTURE_LAYOUT_PROGRESSIVE_EXT = 0,
+ VK_VIDEO_DECODE_H264_PICTURE_LAYOUT_INTERLACED_INTERLEAVED_LINES_BIT_EXT = 0x00000001,
+ VK_VIDEO_DECODE_H264_PICTURE_LAYOUT_INTERLACED_SEPARATE_PLANES_BIT_EXT = 0x00000002,
+ VK_VIDEO_DECODE_H264_PICTURE_LAYOUT_FLAG_BITS_MAX_ENUM_EXT = 0x7FFFFFFF
+} VkVideoDecodeH264PictureLayoutFlagBitsEXT;
+typedef VkFlags VkVideoDecodeH264PictureLayoutFlagsEXT;
+typedef VkFlags VkVideoDecodeH264CreateFlagsEXT;
+typedef struct VkVideoDecodeH264ProfileEXT {
+ VkStructureType sType;
+ const void* pNext;
+ StdVideoH264ProfileIdc stdProfileIdc;
+ VkVideoDecodeH264PictureLayoutFlagsEXT pictureLayout;
+} VkVideoDecodeH264ProfileEXT;
+
+typedef struct VkVideoDecodeH264CapabilitiesEXT {
+ VkStructureType sType;
+ void* pNext;
+ uint32_t maxLevel;
+ VkOffset2D fieldOffsetGranularity;
+ VkExtensionProperties stdExtensionVersion;
+} VkVideoDecodeH264CapabilitiesEXT;
+
+typedef struct VkVideoDecodeH264SessionCreateInfoEXT {
+ VkStructureType sType;
+ const void* pNext;
+ VkVideoDecodeH264CreateFlagsEXT flags;
+ const VkExtensionProperties* pStdExtensionVersion;
+} VkVideoDecodeH264SessionCreateInfoEXT;
+
+typedef struct VkVideoDecodeH264SessionParametersAddInfoEXT {
+ VkStructureType sType;
+ const void* pNext;
+ uint32_t spsStdCount;
+ const StdVideoH264SequenceParameterSet* pSpsStd;
+ uint32_t ppsStdCount;
+ const StdVideoH264PictureParameterSet* pPpsStd;
+} VkVideoDecodeH264SessionParametersAddInfoEXT;
+
+typedef struct VkVideoDecodeH264SessionParametersCreateInfoEXT {
+ VkStructureType sType;
+ const void* pNext;
+ uint32_t maxSpsStdCount;
+ uint32_t maxPpsStdCount;
+ const VkVideoDecodeH264SessionParametersAddInfoEXT* pParametersAddInfo;
+} VkVideoDecodeH264SessionParametersCreateInfoEXT;
+
+typedef struct VkVideoDecodeH264PictureInfoEXT {
+ VkStructureType sType;
+ const void* pNext;
+ const StdVideoDecodeH264PictureInfo* pStdPictureInfo;
+ uint32_t slicesCount;
+ const uint32_t* pSlicesDataOffsets;
+} VkVideoDecodeH264PictureInfoEXT;
+
+typedef struct VkVideoDecodeH264MvcEXT {
+ VkStructureType sType;
+ const void* pNext;
+ const StdVideoDecodeH264Mvc* pStdMvc;
+} VkVideoDecodeH264MvcEXT;
+
+typedef struct VkVideoDecodeH264DpbSlotInfoEXT {
+ VkStructureType sType;
+ const void* pNext;
+ const StdVideoDecodeH264ReferenceInfo* pStdReferenceInfo;
+} VkVideoDecodeH264DpbSlotInfoEXT;
+
+
+
+#define VK_EXT_video_decode_h265 1
+#include "vk_video/vulkan_video_codec_h265std.h"
+#include "vk_video/vulkan_video_codec_h265std_decode.h"
+#define VK_EXT_VIDEO_DECODE_H265_SPEC_VERSION 1
+#define VK_EXT_VIDEO_DECODE_H265_EXTENSION_NAME "VK_EXT_video_decode_h265"
+typedef VkFlags VkVideoDecodeH265CreateFlagsEXT;
+typedef struct VkVideoDecodeH265ProfileEXT {
+ VkStructureType sType;
+ const void* pNext;
+ StdVideoH265ProfileIdc stdProfileIdc;
+} VkVideoDecodeH265ProfileEXT;
+
+typedef struct VkVideoDecodeH265CapabilitiesEXT {
+ VkStructureType sType;
+ void* pNext;
+ uint32_t maxLevel;
+ VkExtensionProperties stdExtensionVersion;
+} VkVideoDecodeH265CapabilitiesEXT;
+
+typedef struct VkVideoDecodeH265SessionCreateInfoEXT {
+ VkStructureType sType;
+ const void* pNext;
+ VkVideoDecodeH265CreateFlagsEXT flags;
+ const VkExtensionProperties* pStdExtensionVersion;
+} VkVideoDecodeH265SessionCreateInfoEXT;
+
+typedef struct VkVideoDecodeH265SessionParametersAddInfoEXT {
+ VkStructureType sType;
+ const void* pNext;
+ uint32_t spsStdCount;
+ const StdVideoH265SequenceParameterSet* pSpsStd;
+ uint32_t ppsStdCount;
+ const StdVideoH265PictureParameterSet* pPpsStd;
+} VkVideoDecodeH265SessionParametersAddInfoEXT;
+
+typedef struct VkVideoDecodeH265SessionParametersCreateInfoEXT {
+ VkStructureType sType;
+ const void* pNext;
+ uint32_t maxSpsStdCount;
+ uint32_t maxPpsStdCount;
+ const VkVideoDecodeH265SessionParametersAddInfoEXT* pParametersAddInfo;
+} VkVideoDecodeH265SessionParametersCreateInfoEXT;
+
+typedef struct VkVideoDecodeH265PictureInfoEXT {
+ VkStructureType sType;
+ const void* pNext;
+ StdVideoDecodeH265PictureInfo* pStdPictureInfo;
+ uint32_t slicesCount;
+ const uint32_t* pSlicesDataOffsets;
+} VkVideoDecodeH265PictureInfoEXT;
+
+typedef struct VkVideoDecodeH265DpbSlotInfoEXT {
+ VkStructureType sType;
+ const void* pNext;
+ const StdVideoDecodeH265ReferenceInfo* pStdReferenceInfo;
+} VkVideoDecodeH265DpbSlotInfoEXT;
+
+
#ifdef __cplusplus
}
#endif
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-16 00:26:32 +0000