Import Mesa 19.2.8

8 files changed, 145 insertions, 930 deletions

diff --git a/lib/mesa/src/freedreno/ir3/ir3_sun.c b/lib/mesa/src/freedreno/ir3/ir3_sun.c
index ed518736d..7fea9a073 100644
--- a/lib/mesa/src/freedreno/ir3/ir3_sun.c
+++ b/lib/mesa/src/freedreno/ir3/ir3_sun.c
@@ -38,7 +38,7 @@
  * is computed in multiple paths into a block, I think we should only have to
  * consider the worst-case.
  *
- * [1] https://www.cs.princeton.edu/~appel/papers/sun.pdf
+ * [1] https://pdfs.semanticscholar.org/ae53/6010b214612c2571f483354c264b0b39c545.pdf
  */
 
 static unsigned
@@ -96,11 +96,11 @@ ir3_sun(struct ir3 *ir)
 
 	ir3_clear_mark(ir);
 
-	struct ir3_instruction *out;
-	foreach_output(out, ir)
-		max = MAX2(max, number_instr(out));
+	for (unsigned i = 0; i < ir->noutputs; i++)
+		if (ir->outputs[i])
+			max = MAX2(max, number_instr(ir->outputs[i]));
 
-	foreach_block (block, &ir->block_list) {
+	list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
 		for (unsigned i = 0; i < block->keeps_count; i++)
 			max = MAX2(max, number_instr(block->keeps[i]));
 		if (block->condition)
diff --git a/lib/mesa/src/freedreno/registers/a2xx.xml b/lib/mesa/src/freedreno/registers/a2xx.xml
index 88cb35542..1b0bf44bd 100644
--- a/lib/mesa/src/freedreno/registers/a2xx.xml
+++ b/lib/mesa/src/freedreno/registers/a2xx.xml
@@ -834,191 +834,6 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 	<value value="56" name="RBPERF_ACCUM_CAM_HIT_FLUSHING"/>
 </enum>
 
-<enum name="a2xx_mh_perfcnt_select">
-	<value value="0" name="CP_R0_REQUESTS"/>
-	<value value="1" name="CP_R1_REQUESTS"/>
-	<value value="2" name="CP_R2_REQUESTS"/>
-	<value value="3" name="CP_R3_REQUESTS"/>
-	<value value="4" name="CP_R4_REQUESTS"/>
-	<value value="5" name="CP_TOTAL_READ_REQUESTS"/>
-	<value value="6" name="CP_TOTAL_WRITE_REQUESTS"/>
-	<value value="7" name="CP_TOTAL_REQUESTS"/>
-	<value value="8" name="CP_DATA_BYTES_WRITTEN"/>
-	<value value="9" name="CP_WRITE_CLEAN_RESPONSES"/>
-	<value value="10" name="CP_R0_READ_BURSTS_RECEIVED"/>
-	<value value="11" name="CP_R1_READ_BURSTS_RECEIVED"/>
-	<value value="12" name="CP_R2_READ_BURSTS_RECEIVED"/>
-	<value value="13" name="CP_R3_READ_BURSTS_RECEIVED"/>
-	<value value="14" name="CP_R4_READ_BURSTS_RECEIVED"/>
-	<value value="15" name="CP_TOTAL_READ_BURSTS_RECEIVED"/>
-	<value value="16" name="CP_R0_DATA_BEATS_READ"/>
-	<value value="17" name="CP_R1_DATA_BEATS_READ"/>
-	<value value="18" name="CP_R2_DATA_BEATS_READ"/>
-	<value value="19" name="CP_R3_DATA_BEATS_READ"/>
-	<value value="20" name="CP_R4_DATA_BEATS_READ"/>
-	<value value="21" name="CP_TOTAL_DATA_BEATS_READ"/>
-	<value value="22" name="VGT_R0_REQUESTS"/>
-	<value value="23" name="VGT_R1_REQUESTS"/>
-	<value value="24" name="VGT_TOTAL_REQUESTS"/>
-	<value value="25" name="VGT_R0_READ_BURSTS_RECEIVED"/>
-	<value value="26" name="VGT_R1_READ_BURSTS_RECEIVED"/>
-	<value value="27" name="VGT_TOTAL_READ_BURSTS_RECEIVED"/>
-	<value value="28" name="VGT_R0_DATA_BEATS_READ"/>
-	<value value="29" name="VGT_R1_DATA_BEATS_READ"/>
-	<value value="30" name="VGT_TOTAL_DATA_BEATS_READ"/>
-	<value value="31" name="TC_TOTAL_REQUESTS"/>
-	<value value="32" name="TC_ROQ_REQUESTS"/>
-	<value value="33" name="TC_INFO_SENT"/>
-	<value value="34" name="TC_READ_BURSTS_RECEIVED"/>
-	<value value="35" name="TC_DATA_BEATS_READ"/>
-	<value value="36" name="TCD_BURSTS_READ"/>
-	<value value="37" name="RB_REQUESTS"/>
-	<value value="38" name="RB_DATA_BYTES_WRITTEN"/>
-	<value value="39" name="RB_WRITE_CLEAN_RESPONSES"/>
-	<value value="40" name="AXI_READ_REQUESTS_ID_0"/>
-	<value value="41" name="AXI_READ_REQUESTS_ID_1"/>
-	<value value="42" name="AXI_READ_REQUESTS_ID_2"/>
-	<value value="43" name="AXI_READ_REQUESTS_ID_3"/>
-	<value value="44" name="AXI_READ_REQUESTS_ID_4"/>
-	<value value="45" name="AXI_READ_REQUESTS_ID_5"/>
-	<value value="46" name="AXI_READ_REQUESTS_ID_6"/>
-	<value value="47" name="AXI_READ_REQUESTS_ID_7"/>
-	<value value="48" name="AXI_TOTAL_READ_REQUESTS"/>
-	<value value="49" name="AXI_WRITE_REQUESTS_ID_0"/>
-	<value value="50" name="AXI_WRITE_REQUESTS_ID_1"/>
-	<value value="51" name="AXI_WRITE_REQUESTS_ID_2"/>
-	<value value="52" name="AXI_WRITE_REQUESTS_ID_3"/>
-	<value value="53" name="AXI_WRITE_REQUESTS_ID_4"/>
-	<value value="54" name="AXI_WRITE_REQUESTS_ID_5"/>
-	<value value="55" name="AXI_WRITE_REQUESTS_ID_6"/>
-	<value value="56" name="AXI_WRITE_REQUESTS_ID_7"/>
-	<value value="57" name="AXI_TOTAL_WRITE_REQUESTS"/>
-	<value value="58" name="AXI_TOTAL_REQUESTS_ID_0"/>
-	<value value="59" name="AXI_TOTAL_REQUESTS_ID_1"/>
-	<value value="60" name="AXI_TOTAL_REQUESTS_ID_2"/>
-	<value value="61" name="AXI_TOTAL_REQUESTS_ID_3"/>
-	<value value="62" name="AXI_TOTAL_REQUESTS_ID_4"/>
-	<value value="63" name="AXI_TOTAL_REQUESTS_ID_5"/>
-	<value value="64" name="AXI_TOTAL_REQUESTS_ID_6"/>
-	<value value="65" name="AXI_TOTAL_REQUESTS_ID_7"/>
-	<value value="66" name="AXI_TOTAL_REQUESTS"/>
-	<value value="67" name="AXI_READ_CHANNEL_BURSTS_ID_0"/>
-	<value value="68" name="AXI_READ_CHANNEL_BURSTS_ID_1"/>
-	<value value="69" name="AXI_READ_CHANNEL_BURSTS_ID_2"/>
-	<value value="70" name="AXI_READ_CHANNEL_BURSTS_ID_3"/>
-	<value value="71" name="AXI_READ_CHANNEL_BURSTS_ID_4"/>
-	<value value="72" name="AXI_READ_CHANNEL_BURSTS_ID_5"/>
-	<value value="73" name="AXI_READ_CHANNEL_BURSTS_ID_6"/>
-	<value value="74" name="AXI_READ_CHANNEL_BURSTS_ID_7"/>
-	<value value="75" name="AXI_READ_CHANNEL_TOTAL_BURSTS"/>
-	<value value="76" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0"/>
-	<value value="77" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1"/>
-	<value value="78" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2"/>
-	<value value="79" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3"/>
-	<value value="80" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4"/>
-	<value value="81" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5"/>
-	<value value="82" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6"/>
-	<value value="83" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7"/>
-	<value value="84" name="AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ"/>
-	<value value="85" name="AXI_WRITE_CHANNEL_BURSTS_ID_0"/>
-	<value value="86" name="AXI_WRITE_CHANNEL_BURSTS_ID_1"/>
-	<value value="87" name="AXI_WRITE_CHANNEL_BURSTS_ID_2"/>
-	<value value="88" name="AXI_WRITE_CHANNEL_BURSTS_ID_3"/>
-	<value value="89" name="AXI_WRITE_CHANNEL_BURSTS_ID_4"/>
-	<value value="90" name="AXI_WRITE_CHANNEL_BURSTS_ID_5"/>
-	<value value="91" name="AXI_WRITE_CHANNEL_BURSTS_ID_6"/>
-	<value value="92" name="AXI_WRITE_CHANNEL_BURSTS_ID_7"/>
-	<value value="93" name="AXI_WRITE_CHANNEL_TOTAL_BURSTS"/>
-	<value value="94" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0"/>
-	<value value="95" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1"/>
-	<value value="96" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2"/>
-	<value value="97" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3"/>
-	<value value="98" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4"/>
-	<value value="99" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5"/>
-	<value value="100" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6"/>
-	<value value="101" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7"/>
-	<value value="102" name="AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN"/>
-	<value value="103" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0"/>
-	<value value="104" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1"/>
-	<value value="105" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2"/>
-	<value value="106" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3"/>
-	<value value="107" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4"/>
-	<value value="108" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5"/>
-	<value value="109" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6"/>
-	<value value="110" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7"/>
-	<value value="111" name="AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES"/>
-	<value value="112" name="TOTAL_MMU_MISSES"/>
-	<value value="113" name="MMU_READ_MISSES"/>
-	<value value="114" name="MMU_WRITE_MISSES"/>
-	<value value="115" name="TOTAL_MMU_HITS"/>
-	<value value="116" name="MMU_READ_HITS"/>
-	<value value="117" name="MMU_WRITE_HITS"/>
-	<value value="118" name="SPLIT_MODE_TC_HITS"/>
-	<value value="119" name="SPLIT_MODE_TC_MISSES"/>
-	<value value="120" name="SPLIT_MODE_NON_TC_HITS"/>
-	<value value="121" name="SPLIT_MODE_NON_TC_MISSES"/>
-	<value value="122" name="STALL_AWAITING_TLB_MISS_FETCH"/>
-	<value value="123" name="MMU_TLB_MISS_READ_BURSTS_RECEIVED"/>
-	<value value="124" name="MMU_TLB_MISS_DATA_BEATS_READ"/>
-	<value value="125" name="CP_CYCLES_HELD_OFF"/>
-	<value value="126" name="VGT_CYCLES_HELD_OFF"/>
-	<value value="127" name="TC_CYCLES_HELD_OFF"/>
-	<value value="128" name="TC_ROQ_CYCLES_HELD_OFF"/>
-	<value value="129" name="TC_CYCLES_HELD_OFF_TCD_FULL"/>
-	<value value="130" name="RB_CYCLES_HELD_OFF"/>
-	<value value="131" name="TOTAL_CYCLES_ANY_CLNT_HELD_OFF"/>
-	<value value="132" name="TLB_MISS_CYCLES_HELD_OFF"/>
-	<value value="133" name="AXI_READ_REQUEST_HELD_OFF"/>
-	<value value="134" name="AXI_WRITE_REQUEST_HELD_OFF"/>
-	<value value="135" name="AXI_REQUEST_HELD_OFF"/>
-	<value value="136" name="AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT"/>
-	<value value="137" name="AXI_WRITE_DATA_HELD_OFF"/>
-	<value value="138" name="CP_SAME_PAGE_BANK_REQUESTS"/>
-	<value value="139" name="VGT_SAME_PAGE_BANK_REQUESTS"/>
-	<value value="140" name="TC_SAME_PAGE_BANK_REQUESTS"/>
-	<value value="141" name="TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS"/>
-	<value value="142" name="RB_SAME_PAGE_BANK_REQUESTS"/>
-	<value value="143" name="TOTAL_SAME_PAGE_BANK_REQUESTS"/>
-	<value value="144" name="CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT"/>
-	<value value="145" name="VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT"/>
-	<value value="146" name="TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT"/>
-	<value value="147" name="RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT"/>
-	<value value="148" name="TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT"/>
-	<value value="149" name="TOTAL_MH_READ_REQUESTS"/>
-	<value value="150" name="TOTAL_MH_WRITE_REQUESTS"/>
-	<value value="151" name="TOTAL_MH_REQUESTS"/>
-	<value value="152" name="MH_BUSY"/>
-	<value value="153" name="CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE"/>
-	<value value="154" name="VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE"/>
-	<value value="155" name="TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE"/>
-	<value value="156" name="RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE"/>
-	<value value="157" name="TC_ROQ_N_VALID_ENTRIES"/>
-	<value value="158" name="ARQ_N_ENTRIES"/>
-	<value value="159" name="WDB_N_ENTRIES"/>
-	<value value="160" name="MH_READ_LATENCY_OUTST_REQ_SUM"/>
-	<value value="161" name="MC_READ_LATENCY_OUTST_REQ_SUM"/>
-	<value value="162" name="MC_TOTAL_READ_REQUESTS"/>
-	<value value="163" name="ELAPSED_CYCLES_MH_GATED_CLK"/>
-	<value value="164" name="ELAPSED_CLK_CYCLES"/>
-	<value value="165" name="CP_W_16B_REQUESTS"/>
-	<value value="166" name="CP_W_32B_REQUESTS"/>
-	<value value="167" name="TC_16B_REQUESTS"/>
-	<value value="168" name="TC_32B_REQUESTS"/>
-	<value value="169" name="PA_REQUESTS"/>
-	<value value="170" name="PA_DATA_BYTES_WRITTEN"/>
-	<value value="171" name="PA_WRITE_CLEAN_RESPONSES"/>
-	<value value="172" name="PA_CYCLES_HELD_OFF"/>
-	<value value="173" name="AXI_READ_REQUEST_DATA_BEATS_ID_0"/>
-	<value value="174" name="AXI_READ_REQUEST_DATA_BEATS_ID_1"/>
-	<value value="175" name="AXI_READ_REQUEST_DATA_BEATS_ID_2"/>
-	<value value="176" name="AXI_READ_REQUEST_DATA_BEATS_ID_3"/>
-	<value value="177" name="AXI_READ_REQUEST_DATA_BEATS_ID_4"/>
-	<value value="178" name="AXI_READ_REQUEST_DATA_BEATS_ID_5"/>
-	<value value="179" name="AXI_READ_REQUEST_DATA_BEATS_ID_6"/>
-	<value value="180" name="AXI_READ_REQUEST_DATA_BEATS_ID_7"/>
-	<value value="181" name="AXI_TOTAL_READ_REQUEST_DATA_BEATS"/>
-</enum>
-
 <domain name="A2XX" width="32">
 
 	<bitset name="a2xx_vgt_current_bin_id_min_max" inline="yes">
@@ -1572,8 +1387,6 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 	<reg32 offset="0x2357" name="A225_GRAS_UCP5W"/>
 	<reg32 offset="0x2360" name="A225_GRAS_UCP_ENABLED"/>
 	<reg32 offset="0x2380" name="PA_SU_POLY_OFFSET_FRONT_SCALE"/>
-	<reg32 offset="0x2381" name="PA_SU_POLY_OFFSET_FRONT_OFFSET"/>
-	<reg32 offset="0x2382" name="PA_SU_POLY_OFFSET_BACK_SCALE"/>
 	<reg32 offset="0x2383" name="PA_SU_POLY_OFFSET_BACK_OFFSET"/>
 	<reg32 offset="0x4000" name="SQ_CONSTANT_0"/>
 	<reg32 offset="0x4800" name="SQ_FETCH_0"/>
@@ -1687,6 +1500,12 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 	<reg32 offset="0x0a4c" name="MH_PERFCOUNTER1_LOW"/>
 	<reg32 offset="0x0a49" name="MH_PERFCOUNTER0_HI"/>
 	<reg32 offset="0x0a4d" name="MH_PERFCOUNTER1_HI"/>
+	<reg32 offset="0x0395" name="RBBM_PERFCOUNTER1_SELECT"/>
+	<reg32 offset="0x0397" name="RBBM_PERFCOUNTER1_LO"/>
+	<reg32 offset="0x0398" name="RBBM_PERFCOUNTER1_HI"/>
+	<reg32 offset="0x0445" name="CP_PERFCOUNTER_SELECT"/>
+	<reg32 offset="0x0446" name="CP_PERFCOUNTER_LO"/>
+	<reg32 offset="0x0447" name="CP_PERFCOUNTER_HI"/>
 	<reg32 offset="0x0f04" name="RB_PERFCOUNTER0_SELECT"/>
 	<reg32 offset="0x0f08" name="RB_PERFCOUNTER0_LOW"/>
 	<reg32 offset="0x0f09" name="RB_PERFCOUNTER0_HI"/>
@@ -1740,11 +1559,11 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 		<value name="SQ_TEX_BORDER_COLOR_ACBCRY_BLACK" value="3"/>
 	</enum>
 	<enum name="sq_tex_sign">
-		<value name="SQ_TEX_SIGN_UNSIGNED" value="0"/>
+		<value name="SQ_TEX_SIGN_UNISIGNED" value="0"/>
 		<value name="SQ_TEX_SIGN_SIGNED" value="1"/>
 		<!-- biased: 2*color-1 (range -1,1 when sampling) -->
-		<value name="SQ_TEX_SIGN_UNSIGNED_BIASED" value="2"/>
-		<!-- gamma: sRGB to linear - doesn't seem to work on adreno? -->
+		<value name="SQ_TEX_SIGN_UNISIGNED_BIASED" value="2"/>
+		<!-- gamma: sRGB to linear? -->
 		<value name="SQ_TEX_SIGN_GAMMA" value="3"/>
 	</enum>
 	<enum name="sq_tex_endian">
@@ -1799,7 +1618,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 		<bitfield name="SWIZ_Y" low="4" high="6" type="sq_tex_swiz"/>
 		<bitfield name="SWIZ_Z" low="7" high="9" type="sq_tex_swiz"/>
 		<bitfield name="SWIZ_W" low="10" high="12" type="sq_tex_swiz"/>
-		<bitfield name="EXP_ADJUST" low="13" high="18" type="int"/>
+		<bitfield name="EXP_ADJUST" low="13" high="18" type="uint"/>
 		<bitfield name="XY_MAG_FILTER" low="19" high="20" type="sq_tex_filter"/>
 		<bitfield name="XY_MIN_FILTER" low="21" high="22" type="sq_tex_filter"/>
 		<bitfield name="MIP_FILTER" low="23" high="24" type="sq_tex_filter"/>
diff --git a/lib/mesa/src/freedreno/registers/a3xx.xml b/lib/mesa/src/freedreno/registers/a3xx.xml
index 93b14e139..bf93b0cb0 100644
--- a/lib/mesa/src/freedreno/registers/a3xx.xml
+++ b/lib/mesa/src/freedreno/registers/a3xx.xml
@@ -1186,6 +1186,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 	<reg32 offset="0x2243" name="VFD_INDEX_MAX" type="uint"/>
 	<reg32 offset="0x2244" name="VFD_INSTANCEID_OFFSET" type="uint"/>
 	<reg32 offset="0x2245" name="VFD_INDEX_OFFSET" type="uint"/>
+	<reg32 offset="0x2245" name="VFD_INDEX_OFFSET" type="uint"/>
 	<array offset="0x2246" name="VFD_FETCH" stride="2" length="16">
 		<reg32 offset="0x0" name="INSTR_0">
 			<bitfield name="FETCHSIZE" low="0" high="6" type="uint"/>
diff --git a/lib/mesa/src/freedreno/registers/a4xx.xml b/lib/mesa/src/freedreno/registers/a4xx.xml
index 0fa914847..5012e1bd3 100644
--- a/lib/mesa/src/freedreno/registers/a4xx.xml
+++ b/lib/mesa/src/freedreno/registers/a4xx.xml
@@ -1304,6 +1304,8 @@ perhaps they should be taken with a grain of salt
 	<reg32 offset="0x0113" name="RBBM_PERFCTR_UCHE_7_HI"/>
 	<reg32 offset="0x0114" name="RBBM_PERFCTR_TP_0_LO"/>
 	<reg32 offset="0x0115" name="RBBM_PERFCTR_TP_0_HI"/>
+	<reg32 offset="0x0114" name="RBBM_PERFCTR_TP_0_LO"/>
+	<reg32 offset="0x0115" name="RBBM_PERFCTR_TP_0_HI"/>
 	<reg32 offset="0x0116" name="RBBM_PERFCTR_TP_1_LO"/>
 	<reg32 offset="0x0117" name="RBBM_PERFCTR_TP_1_HI"/>
 	<reg32 offset="0x0118" name="RBBM_PERFCTR_TP_2_LO"/>
@@ -1433,6 +1435,7 @@ perhaps they should be taken with a grain of salt
 
 	<reg32 offset="0x0099" name="RBBM_SP_REGFILE_SLEEP_CNTL_0"/>
 	<reg32 offset="0x009a" name="RBBM_SP_REGFILE_SLEEP_CNTL_1"/>
+	<reg32 offset="0x0168" name="RBBM_PERFCTR_PWR_1_LO"/>
 	<reg32 offset="0x0170" name="RBBM_PERFCTR_CTL"/>
 	<reg32 offset="0x0171" name="RBBM_PERFCTR_LOAD_CMD0"/>
 	<reg32 offset="0x0172" name="RBBM_PERFCTR_LOAD_CMD1"/>
diff --git a/lib/mesa/src/freedreno/registers/a5xx.xml b/lib/mesa/src/freedreno/registers/a5xx.xml
index 42726fceb..16b8d2c7b 100644
--- a/lib/mesa/src/freedreno/registers/a5xx.xml
+++ b/lib/mesa/src/freedreno/registers/a5xx.xml
@@ -1385,6 +1385,10 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 	<reg32 offset="0x0468" name="RBBM_PERFCTR_LOAD_CMD3"/>
 	<reg32 offset="0x0469" name="RBBM_PERFCTR_LOAD_VALUE_LO"/>
 	<reg32 offset="0x046a" name="RBBM_PERFCTR_LOAD_VALUE_HI"/>
+	<reg32 offset="0x046b" name="RBBM_PERFCTR_RBBM_SEL_0"/>
+	<reg32 offset="0x046c" name="RBBM_PERFCTR_RBBM_SEL_1"/>
+	<reg32 offset="0x046d" name="RBBM_PERFCTR_RBBM_SEL_2"/>
+	<reg32 offset="0x046e" name="RBBM_PERFCTR_RBBM_SEL_3"/>
 	<reg32 offset="0x046f" name="RBBM_PERFCTR_GPU_BUSY_MASKED"/>
 	<reg32 offset="0x04ed" name="RBBM_AHB_ERROR"/>
 	<reg32 offset="0x0504" name="RBBM_CFG_DBGBUS_EVENT_LOGIC"/>
@@ -1703,6 +1707,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 	<reg32 offset="0xa892" name="GPMU_PWR_COL_INTER_FRAME_CTRL"/>
 	<reg32 offset="0xa893" name="GPMU_PWR_COL_INTER_FRAME_HYST"/>
 	<reg32 offset="0xa894" name="GPMU_PWR_COL_BINNING_CTRL"/>
+	<reg32 offset="0xa8a3" name="GPMU_CLOCK_THROTTLE_CTRL"/>
 	<reg32 offset="0xa8c1" name="GPMU_WFI_CONFIG"/>
 	<reg32 offset="0xa8d6" name="GPMU_RBBM_INTR_INFO"/>
 	<reg32 offset="0xa8d8" name="GPMU_CM3_SYSRESET"/>
diff --git a/lib/mesa/src/freedreno/registers/a6xx.xml b/lib/mesa/src/freedreno/registers/a6xx.xml
index 2cfa49f0a..6868ed552 100644
--- a/lib/mesa/src/freedreno/registers/a6xx.xml
+++ b/lib/mesa/src/freedreno/registers/a6xx.xml
@@ -26,11 +26,10 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 	<value value="0x18" name="RB6_R16_UINT"/>
 	<value value="0x19" name="RB6_R16_SINT"/>
 	<value value="0x30" name="RB6_R8G8B8A8_UNORM"/>
-	<value value="0x31" name="RB6_R8G8B8X8_UNORM"/> <!-- 32 bpp format, samples 1 for alpha -->
+	<value value="0x31" name="RB6_R8G8B8_UNORM"/>
 	<value value="0x32" name="RB6_R8G8B8A8_SNORM"/>
 	<value value="0x33" name="RB6_R8G8B8A8_UINT"/>
 	<value value="0x34" name="RB6_R8G8B8A8_SINT"/>
-	<value value="0x36" name="RB6_R10G10B10A2_FLOAT16"/>  <!-- float16 for 2d blit? -->
 	<value value="0x37" name="RB6_R10G10B10A2_UNORM"/>  <!-- GL_RGB10_A2 -->
 	<value value="0x3a" name="RB6_R10G10B10A2_UINT"/>   <!-- GL_RGB10_A2UI -->
 	<value value="0x42" name="RB6_R11G11B10_FLOAT"/>    <!-- GL_R11F_G11F_B10F -->
@@ -53,8 +52,8 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 	<value value="0x82" name="RB6_R32G32B32A32_FLOAT"/>
 	<value value="0x83" name="RB6_R32G32B32A32_UINT"/>
 	<value value="0x84" name="RB6_R32G32B32A32_SINT"/>
-	<value value="0x91" name="RB6_Z24_UNORM_S8_UINT_AS_R8G8B8A8"/>
-	<value value="0xa0" name="RB6_Z24_UNORM_S8_UINT"/>
+	<value value="0x91" name="RB6_Z24_UNORM_S8_UINT"/>
+	<value value="0xa0" name="RB6_X8Z24_UNORM"/>
 </enum>
 
 <!-- these might be same as a5xx -->
@@ -231,9 +230,6 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 	<value value="0xcc" name="TFMT6_ASTC_10x10"/>
 	<value value="0xcd" name="TFMT6_ASTC_12x10"/>
 	<value value="0xce" name="TFMT6_ASTC_12x12"/>
-
-	<!-- same as X8Z24_UNORM but for sampling stencil (integer, 2nd channel) -->
-	<value value="0xea" name="TFMT6_S8Z24_UINT"/>
 </enum>
 
 <enum name="a6xx_tex_fetchsize">
@@ -948,7 +944,7 @@ blending?  The one exception is that 16b unorm and 32b float use the
 same value... maybe 16b unorm is uncommon enough that it was just easier
 to upconvert to 32b float internally?
 
- 8b unorm:  10 (sometimes 0, is the high bit part of something else?)
+ 8b unorm:  10
 16b unorm:   4
 
 32b int:     7
@@ -965,12 +961,10 @@ to upconvert to 32b float internally?
 	<value value="0x5"  name="R2D_INT8"/>
 	<value value="0x4"  name="R2D_FLOAT32"/>
 	<value value="0x3"  name="R2D_FLOAT16"/>
-	<value value="0x1"  name="R2D_UNORM8_SRGB"/>
-	<value value="0x0"  name="R2D_RAW"/>
 </enum>
 
 <domain name="A6XX" width="32">
-	<bitset name="A6XX_RBBM_INT_0_MASK" inline="yes">
+	<bitset name="A6XX_RBBM_INT_0_MASK">
 		<bitfield name="RBBM_GPU_IDLE" pos="0"/>
 		<bitfield name="CP_AHB_ERROR" pos="1"/>
 		<bitfield name="RBBM_ATB_ASYNCFIFO_OVERFLOW" pos="6"/>
@@ -1376,36 +1370,6 @@ to upconvert to 32b float internally?
 	<reg32 offset="0x050A" name="RBBM_PERFCTR_RBBM_SEL_3"/>
 	<reg32 offset="0x050B" name="RBBM_PERFCTR_GPU_BUSY_MASKED"/>
 	<reg32 offset="0x0533" name="RBBM_ISDB_CNT"/>
-
-	<!---
-	    This block of registers aren't tied to perf counters. They
-	    count various geometry stats, for example number of
-	    vertices in, number of primnitives assembled etc.
-	-->
-
-	<reg32 offset="0x0540" name="RBBM_PRIMCTR_0_LO"/>  <!-- vs vertices in -->
-	<reg32 offset="0x0541" name="RBBM_PRIMCTR_0_HI"/>
-	<reg32 offset="0x0542" name="RBBM_PRIMCTR_1_LO"/>  <!-- vs primitives out -->
-	<reg32 offset="0x0543" name="RBBM_PRIMCTR_1_HI"/>
-	<reg32 offset="0x0544" name="RBBM_PRIMCTR_2_LO"/>  <!-- hs vertices in -->
-	<reg32 offset="0x0545" name="RBBM_PRIMCTR_2_HI"/>
-	<reg32 offset="0x0546" name="RBBM_PRIMCTR_3_LO"/>  <!-- hs patches out -->
-	<reg32 offset="0x0547" name="RBBM_PRIMCTR_3_HI"/>
-	<reg32 offset="0x0548" name="RBBM_PRIMCTR_4_LO"/>  <!-- dss vertices in -->
-	<reg32 offset="0x0549" name="RBBM_PRIMCTR_4_HI"/>
-	<reg32 offset="0x054a" name="RBBM_PRIMCTR_5_LO"/>  <!-- ds primitives out -->
-	<reg32 offset="0x054b" name="RBBM_PRIMCTR_5_HI"/>
-	<reg32 offset="0x054c" name="RBBM_PRIMCTR_6_LO"/>  <!-- gs primitives in -->
-	<reg32 offset="0x054d" name="RBBM_PRIMCTR_6_HI"/>
-	<reg32 offset="0x054e" name="RBBM_PRIMCTR_7_LO"/>  <!-- gs primitives out -->
-	<reg32 offset="0x054f" name="RBBM_PRIMCTR_7_HI"/>
-	<reg32 offset="0x0550" name="RBBM_PRIMCTR_8_LO"/>  <!-- gs primitives out -->
-	<reg32 offset="0x0551" name="RBBM_PRIMCTR_8_HI"/>
-	<reg32 offset="0x0552" name="RBBM_PRIMCTR_9_LO"/>  <!-- raster primitives in -->
-	<reg32 offset="0x0553" name="RBBM_PRIMCTR_9_HI"/>
-	<reg32 offset="0x0554" name="RBBM_PRIMCTR_10_LO"/>
-	<reg32 offset="0x0555" name="RBBM_PRIMCTR_10_HI"/>
-
 	<reg32 offset="0xF400" name="RBBM_SECVID_TRUST_CNTL"/>
 	<reg32 offset="0xF800" name="RBBM_SECVID_TSB_TRUSTED_BASE_LO"/>
 	<reg32 offset="0xF801" name="RBBM_SECVID_TSB_TRUSTED_BASE_HI"/>
@@ -1780,7 +1744,6 @@ to upconvert to 32b float internally?
 	</reg32>
 	<reg32 offset="0x0c03" name="VSC_SIZE_ADDRESS_LO"/>
 	<reg32 offset="0x0c04" name="VSC_SIZE_ADDRESS_HI"/>
-	<reg64 offset="0x0c03" name="VSC_SIZE_ADDRESS" type="waddress"/>
 	<reg32 offset="0x0c06" name="VSC_BIN_COUNT">
 		<bitfield name="NX" low="1" high="10" type="uint"/>
 		<bitfield name="NY" low="11" high="20" type="uint"/>
@@ -1821,12 +1784,10 @@ to upconvert to 32b float internally?
 	 -->
 	<reg32 offset="0x0c30" name="VSC_PIPE_DATA2_ADDRESS_LO"/>
 	<reg32 offset="0x0c31" name="VSC_PIPE_DATA2_ADDRESS_HI"/>
-	<reg64 offset="0x0c30" name="VSC_PIPE_DATA2_ADDRESS" type="waddress"/>
 	<reg32 offset="0x0c32" name="VSC_PIPE_DATA2_PITCH"/>
 	<reg32 offset="0x0c33" name="VSC_PIPE_DATA2_ARRAY_PITCH" shr="4" type="uint"/>
 	<reg32 offset="0x0c34" name="VSC_PIPE_DATA_ADDRESS_LO"/>
 	<reg32 offset="0x0c35" name="VSC_PIPE_DATA_ADDRESS_HI"/>
-	<reg64 offset="0x0c34" name="VSC_PIPE_DATA_ADDRESS" type="waddress"/>
 	<reg32 offset="0x0c36" name="VSC_PIPE_DATA_PITCH"/>
 	<reg32 offset="0x0c37" name="VSC_PIPE_DATA_ARRAY_PITCH" shr="4" type="uint"/>
 
@@ -1862,20 +1823,9 @@ to upconvert to 32b float internally?
 
 	<reg32 offset="0x8000" name="GRAS_UNKNOWN_8000"/>
 	<reg32 offset="0x8001" name="GRAS_UNKNOWN_8001"/>
-	<reg32 offset="0x8002" name="GRAS_UNKNOWN_8002"/>
-	<reg32 offset="0x8003" name="GRAS_UNKNOWN_8003"/>
-
-	<enum name="a6xx_layer_type">
-	  <value value="0x0" name="LAYER_MULTISAMPLE_ARRAY"/>
-	  <value value="0x1" name="LAYER_3D"/>
-	  <value value="0x2" name="LAYER_CUBEMAP"/>
-	  <value value="0x3" name="LAYER_2D_ARRAY"/>
-	</enum>
 
-	<reg32 offset="0x8004" name="GRAS_LAYER_CNTL">
-		<bitfield name="LAYERED" pos="0" type="boolean"/>
-		<bitfield name="TYPE" low="1" high="2" type="a6xx_layer_type"/>
-	</reg32>
+	<!-- always 0x0 ? -->
+	<reg32 offset="0x8004" name="GRAS_UNKNOWN_8004"/>
 
 	<reg32 offset="0x8005" name="GRAS_CNTL">
 		<!-- see also RB_RENDER_CONTROL0 -->
@@ -1939,12 +1889,6 @@ to upconvert to 32b float internally?
 	<!-- always 0x0 ? -->
 	<reg32 offset="0x809b" name="GRAS_UNKNOWN_809B"/>
 
-	<reg32 offset="0x809c" name="GRAS_UNKNOWN_809C">
-		<bitfield name="GS_WRITES_LAYER" pos="0" type="boolean"/>
-	</reg32>
-
-	<reg32 offset="0x809d" name="GRAS_UNKNOWN_809D"/>
-
 	<reg32 offset="0x80a0" name="GRAS_UNKNOWN_80A0"/>
 
 	<reg32 offset="0x80a2" name="GRAS_RAS_MSAA_CNTL">
@@ -1981,9 +1925,10 @@ to upconvert to 32b float internally?
 		<bitfield name="LRZ_WRITE" pos="1" type="boolean"/>
 		<doc>update MAX instead of MIN value, ie. GL_GREATER/GL_GEQUAL</doc>
 		<bitfield name="GREATER" pos="2" type="boolean"/>
+		<!-- set at end of batch that had LRZ enabled (to flush/disable it?) -->
 		<bitfield name="UNK3" pos="3" type="boolean"/>
 		<!-- set when depth-test + depth-write enabled -->
-		<bitfield name="Z_TEST_ENABLE" pos="4" type="boolean"/>
+		<bitfield name="UNK4" pos="4" type="boolean"/>
 	</reg32>
 	<reg32 offset="0x8101" name="GRAS_UNKNOWN_8101"/>
 	<reg32 offset="0x8102" name="GRAS_2D_BLIT_INFO">
@@ -1991,14 +1936,12 @@ to upconvert to 32b float internally?
 	</reg32>
 	<reg32 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE_LO"/>
 	<reg32 offset="0x8104" name="GRAS_LRZ_BUFFER_BASE_HI"/>
-	<reg64 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE" type="waddress"/>
 	<reg32 offset="0x8105" name="GRAS_LRZ_BUFFER_PITCH">
 		<bitfield name="PITCH" low="0" high="10" shr="5" type="uint"/>
 		<bitfield name="ARRAY_PITCH" low="11" high="21" shr="5" type="uint"/> <!-- ??? -->
 	</reg32>
 	<reg32 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO"/>
 	<reg32 offset="0x8107" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI"/>
-	<reg32 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE" type="waddress"/>
 
 	<reg32 offset="0x8109" name="GRAS_SAMPLE_CNTL">
 		<bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>
@@ -2011,22 +1954,19 @@ to upconvert to 32b float internally?
 	  <value value="0x1" name="ROTATE_90"/>
 	  <value value="0x2" name="ROTATE_180"/>
 	  <value value="0x3" name="ROTATE_270"/>
-	  <value value="0x4" name="ROTATE_HFLIP"/>
-	  <value value="0x5" name="ROTATE_VFLIP"/>
 	</enum>
 
 	<bitset name="a6xx_2d_blit_cntl" inline="yes">
-		<bitfield name="ROTATE" low="0" high="2" type="a6xx_rotation"/>
-		<bitfield name="SOLID_COLOR" pos="7" type="boolean"/>
+		<bitfield name="ROTATE" low="0" high="1" type="a6xx_rotation"/>
+		<bitfield name="HORIZONTAL_FLIP" low="2" high="2" type="boolean"/>
+		<bitfield name="SOLID_COLOR" low="4" high="4" type="boolean"/>
 		<bitfield name="COLOR_FORMAT" low="8" high="15" type="a6xx_color_fmt"/>
 		<bitfield name="SCISSOR" pos="16" type="boolean"/>
-
-		<bitfield name="UNK" low="17" high="18" type="uint"/>
-
-		<!-- required when blitting D24S8/D24X8 -->
-		<bitfield name="D24S8" pos="19" type="boolean"/>
-		<!-- some sort of channel mask, disabled channels are set to zero ? -->
-		<bitfield name="MASK" low="20" high="23"/>
+		<!-- double check these:
+		<bitfield name="FLAGS" pos="18" type="boolean"/>
+		<bitfield name="TILE_MODE" low="20" high="21" type="a6xx_tile_mode"/>
+		<bitfield name="COLOR_SWAP" low="22" high="23" type="a3xx_color_swap"/>
+		-->
 		<bitfield name="IFMT" low="24" high="28" type="a6xx_2d_ifmt"/>
 	</bitset>
 
@@ -2210,9 +2150,6 @@ to upconvert to 32b float internally?
 		 -->
 		<reg32 offset="0x5" name="BASE_LO"/>
 		<reg32 offset="0x6" name="BASE_HI"/>
-
-		<reg64 offset="0x5" name="BASE" type="waddress"/>
-
 		<reg32 offset="0x7" name="BASE_GMEM"/>
 	</array>
 
@@ -2256,7 +2193,6 @@ to upconvert to 32b float internally?
 	</reg32>
 	<reg32 offset="0x8875" name="RB_DEPTH_BUFFER_BASE_LO"/>
 	<reg32 offset="0x8876" name="RB_DEPTH_BUFFER_BASE_HI"/>
-	<reg64 offset="0x8875" name="RB_DEPTH_BUFFER_BASE" type="waddress"/>
 	<reg32 offset="0x8877" name="RB_DEPTH_BUFFER_BASE_GMEM"/>
 
 	<!-- always 0x0 ? -->
@@ -2294,7 +2230,6 @@ to upconvert to 32b float internally?
 	</reg32>
 	<reg32 offset="0x8884" name="RB_STENCIL_BUFFER_BASE_LO"/>
 	<reg32 offset="0x8885" name="RB_STENCIL_BUFFER_BASE_HI"/>
-	<reg64 offset="0x8884" name="RB_STENCIL_BUFFER_BASE" type="waddress"/>
 	<reg32 offset="0x8886" name="RB_STENCIL_BUFFER_BASE_GMEM"/>
 	<reg32 offset="0x8887" name="RB_STENCILREF">
 		<bitfield name="REF" low="0" high="7"/>
@@ -2333,13 +2268,11 @@ to upconvert to 32b float internally?
 		<bitfield name="COLOR_FORMAT" low="7" high="14" type="a6xx_color_fmt"/>
 		<bitfield name="COLOR_SWAP" low="5" high="6" type="a3xx_color_swap"/>
 	</reg32>
-	<reg64 offset="0x88d8" name="RB_BLIT_DST" type="waddress"/>
 	<reg32 offset="0x88d8" name="RB_BLIT_DST_LO"/>
 	<reg32 offset="0x88d9" name="RB_BLIT_DST_HI"/>
 	<reg32 offset="0x88da" name="RB_BLIT_DST_PITCH" shr="6" type="uint"/>
 	<!-- array-pitch is size of layer -->
 	<reg32 offset="0x88db" name="RB_BLIT_DST_ARRAY_PITCH" shr="6" type="uint"/>
-	<reg64 offset="0x88dc" name="RB_BLIT_FLAG_DST" type="waddress"/>
 	<reg32 offset="0x88dc" name="RB_BLIT_FLAG_DST_LO"/>
 	<reg32 offset="0x88dd" name="RB_BLIT_FLAG_DST_HI"/>
 	<reg32 offset="0x88de" name="RB_BLIT_FLAG_DST_PITCH">
@@ -2374,7 +2307,6 @@ to upconvert to 32b float internally?
 
 	<reg32 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE_LO"/>
 	<reg32 offset="0x8901" name="RB_DEPTH_FLAG_BUFFER_BASE_HI"/>
-	<reg64 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE" type="waddress"/>
 	<reg32 offset="0x8902" name="RB_DEPTH_FLAG_BUFFER_PITCH">
 		<bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
 		<bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/>
@@ -2382,7 +2314,6 @@ to upconvert to 32b float internally?
 	<array offset="0x8903" name="RB_MRT_FLAG_BUFFER" stride="3" length="8">
 		<reg32 offset="0" name="ADDR_LO"/>
 		<reg32 offset="1" name="ADDR_HI"/>
-		<reg64 offset="0" name="ADDR" type="waddress"/>
 		<reg32 offset="2" name="PITCH">
 			<bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
 			<bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/> <!-- ??? -->
@@ -2394,20 +2325,13 @@ to upconvert to 32b float internally?
 	<reg32 offset="0x8c00" name="RB_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl"/>
 	<reg32 offset="0x8c01" name="RB_UNKNOWN_8C01"/>
 
-	<bitset name="a6xx_2d_surf_info" inline="yes">
+	<reg32 offset="0x8c17" name="RB_2D_DST_INFO">
 		<bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_color_fmt"/>
 		<bitfield name="TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
 		<bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>
 		<!-- b12 seems to be set when UBWC "FLAGS" buffer enabled -->
 		<bitfield name="FLAGS" pos="12" type="boolean"/>
-		<bitfield name="SRGB" pos="13" type="boolean"/>
-		<!-- the rest is only for src -->
-		<bitfield name="SAMPLES" low="14" high="15" type="a3xx_msaa_samples"/>
-		<bitfield name="FILTER" pos="16" type="boolean"/>
-		<bitfield name="SAMPLES_AVERAGE" pos="18" type="boolean"/>
-	</bitset>
-
-	<reg32 offset="0x8c17" name="RB_2D_DST_INFO" type="a6xx_2d_surf_info"/>
+	</reg32>
 	<reg32 offset="0x8c18" name="RB_2D_DST_LO"/>
 	<reg32 offset="0x8c19" name="RB_2D_DST_HI"/>
 	<reg32 offset="0x8c1a" name="RB_2D_DST_SIZE">
@@ -2434,20 +2358,11 @@ to upconvert to 32b float internally?
 
 	<reg32 offset="0x8e07" name="RB_CCU_CNTL"/>  <!-- always 7c400004 or 10000000 -->
 
-	<reg32 offset="0x9100" name="VPC_UNKNOWN_9100"/>
-
 	<!-- always 0x00ffff00 ? */ -->
 	<reg32 offset="0x9101" name="VPC_UNKNOWN_9101"/>
-	<reg32 offset="0x9102" name="VPC_UNKNOWN_9102"/>
-	<reg32 offset="0x9103" name="VPC_UNKNOWN_9103"/>
 
 	<reg32 offset="0x9104" name="VPC_GS_SIV_CNTL"/>
 
-	<reg32 offset="0x9105" name="VPC_UNKNOWN_9105">
-		<bitfield name="LAYERLOC" low="0" high="7" type="uint"/>
-	</reg32>
-
-	<reg32 offset="0x9106" name="VPC_UNKNOWN_9106"/>
 	<reg32 offset="0x9107" name="VPC_UNKNOWN_9107"/>
 	<reg32 offset="0x9108" name="VPC_UNKNOWN_9108"/>
 
@@ -2479,18 +2394,12 @@ to upconvert to 32b float internally?
 		<bitfield name="B_OFF" low="14" high="22" shr="2" type="uint"/>
 		<bitfield name="B_EN" pos="23" type="boolean"/>
 	</reg32>
-
-	<reg32 offset="0x9218" name="VPC_SO_STREAM_COUNTS_LO"/>
-	<reg32 offset="0x9219" name="VPC_SO_STREAM_COUNTS_HI"/>
-
 	<array offset="0x921a" name="VPC_SO" stride="7" length="4">
-		<reg64 offset="0" name="BUFFER_BASE" type="waddress"/>
 		<reg32 offset="0" name="BUFFER_BASE_LO"/>
 		<reg32 offset="1" name="BUFFER_BASE_HI"/>
 		<reg32 offset="2" name="BUFFER_SIZE"/>
 		<reg32 offset="3" name="NCOMP"/>  <!-- component count -->
 		<reg32 offset="4" name="BUFFER_OFFSET"/>
-		<reg64 offset="5" name="FLUSH_BASE" type="waddress"/>
 		<reg32 offset="5" name="FLUSH_BASE_LO"/>
 		<reg32 offset="6" name="FLUSH_BASE_HI"/>
 	</array>
@@ -2510,7 +2419,7 @@ to upconvert to 32b float internally?
 			hw streamout (rather than stg instructions in shader)
 		</doc>
 		<bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
-		<bitfield name="POSITIONLOC" low="8" high="15" type="uint"/>
+		<bitfield name="NUMNONPOSVAR" low="8" high="15" type="uint"/>
 		<!--
 		This seems to be the OUTLOC for the psize output.  It could possibly
 		be the max-OUTLOC position, but it is only set when VS writes psize
@@ -2519,28 +2428,16 @@ to upconvert to 32b float internally?
 		<bitfield name="PSIZELOC" low="16" high="23" type="uint"/>
 	</reg32>
 
-	<reg32 offset="0x9302" name="VPC_PACK_GS">
+	<reg32 offset="0x9303" name="VPC_PACK_3">
 		<doc>
+		  domain shader version
+
 			num of varyings plus four for gl_Position (plus one if gl_PointSize)
 			plus # of transform-feedback (streamout) varyings if using the
 			hw streamout (rather than stg instructions in shader)
 		</doc>
 		<bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
-		<bitfield name="POSITIONLOC" low="8" high="15" type="uint"/>
-		<!--
-		This seems to be the OUTLOC for the psize output.  It could possibly
-		be the max-OUTLOC position, but it is only set when VS writes psize
-		(and blob always puts psize at highest OUTLOC)
-		 -->
-		<bitfield name="PSIZELOC" low="16" high="23" type="uint"/>
-	</reg32>
-
-	<reg32 offset="0x9303" name="VPC_PACK_3">
-		<doc>
-			domain shader version of VPC_PACK
-		</doc>
-		<bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
-		<bitfield name="POSITIONLOC" low="8" high="15" type="uint"/>
+		<bitfield name="NUMNONPOSVAR" low="8" high="15" type="uint"/>
 		<!--
 		This seems to be the OUTLOC for the psize output.  It could possibly
 		be the max-OUTLOC position, but it is only set when VS writes psize
@@ -2581,16 +2478,10 @@ to upconvert to 32b float internally?
 	  <value value="0x3" name="TESS_FRACTIONAL_EVEN"/>
 	</enum>
 
-	<enum name="a6xx_tess_output">
-	  <value value="0x0" name="TESS_POINTS"/>
-	  <value value="0x1" name="TESS_LINES"/>
-	  <value value="0x2" name="TESS_CW_TRIS"/>
-	  <value value="0x3" name="TESS_CCW_TRIS"/>
-	</enum>
-
 	<reg32 offset="0x9802" name="PC_TESS_CNTL">
 	  <bitfield name="SPACING" low="0" high="1" type="a6xx_tess_spacing"/>
-	  <bitfield name="OUTPUT" low="2" high="3" type="a6xx_tess_output"/>
+	  <bitfield name="CCW" pos="2" type="boolean"/>
+	  <bitfield name="PRIMITIVES" pos="3" type="boolean"/>
 	</reg32>
 
 	<!-- probably: -->
@@ -2623,16 +2514,6 @@ to upconvert to 32b float internally?
 		<bitfield name="PSIZE" pos="8" type="boolean"/>
 	</reg32>
 
-	<reg32 offset="0x9b02" name="PC_PRIMITIVE_CNTL_2">
-		<doc>
-		  geometry shader
-		</doc>
-		<bitfield name="STRIDE_IN_VPC" low="0" high="6" type="uint"/>
-		<bitfield name="PSIZE" pos="8" type="boolean"/>
-		<bitfield name="LAYER" pos="9" type="boolean"/>
-		<bitfield name="PRIMITIVE_ID" pos="11" type="boolean"/>
-	</reg32>
-
 	<reg32 offset="0x9b03" name="PC_PRIMITIVE_CNTL_3">
 		<doc>
 		        hull shader?
@@ -2655,22 +2536,8 @@ to upconvert to 32b float internally?
 		<bitfield name="PSIZE" pos="8" type="boolean"/>
 	</reg32>
 
-	<reg32 offset="0x9b05" name="PC_PRIMITIVE_CNTL_5">
-		<doc>
-		  geometry shader
-		</doc>
-		<bitfield name="GS_VERTICES_OUT" low="0" high="7" type="uint"/>
-		<bitfield name="GS_INVOCATIONS" low="10" high="14" type="uint"/>
-		<bitfield name="GS_OUTPUT" low="16" high="17" type="a6xx_tess_output"/>
-	</reg32>
-
-	<reg32 offset="0x9b06" name="PC_PRIMITIVE_CNTL_6">
-		<doc>
-		  size in vec4s of per-primitive storage for gs
-		</doc>
-		<bitfield name="STRIDE_IN_VPC" low="0" high="8" type="uint"/>
-	</reg32>
-
+	<!-- always 0x0 ? -->
+	<reg32 offset="0x9b06" name="PC_UNKNOWN_9B06"/>
 	<reg32 offset="0x9b07" name="PC_UNKNOWN_9B07"/>
 
 	<reg32 offset="0x9e08" name="PC_TESSFACTOR_ADDR_LO"/>
@@ -2699,7 +2566,6 @@ to upconvert to 32b float internally?
 	<reg32 offset="0xa004" name="VFD_CONTROL_4">
 	</reg32>
 	<reg32 offset="0xa005" name="VFD_CONTROL_5">
-		<bitfield name="REGID_GSHEADER" low="0" high="7" type="a3xx_regid"/>
 	</reg32>
 	<reg32 offset="0xa006" name="VFD_CONTROL_6">
 	</reg32>
@@ -2710,17 +2576,11 @@ to upconvert to 32b float internally?
 
 	<!-- always 0x0 ? -->
 	<reg32 offset="0xa008" name="VFD_UNKNOWN_A008"/>
-	<reg32 offset="0xa009" name="VFD_ADD_OFFSET">
-		<!-- add VFD_INDEX_OFFSET to REGID4VTX -->
-		<bitfield name="VERTEX" pos="0" type="boolean"/>
-		<!-- add VFD_INSTANCE_START_OFFSET to REGID4INST -->
-		<bitfield name="INSTANCE" pos="1" type="boolean"/>
-	</reg32>
+	<reg32 offset="0xa009" name="VFD_UNKNOWN_A009"/>
 
 	<reg32 offset="0xa00e" name="VFD_INDEX_OFFSET"/>
 	<reg32 offset="0xa00f" name="VFD_INSTANCE_START_OFFSET"/>
 	<array offset="0xa010" name="VFD_FETCH" stride="4" length="32">
-		<reg64 offset="0x0" name="BASE" type="address"/>
 		<reg32 offset="0x0" name="BASE_LO"/>
 		<reg32 offset="0x1" name="BASE_HI"/>
 		<reg32 offset="0x2" name="SIZE" type="uint"/>
@@ -2748,6 +2608,34 @@ to upconvert to 32b float internally?
 	<!-- always 0x1 ? -->
 	<reg32 offset="0xa0f8" name="SP_UNKNOWN_A0F8"/>
 
+	<reg32 offset="0xa802" name="SP_PRIMITIVE_CNTL">
+		<!-- # of VS outputs including pos/psize -->
+		<bitfield name="VSOUT" low="0" high="4" type="uint"/>
+	</reg32>
+	<array offset="0xa803" name="SP_VS_OUT" stride="1" length="16">
+		<reg32 offset="0x0" name="REG">
+			<bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
+			<bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
+			<bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
+			<bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
+		</reg32>
+	</array>
+	<!--
+	Starting with a5xx, position/psize outputs from shader end up in the
+	SP_VS_OUT map, with highest OUTLOCn position.  (Generally they are
+	the last entries too, except when gl_PointCoord is used, blob inserts
+	an extra varying after, but with a lower OUTLOC position.  If present,
+	psize is last, preceded by position.
+	 -->
+	<array offset="0xa813" name="SP_VS_VPC_DST" stride="1" length="8">
+		<reg32 offset="0x0" name="REG">
+			<bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
+			<bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
+			<bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
+			<bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
+		</reg32>
+	</array>
+
 	<bitset name="a6xx_sp_xs_ctrl_reg0" inline="yes">
 		<!--
 		When b31 set we just see FULLREGFOOTPRINT set.  The pattern of
@@ -2769,8 +2657,6 @@ to upconvert to 32b float internally?
 		<bitfield name="BRANCHSTACK" low="14" high="19" type="uint"/>
 		<bitfield name="THREADSIZE" pos="20" type="a3xx_threadsize"/>
 		<bitfield name="VARYING" pos="22" type="boolean"/>
-		<!-- set when dFdxFine/dFdyFine is used -->
-		<bitfield name="DIFF_FINE" pos="23" type="boolean"/>
 		<bitfield name="PIXLODENABLE" pos="26" type="boolean"/>
 		<bitfield name="MERGEDREGS" pos="31" type="boolean"/>
 	</bitset>
@@ -2787,34 +2673,6 @@ to upconvert to 32b float internally?
 	</bitset>
 
 	<reg32 offset="0xa800" name="SP_VS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
-	<reg32 offset="0xa802" name="SP_PRIMITIVE_CNTL">
-		<!-- # of VS outputs including pos/psize -->
-		<bitfield name="VSOUT" low="0" high="4" type="uint"/>
-	</reg32>
-	<array offset="0xa803" name="SP_VS_OUT" stride="1" length="16">
-		<reg32 offset="0x0" name="REG">
-			<bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
-			<bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
-			<bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
-			<bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
-		</reg32>
-	</array>
-	<!--
-	Starting with a5xx, position/psize outputs from shader end up in the
-	SP_VS_OUT map, with highest OUTLOCn position.  (Generally they are
-	the last entries too, except when gl_PointCoord is used, blob inserts
-	an extra varying after, but with a lower OUTLOC position.  If present,
-	psize is last, preceded by position.
-	 -->
-	<array offset="0xa813" name="SP_VS_VPC_DST" stride="1" length="8">
-		<reg32 offset="0x0" name="REG">
-			<bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
-			<bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
-			<bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
-			<bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
-		</reg32>
-	</array>
-
 	<reg32 offset="0xa81b" name="SP_UNKNOWN_A81B"/>
 	<reg32 offset="0xa81c" name="SP_VS_OBJ_START_LO"/>
 	<reg32 offset="0xa81d" name="SP_VS_OBJ_START_HI"/>
@@ -2862,31 +2720,6 @@ to upconvert to 32b float internally?
 
 	<reg32 offset="0xa870" name="SP_GS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
 	<reg32 offset="0xa871" name="SP_GS_UNKNOWN_A871"/>
-
-	<reg32 offset="0xa873" name="SP_PRIMITIVE_CNTL_GS">
-		<!-- # of VS outputs including pos/psize -->
-		<bitfield name="GSOUT" low="0" high="4" type="uint"/>
-		<bitfield name="FLAGS_REGID" low="6" high="13" type="a3xx_regid"/>
-	</reg32>
-
-	<array offset="0xa874" name="SP_GS_OUT" stride="1" length="16">
-		<reg32 offset="0x0" name="REG">
-			<bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
-			<bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
-			<bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
-			<bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
-		</reg32>
-	</array>
-
-	<array offset="0xa884" name="SP_GS_VPC_DST" stride="1" length="8">
-		<reg32 offset="0x0" name="REG">
-			<bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
-			<bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
-			<bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
-			<bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
-		</reg32>
-	</array>
-
 	<reg32 offset="0xa88d" name="SP_GS_OBJ_START_LO"/>
 	<reg32 offset="0xa88e" name="SP_GS_OBJ_START_HI"/>
 	<reg32 offset="0xa893" name="SP_GS_TEX_COUNT" type="uint"/>
@@ -2911,14 +2744,6 @@ to upconvert to 32b float internally?
 	<reg32 offset="0xa8af" name="SP_GS_TEX_CONST_HI"/>
 
 	<reg32 offset="0xa980" name="SP_FS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
-	<reg32 offset="0xa981" name="SP_UNKNOWN_A981">
-		<bitfield name="FACE0" pos="0" type="boolean"/>
-		<bitfield name="FACE1" pos="1" type="boolean"/>
-		<bitfield name="FACE2" pos="2" type="boolean"/>
-		<bitfield name="FACE3" pos="3" type="boolean"/>
-		<bitfield name="FACE4" pos="4" type="boolean"/>
-		<bitfield name="FACE5" pos="5" type="boolean"/>
-	</reg32>
 	<reg32 offset="0xa982" name="SP_UNKNOWN_A982"/>
 	<reg32 offset="0xa983" name="SP_FS_OBJ_START_LO"/>
 	<reg32 offset="0xa984" name="SP_FS_OBJ_START_HI"/>
@@ -2965,28 +2790,7 @@ to upconvert to 32b float internally?
 		</reg32>
 	</array>
 
-	<reg32 offset="0xa99e" name="SP_FS_PREFETCH_CNTL">
-		<!-- unknown bits 0x7fc0 always set -->
-		<bitfield name="COUNT" low="0" high="2" type="uint"/>
-		<!-- b3 set if no other use of varyings in the shader itself.. maybe alternative to dummy bary.f? -->
-		<bitfield name="UNK3" pos="3" type="boolean"/>
-		<bitfield name="UNK4" low="4" high="11" type="a3xx_regid"/>
-	</reg32>
-	<array offset="0xa99f" name="SP_FS_PREFETCH" stride="1" length="4">
-		<reg32 offset="0" name="CMD">
-			<bitfield name="SRC" low="0" high="6" type="uint"/>
-			<bitfield name="SAMP_ID" low="7" high="10" type="uint"/>
-			<bitfield name="TEX_ID" low="11" high="15" type="uint"/>
-			<bitfield name="DST" low="16" high="21" type="a3xx_regid"/>
-			<bitfield name="WRMASK" low="22" high="25" type="hex"/>
-			<bitfield name="HALF" pos="26" type="boolean"/>
-			<!--
-			CMD seems always 0x4??  3d, textureProj, textureLod seem to
-			skip pre-fetch.. TODO test texelFetch
-			 -->
-			<bitfield name="CMD" low="27" high="31"/>
-		</reg32>
-	</array>
+	<reg32 offset="0xa99e" name="SP_UNKNOWN_A99E"/>
 
 	<reg32 offset="0xa9a7" name="SP_FS_TEX_COUNT" type="uint"/>
 
@@ -3046,19 +2850,14 @@ to upconvert to 32b float internally?
 	<reg32 offset="0xab20" name="SP_IBO_COUNT" type="uint"/>
 
 	<!--
-	not really src, COLOR_FORMAT/SRGB seem to be related to ifmt which is for dst
+	I believe this describes the src format, but haven't seen traces with
+	src_format != dst_format
 	 -->
 	<reg32 offset="0xacc0" name="SP_2D_SRC_FORMAT">
 		<bitfield name="NORM" pos="0" type="boolean"/>
 		<bitfield name="SINT" pos="1" type="boolean"/>
 		<bitfield name="UINT" pos="2" type="boolean"/>
-		<!-- looks like HW only cares about the base type of this format,
-		     which matches the ifmt? -->
 		<bitfield name="COLOR_FORMAT" low="3" high="10" type="a6xx_color_fmt"/>
-		<!-- set when ifmt is R2D_UNORM8_SRGB -->
-		<bitfield name="SRGB" pos="11" type="boolean"/>
-		<!-- some sort of channel mask, not sure what it is for -->
-		<bitfield name="MASK" low="12" high="15"/>
 	</reg32>
 
 	<!-- always 0x0 -->
@@ -3085,7 +2884,6 @@ to upconvert to 32b float internally?
 	</reg32>
 
 	<!-- looks to work in the same way as a5xx: -->
-	<reg64 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR" type="address"/>
 	<reg32 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR_LO"/>
 	<reg32 offset="0xb303" name="SP_TP_BORDER_COLOR_BASE_ADDR_HI"/>
 	<!-- always 0x0 ? -->
@@ -3098,7 +2896,15 @@ to upconvert to 32b float internally?
 	badly named or the functionality moved in a6xx.  But downstream kernel
 	calls this "a6xx_sp_ps_tp_2d_cluster"
 	 -->
-	<reg32 offset="0xb4c0" name="SP_PS_2D_SRC_INFO" type="a6xx_2d_surf_info"/>
+	<reg32 offset="0xb4c0" name="SP_PS_2D_SRC_INFO">
+		<bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_color_fmt"/>
+		<bitfield name="TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
+		<bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>
+		<!-- b12 seems to be set when UBWC "FLAGS" buffer enabled -->
+		<bitfield name="FLAGS" pos="12" type="boolean"/>
+		<bitfield name="SAMPLES" low="14" high="15" type="a3xx_msaa_samples"/>
+		<bitfield name="FILTER" pos="16" type="boolean"/>
+	</reg32>
 	<reg32 offset="0xb4c1" name="SP_PS_2D_SRC_SIZE">
 		<bitfield name="WIDTH" low="0" high="14" type="uint"/>
 		<bitfield name="HEIGHT" low="15" high="29" type="uint"/>
@@ -3319,12 +3125,7 @@ to upconvert to 32b float internally?
 		 -->
 		<bitfield name="ARRAY_PITCH" low="0" high="13" shr="12" type="uint"/>
 		<bitfield name="MIN_LAYERSZ" low="23" high="26" shr="12"/>
-		<!--
-		by default levels with w < 16 are linear
-		TILE_ALL makes all levels have tiling
-		seems required when using UBWC, since all levels have UBWC (can possibly be disabled?)
-		 -->
-		<bitfield name="TILE_ALL" pos="27" type="boolean"/>
+		<bitfield name="UNK27" pos="27" type="boolean"/>
 		<bitfield name="FLAG" pos="28" type="boolean"/>
 	</reg32>
 	<reg32 offset="4" name="4">
@@ -3345,10 +3146,11 @@ to upconvert to 32b float internally?
 		<bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/>
 	</reg32>
 	<reg32 offset="10" name="10">
+		<!--
+		I see some other bits set by blob above FLAG_BUFFER_PITCH, but they
+		don't seem to be particularly sensible... or needed for UBWC to work
+		 -->
 		<bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/>
-		<!-- log2 size of the first level, required for mipmapping -->
-		<bitfield name="FLAG_BUFFER_LOGW" low="8" high="11" type="uint"/>
-		<bitfield name="FLAG_BUFFER_LOGH" low="12" high="15" type="uint"/>
 	</reg32>
 	<reg32 offset="11" name="11"/>
 	<reg32 offset="12" name="12"/>
@@ -3432,6 +3234,18 @@ with a better name.
 	</reg32>
 </domain>
 
+<domain name="CP_UNK_A6XX_55" width="32">
+	<reg32 offset="0" name="0">
+		<bitfield name="BASE_LO" low="0" high="31"/>
+	</reg32>
+	<reg32 offset="1" name="1">
+		<bitfield name="BASE_HI" low="0" high="16"/>
+	</reg32>
+	<reg32 offset="2" name="2">
+		<bitfield name="SIZE" low="0" high="15"/>
+	</reg32>
+</domain>
+
 <domain name="A6XX_PDC" width="32">
 	<reg32 offset="0x1140" name="GPU_ENABLE_PDC"/>
 	<reg32 offset="0x1148" name="GPU_SEQ_START_ADDR"/>
diff --git a/lib/mesa/src/freedreno/registers/adreno_pm4.xml b/lib/mesa/src/freedreno/registers/adreno_pm4.xml
index 78847fbc0..06175d3e1 100644
--- a/lib/mesa/src/freedreno/registers/adreno_pm4.xml
+++ b/lib/mesa/src/freedreno/registers/adreno_pm4.xml
@@ -15,9 +15,6 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 	<value name="VIZQUERY_START" value="7"/> <!-- on a2xx (??) -->
 	<value name="VIZQUERY_END" value="8"/>
 	<value name="SC_WAIT_WC" value="9"/>
-	<value name="WRITE_PRIMITIVE_COUNTS" value="9" variants="A6XX"/>
-	<value name="START_PRIMITIVE_CTRS" value="11" variants="A6XX"/>
-	<value name="STOP_PRIMITIVE_CTRS" value="12" variants="A6XX"/>
 	<value name="RST_PIX_CNT" value="13"/>
 	<value name="RST_VTX_CNT" value="14"/>
 	<value name="TILE_FLUSH" value="15"/>
@@ -65,39 +62,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 	<value name="DI_PT_LINESTRIP_ADJ" value="0xb"/>
 	<value name="DI_PT_TRI_ADJ" value="0xc"/>
 	<value name="DI_PT_TRISTRIP_ADJ" value="0xd"/>
-
-	<value name="DI_PT_PATCHES0" value="0x1f"/>
-	<value name="DI_PT_PATCHES1" value="0x20"/>
-	<value name="DI_PT_PATCHES2" value="0x21"/>
-	<value name="DI_PT_PATCHES3" value="0x22"/>
-	<value name="DI_PT_PATCHES4" value="0x23"/>
-	<value name="DI_PT_PATCHES5" value="0x24"/>
-	<value name="DI_PT_PATCHES6" value="0x25"/>
-	<value name="DI_PT_PATCHES7" value="0x26"/>
-	<value name="DI_PT_PATCHES8" value="0x27"/>
-	<value name="DI_PT_PATCHES9" value="0x28"/>
-	<value name="DI_PT_PATCHES10" value="0x29"/>
-	<value name="DI_PT_PATCHES11" value="0x2a"/>
-	<value name="DI_PT_PATCHES12" value="0x2b"/>
-	<value name="DI_PT_PATCHES13" value="0x2c"/>
-	<value name="DI_PT_PATCHES14" value="0x2d"/>
-	<value name="DI_PT_PATCHES15" value="0x2e"/>
-	<value name="DI_PT_PATCHES16" value="0x2f"/>
-	<value name="DI_PT_PATCHES17" value="0x30"/>
-	<value name="DI_PT_PATCHES18" value="0x31"/>
-	<value name="DI_PT_PATCHES19" value="0x32"/>
-	<value name="DI_PT_PATCHES20" value="0x33"/>
-	<value name="DI_PT_PATCHES21" value="0x34"/>
-	<value name="DI_PT_PATCHES22" value="0x35"/>
-	<value name="DI_PT_PATCHES23" value="0x36"/>
-	<value name="DI_PT_PATCHES24" value="0x37"/>
-	<value name="DI_PT_PATCHES25" value="0x38"/>
-	<value name="DI_PT_PATCHES26" value="0x39"/>
-	<value name="DI_PT_PATCHES27" value="0x3a"/>
-	<value name="DI_PT_PATCHES28" value="0x3b"/>
-	<value name="DI_PT_PATCHES29" value="0x3c"/>
-	<value name="DI_PT_PATCHES30" value="0x3d"/>
-	<value name="DI_PT_PATCHES31" value="0x3e"/>
+	<value name="DI_PT_PATCHES" value="0x29"/>
 </enum>
 
 <enum name="pc_di_src_sel">
@@ -157,12 +122,6 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 	<value name="CP_PREEMPT_ENABLE" value="0x1c"/>
 	<value name="CP_PREEMPT_TOKEN" value="0x1e"/>
 	<value name="CP_INDIRECT_BUFFER" value="0x3f"/>
-	<doc>
-		Takes the same arguments as CP_INDIRECT_BUFFER, but jumps to
-		another buffer at the same level. Must be at the end of IB, and
-		doesn't work with draw state IB's.
-	</doc>
-	<value name="CP_INDIRECT_BUFFER_CHAIN" value="0x57" variants="A5XX-"/>
 	<doc>indirect buffer dispatch.  same as IB, but init is pipelined</doc>
 	<value name="CP_INDIRECT_BUFFER_PFD" value="0x37"/>
 	<doc>wait for the IDLE state of the engine</doc>
@@ -225,7 +184,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 	<doc>load sequencer instruction memory (code embedded in packet)</doc>
 	<value name="CP_IM_LOAD_IMMEDIATE" value="0x2b"/>
 	<doc>load constants from a location in memory</doc>
-	<value name="CP_LOAD_CONSTANT_CONTEXT" value="0x2e" variants="A2XX"/>
+	<value name="CP_LOAD_CONSTANT_CONTEXT" value="0x2e"/>
 	<doc>selective invalidation of state pointers</doc>
 	<value name="CP_INVALIDATE_STATE" value="0x3b"/>
 	<doc>dynamically changes shader instruction memory partition</doc>
@@ -272,7 +231,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 	<doc>Load a buffer with pre-fetch enabled</doc>
 	<value name="CP_INDIRECT_BUFFER_PFE" value="0x3f" variants="A5XX"/>
 	<doc>Set bin (?)</doc>
-	<value name="CP_SET_BIN" value="0x4c" variants="A2XX"/>
+	<value name="CP_SET_BIN" value="0x4c"/>
 
 	<doc>test 2 memory locations to dword values specified</doc>
 	<value name="CP_TEST_TWO_MEMS" value="0x71"/>
@@ -316,7 +275,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 		for A4xx
 		Write to register with address that does not fit into type-0 pkt
 	</doc>
-	<value name="CP_WIDE_REG_WRITE" value="0x74" variants="A4XX"/>
+	<value name="CP_WIDE_REG_WRITE" value="0x74"/>
 
 	<doc>copy from ME scratch RAM to a register</doc>
 	<value name="CP_SCRATCH_TO_REG" value="0x4d"/>
@@ -419,16 +378,15 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 
 	<!-- jmptable entry used to handle type4 packet on a5xx+: -->
 	<value name="PKT4" value="0x04" variants="A5XX,A6XX"/>
+<!--
+unknown a6xx opcodes:
 
-	<!-- TODO do these exist on A5xx? -->
-	<value name="CP_SCRATCH_WRITE" value="0x4c" variants="A6XX"/>
-	<value name="CP_REG_TO_MEM_OFFSET_MEM" value="0x74" variants="A6XX"/>
-	<value name="CP_REG_TO_MEM_OFFSET_REG" value="0x72" variants="A6XX"/>
-	<value name="CP_WAIT_MEM_GTE" value="0x14" variants="A6XX"/>
-	<value name="CP_WAIT_TWO_REGS" value="0x70" variants="A6XX"/>
-	<value name="CP_MEMCPY" value="0x75" variants="A6XX"/>
-	<value name="CP_SET_BIN_DATA5_OFFSET" value="0x2e" variants="A6XX"/>
-	<value name="CP_SET_CTXSWITCH_IB" value="0x55" variants="A6XX"/>
+opcode: (null) (14) (5 dwords)
+opcode: (null) (55) (4 dwords)
+opcode: (null) (6d) (4 dwords)
+ -->
+	<value name="CP_UNK_A6XX_14" value="0x14" variants="A6XX"/>
+	<value name="CP_UNK_A6XX_55" value="0x55" variants="A6XX"/>
 
 	<!--
 	Seems to always have the payload:
@@ -652,7 +610,6 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
 	<bitfield name="VIS_CULL" low="8" high="9" type="pc_di_vis_cull_mode"/>
 	<bitfield name="INDEX_SIZE" low="10" high="11" type="a4xx_index_size"/>
 	<bitfield name="PATCH_TYPE" low="12" high="13" type="a6xx_patch_type"/>
-	<bitfield name="GS_ENABLE" pos="16" type="boolean"/>
 	<bitfield name="TESS_ENABLE" pos="17" type="boolean"/>
 </bitset>
 
@@ -693,23 +650,9 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
 	</reg32>
 	<reg32 offset="3" name="3">
 	</reg32>
-
-	<stripe variants="A5XX-">
-		<reg32 offset="4" name="4">
-			<bitfield name="INDX_BASE_LO" low="0" high="31"/>
-		</reg32>
-		<reg32 offset="5" name="5">
-			<bitfield name="INDX_BASE_HI" low="0" high="31"/>
-		</reg32>
-		<reg32 offset="6" name="6">
-			<bitfield name="INDX_SIZE" low="0" high="31"/>
-		</reg32>
-	</stripe>
-
 	<reg32 offset="4" name="4">
 		<bitfield name="INDX_BASE" low="0" high="31"/>
 	</reg32>
-
 	<reg32 offset="5" name="5">
 		<bitfield name="INDX_SIZE" low="0" high="31"/>
 	</reg32>
@@ -769,9 +712,13 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
 			<bitfield name="DISABLE" pos="17" type="boolean"/>
 			<bitfield name="DISABLE_ALL_GROUPS" pos="18" type="boolean"/>
 			<bitfield name="LOAD_IMMED" pos="19" type="boolean"/>
-			<bitfield name="BINNING" pos="20" variants="A6XX-" type="boolean"/>
-			<bitfield name="GMEM" pos="21" variants="A6XX-" type="boolean"/>
-			<bitfield name="SYSMEM" pos="22" variants="A6XX-" type="boolean"/>
+			<!--
+			I think this is a bitmask of states that this group applies to
+			(ie. binning/bypass/gmem)?  At least starting w/ a6xx blob
+			emits different VS state at the same time, with ENABLE_MASK=0x1
+			for binning pass VS state, and ENABLE_MASK=0x6 for full VS.
+			-->
+			<bitfield name="ENABLE_MASK" low="20" high="23" variants="A6XX-"/>
 			<bitfield name="GROUP_ID" low="24" high="28" type="uint"/>
 		</reg32>
 		<reg32 offset="1" name="1">
@@ -837,112 +784,14 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
 	</reg32>
 </domain>
 
-<domain name="CP_SET_BIN_DATA5_OFFSET" width="32">
-	<doc>
-                Like CP_SET_BIN_DATA5, but set the pointers as offsets from the
-                pointers stored in VSC_PIPE_{DATA,DATA2,SIZE}_ADDRESS. Useful
-                for Vulkan where these values aren't known when the command
-                stream is recorded.
-	</doc>
-	<reg32 offset="0" name="0">
-		<!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: -->
-		<bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
-		<!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: -->
-		<bitfield name="VSC_N" low="22" high="26" type="uint"/>
-	</reg32>
-	<!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS -->
-	<reg32 offset="1" name="1">
-		<bitfield name="BIN_DATA_OFFSET" low="0" high="31" type="uint"/>
-	</reg32>
-	<!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)-->
-	<reg32 offset="2" name="2">
-		<bitfield name="BIN_SIZE_OFFSET" low="0" high="31" type="uint"/>
-	</reg32>
-	<!-- BIN_DATA2_ADDR -> VSC_PIPE[p].DATA2_ADDRESS -->
-	<reg32 offset="3" name="3">
-		<bitfield name="BIN_DATA2_OFFSET" low="0" high="31" type="uint"/>
-	</reg32>
-</domain>
-
-<domain name="CP_REG_RMW" width="32">
-	<doc>
-                Modifies DST_REG using two sources that can either be registers
-                or immediates. If SRC1_ADD is set, then do the following:
-
-			$dst = (($dst &amp; $src0) rot $rotate) + $src1
-
-		Otherwise:
-
-			$dst = (($dst &amp; $src0) rot $rotate) | $src1
-
-		Here "rot" means rotate left.
-	</doc>
-	<reg32 offset="0" name="0">
-		<bitfield name="DST_REG" low="0" high="17" type="hex"/>
-		<bitfield name="ROTATE" low="24" high="28" type="uint"/>
-		<bitfield name="SRC1_ADD" pos="29" type="boolean"/>
-		<bitfield name="SRC1_IS_REG" pos="30" type="boolean"/>
-		<bitfield name="SRC0_IS_REG" pos="31" type="boolean"/>
-	</reg32>
-	<reg32 offset="1" name="1">
-		<bitfield name="SRC0" low="0" high="31" type="uint"/>
-	</reg32>
-	<reg32 offset="2" name="2">
-		<bitfield name="SRC1" low="0" high="31" type="uint"/>
-	</reg32>
-</domain>
-
 <domain name="CP_REG_TO_MEM" width="32">
 	<reg32 offset="0" name="0">
 		<bitfield name="REG" low="0" high="15" type="hex"/>
-		<!-- number of registers/dwords copied is max(CNT, 1). -->
-		<bitfield name="CNT" low="18" high="29" type="uint"/>
-		<bitfield name="64B" pos="30" type="boolean"/>
-		<bitfield name="ACCUMULATE" pos="31" type="boolean"/>
-	</reg32>
-	<reg32 offset="1" name="1">
-		<bitfield name="DEST" low="0" high="31"/>
-	</reg32>
-	<reg32 offset="2" name="2" variants="A5XX-">
-		<bitfield name="DEST_HI" low="0" high="31"/>
-	</reg32>
-</domain>
-
-<domain name="CP_REG_TO_MEM_OFFSET_REG" width="32">
-	<doc>
-                Like CP_REG_TO_MEM, but the memory address to write to can be
-                offsetted using either one or two registers or scratch
-                registers.
-	</doc>
-	<reg32 offset="0" name="0">
-		<bitfield name="REG" low="0" high="15" type="hex"/>
-		<!-- number of registers/dwords copied is max(CNT, 1). -->
-		<bitfield name="CNT" low="18" high="29" type="uint"/>
-		<bitfield name="64B" pos="30" type="boolean"/>
-		<bitfield name="ACCUMULATE" pos="31" type="boolean"/>
-	</reg32>
-	<reg32 offset="1" name="1">
-		<bitfield name="DEST" low="0" high="31"/>
-	</reg32>
-	<reg32 offset="2" name="2" variants="A5XX-">
-		<bitfield name="DEST_HI" low="0" high="31"/>
-	</reg32>
-	<reg32 offset="3" name="3">
-		<bitfield name="OFFSET0" low="0" high="17" type="hex"/>
-		<bitfield name="OFFSET0_SCRATCH" pos="19" type="boolean"/>
-	</reg32>
-	<!-- followed by an optional identical OFFSET1 dword -->
-</domain>
-
-<domain name="CP_REG_TO_MEM_OFFSET_MEM" width="32">
-	<doc>
-                Like CP_REG_TO_MEM, but the memory address to write to can be
-                offsetted using a DWORD in memory.
-	</doc>
-	<reg32 offset="0" name="0">
-		<bitfield name="REG" low="0" high="15" type="hex"/>
-		<!-- number of registers/dwords copied is max(CNT, 1). -->
-		<bitfield name="CNT" low="18" high="29" type="uint"/>
+		<!--
+		number of regsiters/dwords copied is CNT+1.. unsure
+		about # of bits
+		 -->
+		<bitfield name="CNT" low="19" high="29" type="uint"/>
 		<bitfield name="64B" pos="30" type="boolean"/>
 		<bitfield name="ACCUMULATE" pos="31" type="boolean"/>
 	</reg32>
@@ -952,23 +801,18 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
 	<reg32 offset="2" name="2" variants="A5XX-">
 		<bitfield name="DEST_HI" low="0" high="31"/>
 	</reg32>
-	<reg32 offset="3" name="3">
-		<bitfield name="OFFSET_LO" low="0" high="31" type="hex"/>
-	</reg32>
-	<reg32 offset="4" name="4">
-		<bitfield name="OFFSET_HI" low="0" high="31" type="hex"/>
-	</reg32>
 </domain>
 
 <domain name="CP_MEM_TO_REG" width="32">
 	<reg32 offset="0" name="0">
 		<bitfield name="REG" low="0" high="15" type="hex"/>
-		<!-- number of registers/dwords copied is max(CNT, 1). -->
+		<!--
+		number of regsiters/dwords copied is CNT+1.. unsure
+		about # of bits
+		 -->
 		<bitfield name="CNT" low="19" high="29" type="uint"/>
-		<!-- shift each DWORD left by 2 while copying -->
-		<bitfield name="SHIFT_BY_2" pos="30" type="boolean"/>
-		<!-- does the same thing as CP_MEM_TO_MEM::UNK31 -->
-		<bitfield name="UNK31" pos="31" type="boolean"/>
+		<bitfield name="64B" pos="30" type="boolean"/>
+		<bitfield name="ACCUMULATE" pos="31" type="boolean"/>
 	</reg32>
 	<reg32 offset="1" name="1">
 		<bitfield name="SRC" low="0" high="31"/>
@@ -990,10 +834,6 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
 
 		<!-- if set treat src/dst as 64bit values -->
 		<bitfield name="DOUBLE" pos="29" type="boolean"/>
-		<!-- execute CP_WAIT_FOR_MEM_WRITES beforehand -->
-		<bitfield name="WAIT_FOR_MEM_WRITES" pos="30" type="boolean"/>
-		<!-- some other kind of wait -->
-		<bitfield name="UNK31" pos="31" type="boolean"/>
 	</reg32>
 	<!--
 	followed by sequence of addresses.. the first is the
@@ -1005,61 +845,6 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
 	 -->
 </domain>
 
-<domain name="CP_MEMCPY" width="32">
-	<reg32 offset="0" name="0">
-		<bitfield name="DWORDS" low="0" high="31" type="uint"/>
-	</reg32>
-	<reg32 offset="1" name="1">
-		<bitfield name="SRC_LO" low="0" high="31" type="hex"/>
-	</reg32>
-	<reg32 offset="2" name="2">
-		<bitfield name="SRC_HI" low="0" high="31" type="hex"/>
-	</reg32>
-	<reg32 offset="3" name="3">
-		<bitfield name="DST_LO" low="0" high="31" type="hex"/>
-	</reg32>
-	<reg32 offset="4" name="4">
-		<bitfield name="DST_HI" low="0" high="31" type="hex"/>
-	</reg32>
-</domain>
-
-<domain name="CP_REG_TO_SCRATCH" width="32">
-	<reg32 offset="0" name="0">
-		<bitfield name="REG" low="0" high="17" type="hex"/>
-		<bitfield name="SCRATCH" low="20" high="22" type="uint"/>
-		<!-- number of registers/dwords copied is CNT + 1. -->
-		<bitfield name="CNT" low="24" high="26" type="uint"/>
-	</reg32>
-</domain>
-
-<domain name="CP_SCRATCH_TO_REG" width="32">
-	<reg32 offset="0" name="0">
-		<bitfield name="REG" low="0" high="17" type="hex"/>
-		<!-- note: CP_MEM_TO_REG always sets this when writing to the register -->
-		<bitfield name="UNK18" pos="18" type="boolean"/>
-		<bitfield name="SCRATCH" low="20" high="22" type="uint"/>
-		<!-- number of registers/dwords copied is CNT + 1. -->
-		<bitfield name="CNT" low="24" high="26" type="uint"/>
-	</reg32>
-</domain>
-
-<domain name="CP_SCRATCH_WRITE" width="32">
-	<reg32 offset="0" name="0">
-		<bitfield name="SCRATCH" low="20" high="22" type="uint"/>
-	</reg32>
-	<!-- followed by one or more DWORDs to write to scratch registers -->
-</domain>
-
-<domain name="CP_MEM_WRITE" width="32">
-	<reg32 offset="0" name="0">
-		<bitfield name="ADDR_LO" low="0" high="31"/>
-	</reg32>
-	<reg32 offset="1" name="1">
-		<bitfield name="ADDR_HI" low="0" high="31"/>
-	</reg32>
-	<!-- followed by the DWORDs to write -->
-</domain>
-
 <enum name="cp_cond_function">
 	<value value="0" name="WRITE_ALWAYS"/>
 	<value value="1" name="WRITE_LT"/>
@@ -1096,10 +881,7 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
 <domain name="CP_COND_WRITE5" width="32">
 	<reg32 offset="0" name="0">
 		<bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
-		<bitfield name="SIGNED_COMPARE" pos="3" type="boolean"/>
-                <!-- if both POLL_MEMORY and POLL_SCRATCH are false, it polls a register at POLL_ADDR_LO instead. -->
 		<bitfield name="POLL_MEMORY" pos="4" type="boolean"/>
-		<bitfield name="POLL_SCRATCH" pos="5" type="boolean"/>
 		<bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
 	</reg32>
 	<reg32 offset="1" name="1">
@@ -1125,71 +907,6 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
 	</reg32>
 </domain>
 
-<domain name="CP_WAIT_MEM_GTE" width="32">
-        <doc>
-                Wait until a memory value is greater than or equal to the
-                reference, using signed comparison.
-	</doc>
-	<reg32 offset="0" name="0">
-		<!-- Reserved for flags, presumably? Unused in FW -->
-		<bitfield name="RESERVED" low="0" high="31" type="hex"/>
-	</reg32>
-	<reg32 offset="1" name="1">
-		<bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
-	</reg32>
-	<reg32 offset="2" name="2">
-		<bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
-	</reg32>
-	<reg32 offset="3" name="3">
-		<bitfield name="REF" low="0" high="31"/>
-	</reg32>
-</domain>
-
-<domain name="CP_WAIT_REG_MEM" width="32">
-        <doc>
-                This uses the same internal comparison as CP_COND_WRITE,
-                but waits until the comparison is true instead. It busy-loops in
-                the CP for the given number of cycles before trying again.
-	</doc>
-	<reg32 offset="0" name="0">
-		<bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
-		<bitfield name="SIGNED_COMPARE" pos="3" type="boolean"/>
-		<bitfield name="POLL_MEMORY" pos="4" type="boolean"/>
-		<bitfield name="POLL_SCRATCH" pos="5" type="boolean"/>
-		<bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
-	</reg32>
-	<reg32 offset="1" name="1">
-		<bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
-	</reg32>
-	<reg32 offset="2" name="2">
-		<bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
-	</reg32>
-	<reg32 offset="3" name="3">
-		<bitfield name="REF" low="0" high="31"/>
-	</reg32>
-	<reg32 offset="4" name="4">
-		<bitfield name="MASK" low="0" high="31"/>
-	</reg32>
-	<reg32 offset="5" name="5">
-		<bitfield name="DELAY_LOOP_CYCLES" low="0" high="31"/>
-	</reg32>
-</domain>
-
-<domain name="CP_WAIT_TWO_REGS" width="32">
-	<doc>
-		Waits for REG0 to not be 0 or REG1 to not equal REF
-	</doc>
-	<reg32 offset="0" name="0">
-		<bitfield name="REG0" low="0" high="17" type="hex"/>
-	</reg32>
-	<reg32 offset="1" name="1">
-		<bitfield name="REG1" low="0" high="17" type="hex"/>
-	</reg32>
-	<reg32 offset="2" name="2">
-		<bitfield name="REF" low="0" high="31" type="uint"/>
-	</reg32>
-</domain>
-
 <domain name="CP_DISPATCH_COMPUTE" width="32">
 	<reg32 offset="0" name="0"/>
 	<reg32 offset="1" name="1">
@@ -1386,22 +1103,13 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
 		<value value="4" name="RM6_GMEM"/>
 		<value value="5" name="RM6_BLIT2D"/>
 		<value value="6" name="RM6_RESOLVE"/>
-		<value value="7" name="RM6_YIELD"/>
 		<value value="0xc" name="RM6_BLIT2DSCALE"/>
-
-		<!--
-			These values come from a6xx_set_marker() in the
-			downstream kernel, and they can only be set by the kernel
-		-->
-		<value value="0xd" name="RM6_IB1LIST_START"/>
-		<value value="0xe" name="RM6_IB1LIST_END"/>
-		<!-- IFPC - inter-frame power collapse -->
-		<value value="0x100" name="RM6_IFPC_ENABLE"/>
-		<value value="0x101" name="RM6_IFPC_DISABLE"/>
 	</enum>
 	<reg32 offset="0" name="0">
 		<bitfield name="MARKER" low="0" high="3"/>
-		<bitfield name="MODE" low="0" high="8" type="a6xx_render_mode"/>
+		<bitfield name="MODE" low="0" high="3" type="a6xx_render_mode"/>
+		<!-- IFPC - inter-frame power collapse -->
+		<bitfield name="IFPC" pos="8" type="boolean"/>
 	</reg32>
 </domain>
 
@@ -1447,122 +1155,19 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
 		<bitfield name="REG" low="0" high="11"/>
 		<!-- the bit to test -->
 		<bitfield name="BIT" low="20" high="24" type="uint"/>
-		<!-- execute CP_WAIT_FOR_ME beforehand -->
-		<bitfield name="WAIT_FOR_ME" pos="25" type="boolean"/>
+		<bitfield name="UNK25" pos="25" type="boolean"/>
 	</reg32>
 </domain>
 
 <!-- I *think* this existed at least as far back as a4xx -->
 <domain name="CP_COND_REG_EXEC" width="32">
-	<enum name="compare_mode">
-		<!-- use the predicate bit set by CP_REG_TEST -->
-		<value value="1" name="PRED_TEST"/>
-		<!-- compare two registers directly for equality -->
-		<value value="2" name="REG_COMPARE"/>
-		<!-- test if certain render modes are set via CP_SET_MARKER -->
-		<value value="3" name="RENDER_MODE" variants="A6XX-"/>
-	</enum>
 	<reg32 offset="0" name="0">
-		<bitfield name="REG0" low="0" high="17" type="hex"/>
-
-		<!--
-			Note: these bits have the same meaning, and use the same
-			internal mechanism as the bits in CP_SET_DRAW_STATE.
-			When RENDER_MODE is selected, they're used as
-			a bitmask of which modes pass the test.
-		-->
-
-		<!-- RM6_BINNING -->
-		<bitfield name="BINNING" pos="20" variants="A6XX-" type="boolean"/>
-		<!-- all others -->
-		<bitfield name="GMEM" pos="21" variants="A6XX-" type="boolean"/>
-		<!-- RM6_BYPASS -->
-		<bitfield name="SYSMEM" pos="22" variants="A6XX-" type="boolean"/>
-
-		<bitfield name="MODE" low="28" high="31" type="compare_mode"/>
+		<bitfield name="UNK28" pos="28" type="boolean"/>
 	</reg32>
-
-	<!-- in REG_COMPARE mode, there's an extra DWORD here with REG1 -->
-
 	<reg32 offset="1" name="1">
 		<bitfield name="DWORDS" low="0" high="31" type="uint"/>
 	</reg32>
 </domain>
 
-<domain name="CP_COND_EXEC" width="32">
-	<doc>
-                Executes the following DWORDs of commands if the dword at ADDR0
-                is not equal to 0 and the dword at ADDR1 is less than REF
-                (signed comparison).
-	</doc>
-	<reg32 offset="0" name="0">
-		<bitfield name="ADDR0_LO" low="0" high="31"/>
-	</reg32>
-	<reg32 offset="1" name="1">
-		<bitfield name="ADDR0_HI" low="0" high="31"/>
-	</reg32>
-	<reg32 offset="2" name="2">
-		<bitfield name="ADDR1_LO" low="0" high="31"/>
-	</reg32>
-	<reg32 offset="3" name="3">
-		<bitfield name="ADDR1_HI" low="0" high="31"/>
-	</reg32>
-	<reg32 offset="4" name="4">
-		<bitfield name="REF" low="0" high="31"/>
-	</reg32>
-	<reg32 offset="1" name="1">
-		<bitfield name="DWORDS" low="0" high="31" type="uint"/>
-	</reg32>
-</domain>
-
-<domain name="CP_SET_CTXSWITCH_IB" width="32">
-	<doc>
-                Used by the userspace driver to set various IB's which are
-                executed during context save/restore for handling
-                state that isn't restored by the
-                context switch routine itself.
-	</doc>
-	<enum name="ctxswitch_ib">
-		<value name="RESTORE_IB" value="0">
-			<doc>Executed unconditionally when switching back to the context.</doc>
-		</value>
-		<value name="YIELD_RESTORE_IB" value="1">
-                        <doc>
-				Executed when switching back after switching
-				away during execution of
-				a CP_SET_MARKER packet with RM6_YIELD as the
-				payload *and* the normal save routine was
-				bypassed for a shorter one. I think this is
-				connected to the "skipsaverestore" bit set by
-				the kernel when preempting.
-			</doc>
-		</value>
-		<value name="SAVE_IB" value="2">
-                        <doc>
-				Executed when switching away from the context,
-				except for context switches initiated via
-				CP_YIELD.
-                        </doc>
-		</value>
-		<value name="RB_SAVE_IB" value="3">
-			<doc>
-				This can only be set by the RB (i.e. the kernel)
-				and executes with protected mode off, but
-				is otherwise similar to SAVE_IB.
-			</doc>
-		</value>
-	</enum>
-	<reg32 offset="0" name="0">
-		<bitfield name="ADDR_LO" low="0" high="31"/>
-	</reg32>
-	<reg32 offset="1" name="1">
-		<bitfield name="ADDR_HI" low="0" high="31"/>
-	</reg32>
-	<reg32 offset="2" name="2">
-		<bitfield name="DWORDS" low="0" high="19" type="uint"/>
-		<bitfield name="TYPE" low="20" high="21" type="ctxswitch_ib"/>
-	</reg32>
-</domain>
-
 </database>
 
diff --git a/lib/mesa/src/freedreno/vulkan/tu_fence.c b/lib/mesa/src/freedreno/vulkan/tu_fence.c
index 9e4a92370..793f0ab3c 100644
--- a/lib/mesa/src/freedreno/vulkan/tu_fence.c
+++ b/lib/mesa/src/freedreno/vulkan/tu_fence.c
@@ -86,7 +86,6 @@ tu_fence_init(struct tu_fence *fence, bool signaled)
 {
    fence->signaled = signaled;
    fence->fd = -1;
-   fence->fence_wsi = NULL;
 }
 
 void
@@ -94,8 +93,6 @@ tu_fence_finish(struct tu_fence *fence)
 {
    if (fence->fd >= 0)
       close(fence->fd);
-   if (fence->fence_wsi)
-      fence->fence_wsi->destroy(fence->fence_wsi);
 }
 
 /**
@@ -211,10 +208,6 @@ tu_fence_init_poll_fds(uint32_t fence_count,
    for (uint32_t i = 0; i < fence_count; i++) {
       TU_FROM_HANDLE(tu_fence, fence, fences[i]);
 
-      /* skip wsi fences */
-      if (fence->fence_wsi)
-            continue;
-
       if (fence->signaled) {
          if (wait_all) {
             /* skip signaled fences */
@@ -296,10 +289,6 @@ tu_fence_update_fences_and_poll_fds(uint32_t fence_count,
    for (uint32_t i = 0; i < fence_count; i++) {
       TU_FROM_HANDLE(tu_fence, fence, fences[i]);
 
-      /* skip wsi fences */
-      if (fence->fence_wsi)
-            continue;
-
       /* no signaled fence in fds */
       if (fence->signaled)
          continue;
@@ -360,18 +349,6 @@ tu_WaitForFences(VkDevice _device,
    if (fds != stack_fds)
       vk_free(&device->alloc, fds);
 
-   if (result != VK_SUCCESS)
-      return result;
-
-   for (uint32_t i = 0; i < fenceCount; ++i) {
-      TU_FROM_HANDLE(tu_fence, fence, pFences[i]);
-      if (fence->fence_wsi) {
-         VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
-         if (result != VK_SUCCESS)
-            return result;
-      }
-   }
-
    return result;
 }
 
@@ -399,15 +376,6 @@ tu_GetFenceStatus(VkDevice _device, VkFence _fence)
       else if (err && errno != ETIME)
          return VK_ERROR_OUT_OF_HOST_MEMORY;
    }
-   if (fence->fence_wsi) {
-      VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
-
-      if (result != VK_SUCCESS) {
-         if (result == VK_TIMEOUT)
-            return VK_NOT_READY;
-         return result;
-      }
-   }
 
    return fence->signaled ? VK_SUCCESS : VK_NOT_READY;
 }