Import Mesa 23.3.6

1 files changed, 155 insertions, 98 deletions

diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c
index f94d28bb9..9c821625f 100644
--- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c
+++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c
@@ -34,13 +34,13 @@
 #include "etnaviv_nir.h"
 #include "etnaviv_uniforms.h"
 #include "etnaviv_util.h"
+#include "nir.h"
 
 #include <math.h>
 #include "util/u_memory.h"
 #include "util/register_allocate.h"
 #include "compiler/nir/nir_builder.h"
 
-#include "tgsi/tgsi_strings.h"
 #include "util/compiler.h"
 #include "util/half_float.h"
 
@@ -222,6 +222,7 @@ src_swizzle(hw_src src, unsigned swizzle)
 #define CONST(x) CONST_VAL(ETNA_UNIFORM_CONSTANT, x)
 #define UNIFORM(x) CONST_VAL(ETNA_UNIFORM_UNIFORM, x)
 #define TEXSCALE(x, i) CONST_VAL(ETNA_UNIFORM_TEXRECT_SCALE_X + (i), x)
+#define TEXSIZE(x, i) CONST_VAL(ETNA_UNIFORM_TEXTURE_WIDTH + (i), x)
 
 static int
 const_add(uint64_t *c, uint64_t value)
@@ -345,9 +346,6 @@ ra_src(struct etna_compile *c, nir_src *src)
 static hw_src
 get_src(struct etna_compile *c, nir_src *src)
 {
-   if (!src->is_ssa)
-      return ra_src(c, src);
-
    nir_instr *instr = src->ssa->parent_instr;
 
    if (instr->pass_flags & BYPASS_SRC) {
@@ -367,12 +365,13 @@ get_src(struct etna_compile *c, nir_src *src)
       case nir_intrinsic_load_instance_id:
       case nir_intrinsic_load_uniform:
       case nir_intrinsic_load_ubo:
+      case nir_intrinsic_load_reg:
          return ra_src(c, src);
       case nir_intrinsic_load_front_face:
          return (hw_src) { .use = 1, .rgroup = INST_RGROUP_INTERNAL };
       case nir_intrinsic_load_frag_coord:
          return SRC_REG(0, INST_SWIZ_IDENTITY);
-      case nir_intrinsic_load_texture_rect_scaling: {
+      case nir_intrinsic_load_texture_scale: {
          int sampler = nir_src_as_int(intr->src[0]);
          nir_const_value values[] = {
             TEXSCALE(sampler, 0),
@@ -381,6 +380,16 @@ get_src(struct etna_compile *c, nir_src *src)
 
          return src_swizzle(const_src(c, values, 2), SWIZZLE(X,Y,X,X));
       }
+      case nir_intrinsic_load_texture_size_etna: {
+         int sampler = nir_src_as_int(intr->src[0]);
+         nir_const_value values[] = {
+            TEXSIZE(sampler, 0),
+            TEXSIZE(sampler, 1),
+            TEXSIZE(sampler, 2),
+         };
+
+         return src_swizzle(const_src(c, values, 3), SWIZZLE(X,Y,Z,X));
+      }
       default:
          compile_error(c, "Unhandled NIR intrinsic type: %s\n",
                        nir_intrinsic_infos[intr->intrinsic].name);
@@ -390,7 +399,7 @@ get_src(struct etna_compile *c, nir_src *src)
    case nir_instr_type_alu:
    case nir_instr_type_tex:
       return ra_src(c, src);
-   case nir_instr_type_ssa_undef: {
+   case nir_instr_type_undef: {
       /* return zero to deal with broken Blur demo */
       nir_const_value value = CONST(0);
       return src_swizzle(const_src(c, &value, 1), SWIZZLE(X,X,X,X));
@@ -404,10 +413,10 @@ get_src(struct etna_compile *c, nir_src *src)
 }
 
 static bool
-vec_dest_has_swizzle(nir_alu_instr *vec, nir_ssa_def *ssa)
+vec_dest_has_swizzle(nir_alu_instr *vec, nir_def *ssa)
 {
-   for (unsigned i = 0; i < 4; i++) {
-      if (!(vec->dest.write_mask & (1 << i)) || vec->src[i].src.ssa != ssa)
+   for (unsigned i = 0; i < vec->def.num_components; i++) {
+      if (vec->src[i].src.ssa != ssa)
          continue;
 
       if (vec->src[i].swizzle[0] != i)
@@ -416,7 +425,7 @@ vec_dest_has_swizzle(nir_alu_instr *vec, nir_ssa_def *ssa)
 
    /* don't deal with possible bypassed vec/mov chain */
    nir_foreach_use(use_src, ssa) {
-      nir_instr *instr = use_src->parent_instr;
+      nir_instr *instr = nir_src_parent_instr(use_src);
       if (instr->type != nir_instr_type_alu)
          continue;
 
@@ -435,16 +444,16 @@ vec_dest_has_swizzle(nir_alu_instr *vec, nir_ssa_def *ssa)
    return false;
 }
 
-/* get allocated dest register for nir_dest
+/* get allocated dest register for nir_def
  * *p_swiz tells how the components need to be placed into register
  */
 static hw_dst
-ra_dest(struct etna_compile *c, nir_dest *dest, unsigned *p_swiz)
+ra_def(struct etna_compile *c, nir_def *def, unsigned *p_swiz)
 {
    unsigned swiz = INST_SWIZ_IDENTITY, mask = 0xf;
-   dest = real_dest(dest, &swiz, &mask);
+   def = real_def(def, &swiz, &mask);
 
-   unsigned r = ra_get_node_reg(c->g, c->live_map[dest_index(c->impl, dest)]);
+   unsigned r = ra_get_node_reg(c->g, c->live_map[def_index(c->impl, def)]);
    unsigned t = reg_get_type(r);
 
    *p_swiz = inst_swiz_compose(swiz, reg_dst_swiz[t]);
@@ -462,17 +471,13 @@ emit_alu(struct etna_compile *c, nir_alu_instr * alu)
    const nir_op_info *info = &nir_op_infos[alu->op];
 
    /* marked as dead instruction (vecN and other bypassed instr) */
-   if (alu->instr.pass_flags)
+   if (is_dead_instruction(&alu->instr))
       return;
 
    assert(!(alu->op >= nir_op_vec2 && alu->op <= nir_op_vec4));
 
    unsigned dst_swiz;
-   hw_dst dst = ra_dest(c, &alu->dest.dest, &dst_swiz);
-
-   /* compose alu write_mask with RA write mask */
-   if (!alu->dest.dest.is_ssa)
-      dst.write_mask = inst_write_mask_compose(alu->dest.write_mask, dst.write_mask);
+   hw_dst dst = ra_def(c, &alu->def, &dst_swiz);
 
    switch (alu->op) {
    case nir_op_fdot2:
@@ -495,30 +500,30 @@ emit_alu(struct etna_compile *c, nir_alu_instr * alu)
       src = src_swizzle(src, dst_swiz);
 
       if (src.rgroup != INST_RGROUP_IMMEDIATE) {
-         src.neg = asrc->negate || (alu->op == nir_op_fneg);
-         src.abs = asrc->abs || (alu->op == nir_op_fabs);
+         src.neg = is_src_mod_neg(&alu->instr, i) || (alu->op == nir_op_fneg);
+         src.abs = is_src_mod_abs(&alu->instr, i) || (alu->op == nir_op_fabs);
       } else {
-         assert(alu->op != nir_op_fneg);
-         assert(!asrc->abs && alu->op != nir_op_fabs);
+         assert(alu->op != nir_op_fabs);
+         assert(!is_src_mod_abs(&alu->instr, i) && alu->op != nir_op_fabs);
 
          if (src.imm_type > 0)
-            assert(!asrc->negate);
+            assert(!is_src_mod_neg(&alu->instr, i));
 
-         if (asrc->negate && src.imm_type == 0)
+         if (is_src_mod_neg(&alu->instr, i) && src.imm_type == 0)
             src.imm_val ^= 0x80000;
       }
 
       srcs[i] = src;
    }
 
-   etna_emit_alu(c, alu->op, dst, srcs, alu->dest.saturate || (alu->op == nir_op_fsat));
+   etna_emit_alu(c, alu->op, dst, srcs, alu->op == nir_op_fsat);
 }
 
 static void
 emit_tex(struct etna_compile *c, nir_tex_instr * tex)
 {
    unsigned dst_swiz;
-   hw_dst dst = ra_dest(c, &tex->dest, &dst_swiz);
+   hw_dst dst = ra_def(c, &tex->def, &dst_swiz);
    nir_src *coord = NULL, *src1 = NULL, *src2 = NULL;
 
    for (unsigned i = 0; i < tex->num_srcs; i++) {
@@ -563,7 +568,7 @@ emit_intrinsic(struct etna_compile *c, nir_intrinsic_instr * intr)
       break;
    case nir_intrinsic_load_uniform: {
       unsigned dst_swiz;
-      struct etna_inst_dst dst = ra_dest(c, &intr->dest, &dst_swiz);
+      struct etna_inst_dst dst = ra_def(c, &intr->def, &dst_swiz);
 
       /* TODO: rework so extra MOV isn't required, load up to 4 addresses at once */
       emit_inst(c, &(struct etna_inst) {
@@ -590,18 +595,21 @@ emit_intrinsic(struct etna_compile *c, nir_intrinsic_instr * intr)
       emit_inst(c, &(struct etna_inst) {
          .opcode = INST_OPCODE_LOAD,
          .type = INST_TYPE_U32,
-         .dst = ra_dest(c, &intr->dest, &dst_swiz),
+         .dst = ra_def(c, &intr->def, &dst_swiz),
          .src[0] = get_src(c, &intr->src[1]),
          .src[1] = const_src(c, &CONST_VAL(ETNA_UNIFORM_UBO0_ADDR + idx, 0), 1),
       });
    } break;
    case nir_intrinsic_load_front_face:
    case nir_intrinsic_load_frag_coord:
-      assert(intr->dest.is_ssa); /* TODO - lower phis could cause this */
       break;
    case nir_intrinsic_load_input:
    case nir_intrinsic_load_instance_id:
-   case nir_intrinsic_load_texture_rect_scaling:
+   case nir_intrinsic_load_texture_scale:
+   case nir_intrinsic_load_texture_size_etna:
+   case nir_intrinsic_decl_reg:
+   case nir_intrinsic_load_reg:
+   case nir_intrinsic_store_reg:
       break;
    default:
       compile_error(c, "Unhandled NIR intrinsic type: %s\n",
@@ -626,7 +634,7 @@ emit_instr(struct etna_compile *c, nir_instr * instr)
       assert(nir_instr_is_last(instr));
       break;
    case nir_instr_type_load_const:
-   case nir_instr_type_ssa_undef:
+   case nir_instr_type_undef:
    case nir_instr_type_deref:
       break;
    default:
@@ -698,36 +706,36 @@ insert_vec_mov(nir_alu_instr *vec, unsigned start_idx, nir_shader *shader)
    unsigned write_mask = (1u << start_idx);
 
    nir_alu_instr *mov = nir_alu_instr_create(shader, nir_op_mov);
-   nir_alu_src_copy(&mov->src[0], &vec->src[start_idx], mov);
+   nir_alu_src_copy(&mov->src[0], &vec->src[start_idx]);
 
    mov->src[0].swizzle[0] = vec->src[start_idx].swizzle[0];
-   mov->src[0].negate = vec->src[start_idx].negate;
-   mov->src[0].abs = vec->src[start_idx].abs;
 
-   unsigned num_components = 1;
+   if (is_src_mod_neg(&vec->instr, start_idx))
+      set_src_mod_neg(&mov->instr, 0);
 
-   for (unsigned i = start_idx + 1; i < 4; i++) {
-      if (!(vec->dest.write_mask & (1 << i)))
-         continue;
+   if (is_src_mod_abs(&vec->instr, start_idx))
+      set_src_mod_abs(&mov->instr, 0);
 
+   unsigned num_components = 1;
+
+   for (unsigned i = start_idx + 1; i < vec->def.num_components; i++) {
       if (nir_srcs_equal(vec->src[i].src, vec->src[start_idx].src) &&
-          vec->src[i].negate == vec->src[start_idx].negate &&
-          vec->src[i].abs == vec->src[start_idx].abs) {
+         is_src_mod_neg(&vec->instr, i) == is_src_mod_neg(&vec->instr, start_idx) &&
+         is_src_mod_abs(&vec->instr, i) == is_src_mod_neg(&vec->instr, start_idx)) {
          write_mask |= (1 << i);
          mov->src[0].swizzle[num_components] = vec->src[i].swizzle[0];
          num_components++;
       }
    }
 
-   mov->dest.write_mask = (1 << num_components) - 1;
-   nir_ssa_dest_init(&mov->instr, &mov->dest.dest, num_components, 32, NULL);
+   nir_def_init(&mov->instr, &mov->def, num_components, 32);
 
    /* replace vec srcs with inserted mov */
    for (unsigned i = 0, j = 0; i < 4; i++) {
       if (!(write_mask & (1 << i)))
          continue;
 
-      nir_instr_rewrite_src(&vec->instr, &vec->src[i].src, nir_src_for_ssa(&mov->dest.dest.ssa));
+      nir_src_rewrite(&vec->src[i].src, &mov->def);
       vec->src[i].swizzle[0] = j++;
    }
 
@@ -737,6 +745,37 @@ insert_vec_mov(nir_alu_instr *vec, unsigned start_idx, nir_shader *shader)
 }
 
 /*
+ * Get the nir_const_value from an alu src.  Also look at
+ * the parent instruction as it could be a fabs/fneg.
+ */
+static nir_const_value *get_alu_cv(nir_alu_src *src)
+ {
+   nir_const_value *cv = nir_src_as_const_value(src->src);
+
+   if (!cv &&
+       (src->src.ssa->parent_instr->type == nir_instr_type_alu)) {
+      nir_alu_instr *parent = nir_instr_as_alu(src->src.ssa->parent_instr);
+
+      if ((parent->op == nir_op_fabs) ||
+          (parent->op == nir_op_fneg)) {
+         cv = nir_src_as_const_value(parent->src[0].src);
+
+         if (cv) {
+            /* Validate that we are only using ETNA_UNIFORM_CONSTANT const_values. */
+            for (unsigned i = 0; i < parent->def.num_components; i++) {
+               if (cv[i].u64 >> 32 != ETNA_UNIFORM_CONSTANT) {
+                  cv = NULL;
+                  break;
+               }
+            }
+         }
+      }
+   }
+
+   return cv;
+ }
+
+/*
  * for vecN instructions:
  * -merge constant sources into a single src
  * -insert movs (nir_lower_vec_to_movs equivalent)
@@ -749,9 +788,7 @@ lower_alu(struct etna_compile *c, nir_alu_instr *alu)
 {
    const nir_op_info *info = &nir_op_infos[alu->op];
 
-   nir_builder b;
-   nir_builder_init(&b, c->impl);
-   b.cursor = nir_before_instr(&alu->instr);
+   nir_builder b = nir_builder_at(nir_before_instr(&alu->instr));
 
    switch (alu->op) {
    case nir_op_vec2:
@@ -764,36 +801,42 @@ lower_alu(struct etna_compile *c, nir_alu_instr *alu)
 
       nir_const_value value[4] = {};
       uint8_t swizzle[4][4] = {};
-      unsigned swiz_max = 0, num_const = 0;
+      unsigned swiz_max = 0, num_different_const_srcs = 0;
+      int first_const = -1;
 
       for (unsigned i = 0; i < info->num_inputs; i++) {
-         nir_const_value *cv = nir_src_as_const_value(alu->src[i].src);
+         nir_const_value *cv = get_alu_cv(&alu->src[i]);
          if (!cv)
             continue;
 
-         unsigned num_components = info->input_sizes[i] ?: alu->dest.dest.ssa.num_components;
+         unsigned num_components = info->input_sizes[i] ?: alu->def.num_components;
          for (unsigned j = 0; j < num_components; j++) {
             int idx = const_add(&value[0].u64, cv[alu->src[i].swizzle[j]].u64);
             swizzle[i][j] = idx;
             swiz_max = MAX2(swiz_max, (unsigned) idx);
          }
-         num_const++;
+
+         if (first_const == -1)
+            first_const = i;
+
+         if (!nir_srcs_equal(alu->src[first_const].src, alu->src[i].src))
+            num_different_const_srcs++;
       }
 
       /* nothing to do */
-      if (num_const <= 1)
+      if (num_different_const_srcs == 0)
          return;
 
       /* resolve with single combined const src */
       if (swiz_max < 4) {
-         nir_ssa_def *def = nir_build_imm(&b, swiz_max + 1, 32, value);
+         nir_def *def = nir_build_imm(&b, swiz_max + 1, 32, value);
 
          for (unsigned i = 0; i < info->num_inputs; i++) {
-            nir_const_value *cv = nir_src_as_const_value(alu->src[i].src);
+            nir_const_value *cv = get_alu_cv(&alu->src[i]);
             if (!cv)
                continue;
 
-            nir_instr_rewrite_src(&alu->instr, &alu->src[i].src, nir_src_for_ssa(def));
+            nir_src_rewrite(&alu->src[i].src, def);
 
             for (unsigned j = 0; j < 4; j++)
                alu->src[i].swizzle[j] = swizzle[i][j];
@@ -802,9 +845,9 @@ lower_alu(struct etna_compile *c, nir_alu_instr *alu)
       }
 
       /* resolve with movs */
-      num_const = 0;
+      unsigned num_const = 0;
       for (unsigned i = 0; i < info->num_inputs; i++) {
-         nir_const_value *cv = nir_src_as_const_value(alu->src[i].src);
+         nir_const_value *cv = get_alu_cv(&alu->src[i]);
          if (!cv)
             continue;
 
@@ -812,8 +855,8 @@ lower_alu(struct etna_compile *c, nir_alu_instr *alu)
          if (num_const == 1)
             continue;
 
-         nir_ssa_def *mov = nir_mov(&b, alu->src[i].src.ssa);
-         nir_instr_rewrite_src(&alu->instr, &alu->src[i].src, nir_src_for_ssa(mov));
+         nir_def *mov = nir_mov(&b, alu->src[i].src.ssa);
+         nir_src_rewrite(&alu->src[i].src, mov);
       }
       return;
    }
@@ -822,7 +865,7 @@ lower_alu(struct etna_compile *c, nir_alu_instr *alu)
    unsigned num_components = 0;
 
    for (unsigned i = 0; i < info->num_inputs; i++) {
-      nir_const_value *cv = nir_src_as_const_value(alu->src[i].src);
+      nir_const_value *cv = get_alu_cv(&alu->src[i]);
       if (cv)
          value[num_components++] = cv[alu->src[i].swizzle[0]];
    }
@@ -832,35 +875,32 @@ lower_alu(struct etna_compile *c, nir_alu_instr *alu)
     * are constant)
     */
    if (num_components > 1) {
-      nir_ssa_def *def = nir_build_imm(&b, num_components, 32, value);
+      nir_def *def = nir_build_imm(&b, num_components, 32, value);
 
       if (num_components == info->num_inputs) {
-         nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, def);
+         nir_def_rewrite_uses(&alu->def, def);
          nir_instr_remove(&alu->instr);
          return;
       }
 
       for (unsigned i = 0, j = 0; i < info->num_inputs; i++) {
-         nir_const_value *cv = nir_src_as_const_value(alu->src[i].src);
+         nir_const_value *cv = get_alu_cv(&alu->src[i]);
          if (!cv)
             continue;
 
-         nir_instr_rewrite_src(&alu->instr, &alu->src[i].src, nir_src_for_ssa(def));
+         nir_src_rewrite(&alu->src[i].src, def);
          alu->src[i].swizzle[0] = j++;
       }
    }
 
    unsigned finished_write_mask = 0;
-   for (unsigned i = 0; i < 4; i++) {
-      if (!(alu->dest.write_mask & (1 << i)))
-            continue;
-
-      nir_ssa_def *ssa = alu->src[i].src.ssa;
+   for (unsigned i = 0; i < alu->def.num_components; i++) {
+      nir_def *ssa = alu->src[i].src.ssa;
 
       /* check that vecN instruction is only user of this */
       bool need_mov = false;
       nir_foreach_use_including_if(use_src, ssa) {
-         if (use_src->is_if || use_src->parent_instr != &alu->instr)
+         if (nir_src_is_if(use_src) || nir_src_parent_instr(use_src) != &alu->instr)
             need_mov = true;
       }
 
@@ -871,7 +911,7 @@ lower_alu(struct etna_compile *c, nir_alu_instr *alu)
          break;
       case nir_instr_type_intrinsic:
          if (nir_instr_as_intrinsic(instr)->intrinsic == nir_intrinsic_load_input) {
-            need_mov = vec_dest_has_swizzle(alu, &nir_instr_as_intrinsic(instr)->dest.ssa);
+            need_mov = vec_dest_has_swizzle(alu, &nir_instr_as_intrinsic(instr)->def);
             break;
          }
          FALLTHROUGH;
@@ -893,8 +933,7 @@ emit_shader(struct etna_compile *c, unsigned *num_temps, unsigned *num_consts)
    bool have_indirect_uniform = false;
    unsigned indirect_max = 0;
 
-   nir_builder b;
-   nir_builder_init(&b, c->impl);
+   nir_builder b = nir_builder_create(c->impl);
 
    /* convert non-dynamic uniform loads to constants, etc */
    nir_foreach_block(block, c->impl) {
@@ -932,13 +971,13 @@ emit_shader(struct etna_compile *c, unsigned *num_temps, unsigned *num_consts)
                base += off[0].u32;
             nir_const_value value[4];
 
-            for (unsigned i = 0; i < intr->dest.ssa.num_components; i++)
+            for (unsigned i = 0; i < intr->def.num_components; i++)
                value[i] = UNIFORM(base * 4 + i);
 
             b.cursor = nir_after_instr(instr);
-            nir_ssa_def *def = nir_build_imm(&b, intr->dest.ssa.num_components, 32, value);
+            nir_def *def = nir_build_imm(&b, intr->def.num_components, 32, value);
 
-            nir_ssa_def_rewrite_uses(&intr->dest.ssa, def);
+            nir_def_rewrite_uses(&intr->def, def);
             nir_instr_remove(instr);
          } break;
          default:
@@ -969,10 +1008,9 @@ emit_shader(struct etna_compile *c, unsigned *num_temps, unsigned *num_consts)
             if (nir_src_is_const(*src) || is_sysval(src->ssa->parent_instr) ||
                 (shader->info.stage == MESA_SHADER_FRAGMENT &&
                  deref->var->data.location == FRAG_RESULT_DEPTH &&
-                 src->is_ssa &&
                  src->ssa->parent_instr->type != nir_instr_type_alu)) {
                b.cursor = nir_before_instr(instr);
-               nir_instr_rewrite_src(instr, src, nir_src_for_ssa(nir_mov(&b, src->ssa)));
+               nir_src_rewrite(src, nir_mov(&b, src->ssa));
             }
          } break;
          default:
@@ -983,7 +1021,7 @@ emit_shader(struct etna_compile *c, unsigned *num_temps, unsigned *num_consts)
 
    /* call directly to avoid validation (load_const don't pass validation at this point) */
    nir_convert_from_ssa(shader, true);
-   nir_opt_dce(shader);
+   nir_trivialize_registers(shader);
 
    etna_ra_assign(c, shader);
 
@@ -1098,6 +1136,11 @@ etna_compile_shader(struct etna_shader_variant *v)
                  false, v->key.sprite_coord_yinvert);
    }
 
+   /*
+    * Remove any dead in variables before we iterate over them
+    */
+   NIR_PASS_V(s, nir_remove_dead_variables, nir_var_shader_in, NULL);
+
    /* setup input linking */
    struct etna_shader_io_file *sf = &v->infile;
    if (s->info.stage == MESA_SHADER_VERTEX) {
@@ -1124,15 +1167,9 @@ etna_compile_shader(struct etna_shader_variant *v)
    NIR_PASS_V(s, nir_lower_io, nir_var_shader_in | nir_var_uniform, etna_glsl_type_size,
             (nir_lower_io_options)0);
 
-   NIR_PASS_V(s, nir_lower_regs_to_ssa);
    NIR_PASS_V(s, nir_lower_vars_to_ssa);
    NIR_PASS_V(s, nir_lower_indirect_derefs, nir_var_all, UINT32_MAX);
-   NIR_PASS_V(s, nir_lower_tex, &(struct nir_lower_tex_options) { .lower_txp = ~0u, .lower_invalid_implicit_lod = true, });
-
-   if (v->key.has_sample_tex_compare)
-      NIR_PASS_V(s, nir_lower_tex_shadow, v->key.num_texture_states,
-                                          v->key.tex_compare_func,
-                                          v->key.tex_swizzle);
+   NIR_PASS_V(s, etna_nir_lower_texture, &v->key);
 
    NIR_PASS_V(s, nir_lower_alu_to_scalar, etna_alu_to_scalar_filter_cb, specs);
    if (c->specs->halti >= 2) {
@@ -1174,19 +1211,21 @@ etna_compile_shader(struct etna_shader_variant *v)
    NIR_PASS_V(s, nir_remove_dead_variables, nir_var_function_temp, NULL);
    NIR_PASS_V(s, nir_opt_algebraic_late);
 
-   NIR_PASS_V(s, nir_move_vec_src_uses_to_dest);
+   NIR_PASS_V(s, nir_move_vec_src_uses_to_dest, false);
    NIR_PASS_V(s, nir_copy_prop);
-   /* only HW supported integer source mod is ineg for iadd instruction (?) */
-   NIR_PASS_V(s, nir_lower_to_source_mods, ~nir_lower_int_source_mods);
    /* need copy prop after uses_to_dest, and before src mods: see
     * dEQP-GLES2.functional.shaders.random.all_features.fragment.95
     */
 
    NIR_PASS_V(s, nir_opt_dce);
+   NIR_PASS_V(s, nir_opt_cse);
 
    NIR_PASS_V(s, nir_lower_bool_to_bitsize);
    NIR_PASS_V(s, etna_lower_alu, c->specs->has_new_transcendentals);
 
+   /* needs to be the last pass that touches pass_flags! */
+   NIR_PASS_V(s, etna_nir_lower_to_source_mods);
+
    if (DBG_ENABLED(ETNA_DBG_DUMP_SHADERS))
       nir_print_shader(s, stdout);
 
@@ -1239,10 +1278,30 @@ etna_shader_vs_lookup(const struct etna_shader_variant *sobj,
       if (sobj->outfile.reg[i].slot == in->slot)
          return &sobj->outfile.reg[i];
 
+   /*
+    * There are valid NIR shaders pairs where the vertex shader has
+    * a VARYING_SLOT_BFC0 shader_out and the corresponding framgent
+    * shader has a VARYING_SLOT_COL0 shader_in.
+    * So at link time if there is no matching VARYING_SLOT_BFC[n],
+    * we must map VARYING_SLOT_BFC0[n] to VARYING_SLOT_COL[n].
+    */
+   gl_varying_slot slot;
+
+   if (in->slot == VARYING_SLOT_COL0)
+      slot = VARYING_SLOT_BFC0;
+   else if (in->slot == VARYING_SLOT_COL1)
+      slot = VARYING_SLOT_BFC1;
+   else
+      return NULL;
+
+   for (int i = 0; i < sobj->outfile.num_reg; i++)
+      if (sobj->outfile.reg[i].slot == slot)
+         return &sobj->outfile.reg[i];
+
    return NULL;
 }
 
-bool
+void
 etna_link_shader(struct etna_shader_link_info *info,
                  const struct etna_shader_variant *vs,
                  const struct etna_shader_variant *fs)
@@ -1296,17 +1355,15 @@ etna_link_shader(struct etna_shader_link_info *info,
 	  * but that one removes all FS inputs ... why?
 	  */
       } else {
-         if (vsio == NULL) { /* not found -- link error */
-            BUG("Semantic value not found in vertex shader outputs\n");
-            return true;
-         }
-         varying->reg = vsio->reg;
+         /* pick a random register to use if there is no VS output */
+         if (vsio == NULL)
+            varying->reg = 0;
+         else
+            varying->reg = vsio->reg;
       }
 
       comp_ofs += varying->num_components;
    }
 
    assert(info->num_varyings == fs->infile.num_reg);
-
-   return false;
 }