Merge Mesa 20.0.8

With Mesa 20.1 even after the kernel change to do wbinvd on all cpus
sthen@ reported that hard hangs still occurred on his Haswell system
with inteldrm.

Mark Kane also reported seeing hangs on Ivy Bridge on bugs@.

Some systems/workloads seem to be more prone to triggering this than
others as I have not seen any hangs on Ivy Bridge and the only hangs
I saw on Haswell when running piglit went away with the wbinvd change.

It seems something is wrong with drm memory attributes or coherency in
the kernel and newer Mesa versions expect behaviour we don't have.

1 files changed, 9 insertions, 11 deletions

diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_surface.c b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_surface.c
index c78973bdb..420329ac3 100644
--- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_surface.c
+++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_surface.c
@@ -43,10 +43,9 @@ static struct etna_resource *
 etna_render_handle_incompatible(struct pipe_context *pctx, struct pipe_resource *prsc)
 {
    struct etna_context *ctx = etna_context(pctx);
-   struct etna_screen *screen = ctx->screen;
    struct etna_resource *res = etna_resource(prsc);
-   bool need_multitiled = screen->specs.pixel_pipes > 1 && !screen->specs.single_buffer;
-   bool want_supertiled = screen->specs.can_supertile;
+   bool need_multitiled = ctx->specs.pixel_pipes > 1 && !ctx->specs.single_buffer;
+   bool want_supertiled = ctx->specs.can_supertile;
 
    /* Resource is compatible if it is tiled and has multi tiling when required
     * TODO: LINEAR_PE feature means render to linear is possible ?
@@ -78,7 +77,6 @@ etna_create_surface(struct pipe_context *pctx, struct pipe_resource *prsc,
                     const struct pipe_surface *templat)
 {
    struct etna_context *ctx = etna_context(pctx);
-   struct etna_screen *screen = ctx->screen;
    struct etna_resource *rsc = etna_render_handle_incompatible(pctx, prsc);
    struct etna_surface *surf = CALLOC_STRUCT(etna_surface);
 
@@ -102,13 +100,13 @@ etna_create_surface(struct pipe_context *pctx, struct pipe_resource *prsc,
     * indicate the tile status module bypasses the memory
     * offset and MMU. */
 
-   if (VIV_FEATURE(screen, chipFeatures, FAST_CLEAR) &&
-       VIV_FEATURE(screen, chipMinorFeatures0, MC20) &&
+   if (VIV_FEATURE(ctx->screen, chipFeatures, FAST_CLEAR) &&
+       VIV_FEATURE(ctx->screen, chipMinorFeatures0, MC20) &&
        !rsc->ts_bo &&
        /* needs to be RS/BLT compatible for transfer_map/unmap */
        (rsc->levels[level].padded_width & ETNA_RS_WIDTH_MASK) == 0 &&
        (rsc->levels[level].padded_height & ETNA_RS_HEIGHT_MASK) == 0 &&
-       etna_resource_hw_tileable(screen->specs.use_blt, prsc)) {
+       etna_resource_hw_tileable(ctx->specs.use_blt, prsc)) {
       etna_screen_resource_alloc_ts(pctx->screen, rsc);
    }
 
@@ -131,7 +129,7 @@ etna_create_surface(struct pipe_context *pctx, struct pipe_resource *prsc,
    struct etna_resource_level *lev = &rsc->levels[level];
 
    /* Setup template relocations for this surface */
-   for (unsigned pipe = 0; pipe < screen->specs.pixel_pipes; ++pipe) {
+   for (unsigned pipe = 0; pipe < ctx->specs.pixel_pipes; ++pipe) {
       surf->reloc[pipe].bo = rsc->bo;
       surf->reloc[pipe].offset = surf->surf.offset;
       surf->reloc[pipe].flags = 0;
@@ -156,7 +154,7 @@ etna_create_surface(struct pipe_context *pctx, struct pipe_resource *prsc,
       surf->ts_reloc.offset = surf->surf.ts_offset;
       surf->ts_reloc.flags = 0;
 
-      if (!screen->specs.use_blt) {
+      if (!ctx->specs.use_blt) {
          /* This (ab)uses the RS as a plain buffer memset().
           * Currently uses a fixed row size of 64 bytes. Some benchmarking with
           * different sizes may be in order. */
@@ -171,13 +169,13 @@ etna_create_surface(struct pipe_context *pctx, struct pipe_resource *prsc,
             .dither = {0xffffffff, 0xffffffff},
             .width = 16,
             .height = etna_align_up(surf->surf.ts_size / 0x40, 4),
-            .clear_value = {screen->specs.ts_clear_value},
+            .clear_value = {ctx->specs.ts_clear_value},
             .clear_mode = VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1,
             .clear_bits = 0xffff
          });
       }
    } else {
-      if (!screen->specs.use_blt)
+      if (!ctx->specs.use_blt)
          etna_rs_gen_clear_surface(ctx, surf, surf->level->clear_value);
    }