Merge Mesa 19.0.5

16 files changed, 280 insertions, 76 deletions

diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_blend.c b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_blend.c
index 9c23411d4..061c9af52 100644
--- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_blend.c
+++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_blend.c
@@ -114,10 +114,11 @@ etna_update_blend(struct etna_context *ctx)
    struct pipe_blend_state *pblend = ctx->blend;
    struct etna_blend_state *blend = etna_blend_state(pblend);
    const struct pipe_rt_blend_state *rt0 = &pblend->rt[0];
+   const struct util_format_description *desc;
    uint32_t colormask;
 
    if (pfb->cbufs[0] &&
-       translate_rs_format_rb_swap(pfb->cbufs[0]->texture->format)) {
+       translate_rs_format_rb_swap(pfb->cbufs[0]->format)) {
       colormask = rt0->colormask & (PIPE_MASK_A | PIPE_MASK_G);
       if (rt0->colormask & PIPE_MASK_R)
          colormask |= PIPE_MASK_B;
@@ -128,11 +129,13 @@ etna_update_blend(struct etna_context *ctx)
    }
 
    /* If the complete render target is written, set full_overwrite:
-    * - The color mask is 1111
-    * - No blending is used
+    * - The color mask covers all channels of the render target
+    * - No blending or logicop is used
     */
-   bool full_overwrite = ((rt0->colormask == 0xf) && blend->fo_allowed) ||
-                         !pfb->cbufs[0];
+   if (pfb->cbufs[0])
+      desc = util_format_description(pfb->cbufs[0]->format);
+   bool full_overwrite = !pfb->cbufs[0] || ((blend->fo_allowed &&
+                         util_format_colormask_full(desc, colormask)));
    blend->PE_COLOR_FORMAT =
             VIVS_PE_COLOR_FORMAT_COMPONENTS(colormask) |
             COND(full_overwrite, VIVS_PE_COLOR_FORMAT_OVERWRITE);
@@ -158,7 +161,7 @@ etna_update_blend_color(struct etna_context *ctx)
    struct compiled_blend_color *cs = &ctx->blend_color;
 
    if (pfb->cbufs[0] &&
-       translate_rs_format_rb_swap(pfb->cbufs[0]->texture->format)) {
+       translate_rs_format_rb_swap(pfb->cbufs[0]->format)) {
       cs->PE_ALPHA_BLEND_COLOR =
          VIVS_PE_ALPHA_BLEND_COLOR_R(etna_cfloat_to_uint8(cs->color[2])) |
          VIVS_PE_ALPHA_BLEND_COLOR_G(etna_cfloat_to_uint8(cs->color[1])) |
diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_compiler.c b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_compiler.c
index bbc61a59f..ceca5b8af 100644
--- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_compiler.c
+++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_compiler.c
@@ -477,8 +477,7 @@ static void
 etna_compile_parse_declarations(struct etna_compile *c)
 {
    struct tgsi_parse_context ctx = { };
-   unsigned status = TGSI_PARSE_OK;
-   status = tgsi_parse_init(&ctx, c->tokens);
+   MAYBE_UNUSED unsigned status = tgsi_parse_init(&ctx, c->tokens);
    assert(status == TGSI_PARSE_OK);
 
    while (!tgsi_parse_end_of_tokens(&ctx)) {
@@ -530,8 +529,7 @@ static void
 etna_compile_pass_check_usage(struct etna_compile *c)
 {
    struct tgsi_parse_context ctx = { };
-   unsigned status = TGSI_PARSE_OK;
-   status = tgsi_parse_init(&ctx, c->tokens);
+   MAYBE_UNUSED unsigned status = tgsi_parse_init(&ctx, c->tokens);
    assert(status == TGSI_PARSE_OK);
 
    for (int idx = 0; idx < c->total_decls; ++idx) {
@@ -662,8 +660,7 @@ etna_compile_pass_optimize_outputs(struct etna_compile *c)
 {
    struct tgsi_parse_context ctx = { };
    int inst_idx = 0;
-   unsigned status = TGSI_PARSE_OK;
-   status = tgsi_parse_init(&ctx, c->tokens);
+   MAYBE_UNUSED unsigned status = tgsi_parse_init(&ctx, c->tokens);
    assert(status == TGSI_PARSE_OK);
 
    while (!tgsi_parse_end_of_tokens(&ctx)) {
@@ -1812,7 +1809,7 @@ static void
 etna_compile_pass_generate_code(struct etna_compile *c)
 {
    struct tgsi_parse_context ctx = { };
-   unsigned status = tgsi_parse_init(&ctx, c->tokens);
+   MAYBE_UNUSED unsigned status = tgsi_parse_init(&ctx, c->tokens);
    assert(status == TGSI_PARSE_OK);
 
    int inst_idx = 0;
diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_context.c b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_context.c
index 303dff583..44b50925a 100644
--- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_context.c
+++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_context.c
@@ -60,6 +60,9 @@ etna_context_destroy(struct pipe_context *pctx)
 {
    struct etna_context *ctx = etna_context(pctx);
 
+   if (ctx->dummy_rt)
+      etna_bo_del(ctx->dummy_rt);
+
    util_copy_framebuffer_state(&ctx->framebuffer_s, NULL);
 
    if (ctx->primconvert)
@@ -211,13 +214,8 @@ etna_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
    ctx->dirty |= ETNA_DIRTY_INDEX_BUFFER;
 
    struct etna_shader_key key = {};
-   struct etna_surface *cbuf = etna_surface(pfb->cbufs[0]);
-
-   if (cbuf) {
-      struct etna_resource *res = etna_resource(cbuf->base.texture);
-
-      key.frag_rb_swap = !!translate_rs_format_rb_swap(res->base.format);
-   }
+   if (pfb->cbufs[0])
+      key.frag_rb_swap = !!translate_rs_format_rb_swap(pfb->cbufs[0]->format);
 
    if (!etna_get_vs(ctx, key) || !etna_get_fs(ctx, key)) {
       BUG("compiled shaders are not okay");
@@ -488,6 +486,16 @@ etna_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags)
    slab_create_child(&ctx->transfer_pool, &screen->transfer_pool);
    list_inithead(&ctx->active_hw_queries);
 
+   /* create dummy RT buffer, used when rendering with no color buffer */
+   ctx->dummy_rt = etna_bo_new(ctx->screen->dev, 64 * 64 * 4,
+                               DRM_ETNA_GEM_CACHE_WC);
+   if (!ctx->dummy_rt)
+      goto fail;
+
+   ctx->dummy_rt_reloc.bo = ctx->dummy_rt;
+   ctx->dummy_rt_reloc.offset = 0;
+   ctx->dummy_rt_reloc.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
+
    return pctx;
 
 fail:
diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_context.h b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_context.h
index 584caa770..6ad9f3431 100644
--- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_context.h
+++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_context.h
@@ -190,6 +190,9 @@ struct etna_context {
 
    /* list of active hardware queries */
    struct list_head active_hw_queries;
+
+   struct etna_bo *dummy_rt;
+   struct etna_reloc dummy_rt_reloc;
 };
 
 static inline struct etna_context *
diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_resource.c b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_resource.c
index 3808c293e..9a7ebf306 100644
--- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_resource.c
+++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_resource.c
@@ -176,10 +176,20 @@ setup_miptree(struct etna_resource *rsc, unsigned paddingX, unsigned paddingY,
    return size;
 }
 
+/* Is rs alignment needed? */
+static bool is_rs_align(struct etna_screen *screen,
+                        const struct pipe_resource *tmpl)
+{
+   return screen->specs.use_blt ? false : (
+      VIV_FEATURE(screen, chipMinorFeatures1, TEXTURE_HALIGN) ||
+      !etna_resource_sampler_only(tmpl));
+}
+
 /* Create a new resource object, using the given template info */
 struct pipe_resource *
 etna_resource_alloc(struct pipe_screen *pscreen, unsigned layout,
-                    uint64_t modifier, const struct pipe_resource *templat)
+                    enum etna_resource_addressing_mode mode, uint64_t modifier,
+                    const struct pipe_resource *templat)
 {
    struct etna_screen *screen = etna_screen(pscreen);
    struct etna_resource *rsc;
@@ -217,11 +227,9 @@ etna_resource_alloc(struct pipe_screen *pscreen, unsigned layout,
        * resolve engine's width.  If not, we must not align resources used
        * only for textures. If this GPU uses the BLT engine, never do RS align.
        */
-      bool rs_align = screen->specs.use_blt ? false : (
-                         VIV_FEATURE(screen, chipMinorFeatures1, TEXTURE_HALIGN) ||
-                         !etna_resource_sampler_only(templat));
-      etna_layout_multiple(layout, screen->specs.pixel_pipes, rs_align, &paddingX,
-                           &paddingY, &halign);
+      etna_layout_multiple(layout, screen->specs.pixel_pipes,
+                           is_rs_align (screen, templat),
+                           &paddingX, &paddingY, &halign);
       assert(paddingX && paddingY);
    } else {
       /* Compressed textures are padded to their block size, but we don't have
@@ -273,6 +281,7 @@ etna_resource_alloc(struct pipe_screen *pscreen, unsigned layout,
    rsc->base.nr_samples = nr_samples;
    rsc->layout = layout;
    rsc->halign = halign;
+   rsc->addressing_mode = mode;
 
    pipe_reference_init(&rsc->base.reference, 1);
    list_inithead(&rsc->list);
@@ -309,12 +318,14 @@ etna_resource_create(struct pipe_screen *pscreen,
 {
    struct etna_screen *screen = etna_screen(pscreen);
 
-   /* Figure out what tiling to use -- for now, assume that texture cannot be linear.
-    * there is a capability LINEAR_TEXTURE_SUPPORT (supported on gc880 and
-    * gc2000 at least), but not sure how it works.
+   /* Figure out what tiling and address mode to use -- for now, assume that
+    * texture cannot be linear. there is a capability LINEAR_TEXTURE_SUPPORT
+    * (supported on gc880 and gc2000 at least), but not sure how it works.
     * Buffers always have LINEAR layout.
     */
    unsigned layout = ETNA_LAYOUT_LINEAR;
+   enum etna_resource_addressing_mode mode = ETNA_ADDRESSING_MODE_TILED;
+
    if (etna_resource_sampler_only(templat)) {
       /* The buffer is only used for texturing, so create something
        * directly compatible with the sampler.  Such a buffer can
@@ -357,7 +368,7 @@ etna_resource_create(struct pipe_screen *pscreen,
       layout = ETNA_LAYOUT_LINEAR;
 
    /* modifier is only used for scanout surfaces, so safe to use LINEAR here */
-   return etna_resource_alloc(pscreen, layout, DRM_FORMAT_MOD_LINEAR, templat);
+   return etna_resource_alloc(pscreen, layout, mode, DRM_FORMAT_MOD_LINEAR, templat);
 }
 
 enum modifier_priority {
@@ -438,7 +449,7 @@ etna_resource_create_modifiers(struct pipe_screen *pscreen,
    tmpl.bind |= PIPE_BIND_SCANOUT;
 
    return etna_resource_alloc(pscreen, modifier_to_layout(modifier),
-                              modifier, &tmpl);
+                              ETNA_ADDRESSING_MODE_TILED, modifier, &tmpl);
 }
 
 static void
@@ -511,6 +522,7 @@ etna_resource_from_handle(struct pipe_screen *pscreen,
    rsc->seqno = 1;
    rsc->layout = modifier_to_layout(handle->modifier);
    rsc->halign = TEXTURE_HALIGN_FOUR;
+   rsc->addressing_mode = ETNA_ADDRESSING_MODE_TILED;
 
 
    level->width = tmpl->width0;
@@ -519,7 +531,7 @@ etna_resource_from_handle(struct pipe_screen *pscreen,
    /* Determine padding of the imported resource. */
    unsigned paddingX = 0, paddingY = 0;
    etna_layout_multiple(rsc->layout, screen->specs.pixel_pipes,
-                        VIV_FEATURE(screen, chipMinorFeatures1, TEXTURE_HALIGN),
+                        is_rs_align(screen, tmpl),
                         &paddingX, &paddingY, &rsc->halign);
 
    if (!screen->specs.use_blt)
diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_resource.h b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_resource.h
index 11ccf8f7b..75aa80b3d 100644
--- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_resource.h
+++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_resource.h
@@ -49,6 +49,11 @@ struct etna_resource_level {
    bool ts_valid;
 };
 
+enum etna_resource_addressing_mode {
+   ETNA_ADDRESSING_MODE_TILED = 0,
+   ETNA_ADDRESSING_MODE_LINEAR,
+};
+
 /* status of queued up but not flushed reads and write operations.
  * In _transfer_map() we need to know if queued up rendering needs
  * to be flushed to preserve the order of cpu and gpu access. */
@@ -66,6 +71,7 @@ struct etna_resource {
    /* only lod 0 used for non-texture buffers */
    /* Layout for surface (tiled, multitiled, split tiled, ...) */
    enum etna_surface_layout layout;
+   enum etna_resource_addressing_mode addressing_mode;
    /* Horizontal alignment for texture unit (TEXTURE_HALIGN_*) */
    unsigned halign;
    struct etna_bo *bo; /* Surface video memory */
@@ -155,7 +161,8 @@ etna_screen_resource_alloc_ts(struct pipe_screen *pscreen,
 
 struct pipe_resource *
 etna_resource_alloc(struct pipe_screen *pscreen, unsigned layout,
-                    uint64_t modifier, const struct pipe_resource *templat);
+                    enum etna_resource_addressing_mode mode, uint64_t modifier,
+                    const struct pipe_resource *templat);
 
 void
 etna_resource_screen_init(struct pipe_screen *pscreen);
diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_screen.c b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_screen.c
index fb51aa5f4..35dcac140 100644
--- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_screen.c
+++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_screen.c
@@ -63,7 +63,7 @@ static const struct debug_named_value debug_options[] = {
    {"no_autodisable", ETNA_DBG_NO_AUTODISABLE, "Disable autodisable"},
    {"no_supertile",   ETNA_DBG_NO_SUPERTILE, "Disable supertiles"},
    {"no_early_z",     ETNA_DBG_NO_EARLY_Z, "Disable early z"},
-   {"cflush_all",     ETNA_DBG_CFLUSH_ALL, "Flush every cash before state update"},
+   {"cflush_all",     ETNA_DBG_CFLUSH_ALL, "Flush every cache before state update"},
    {"msaa2x",         ETNA_DBG_MSAA_2X, "Force 2x msaa"},
    {"msaa4x",         ETNA_DBG_MSAA_4X, "Force 4x msaa"},
    {"flush_all",      ETNA_DBG_FLUSH_ALL, "Flush after every rendered primitive"},
@@ -360,6 +360,9 @@ etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
       return 0;
 
+   case PIPE_CAP_MAX_VARYINGS:
+      return screen->specs.max_varyings;
+
    case PIPE_CAP_PCI_GROUP:
    case PIPE_CAP_PCI_BUS:
    case PIPE_CAP_PCI_DEVICE:
diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_shader.c b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_shader.c
index 27c735b83..d2d736bde 100644
--- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_shader.c
+++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_shader.c
@@ -230,8 +230,7 @@ etna_shader_link(struct etna_context *ctx)
 }
 
 static bool
-etna_shader_update_vs_inputs(struct etna_context *ctx,
-                             struct compiled_shader_state *cs,
+etna_shader_update_vs_inputs(struct compiled_shader_state *cs,
                              const struct etna_shader_variant *vs,
                              const struct compiled_vertex_elements_state *ves)
 {
@@ -246,7 +245,7 @@ etna_shader_update_vs_inputs(struct etna_context *ctx,
    num_vs_inputs = MAX2(ves->num_elements, vs->infile.num_reg);
    if (num_vs_inputs != ves->num_elements) {
       BUG("Number of elements %u does not match the number of VS inputs %zu",
-          ctx->vertex_elements->num_elements, ctx->shader.vs->infile.num_reg);
+          ves->num_elements, vs->infile.num_reg);
       return false;
    }
 
@@ -312,7 +311,7 @@ dump_shader_info(struct etna_shader_variant *v, struct pipe_debug_callback *debu
 bool
 etna_shader_update_vertex(struct etna_context *ctx)
 {
-   return etna_shader_update_vs_inputs(ctx, &ctx->shader_state, ctx->shader.vs,
+   return etna_shader_update_vs_inputs(&ctx->shader_state, ctx->shader.vs,
                                        ctx->vertex_elements);
 }
 
diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_state.c b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_state.c
index 520cc5a77..e23722b0d 100644
--- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_state.c
+++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_state.c
@@ -190,8 +190,9 @@ etna_set_framebuffer_state(struct pipe_context *pctx,
       cs->TS_COLOR_STATUS_BASE.bo = NULL;
       cs->TS_COLOR_SURFACE_BASE.bo = NULL;
 
-      for (int i = 0; i < ETNA_MAX_PIXELPIPES; i++)
-         cs->PE_PIPE_COLOR_ADDR[i].bo = NULL;
+      cs->PE_COLOR_ADDR = ctx->dummy_rt_reloc;
+      for (int i = 0; i < ctx->specs.pixel_pipes; i++)
+         cs->PE_PIPE_COLOR_ADDR[i] = ctx->dummy_rt_reloc;
    }
 
    if (sv->zsbuf != NULL) {
diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_texture.c b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_texture.c
index 72ef00bcb..b06f20531 100644
--- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_texture.c
+++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_texture.c
@@ -172,7 +172,9 @@ etna_resource_sampler_compatible(struct etna_resource *res)
    if (res->layout == ETNA_LAYOUT_SUPER_TILED && VIV_FEATURE(screen, chipMinorFeatures2, SUPERTILED_TEXTURE))
       return true;
 
-   /* TODO: LINEAR_TEXTURE_SUPPORT */
+   /* This GPU supports texturing from linear textures? */
+   if (res->layout == ETNA_LAYOUT_LINEAR && VIV_FEATURE(screen, chipMinorFeatures1, LINEAR_TEXTURE_SUPPORT))
+      return true;
 
    /* Otherwise, only support tiled layouts */
    if (res->layout != ETNA_LAYOUT_TILED)
@@ -203,6 +205,7 @@ etna_texture_handle_incompatible(struct pipe_context *pctx, struct pipe_resource
                            PIPE_BIND_BLENDABLE);
          res->texture =
             etna_resource_alloc(pctx->screen, ETNA_LAYOUT_TILED,
+                                ETNA_ADDRESSING_MODE_TILED,
                                 DRM_FORMAT_MOD_LINEAR, &templat);
       }
 
diff --git a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_transfer.c b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_transfer.c
index 30ae3bfc3..0294697af 100644
--- a/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_transfer.c
+++ b/lib/mesa/src/gallium/drivers/etnaviv/etnaviv_transfer.c
@@ -208,7 +208,8 @@ etna_transfer_map(struct pipe_context *pctx, struct pipe_resource *prsc,
       templ.bind = PIPE_BIND_RENDER_TARGET;
 
       trans->rsc = etna_resource_alloc(pctx->screen, ETNA_LAYOUT_LINEAR,
-                                       DRM_FORMAT_MOD_LINEAR, &templ);
+                                       ETNA_ADDRESSING_MODE_TILED, DRM_FORMAT_MOD_LINEAR,
+                                       &templ);
       if (!trans->rsc) {
          slab_free(&ctx->transfer_pool, trans);
          return NULL;
diff --git a/lib/mesa/src/gallium/drivers/etnaviv/hw/cmdstream.xml.h b/lib/mesa/src/gallium/drivers/etnaviv/hw/cmdstream.xml.h
index 63d4e9342..77cbebfe3 100644
--- a/lib/mesa/src/gallium/drivers/etnaviv/hw/cmdstream.xml.h
+++ b/lib/mesa/src/gallium/drivers/etnaviv/hw/cmdstream.xml.h
@@ -8,11 +8,11 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
 git clone git://0x04.net/rules-ng-ng
 
 The rules-ng-ng source files this header was generated from are:
-- cmdstream.xml (  16929 bytes, from 2017-10-13 12:22:46)
-- copyright.xml (   1597 bytes, from 2016-10-29 07:29:22)
-- common.xml    (  26187 bytes, from 2017-10-31 19:05:01)
+- cmdstream.xml (  16930 bytes, from 2019-01-04 11:37:39)
+- copyright.xml (   1597 bytes, from 2018-02-10 13:09:26)
+- common.xml    (  35468 bytes, from 2018-02-10 13:09:26)
 
-Copyright (C) 2012-2017 by the following authors:
+Copyright (C) 2012-2019 by the following authors:
 - Wladimir J. van der Laan <laanwj@gmail.com>
 - Christian Gmeiner <christian.gmeiner@gmail.com>
 - Lucas Stach <l.stach@pengutronix.de>
diff --git a/lib/mesa/src/gallium/drivers/etnaviv/hw/common.xml.h b/lib/mesa/src/gallium/drivers/etnaviv/hw/common.xml.h
index 60bde8b96..4af7ec369 100644
--- a/lib/mesa/src/gallium/drivers/etnaviv/hw/common.xml.h
+++ b/lib/mesa/src/gallium/drivers/etnaviv/hw/common.xml.h
@@ -8,12 +8,12 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
 git clone git://0x04.net/rules-ng-ng
 
 The rules-ng-ng source files this header was generated from are:
-- texdesc_3d.xml (   3183 bytes, from 2017-10-31 19:05:01)
-- copyright.xml  (   1597 bytes, from 2016-10-29 07:29:22)
-- common.xml     (  26187 bytes, from 2017-10-31 19:05:01)
-- common_3d.xml  (  14615 bytes, from 2017-11-04 14:03:35)
+- texdesc_3d.xml (   3183 bytes, from 2018-02-10 13:09:26)
+- copyright.xml  (   1597 bytes, from 2018-02-10 13:09:26)
+- common.xml     (  35468 bytes, from 2018-02-10 13:09:26)
+- common_3d.xml  (  14843 bytes, from 2019-01-18 10:13:41)
 
-Copyright (C) 2012-2017 by the following authors:
+Copyright (C) 2012-2018 by the following authors:
 - Wladimir J. van der Laan <laanwj@gmail.com>
 - Christian Gmeiner <christian.gmeiner@gmail.com>
 - Lucas Stach <l.stach@pengutronix.de>
@@ -320,5 +320,166 @@ DEALINGS IN THE SOFTWARE.
 #define chipMinorFeatures6_DEC					0x00000004
 #define chipMinorFeatures6_VS_TILE_NV12				0x00000008
 #define chipMinorFeatures6_VS_TILE_NV12_10BIT			0x00000010
+#define chipMinorFeatures6_RENDER_TARGET_8			0x00000020
+#define chipMinorFeatures6_TEX_LOD_FLOW_CORR			0x00000040
+#define chipMinorFeatures6_FACE_LOD				0x00000080
+#define chipMinorFeatures6_MULTI_CORE_SEMAPHORE_STALL_V2	0x00000100
+#define chipMinorFeatures6_VMSAA				0x00000200
+#define chipMinorFeatures6_CHIP_ENABLE_LINK			0x00000400
+#define chipMinorFeatures6_MULTI_SRC_BLT_1_5_ENHANCEMENT	0x00000800
+#define chipMinorFeatures6_MULTI_SRC_BLT_BILINEAR_FILTER	0x00001000
+#define chipMinorFeatures6_RA_HZEZ_CLOCK_CONTROL		0x00002000
+#define chipMinorFeatures6_CACHE128B256BPERLINE			0x00004000
+#define chipMinorFeatures6_V4_COMPRESSION			0x00008000
+#define chipMinorFeatures6_PE2D_MAJOR_SUPER_TILE		0x00010000
+#define chipMinorFeatures6_PE_32BPC_COLORMASK_FIX		0x00020000
+#define chipMinorFeatures6_ALPHA_BLENDING_OPT			0x00040000
+#define chipMinorFeatures6_NEW_GPIPE				0x00080000
+#define chipMinorFeatures6_PIPELINE_32_ATTRIBUTES		0x00100000
+#define chipMinorFeatures6_MSAA_SHADING				0x00200000
+#define chipMinorFeatures6_NO_ANISTRO_FILTER			0x00400000
+#define chipMinorFeatures6_NO_ASTC				0x00800000
+#define chipMinorFeatures6_NO_DXT				0x01000000
+#define chipMinorFeatures6_HWTFB				0x02000000
+#define chipMinorFeatures6_RA_DEPTH_WRITE_MSAA1X_FIX		0x04000000
+#define chipMinorFeatures6_EZHZ_CLOCKGATE_FIX			0x08000000
+#define chipMinorFeatures6_SH_SNAP2PAGE_FIX			0x10000000
+#define chipMinorFeatures6_SH_HALFDEPENDENCY_FIX		0x20000000
+#define chipMinorFeatures6_USC_MCFILL_FIX			0x40000000
+#define chipMinorFeatures6_TPG_TCPERF_FIX			0x80000000
+#define chipMinorFeatures7_USC_MDFIFO_OVERFLOW_FIX		0x00000001
+#define chipMinorFeatures7_SH_TEXLD_BARRIER_IN_CS_FIX		0x00000002
+#define chipMinorFeatures7_RS_NEW_BASEADDR			0x00000004
+#define chipMinorFeatures7_PE_8BPP_DUALPIPE_FIX			0x00000008
+#define chipMinorFeatures7_SH_ADVANCED_INSTR			0x00000010
+#define chipMinorFeatures7_SH_FLAT_INTERPOLATION_DUAL16_FIX	0x00000020
+#define chipMinorFeatures7_USC_CONTINUOUS_FLUS_FIX		0x00000040
+#define chipMinorFeatures7_SH_SUPPORT_V4			0x00000080
+#define chipMinorFeatures7_SH_SUPPORT_ALPHA_KILL		0x00000100
+#define chipMinorFeatures7_PE_NO_ALPHA_TEST			0x00000200
+#define chipMinorFeatures7_TX_LOD_NEAREST_SELECT		0x00000400
+#define chipMinorFeatures7_SH_FIX_LDEXP				0x00000800
+#define chipMinorFeatures7_SUPPORT_MOVAI			0x00001000
+#define chipMinorFeatures7_SH_SNAP2PAGE_MAXPAGES_FIX		0x00002000
+#define chipMinorFeatures7_PE_RGBA16I_FIX			0x00004000
+#define chipMinorFeatures7_BLT_8bpp_256TILE_FC_FIX		0x00008000
+#define chipMinorFeatures7_PE_64BIT_FENCE_FIX			0x00010000
+#define chipMinorFeatures7_USC_FULL_CACHE_FIX			0x00020000
+#define chipMinorFeatures7_TX_YUV_ASSEMBLER_10BIT		0x00040000
+#define chipMinorFeatures7_FE_32BIT_INDEX_FIX			0x00080000
+#define chipMinorFeatures7_BLT_64BPP_MASKED_CLEAR_FIX		0x00100000
+#define chipMinorFeatures7_BIT_SECURITY				0x00200000
+#define chipMinorFeatures7_BIT_ROBUSTNESS			0x00400000
+#define chipMinorFeatures7_USC_ATOMIC_FIX			0x00800000
+#define chipMinorFeatures7_SH_PSO_MSAA1x_FIX			0x01000000
+#define chipMinorFeatures7_BIT_USC_VX_PERF_FIX			0x02000000
+#define chipMinorFeatures7_EVIS_NO_ABSDIFF			0x04000000
+#define chipMinorFeatures7_EVIS_NO_BITREPLACE			0x08000000
+#define chipMinorFeatures7_EVIS_NO_BOXFILTER			0x10000000
+#define chipMinorFeatures7_EVIS_NO_CORDIAC			0x20000000
+#define chipMinorFeatures7_EVIS_NO_DP32				0x40000000
+#define chipMinorFeatures7_EVIS_NO_FILTER			0x80000000
+#define chipMinorFeatures8_EVIS_NO_IADD				0x00000001
+#define chipMinorFeatures8_EVIS_NO_SELECTADD			0x00000002
+#define chipMinorFeatures8_EVIS_LERP_7OUTPUT			0x00000004
+#define chipMinorFeatures8_EVIS_ACCSQ_8OUTPUT			0x00000008
+#define chipMinorFeatures8_USC_GOS_ADDR_FIX			0x00000010
+#define chipMinorFeatures8_TX_8BIT_UVFRAC			0x00000020
+#define chipMinorFeatures8_TX_DESC_CACHE_CLOCKGATE_FIX		0x00000040
+#define chipMinorFeatures8_RSBLT_MSAA_DECOMPRESSION		0x00000080
+#define chipMinorFeatures8_TX_INTEGER_COORDINATE		0x00000100
+#define chipMinorFeatures8_DRAWID				0x00000200
+#define chipMinorFeatures8_PSIO_SAMPLEMASK_IN_R0ZW_FIX		0x00000400
+#define chipMinorFeatures8_TX_INTEGER_COORDINATE_V2		0x00000800
+#define chipMinorFeatures8_MULTI_CORE_BLOCK_SET_CONFIG		0x00001000
+#define chipMinorFeatures8_VG_RESOLVE_ENGINE			0x00002000
+#define chipMinorFeatures8_VG_PE_COLOR_KEY			0x00004000
+#define chipMinorFeatures8_VG_IM_INDEX_FORMAT			0x00008000
+#define chipMinorFeatures8_SNAPPAGE_CMD				0x00010000
+#define chipMinorFeatures8_SH_NO_INDEX_CONST_ON_A0		0x00020000
+#define chipMinorFeatures8_SH_NO_ONECONST_LIMIT			0x00040000
+#define chipMinorFeatures8_SH_IMG_LDST_ON_TEMP			0x00080000
+#define chipMinorFeatures8_COMPUTE_ONLY				0x00100000
+#define chipMinorFeatures8_SH_IMG_LDST_CLAMP			0x00200000
+#define chipMinorFeatures8_SH_ICACHE_ALLOC_COUNT_FIX		0x00400000
+#define chipMinorFeatures8_SH_ICACHE_PREFETCH			0x00800000
+#define chipMinorFeatures8_PE2D_SEPARATE_CACHE			0x01000000
+#define chipMinorFeatures8_VG_AYUV_INPUT_OUTPUT			0x02000000
+#define chipMinorFeatures8_VG_DOUBLE_IMAGE			0x04000000
+#define chipMinorFeatures8_VG_RECTANGLE_STRIPE_MODE		0x08000000
+#define chipMinorFeatures8_VG_MMU				0x10000000
+#define chipMinorFeatures8_VG_IM_FILTER				0x20000000
+#define chipMinorFeatures8_VG_IM_YUV_PACKET			0x40000000
+#define chipMinorFeatures8_VG_IM_YUV_PLANAR			0x80000000
+#define chipMinorFeatures9_VG_PE_YUV_PACKET			0x00000001
+#define chipMinorFeatures9_VG_COLOR_PRECISION_8_BIT		0x00000002
+#define chipMinorFeatures9_PE_MSAA_OQ_FIX			0x00000004
+#define chipMinorFeatures9_PSIO_MSAA_CL_FIX			0x00000008
+#define chipMinorFeatures9_USC_DEFER_FILL_FIX			0x00000010
+#define chipMinorFeatures9_SH_CLOCK_GATE_FIX			0x00000020
+#define chipMinorFeatures9_FE_NEED_DUMMYDRAW			0x00000040
+#define chipMinorFeatures9_PE2D_LINEAR_YUV420_OUTPUT		0x00000080
+#define chipMinorFeatures9_PE2D_LINEAR_YUV420_10BIT		0x00000100
+#define chipMinorFeatures9_MULTI_CLUSTER			0x00000200
+#define chipMinorFeatures9_VG_TS_CULLING			0x00000400
+#define chipMinorFeatures9_VG_FP25				0x00000800
+#define chipMinorFeatures9_SH_MULTI_WG_PACK			0x00001000
+#define chipMinorFeatures9_SH_DUAL16_SAMPLEMASK_ZW		0x00002000
+#define chipMinorFeatures9_TPG_TRIVIAL_MODE_FIX			0x00004000
+#define chipMinorFeatures9_TX_ASTC_MULTISLICE_FIX		0x00008000
+#define chipMinorFeatures9_FE_ROBUST_FIX			0x00010000
+#define chipMinorFeatures9_SH_GPIPE_ACCESS_FULLTEMPS		0x00020000
+#define chipMinorFeatures9_PSIO_INTERLOCK			0x00040000
+#define chipMinorFeatures9_PA_WIDELINE_FIX			0x00080000
+#define chipMinorFeatures9_WIDELINE_HELPER_FIX			0x00100000
+#define chipMinorFeatures9_G2D_3RD_PARTY_COMPRESSION_1_1	0x00200000
+#define chipMinorFeatures9_TX_FLUSH_L1CACHE			0x00400000
+#define chipMinorFeatures9_PE_DITHER_FIX2			0x00800000
+#define chipMinorFeatures9_G2D_DEC400				0x01000000
+#define chipMinorFeatures9_SH_TEXLD_U_FIX			0x02000000
+#define chipMinorFeatures9_MC_FCCACHE_BYTEMASK			0x04000000
+#define chipMinorFeatures9_SH_MULTI_WG_PACK_FIX			0x08000000
+#define chipMinorFeatures9_DC_OVERLAY_SCALING			0x10000000
+#define chipMinorFeatures9_DC_SOURCE_ROTATION			0x20000000
+#define chipMinorFeatures9_DC_TILED				0x40000000
+#define chipMinorFeatures9_DC_YUV_L1				0x80000000
+#define chipMinorFeatures10_DC_D30_OUTPUT			0x00000001
+#define chipMinorFeatures10_DC_MMU				0x00000002
+#define chipMinorFeatures10_DC_COMPRESSION			0x00000004
+#define chipMinorFeatures10_DC_QOS				0x00000008
+#define chipMinorFeatures10_PE_ADVANCE_BLEND_PART0		0x00000010
+#define chipMinorFeatures10_FE_PATCHLIST_FETCH_FIX		0x00000020
+#define chipMinorFeatures10_RA_CG_FIX				0x00000040
+#define chipMinorFeatures10_EVIS_VX2				0x00000080
+#define chipMinorFeatures10_NN_FLOAT				0x00000100
+#define chipMinorFeatures10_DEC400				0x00000200
+#define chipMinorFeatures10_LS_SUPPORT_PERCOMP_DEPENDENCY	0x00000400
+#define chipMinorFeatures10_TP_ENGINE				0x00000800
+#define chipMinorFeatures10_MULTI_CORE_BLOCK_SET_CONFIG2	0x00001000
+#define chipMinorFeatures10_PE_VMSAA_COVERAGE_CACHE_FIX		0x00002000
+#define chipMinorFeatures10_SECURITY_AHB			0x00004000
+#define chipMinorFeatures10_MULTICORE_SEMAPHORESTALL_V3		0x00008000
+#define chipMinorFeatures10_SMALLBATCH				0x00010000
+#define chipMinorFeatures10_SH_CMPLX				0x00020000
+#define chipMinorFeatures10_SH_IDIV0_SWZL_EHS			0x00040000
+#define chipMinorFeatures10_TX_LERP_LESS_BIT			0x00080000
+#define chipMinorFeatures10_SH_GM_ENDIAN			0x00100000
+#define chipMinorFeatures10_SH_GM_USC_UNALLOC			0x00200000
+#define chipMinorFeatures10_SH_END_OF_BB			0x00400000
+#define chipMinorFeatures10_VIP_V7				0x00800000
+#define chipMinorFeatures10_TX_BORDER_CLAMP_FIX			0x01000000
+#define chipMinorFeatures10_SH_IMG_LD_LASTPIXEL_FIX		0x02000000
+#define chipMinorFeatures10_ASYNC_BLT				0x04000000
+#define chipMinorFeatures10_ASYNC_FE_FENCE_FIX			0x08000000
+#define chipMinorFeatures10_PSCS_THROTTLE			0x10000000
+#define chipMinorFeatures10_SEPARATE_LS				0x20000000
+#define chipMinorFeatures10_MCFE				0x40000000
+#define chipMinorFeatures10_WIDELINE_TRIANGLE_EMU		0x80000000
+#define chipMinorFeatures11_VG_RESOLUTION_8K			0x00000001
+#define chipMinorFeatures11_FENCE_32BIT				0x00000002
+#define chipMinorFeatures11_FENCE_64BIT				0x00000004
+#define chipMinorFeatures11_NN_INTERLEVE8			0x00000008
+#define chipMinorFeatures11_TP_REORDER				0x00000010
+#define chipMinorFeatures11_PE_DEPTH_ONLY_OQFIX			0x00000020
 
 #endif /* COMMON_XML */
diff --git a/lib/mesa/src/gallium/drivers/etnaviv/hw/isa.xml.h b/lib/mesa/src/gallium/drivers/etnaviv/hw/isa.xml.h
index ae4905450..5e8017310 100644
--- a/lib/mesa/src/gallium/drivers/etnaviv/hw/isa.xml.h
+++ b/lib/mesa/src/gallium/drivers/etnaviv/hw/isa.xml.h
@@ -8,10 +8,10 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
 git clone git://0x04.net/rules-ng-ng
 
 The rules-ng-ng source files this header was generated from are:
-- isa.xml       (  37079 bytes, from 2017-10-19 09:48:25)
-- copyright.xml (   1597 bytes, from 2016-10-29 07:29:22)
+- isa.xml       (  37079 bytes, from 2018-02-10 13:09:26)
+- copyright.xml (   1597 bytes, from 2018-02-10 13:09:26)
 
-Copyright (C) 2012-2017 by the following authors:
+Copyright (C) 2012-2018 by the following authors:
 - Wladimir J. van der Laan <laanwj@gmail.com>
 - Christian Gmeiner <christian.gmeiner@gmail.com>
 - Lucas Stach <l.stach@pengutronix.de>
diff --git a/lib/mesa/src/gallium/drivers/etnaviv/hw/state.xml.h b/lib/mesa/src/gallium/drivers/etnaviv/hw/state.xml.h
index 485c0eb28..5b4b86982 100644
--- a/lib/mesa/src/gallium/drivers/etnaviv/hw/state.xml.h
+++ b/lib/mesa/src/gallium/drivers/etnaviv/hw/state.xml.h
@@ -8,17 +8,17 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
 git clone git://0x04.net/rules-ng-ng
 
 The rules-ng-ng source files this header was generated from are:
-- state.xml     (  26087 bytes, from 2017-10-30 13:44:54)
-- common.xml    (  26187 bytes, from 2017-10-31 19:05:01)
-- common_3d.xml (  14615 bytes, from 2017-11-04 14:03:35)
-- state_hi.xml  (  27733 bytes, from 2017-10-02 19:00:30)
-- copyright.xml (   1597 bytes, from 2016-10-29 07:29:22)
-- state_2d.xml  (  51552 bytes, from 2016-10-29 07:29:22)
-- state_3d.xml  (  79992 bytes, from 2017-11-07 10:44:35)
-- state_blt.xml (  13405 bytes, from 2017-10-16 17:42:46)
-- state_vg.xml  (   5975 bytes, from 2016-10-29 07:29:22)
-
-Copyright (C) 2012-2017 by the following authors:
+- state.xml     (  26087 bytes, from 2018-02-10 13:09:26)
+- common.xml    (  35468 bytes, from 2018-02-10 13:09:26)
+- common_3d.xml (  14843 bytes, from 2019-01-18 10:13:41)
+- state_hi.xml  (  30232 bytes, from 2018-03-30 07:48:22)
+- copyright.xml (   1597 bytes, from 2018-02-10 13:09:26)
+- state_2d.xml  (  51552 bytes, from 2018-02-10 13:09:26)
+- state_3d.xml  (  79992 bytes, from 2019-01-18 10:10:57)
+- state_blt.xml (  13405 bytes, from 2018-02-10 13:09:26)
+- state_vg.xml  (   5975 bytes, from 2018-02-10 13:09:26)
+
+Copyright (C) 2012-2018 by the following authors:
 - Wladimir J. van der Laan <laanwj@gmail.com>
 - Christian Gmeiner <christian.gmeiner@gmail.com>
 - Lucas Stach <l.stach@pengutronix.de>
diff --git a/lib/mesa/src/gallium/drivers/etnaviv/hw/state_3d.xml.h b/lib/mesa/src/gallium/drivers/etnaviv/hw/state_3d.xml.h
index 13122789e..dacf252fe 100644
--- a/lib/mesa/src/gallium/drivers/etnaviv/hw/state_3d.xml.h
+++ b/lib/mesa/src/gallium/drivers/etnaviv/hw/state_3d.xml.h
@@ -8,17 +8,17 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
 git clone git://0x04.net/rules-ng-ng
 
 The rules-ng-ng source files this header was generated from are:
-- state.xml     (  26087 bytes, from 2017-10-30 13:44:54)
-- common.xml    (  26187 bytes, from 2017-10-31 19:05:01)
-- common_3d.xml (  14615 bytes, from 2017-11-04 14:03:35)
-- state_hi.xml  (  27733 bytes, from 2017-10-02 19:00:30)
-- copyright.xml (   1597 bytes, from 2016-10-29 07:29:22)
-- state_2d.xml  (  51552 bytes, from 2016-10-29 07:29:22)
-- state_3d.xml  (  79992 bytes, from 2017-11-07 10:44:35)
-- state_blt.xml (  13405 bytes, from 2017-10-16 17:42:46)
-- state_vg.xml  (   5975 bytes, from 2016-10-29 07:29:22)
-
-Copyright (C) 2012-2017 by the following authors:
+- state.xml     (  26087 bytes, from 2018-02-10 13:09:26)
+- common.xml    (  35468 bytes, from 2018-02-10 13:09:26)
+- common_3d.xml (  14843 bytes, from 2019-01-18 10:13:41)
+- state_hi.xml  (  30232 bytes, from 2018-03-30 07:48:22)
+- copyright.xml (   1597 bytes, from 2018-02-10 13:09:26)
+- state_2d.xml  (  51552 bytes, from 2018-02-10 13:09:26)
+- state_3d.xml  (  79992 bytes, from 2019-01-18 10:10:57)
+- state_blt.xml (  13405 bytes, from 2018-02-10 13:09:26)
+- state_vg.xml  (   5975 bytes, from 2018-02-10 13:09:26)
+
+Copyright (C) 2012-2019 by the following authors:
 - Wladimir J. van der Laan <laanwj@gmail.com>
 - Christian Gmeiner <christian.gmeiner@gmail.com>
 - Lucas Stach <l.stach@pengutronix.de>
@@ -1400,6 +1400,9 @@ DEALINGS IN THE SOFTWARE.
 #define VIVS_TE_SAMPLER_CONFIG0_FORMAT__SHIFT			13
 #define VIVS_TE_SAMPLER_CONFIG0_FORMAT(x)			(((x) << VIVS_TE_SAMPLER_CONFIG0_FORMAT__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_FORMAT__MASK)
 #define VIVS_TE_SAMPLER_CONFIG0_ROUND_UV			0x00080000
+#define VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE__MASK		0x00300000
+#define VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE__SHIFT		20
+#define VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE(x)		(((x) << VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE__MASK)
 #define VIVS_TE_SAMPLER_CONFIG0_ENDIAN__MASK			0x00c00000
 #define VIVS_TE_SAMPLER_CONFIG0_ENDIAN__SHIFT			22
 #define VIVS_TE_SAMPLER_CONFIG0_ENDIAN(x)			(((x) << VIVS_TE_SAMPLER_CONFIG0_ENDIAN__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_ENDIAN__MASK)
@@ -1520,6 +1523,9 @@ DEALINGS IN THE SOFTWARE.
 #define VIVS_NTE_SAMPLER_CONFIG0_FORMAT__SHIFT			13
 #define VIVS_NTE_SAMPLER_CONFIG0_FORMAT(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG0_FORMAT__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_FORMAT__MASK)
 #define VIVS_NTE_SAMPLER_CONFIG0_ROUND_UV			0x00080000
+#define VIVS_NTE_SAMPLER_CONFIG0_ADDRESSING_MODE__MASK		0x00300000
+#define VIVS_NTE_SAMPLER_CONFIG0_ADDRESSING_MODE__SHIFT		20
+#define VIVS_NTE_SAMPLER_CONFIG0_ADDRESSING_MODE(x)		(((x) << VIVS_NTE_SAMPLER_CONFIG0_ADDRESSING_MODE__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_ADDRESSING_MODE__MASK)
 #define VIVS_NTE_SAMPLER_CONFIG0_ENDIAN__MASK			0x00c00000
 #define VIVS_NTE_SAMPLER_CONFIG0_ENDIAN__SHIFT			22
 #define VIVS_NTE_SAMPLER_CONFIG0_ENDIAN(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG0_ENDIAN__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_ENDIAN__MASK)