Merge Mesa 20.1.6

7 files changed, 86 insertions, 137 deletions

diff --git a/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_draw.c b/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_draw.c
index e6572d624..99e44db37 100644
--- a/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_draw.c
+++ b/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_draw.c
@@ -28,7 +28,7 @@
 #include "util/u_string.h"
 #include "util/u_memory.h"
 #include "util/u_prim.h"
-#include "util/u_format.h"
+#include "util/format/u_format.h"
 
 #include "freedreno_state.h"
 #include "freedreno_resource.h"
@@ -126,7 +126,7 @@ fd3_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
 			.color_two_side = ctx->rasterizer->light_twoside,
 			.vclamp_color = ctx->rasterizer->clamp_vertex_color,
 			.fclamp_color = ctx->rasterizer->clamp_fragment_color,
-			.half_precision = ctx->in_blit &&
+			.half_precision = ctx->in_discard_blit &&
 					fd_half_precision(&ctx->batch->framebuffer),
 			.has_per_samp = (fd3_ctx->fsaturate || fd3_ctx->vsaturate),
 			.vsaturate_s = fd3_ctx->vsaturate_s,
@@ -141,7 +141,7 @@ fd3_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
 		.sprite_coord_mode = ctx->rasterizer->sprite_coord_mode,
 	};
 
-	if (fd3_needs_manual_clipping(ctx->prog.vp, ctx->rasterizer))
+	if (fd3_needs_manual_clipping(ctx->prog.vs, ctx->rasterizer))
 		emit.key.ucp_enables = ctx->rasterizer->clip_plane_enable;
 
 	fixup_shader_state(ctx, &emit.key);
@@ -165,8 +165,8 @@ fd3_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
 	/* and now binning pass: */
 	emit.binning_pass = true;
 	emit.dirty = dirty & ~(FD_DIRTY_BLEND);
-	emit.vp = NULL;   /* we changed key so need to refetch vp */
-	emit.fp = NULL;
+	emit.vs = NULL;   /* we changed key so need to refetch vs */
+	emit.fs = NULL;
 	draw_impl(ctx, ctx->batch->binning, &emit, index_offset);
 
 	fd_context_all_clean(ctx);
diff --git a/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_emit.c b/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
index a966934fe..ee75455c2 100644
--- a/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
+++ b/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
@@ -28,7 +28,7 @@
 #include "util/u_string.h"
 #include "util/u_memory.h"
 #include "util/u_helpers.h"
-#include "util/u_format.h"
+#include "util/format/u_format.h"
 #include "util/u_viewport.h"
 
 #include "freedreno_resource.h"
@@ -215,8 +215,7 @@ emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
 				unsigned end   = fd_sampler_last_level(&view->base);
 
 				for (j = 0; j < (end - start + 1); j++) {
-					struct fd_resource_slice *slice =
-						fd_resource_slice(rsc, j + start);
+					struct fdl_slice *slice = fd_resource_slice(rsc, j + start);
 					OUT_RELOC(ring, rsc->bo, slice->offset, 0, 0);
 				}
 			}
@@ -311,18 +310,19 @@ fd3_emit_gmem_restore_tex(struct fd_ringbuffer *ring,
 
 		/* note: PIPE_BUFFER disallowed for surfaces */
 		unsigned lvl = psurf[i]->u.tex.level;
-		struct fd_resource_slice *slice = fd_resource_slice(rsc, lvl);
+		struct fdl_slice *slice = fd_resource_slice(rsc, lvl);
 
 		debug_assert(psurf[i]->u.tex.first_layer == psurf[i]->u.tex.last_layer);
 
-		OUT_RING(ring, A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(format)) |
+		OUT_RING(ring, A3XX_TEX_CONST_0_TILE_MODE(rsc->layout.tile_mode) |
+				 A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(format)) |
 				 A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D) |
 				 fd3_tex_swiz(format,  PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y,
 							  PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W));
 		OUT_RING(ring, A3XX_TEX_CONST_1_FETCHSIZE(TFETCH_DISABLE) |
 				 A3XX_TEX_CONST_1_WIDTH(psurf[i]->width) |
 				 A3XX_TEX_CONST_1_HEIGHT(psurf[i]->height));
-		OUT_RING(ring, A3XX_TEX_CONST_2_PITCH(slice->pitch * rsc->cpp) |
+		OUT_RING(ring, A3XX_TEX_CONST_2_PITCH(slice->pitch) |
 				 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
 		OUT_RING(ring, 0x00000000);
 	}
@@ -372,9 +372,6 @@ fd3_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd3_emit *emit)
 			continue;
 		if (vp->inputs[i].sysval) {
 			switch(vp->inputs[i].slot) {
-			case SYSTEM_VALUE_FIRST_VERTEX:
-				/* handled elsewhere */
-				break;
 			case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
 				vertex_regid = vp->inputs[i].regid;
 				break;
@@ -440,7 +437,7 @@ fd3_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd3_emit *emit)
 					COND(isint, A3XX_VFD_DECODE_INSTR_INT) |
 					COND(switchnext, A3XX_VFD_DECODE_INSTR_SWITCHNEXT));
 
-			total_in += vp->inputs[i].ncomp;
+			total_in += util_bitcount(vp->inputs[i].compmask);
 			j++;
 		}
 	}
@@ -738,7 +735,6 @@ fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
 			bool is_int = util_format_is_pure_integer(format);
 			bool has_alpha = util_format_has_alpha(format);
 			uint32_t control = blend->rb_mrt[i].control;
-			uint32_t blend_control = blend->rb_mrt[i].blend_control_alpha;
 
 			if (is_int) {
 				control &= (A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK |
@@ -749,10 +745,7 @@ fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
 			if (format == PIPE_FORMAT_NONE)
 				control &= ~A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
 
-			if (has_alpha) {
-				blend_control |= blend->rb_mrt[i].blend_control_rgb;
-			} else {
-				blend_control |= blend->rb_mrt[i].blend_control_no_alpha_rgb;
+			if (!has_alpha) {
 				control &= ~A3XX_RB_MRT_CONTROL_BLEND2;
 			}
 
@@ -772,7 +765,7 @@ fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
 			OUT_RING(ring, control);
 
 			OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
-			OUT_RING(ring, blend_control |
+			OUT_RING(ring, blend->rb_mrt[i].blend_control |
 					COND(!is_float, A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE));
 		}
 	}
diff --git a/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_emit.h b/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_emit.h
index 88a3692ef..7a905628d 100644
--- a/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_emit.h
+++ b/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_emit.h
@@ -54,35 +54,35 @@ struct fd3_emit {
 	bool rasterflat;
 
 	/* cached to avoid repeated lookups of same variants: */
-	const struct ir3_shader_variant *vp, *fp;
+	const struct ir3_shader_variant *vs, *fs;
 };
 
 static inline const struct ir3_shader_variant *
 fd3_emit_get_vp(struct fd3_emit *emit)
 {
-	if (!emit->vp) {
-		struct ir3_shader *shader = emit->prog->vp;
-		emit->vp = ir3_shader_variant(shader, emit->key,
+	if (!emit->vs) {
+		struct ir3_shader *shader = emit->prog->vs;
+		emit->vs = ir3_shader_variant(shader, emit->key,
 				emit->binning_pass, emit->debug);
 	}
-	return emit->vp;
+	return emit->vs;
 }
 
 static inline const struct ir3_shader_variant *
 fd3_emit_get_fp(struct fd3_emit *emit)
 {
-	if (!emit->fp) {
+	if (!emit->fs) {
 		if (emit->binning_pass) {
 			/* use dummy stateobj to simplify binning vs non-binning: */
-			static const struct ir3_shader_variant binning_fp = {};
-			emit->fp = &binning_fp;
+			static const struct ir3_shader_variant binning_fs = {};
+			emit->fs = &binning_fs;
 		} else {
-			struct ir3_shader *shader = emit->prog->fp;
-			emit->fp = ir3_shader_variant(shader, emit->key,
+			struct ir3_shader *shader = emit->prog->fs;
+			emit->fs = ir3_shader_variant(shader, emit->key,
 					false, emit->debug);
 		}
 	}
-	return emit->fp;
+	return emit->fs;
 }
 
 void fd3_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd3_emit *emit);
diff --git a/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_format.c b/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_format.c
index 0012b81e4..b5a5bb1bf 100644
--- a/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_format.c
+++ b/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_format.c
@@ -23,7 +23,7 @@
  */
 
 #include "pipe/p_defines.h"
-#include "util/u_format.h"
+#include "util/format/u_format.h"
 
 #include "fd3_format.h"
 
@@ -75,10 +75,10 @@ static struct fd3_format formats[PIPE_FORMAT_COUNT] = {
 	/* 8-bit */
 	VT(R8_UNORM,   8_UNORM, R8_UNORM, WZYX),
 	VT(R8_SNORM,   8_SNORM, NONE,     WZYX),
-	VT(R8_UINT,    8_UINT,  R8_UINT,  WZYX),
-	VT(R8_SINT,    8_SINT,  R8_SINT,  WZYX),
+	VT(R8_UINT,    8_UINT,  NONE,     WZYX),
+	VT(R8_SINT,    8_SINT,  NONE,     WZYX),
 	V_(R8_USCALED, 8_UINT,  NONE,     WZYX),
-	V_(R8_SSCALED, 8_UINT,  NONE,     WZYX),
+	V_(R8_SSCALED, 8_SINT,  NONE,     WZYX),
 
 	_T(A8_UNORM,   8_UNORM, A8_UNORM, WZYX),
 	_T(L8_UNORM,   8_UNORM, R8_UNORM, WZYX),
@@ -99,7 +99,7 @@ static struct fd3_format formats[PIPE_FORMAT_COUNT] = {
 	VT(R16_UINT,    16_UINT,  R16_UINT, WZYX),
 	VT(R16_SINT,    16_SINT,  R16_SINT, WZYX),
 	V_(R16_USCALED, 16_UINT,  NONE,     WZYX),
-	V_(R16_SSCALED, 16_UINT,  NONE,     WZYX),
+	V_(R16_SSCALED, 16_SINT,  NONE,     WZYX),
 	VT(R16_FLOAT,   16_FLOAT, R16_FLOAT,WZYX),
 
 	_T(A16_UINT,    16_UINT,  NONE,     WZYX),
@@ -111,8 +111,8 @@ static struct fd3_format formats[PIPE_FORMAT_COUNT] = {
 
 	VT(R8G8_UNORM,   8_8_UNORM, R8G8_UNORM, WZYX),
 	VT(R8G8_SNORM,   8_8_SNORM, R8G8_SNORM, WZYX),
-	VT(R8G8_UINT,    8_8_UINT,  NONE,       WZYX),
-	VT(R8G8_SINT,    8_8_SINT,  NONE,       WZYX),
+	VT(R8G8_UINT,    8_8_UINT,  R8G8_UINT,  WZYX),
+	VT(R8G8_SINT,    8_8_SINT,  R8G8_SINT,  WZYX),
 	V_(R8G8_USCALED, 8_8_UINT,  NONE,       WZYX),
 	V_(R8G8_SSCALED, 8_8_SINT,  NONE,       WZYX),
 
@@ -137,7 +137,7 @@ static struct fd3_format formats[PIPE_FORMAT_COUNT] = {
 	VT(R32_UINT,    32_UINT,  R32_UINT, WZYX),
 	VT(R32_SINT,    32_SINT,  R32_SINT, WZYX),
 	V_(R32_USCALED, 32_UINT,  NONE,     WZYX),
-	V_(R32_SSCALED, 32_UINT,  NONE,     WZYX),
+	V_(R32_SSCALED, 32_SINT,  NONE,     WZYX),
 	VT(R32_FLOAT,   32_FLOAT, R32_FLOAT,WZYX),
 	V_(R32_FIXED,   32_FIXED, NONE,     WZYX),
 
@@ -189,7 +189,7 @@ static struct fd3_format formats[PIPE_FORMAT_COUNT] = {
 	_T(B10G10R10X2_UNORM,   10_10_10_2_UNORM, R10G10B10A2_UNORM, WXYZ),
 	V_(R10G10B10A2_SNORM,   10_10_10_2_SNORM, NONE,              WZYX),
 	V_(B10G10R10A2_SNORM,   10_10_10_2_SNORM, NONE,              WXYZ),
-	V_(R10G10B10A2_UINT,    10_10_10_2_UINT,  NONE,              WZYX),
+	VT(R10G10B10A2_UINT,    10_10_10_2_UINT,  NONE,              WZYX),
 	V_(B10G10R10A2_UINT,    10_10_10_2_UINT,  NONE,              WXYZ),
 	V_(R10G10B10A2_USCALED, 10_10_10_2_UINT,  NONE,              WZYX),
 	V_(B10G10R10A2_USCALED, 10_10_10_2_UINT,  NONE,              WXYZ),
@@ -344,14 +344,6 @@ fd3_pipe2fetchsize(enum pipe_format format)
 	}
 }
 
-unsigned
-fd3_pipe2nblocksx(enum pipe_format format, unsigned width)
-{
-	if (util_format_description(format)->layout == UTIL_FORMAT_LAYOUT_RGTC)
-		format = PIPE_FORMAT_R8G8B8A8_UNORM;
-	return util_format_get_nblocksx(format, width);
-}
-
 enum a3xx_color_fmt
 fd3_fs_output_format(enum pipe_format format)
 {
diff --git a/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_format.h b/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_format.h
index 7286770d8..1e4597242 100644
--- a/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_format.h
+++ b/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_format.h
@@ -25,7 +25,7 @@
 #ifndef FD3_FORMAT_H_
 #define FD3_FORMAT_H_
 
-#include "util/u_format.h"
+#include "util/format/u_format.h"
 #include "freedreno_util.h"
 
 #include "a3xx.xml.h"
@@ -36,7 +36,6 @@ enum a3xx_tex_fetchsize fd3_pipe2fetchsize(enum pipe_format format);
 enum a3xx_color_fmt fd3_pipe2color(enum pipe_format format);
 enum a3xx_color_fmt fd3_fs_output_format(enum pipe_format format);
 enum a3xx_color_swap fd3_pipe2swap(enum pipe_format format);
-unsigned fd3_pipe2nblocksx(enum pipe_format format, unsigned width);
 
 uint32_t fd3_tex_swiz(enum pipe_format format, unsigned swizzle_r,
 		unsigned swizzle_g, unsigned swizzle_b, unsigned swizzle_a);
diff --git a/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c b/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
index 8bb8b681a..a0fc1d3f9 100644
--- a/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
+++ b/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
@@ -28,7 +28,7 @@
 #include "util/u_string.h"
 #include "util/u_memory.h"
 #include "util/u_inlines.h"
-#include "util/u_format.h"
+#include "util/format/u_format.h"
 
 #include "freedreno_draw.h"
 #include "freedreno_state.h"
@@ -43,7 +43,7 @@
 
 static void
 emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
-		 struct pipe_surface **bufs, uint32_t *bases, uint32_t bin_w,
+		 struct pipe_surface **bufs, const uint32_t *bases, uint32_t bin_w,
 		 bool decode_srgb)
 {
 	enum a3xx_tile_mode tile_mode;
@@ -55,7 +55,7 @@ emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
 		enum a3xx_color_swap swap = WZYX;
 		bool srgb = false;
 		struct fd_resource *rsc = NULL;
-		struct fd_resource_slice *slice = NULL;
+		struct fdl_slice *slice = NULL;
 		uint32_t stride = 0;
 		uint32_t base = 0;
 		uint32_t offset = 0;
@@ -91,17 +91,17 @@ emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
 
 			offset = fd_resource_offset(rsc, psurf->u.tex.level,
 					psurf->u.tex.first_layer);
-			swap = rsc->tile_mode ? WZYX : fd3_pipe2swap(pformat);
+			swap = rsc->layout.tile_mode ? WZYX : fd3_pipe2swap(pformat);
 
 			if (bin_w) {
-				stride = bin_w * rsc->cpp;
+				stride = bin_w << fdl_cpp_shift(&rsc->layout);
 
 				if (bases) {
 					base = bases[i];
 				}
 			} else {
-				stride = slice->pitch * rsc->cpp;
-				tile_mode = rsc->tile_mode;
+				stride = slice->pitch;
+				tile_mode = rsc->layout.tile_mode;
 			}
 		} else if (i < nr_bufs && bases) {
 			base = bases[i];
@@ -129,7 +129,7 @@ emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
 static bool
 use_hw_binning(struct fd_batch *batch)
 {
-	struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
+	const struct fd_gmem_stateobj *gmem = batch->gmem_state;
 
 	/* workaround: combining scissor optimization and hw binning
 	 * seems problematic.  Seems like we end up with a mismatch
@@ -163,7 +163,7 @@ static void
 emit_binning_workaround(struct fd_batch *batch)
 {
 	struct fd_context *ctx = batch->ctx;
-	struct fd_gmem_stateobj *gmem = &ctx->gmem;
+	const struct fd_gmem_stateobj *gmem = batch->gmem_state;
 	struct fd_ringbuffer *ring = batch->gmem;
 	struct fd3_emit emit = {
 			.debug = &ctx->debug,
@@ -330,7 +330,7 @@ emit_gmem2mem_surf(struct fd_batch *batch,
 		format = rsc->base.format;
 	}
 
-	struct fd_resource_slice *slice = fd_resource_slice(rsc, psurf->u.tex.level);
+	struct fdl_slice *slice = fd_resource_slice(rsc, psurf->u.tex.level);
 	uint32_t offset = fd_resource_offset(rsc, psurf->u.tex.level,
 			psurf->u.tex.first_layer);
 
@@ -345,8 +345,8 @@ emit_gmem2mem_surf(struct fd_batch *batch,
 				 A3XX_RB_COPY_CONTROL_DEPTH32_RESOLVE));
 
 	OUT_RELOCW(ring, rsc->bo, offset, 0, -1);    /* RB_COPY_DEST_BASE */
-	OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(slice->pitch * rsc->cpp));
-	OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(LINEAR) |
+	OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(slice->pitch));
+	OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(rsc->layout.tile_mode) |
 			A3XX_RB_COPY_DEST_INFO_FORMAT(fd3_pipe2color(format)) |
 			A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
 			A3XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE) |
@@ -357,10 +357,11 @@ emit_gmem2mem_surf(struct fd_batch *batch,
 }
 
 static void
-fd3_emit_tile_gmem2mem(struct fd_batch *batch, struct fd_tile *tile)
+fd3_emit_tile_gmem2mem(struct fd_batch *batch, const struct fd_tile *tile)
 {
 	struct fd_context *ctx = batch->ctx;
 	struct fd_ringbuffer *ring = batch->gmem;
+	const struct fd_gmem_stateobj *gmem = batch->gmem_state;
 	struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 	struct fd3_emit emit = {
 			.debug = &ctx->debug,
@@ -419,7 +420,7 @@ fd3_emit_tile_gmem2mem(struct fd_batch *batch, struct fd_tile *tile)
 	OUT_RING(ring, A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
 			A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
 			A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
-			A3XX_RB_RENDER_CONTROL_BIN_WIDTH(ctx->gmem.bin_w));
+			A3XX_RB_RENDER_CONTROL_BIN_WIDTH(batch->gmem_state->bin_w));
 
 	OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
 	OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
@@ -451,10 +452,10 @@ fd3_emit_tile_gmem2mem(struct fd_batch *batch, struct fd_tile *tile)
 		struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
 		if (!rsc->stencil || batch->resolve & FD_BUFFER_DEPTH)
 			emit_gmem2mem_surf(batch, RB_COPY_DEPTH_STENCIL, false,
-							   ctx->gmem.zsbuf_base[0], pfb->zsbuf);
+							   gmem->zsbuf_base[0], pfb->zsbuf);
 		if (rsc->stencil && batch->resolve & FD_BUFFER_STENCIL)
 			emit_gmem2mem_surf(batch, RB_COPY_DEPTH_STENCIL, true,
-							   ctx->gmem.zsbuf_base[1], pfb->zsbuf);
+							   gmem->zsbuf_base[1], pfb->zsbuf);
 	}
 
 	if (batch->resolve & FD_BUFFER_COLOR) {
@@ -464,7 +465,7 @@ fd3_emit_tile_gmem2mem(struct fd_batch *batch, struct fd_tile *tile)
 			if (!(batch->resolve & (PIPE_CLEAR_COLOR0 << i)))
 				continue;
 			emit_gmem2mem_surf(batch, RB_COPY_RESOLVE, false,
-							   ctx->gmem.cbuf_base[i], pfb->cbufs[i]);
+							   gmem->cbuf_base[i], pfb->cbufs[i]);
 		}
 	}
 
@@ -482,7 +483,7 @@ fd3_emit_tile_gmem2mem(struct fd_batch *batch, struct fd_tile *tile)
 /* transfer from system memory to gmem */
 
 static void
-emit_mem2gmem_surf(struct fd_batch *batch, uint32_t bases[],
+emit_mem2gmem_surf(struct fd_batch *batch, const uint32_t bases[],
 		struct pipe_surface **psurf, uint32_t bufs, uint32_t bin_w)
 {
 	struct fd_ringbuffer *ring = batch->gmem;
@@ -512,7 +513,7 @@ emit_mem2gmem_surf(struct fd_batch *batch, uint32_t bases[],
 		OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2);
 		OUT_RING(ring, A3XX_RB_DEPTH_INFO_DEPTH_BASE(bases[0]) |
 				 A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(DEPTHX_32));
-		OUT_RING(ring, A3XX_RB_DEPTH_PITCH(4 * batch->ctx->gmem.bin_w));
+		OUT_RING(ring, A3XX_RB_DEPTH_PITCH(4 * batch->gmem_state->bin_w));
 
 		if (psurf[0]->format == PIPE_FORMAT_Z32_FLOAT) {
 			OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(0), 1);
@@ -538,10 +539,10 @@ emit_mem2gmem_surf(struct fd_batch *batch, uint32_t bases[],
 }
 
 static void
-fd3_emit_tile_mem2gmem(struct fd_batch *batch, struct fd_tile *tile)
+fd3_emit_tile_mem2gmem(struct fd_batch *batch, const struct fd_tile *tile)
 {
 	struct fd_context *ctx = batch->ctx;
-	struct fd_gmem_stateobj *gmem = &ctx->gmem;
+	const struct fd_gmem_stateobj *gmem = batch->gmem_state;
 	struct fd_ringbuffer *ring = batch->gmem;
 	struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 	struct fd3_emit emit = {
@@ -667,7 +668,7 @@ fd3_emit_tile_mem2gmem(struct fd_batch *batch, struct fd_tile *tile)
 
 	if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_COLOR)) {
 		emit.prog = &ctx->blit_prog[pfb->nr_cbufs - 1];
-		emit.fp = NULL;      /* frag shader changed so clear cache */
+		emit.fs = NULL;      /* frag shader changed so clear cache */
 		fd3_program_emit(ring, &emit, pfb->nr_cbufs, pfb->cbufs);
 		emit_mem2gmem_surf(batch, gmem->cbuf_base, pfb->cbufs, pfb->nr_cbufs, bin_w);
 	}
@@ -688,7 +689,7 @@ fd3_emit_tile_mem2gmem(struct fd_batch *batch, struct fd_tile *tile)
 				emit.prog = &ctx->blit_zs;
 			emit.key.half_precision = false;
 		}
-		emit.fp = NULL;      /* frag shader changed so clear cache */
+		emit.fs = NULL;      /* frag shader changed so clear cache */
 		fd3_program_emit(ring, &emit, 1, &pfb->zsbuf);
 		emit_mem2gmem_surf(batch, gmem->zsbuf_base, &pfb->zsbuf, 1, bin_w);
 	}
@@ -738,7 +739,9 @@ fd3_emit_sysmem_prep(struct fd_batch *batch)
 		struct pipe_surface *psurf = pfb->cbufs[i];
 		if (!psurf)
 			continue;
-		pitch = fd_resource(psurf->texture)->slices[psurf->u.tex.level].pitch;
+		struct fd_resource *rsc = fd_resource(psurf->texture);
+		struct fdl_slice *slice = fd_resource_slice(rsc, psurf->u.tex.level);
+		pitch = slice->pitch / rsc->layout.cpp;
 	}
 
 	fd3_emit_restore(batch, ring);
@@ -774,6 +777,7 @@ static void
 update_vsc_pipe(struct fd_batch *batch)
 {
 	struct fd_context *ctx = batch->ctx;
+	const struct fd_gmem_stateobj *gmem = batch->gmem_state;
 	struct fd3_context *fd3_ctx = fd3_context(ctx);
 	struct fd_ringbuffer *ring = batch->gmem;
 	int i;
@@ -782,10 +786,10 @@ update_vsc_pipe(struct fd_batch *batch)
 	OUT_RELOCW(ring, fd3_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS */
 
 	for (i = 0; i < 8; i++) {
-		struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[i];
+		const struct fd_vsc_pipe *pipe = &gmem->vsc_pipe[i];
 
-		if (!pipe->bo) {
-			pipe->bo = fd_bo_new(ctx->dev, 0x40000,
+		if (!ctx->vsc_pipe_bo[i]) {
+			ctx->vsc_pipe_bo[i] = fd_bo_new(ctx->dev, 0x40000,
 					DRM_FREEDRENO_GEM_TYPE_KMEM, "vsc_pipe[%u]", i);
 		}
 
@@ -794,8 +798,8 @@ update_vsc_pipe(struct fd_batch *batch)
 				A3XX_VSC_PIPE_CONFIG_Y(pipe->y) |
 				A3XX_VSC_PIPE_CONFIG_W(pipe->w) |
 				A3XX_VSC_PIPE_CONFIG_H(pipe->h));
-		OUT_RELOCW(ring, pipe->bo, 0, 0, 0);       /* VSC_PIPE[i].DATA_ADDRESS */
-		OUT_RING(ring, fd_bo_size(pipe->bo) - 32); /* VSC_PIPE[i].DATA_LENGTH */
+		OUT_RELOCW(ring, ctx->vsc_pipe_bo[i], 0, 0, 0);       /* VSC_PIPE[i].DATA_ADDRESS */
+		OUT_RING(ring, fd_bo_size(ctx->vsc_pipe_bo[i]) - 32); /* VSC_PIPE[i].DATA_LENGTH */
 	}
 }
 
@@ -803,7 +807,7 @@ static void
 emit_binning_pass(struct fd_batch *batch)
 {
 	struct fd_context *ctx = batch->ctx;
-	struct fd_gmem_stateobj *gmem = &ctx->gmem;
+	const struct fd_gmem_stateobj *gmem = batch->gmem_state;
 	struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 	struct fd_ringbuffer *ring = batch->gmem;
 	int i;
@@ -932,7 +936,7 @@ fd3_emit_tile_init(struct fd_batch *batch)
 {
 	struct fd_ringbuffer *ring = batch->gmem;
 	struct pipe_framebuffer_state *pfb = &batch->framebuffer;
-	struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
+	const struct fd_gmem_stateobj *gmem = batch->gmem_state;
 	uint32_t rb_render_control;
 
 	fd3_emit_restore(batch, ring);
@@ -968,7 +972,7 @@ fd3_emit_tile_init(struct fd_batch *batch)
 
 /* before mem2gmem */
 static void
-fd3_emit_tile_prep(struct fd_batch *batch, struct fd_tile *tile)
+fd3_emit_tile_prep(struct fd_batch *batch, const struct fd_tile *tile)
 {
 	struct fd_ringbuffer *ring = batch->gmem;
 	struct pipe_framebuffer_state *pfb = &batch->framebuffer;
@@ -981,12 +985,12 @@ fd3_emit_tile_prep(struct fd_batch *batch, struct fd_tile *tile)
 
 /* before IB to rendering cmds: */
 static void
-fd3_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile)
+fd3_emit_tile_renderprep(struct fd_batch *batch, const struct fd_tile *tile)
 {
 	struct fd_context *ctx = batch->ctx;
 	struct fd3_context *fd3_ctx = fd3_context(ctx);
 	struct fd_ringbuffer *ring = batch->gmem;
-	struct fd_gmem_stateobj *gmem = &ctx->gmem;
+	const struct fd_gmem_stateobj *gmem = batch->gmem_state;
 	struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 
 	uint32_t x1 = tile->xoff;
@@ -1004,18 +1008,21 @@ fd3_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile)
 	OUT_RING(ring, reg);
 	if (pfb->zsbuf) {
 		struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
-		OUT_RING(ring, A3XX_RB_DEPTH_PITCH(rsc->cpp * gmem->bin_w));
+		OUT_RING(ring, A3XX_RB_DEPTH_PITCH(gmem->bin_w <<
+						fdl_cpp_shift(&rsc->layout)));
 		if (rsc->stencil) {
 			OUT_PKT0(ring, REG_A3XX_RB_STENCIL_INFO, 2);
 			OUT_RING(ring, A3XX_RB_STENCIL_INFO_STENCIL_BASE(gmem->zsbuf_base[1]));
-			OUT_RING(ring, A3XX_RB_STENCIL_PITCH(rsc->stencil->cpp * gmem->bin_w));
+			OUT_RING(ring, A3XX_RB_STENCIL_PITCH(gmem->bin_w <<
+							fdl_cpp_shift(&rsc->stencil->layout)));
 		}
 	} else {
 		OUT_RING(ring, 0x00000000);
 	}
 
 	if (use_hw_binning(batch)) {
-		struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[tile->p];
+		const struct fd_vsc_pipe *pipe = &gmem->vsc_pipe[tile->p];
+		struct fd_bo *pipe_bo = ctx->vsc_pipe_bo[tile->p];
 
 		assert(pipe->w && pipe->h);
 
@@ -1028,7 +1035,7 @@ fd3_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile)
 
 
 		OUT_PKT3(ring, CP_SET_BIN_DATA, 2);
-		OUT_RELOCW(ring, pipe->bo, 0, 0, 0);    /* BIN_DATA_ADDR <- VSC_PIPE[p].DATA_ADDRESS */
+		OUT_RELOCW(ring, pipe_bo, 0, 0, 0);     /* BIN_DATA_ADDR <- VSC_PIPE[p].DATA_ADDRESS */
 		OUT_RELOCW(ring, fd3_ctx->vsc_size_mem, /* BIN_SIZE_ADDR <- VSC_SIZE_ADDRESS + (p * 4) */
 				(tile->p * 4), 0, 0);
 	} else {
diff --git a/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_program.c b/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_program.c
index af7f19d59..9ecffcc06 100644
--- a/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_program.c
+++ b/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_program.c
@@ -29,7 +29,7 @@
 #include "util/u_math.h"
 #include "util/u_memory.h"
 #include "util/u_inlines.h"
-#include "util/u_format.h"
+#include "util/format/u_format.h"
 
 #include "freedreno_program.h"
 
@@ -38,43 +38,6 @@
 #include "fd3_texture.h"
 #include "fd3_format.h"
 
-static struct ir3_shader *
-create_shader_stateobj(struct pipe_context *pctx, const struct pipe_shader_state *cso,
-		gl_shader_stage type)
-{
-	struct fd_context *ctx = fd_context(pctx);
-	struct ir3_compiler *compiler = ctx->screen->compiler;
-	return ir3_shader_create(compiler, cso, type, &ctx->debug, pctx->screen);
-}
-
-static void *
-fd3_fp_state_create(struct pipe_context *pctx,
-		const struct pipe_shader_state *cso)
-{
-	return create_shader_stateobj(pctx, cso, MESA_SHADER_FRAGMENT);
-}
-
-static void
-fd3_fp_state_delete(struct pipe_context *pctx, void *hwcso)
-{
-	struct ir3_shader *so = hwcso;
-	ir3_shader_destroy(so);
-}
-
-static void *
-fd3_vp_state_create(struct pipe_context *pctx,
-		const struct pipe_shader_state *cso)
-{
-	return create_shader_stateobj(pctx, cso, MESA_SHADER_VERTEX);
-}
-
-static void
-fd3_vp_state_delete(struct pipe_context *pctx, void *hwcso)
-{
-	struct ir3_shader *so = hwcso;
-	ir3_shader_destroy(so);
-}
-
 bool
 fd3_needs_manual_clipping(const struct ir3_shader *shader,
 						  const struct pipe_rasterizer_state *rast)
@@ -211,7 +174,7 @@ fd3_program_emit(struct fd_ringbuffer *ring, struct fd3_emit *emit,
 	face_regid      = ir3_find_sysval_regid(fp, SYSTEM_VALUE_FRONT_FACE);
 	coord_regid     = ir3_find_sysval_regid(fp, SYSTEM_VALUE_FRAG_COORD);
 	zwcoord_regid   = (coord_regid == regid(63,0)) ? regid(63,0) : (coord_regid + 2);
-	vcoord_regid    = ir3_find_sysval_regid(fp, SYSTEM_VALUE_BARYCENTRIC_PIXEL);
+	vcoord_regid    = ir3_find_sysval_regid(fp, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL);
 
 	/* adjust regids for alpha output formats. there is no alpha render
 	 * format, so it's just treated like red
@@ -274,7 +237,7 @@ fd3_program_emit(struct fd_ringbuffer *ring, struct fd3_emit *emit,
 			A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(fp->varying_in));
 
 	struct ir3_shader_linkage l = {0};
-	ir3_link_shaders(&l, vp, fp);
+	ir3_link_shaders(&l, vp, fp, false);
 
 	for (i = 0, j = 0; (i < 16) && (j < l.cnt); i++) {
 		uint32_t reg = 0;
@@ -335,7 +298,7 @@ fd3_program_emit(struct fd_ringbuffer *ring, struct fd3_emit *emit,
 				A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP |
 				A3XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
 				A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE |
-				COND(fp->num_samp > 0, A3XX_SP_FS_CTRL_REG0_PIXLODENABLE) |
+				COND(fp->need_pixlod, A3XX_SP_FS_CTRL_REG0_PIXLODENABLE) |
 				A3XX_SP_FS_CTRL_REG0_LENGTH(fpbuffersz));
 		OUT_RING(ring, A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(fp->constlen) |
 				A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(fp->total_in) |
@@ -358,7 +321,7 @@ fd3_program_emit(struct fd_ringbuffer *ring, struct fd3_emit *emit,
 	OUT_PKT0(ring, REG_A3XX_SP_FS_MRT_REG(0), 4);
 	for (i = 0; i < 4; i++) {
 		uint32_t mrt_reg = A3XX_SP_FS_MRT_REG_REGID(color_regid[i]) |
-			COND(fp->key.half_precision, A3XX_SP_FS_MRT_REG_HALF_PRECISION);
+			COND(color_regid[i] & HALF_REG_ID, A3XX_SP_FS_MRT_REG_HALF_PRECISION);
 
 		if (i < nr) {
 			enum pipe_format fmt = pipe_surface_format(bufs[i]);
@@ -485,11 +448,6 @@ fd3_program_emit(struct fd_ringbuffer *ring, struct fd3_emit *emit,
 void
 fd3_prog_init(struct pipe_context *pctx)
 {
-	pctx->create_fs_state = fd3_fp_state_create;
-	pctx->delete_fs_state = fd3_fp_state_delete;
-
-	pctx->create_vs_state = fd3_vp_state_create;
-	pctx->delete_vs_state = fd3_vp_state_delete;
-
+	ir3_prog_init(pctx);
 	fd_prog_init(pctx);
 }