Merge Mesa 19.2.8

6 files changed, 33 insertions, 21 deletions

diff --git a/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_context.c b/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_context.c
index 59dcaa4bf..878f67afb 100644
--- a/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_context.c
+++ b/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_context.c
@@ -79,6 +79,7 @@ fd3_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags)
 		return NULL;
 
 	pctx = &fd3_ctx->base.base;
+	pctx->screen = pscreen;
 
 	fd3_ctx->base.dev = fd_device_ref(screen->dev);
 	fd3_ctx->base.screen = fd_screen(pscreen);
diff --git a/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_emit.c b/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
index aa787d5ad..a966934fe 100644
--- a/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
+++ b/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
@@ -552,7 +552,7 @@ fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
 			val |= A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z;
 			val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
 		}
-		if (fp->has_kill) {
+		if (fp->no_earlyz) {
 			val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
 		}
 		if (!ctx->rasterizer->depth_clip_near) {
@@ -945,17 +945,16 @@ fd3_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
 	fd_hw_query_enable(batch, ring);
 }
 
-static void
-fd3_emit_ib(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
+void
+fd3_emit_init_screen(struct pipe_screen *pscreen)
 {
-	__OUT_IB(ring, true, target);
+	struct fd_screen *screen = fd_screen(pscreen);
+	screen->emit_const = fd3_emit_const;
+	screen->emit_const_bo = fd3_emit_const_bo;
+	screen->emit_ib = fd3_emit_ib;
 }
 
 void
 fd3_emit_init(struct pipe_context *pctx)
 {
-	struct fd_context *ctx = fd_context(pctx);
-	ctx->emit_const = fd3_emit_const;
-	ctx->emit_const_bo = fd3_emit_const_bo;
-	ctx->emit_ib = fd3_emit_ib;
 }
diff --git a/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_emit.h b/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_emit.h
index a2270cbe1..88a3692ef 100644
--- a/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_emit.h
+++ b/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_emit.h
@@ -92,9 +92,16 @@ void fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
 
 void fd3_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring);
 
+void fd3_emit_init_screen(struct pipe_screen *pscreen);
 void fd3_emit_init(struct pipe_context *pctx);
 
 static inline void
+fd3_emit_ib(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
+{
+	__OUT_IB(ring, true, target);
+}
+
+static inline void
 fd3_emit_cache_flush(struct fd_batch *batch, struct fd_ringbuffer *ring)
 {
 	fd_wfi(batch, ring);
diff --git a/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_format.c b/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_format.c
index f8508977a..0012b81e4 100644
--- a/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_format.c
+++ b/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_format.c
@@ -285,6 +285,10 @@ static struct fd3_format formats[PIPE_FORMAT_COUNT] = {
 	_T(LATC1_SNORM, 8_8_8_8_SNORM, NONE, WZYX),
 	_T(LATC2_UNORM, 8_8_8_8_UNORM, NONE, WZYX),
 	_T(LATC2_SNORM, 8_8_8_8_SNORM, NONE, WZYX),
+
+	_T(ATC_RGB,               ATC_RGB,               NONE, WZYX),
+	_T(ATC_RGBA_EXPLICIT,     ATC_RGBA_EXPLICIT,     NONE, WZYX),
+	_T(ATC_RGBA_INTERPOLATED, ATC_RGBA_INTERPOLATED, NONE, WZYX),
 };
 
 enum a3xx_vtx_fmt
diff --git a/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c b/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
index 7de0a92cd..8bb8b681a 100644
--- a/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
+++ b/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
@@ -49,12 +49,6 @@ emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
 	enum a3xx_tile_mode tile_mode;
 	unsigned i;
 
-	if (bin_w) {
-		tile_mode = TILE_32X32;
-	} else {
-		tile_mode = LINEAR;
-	}
-
 	for (i = 0; i < A3XX_MAX_RENDER_TARGETS; i++) {
 		enum pipe_format pformat = 0;
 		enum a3xx_color_fmt format = 0;
@@ -66,6 +60,12 @@ emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
 		uint32_t base = 0;
 		uint32_t offset = 0;
 
+		if (bin_w) {
+			tile_mode = TILE_32X32;
+		} else {
+			tile_mode = LINEAR;
+		}
+
 		if ((i < nr_bufs) && bufs[i]) {
 			struct pipe_surface *psurf = bufs[i];
 
@@ -82,7 +82,6 @@ emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
 			}
 			slice = fd_resource_slice(rsc, psurf->u.tex.level);
 			format = fd3_pipe2color(pformat);
-			swap = fd3_pipe2swap(pformat);
 			if (decode_srgb)
 				srgb = util_format_is_srgb(pformat);
 			else
@@ -92,6 +91,7 @@ emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
 
 			offset = fd_resource_offset(rsc, psurf->u.tex.level,
 					psurf->u.tex.first_layer);
+			swap = rsc->tile_mode ? WZYX : fd3_pipe2swap(pformat);
 
 			if (bin_w) {
 				stride = bin_w * rsc->cpp;
@@ -101,6 +101,7 @@ emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
 				}
 			} else {
 				stride = slice->pitch * rsc->cpp;
+				tile_mode = rsc->tile_mode;
 			}
 		} else if (i < nr_bufs && bases) {
 			base = bases[i];
@@ -711,7 +712,7 @@ patch_draws(struct fd_batch *batch, enum pc_di_vis_cull_mode vismode)
 		struct fd_cs_patch *patch = fd_patch_element(&batch->draw_patches, i);
 		*patch->cs = patch->val | DRAW(0, 0, 0, vismode, 0);
 	}
-	util_dynarray_resize(&batch->draw_patches, 0);
+	util_dynarray_clear(&batch->draw_patches);
 }
 
 static void
@@ -722,7 +723,7 @@ patch_rbrc(struct fd_batch *batch, uint32_t val)
 		struct fd_cs_patch *patch = fd_patch_element(&batch->rbrc_patches, i);
 		*patch->cs = patch->val | val;
 	}
-	util_dynarray_resize(&batch->rbrc_patches, 0);
+	util_dynarray_clear(&batch->rbrc_patches);
 }
 
 /* for rendering directly to system memory: */
@@ -867,7 +868,7 @@ emit_binning_pass(struct fd_batch *batch)
 			A3XX_PC_VSTREAM_CONTROL_N(0));
 
 	/* emit IB to binning drawcmds: */
-	ctx->emit_ib(ring, batch->binning);
+	fd3_emit_ib(ring, batch->binning);
 	fd_reset_wfi(batch);
 
 	fd_wfi(batch, ring);
@@ -1016,7 +1017,7 @@ fd3_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile)
 	if (use_hw_binning(batch)) {
 		struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[tile->p];
 
-		assert(pipe->w * pipe->h);
+		assert(pipe->w && pipe->h);
 
 		fd_event_write(batch, ring, HLSQ_FLUSH);
 		fd_wfi(batch, ring);
diff --git a/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_program.c b/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_program.c
index 29371049b..af7f19d59 100644
--- a/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_program.c
+++ b/lib/mesa/src/gallium/drivers/freedreno/a3xx/fd3_program.c
@@ -44,7 +44,7 @@ create_shader_stateobj(struct pipe_context *pctx, const struct pipe_shader_state
 {
 	struct fd_context *ctx = fd_context(pctx);
 	struct ir3_compiler *compiler = ctx->screen->compiler;
-	return ir3_shader_create(compiler, cso, type, &ctx->debug);
+	return ir3_shader_create(compiler, cso, type, &ctx->debug, pctx->screen);
 }
 
 static void *
@@ -211,7 +211,7 @@ fd3_program_emit(struct fd_ringbuffer *ring, struct fd3_emit *emit,
 	face_regid      = ir3_find_sysval_regid(fp, SYSTEM_VALUE_FRONT_FACE);
 	coord_regid     = ir3_find_sysval_regid(fp, SYSTEM_VALUE_FRAG_COORD);
 	zwcoord_regid   = (coord_regid == regid(63,0)) ? regid(63,0) : (coord_regid + 2);
-	vcoord_regid    = ir3_find_sysval_regid(fp, SYSTEM_VALUE_VARYING_COORD);
+	vcoord_regid    = ir3_find_sysval_regid(fp, SYSTEM_VALUE_BARYCENTRIC_PIXEL);
 
 	/* adjust regids for alpha output formats. there is no alpha render
 	 * format, so it's just treated like red