Import Mesa 19.2.8

3 files changed, 225 insertions, 167 deletions

diff --git a/lib/mesa/src/gallium/drivers/freedreno/ir3/ir3_cache.c b/lib/mesa/src/gallium/drivers/freedreno/ir3/ir3_cache.c
index 2de23e498..8e7070a72 100644
--- a/lib/mesa/src/gallium/drivers/freedreno/ir3/ir3_cache.c
+++ b/lib/mesa/src/gallium/drivers/freedreno/ir3/ir3_cache.c
@@ -97,6 +97,10 @@ ir3_cache_lookup(struct ir3_cache *cache, const struct ir3_cache_key *key,
 	struct ir3_shader_variant *vs = ir3_shader_variant(key->vs, key->key, false, debug);
 	struct ir3_shader_variant *fs = ir3_shader_variant(key->fs, key->key, false, debug);
 
+	if (!bs || !vs || !fs) {
+		return NULL;
+	}
+
 	struct ir3_program_state *state =
 		cache->funcs->create_state(cache->data, bs, vs, fs, &key->key);
 	state->key = *key;
diff --git a/lib/mesa/src/gallium/drivers/freedreno/ir3/ir3_gallium.c b/lib/mesa/src/gallium/drivers/freedreno/ir3/ir3_gallium.c
index 7e7b69967..b72e6c754 100644
--- a/lib/mesa/src/gallium/drivers/freedreno/ir3/ir3_gallium.c
+++ b/lib/mesa/src/gallium/drivers/freedreno/ir3/ir3_gallium.c
@@ -25,6 +25,7 @@
  */
 
 #include "pipe/p_state.h"
+#include "pipe/p_screen.h"
 #include "util/u_string.h"
 #include "util/u_memory.h"
 #include "util/u_inlines.h"
@@ -43,31 +44,25 @@
 #include "ir3/ir3_nir.h"
 
 static void
-dump_shader_info(struct ir3_shader_variant *v, struct pipe_debug_callback *debug)
+dump_shader_info(struct ir3_shader_variant *v, bool binning_pass,
+		struct pipe_debug_callback *debug)
 {
 	if (!unlikely(fd_mesa_debug & FD_DBG_SHADERDB))
 		return;
 
-	pipe_debug_message(debug, SHADER_INFO, "\n"
-			"SHADER-DB: %s prog %d/%d: %u instructions, %u dwords\n"
-			"SHADER-DB: %s prog %d/%d: %u half, %u full\n"
-			"SHADER-DB: %s prog %d/%d: %u const, %u constlen\n"
-			"SHADER-DB: %s prog %d/%d: %u (ss), %u (sy)\n",
+	pipe_debug_message(debug, SHADER_INFO,
+			"%s%s shader: %u inst, %u dwords, "
+			"%u half, %u full, %u constlen, "
+			"%u (ss), %u (sy), %d max_sun, %d loops\n",
+			binning_pass ? "B" : "",
 			ir3_shader_stage(v->shader),
-			v->shader->id, v->id,
 			v->info.instrs_count,
 			v->info.sizedwords,
-			ir3_shader_stage(v->shader),
-			v->shader->id, v->id,
 			v->info.max_half_reg + 1,
 			v->info.max_reg + 1,
-			ir3_shader_stage(v->shader),
-			v->shader->id, v->id,
-			v->info.max_const + 1,
 			v->constlen,
-			ir3_shader_stage(v->shader),
-			v->shader->id, v->id,
-			v->info.ss, v->info.sy);
+			v->info.ss, v->info.sy,
+			v->max_sun, v->loops);
 }
 
 struct ir3_shader_variant *
@@ -86,7 +81,7 @@ ir3_shader_variant(struct ir3_shader *shader, struct ir3_shader_key key,
 	v = ir3_shader_get_variant(shader, &key, binning_pass, &created);
 
 	if (created) {
-		dump_shader_info(v, debug);
+		dump_shader_info(v, binning_pass, debug);
 	}
 
 	return v;
@@ -116,7 +111,8 @@ copy_stream_out(struct ir3_stream_output_info *i,
 struct ir3_shader *
 ir3_shader_create(struct ir3_compiler *compiler,
 		const struct pipe_shader_state *cso, gl_shader_stage type,
-		struct pipe_debug_callback *debug)
+		struct pipe_debug_callback *debug,
+		struct pipe_screen *screen)
 {
 	nir_shader *nir;
 	if (cso->type == PIPE_SHADER_IR_NIR) {
@@ -127,7 +123,7 @@ ir3_shader_create(struct ir3_compiler *compiler,
 		if (ir3_shader_debug & IR3_DBG_DISASM) {
 			tgsi_dump(cso->tokens, 0);
 		}
-		nir = ir3_tgsi_to_nir(compiler, cso->tokens);
+		nir = tgsi_to_nir(cso->tokens, screen);
 	}
 
 	struct ir3_shader *shader = ir3_shader_from_nir(compiler, nir);
@@ -139,9 +135,11 @@ ir3_shader_create(struct ir3_compiler *compiler,
 		 * (as otherwise nothing will trigger the shader to be
 		 * actually compiled)
 		 */
-		static struct ir3_shader_key key;
-		memset(&key, 0, sizeof(key));
+		static struct ir3_shader_key key; /* static is implicitly zeroed */
 		ir3_shader_variant(shader, key, false, debug);
+
+		if (nir->info.stage != MESA_SHADER_FRAGMENT)
+			ir3_shader_variant(shader, key, true, debug);
 	}
 	return shader;
 }
@@ -152,7 +150,8 @@ ir3_shader_create(struct ir3_compiler *compiler,
 struct ir3_shader *
 ir3_shader_create_compute(struct ir3_compiler *compiler,
 		const struct pipe_compute_state *cso,
-		struct pipe_debug_callback *debug)
+		struct pipe_debug_callback *debug,
+		struct pipe_screen *screen)
 {
 	nir_shader *nir;
 	if (cso->ir_type == PIPE_SHADER_IR_NIR) {
@@ -163,7 +162,7 @@ ir3_shader_create_compute(struct ir3_compiler *compiler,
 		if (ir3_shader_debug & IR3_DBG_DISASM) {
 			tgsi_dump(cso->prog, 0);
 		}
-		nir = ir3_tgsi_to_nir(compiler, cso->prog);
+		nir = tgsi_to_nir(cso->prog, screen);
 	}
 
 	struct ir3_shader *shader = ir3_shader_from_nir(compiler, nir);
@@ -171,12 +170,6 @@ ir3_shader_create_compute(struct ir3_compiler *compiler,
 	return shader;
 }
 
-struct nir_shader *
-ir3_tgsi_to_nir(struct ir3_compiler *compiler, const struct tgsi_token *tokens)
-{
-	return tgsi_to_nir(tokens, ir3_get_compiler_options(compiler));
-}
-
 /* This has to reach into the fd_context a bit more than the rest of
  * ir3, but it needs to be aligned with the compiler, so both agree
  * on which const regs hold what.  And the logic is identical between
@@ -207,47 +200,60 @@ ring_wfi(struct fd_batch *batch, struct fd_ringbuffer *ring)
 }
 
 static void
-emit_user_consts(struct fd_context *ctx, const struct ir3_shader_variant *v,
+emit_const(struct fd_screen *screen, struct fd_ringbuffer *ring,
+		const struct ir3_shader_variant *v, uint32_t dst_offset,
+		uint32_t offset, uint32_t size,
+		const void *user_buffer, struct pipe_resource *buffer)
+{
+	assert(dst_offset + size <= v->constlen * 4);
+
+	screen->emit_const(ring, v->type, dst_offset,
+			offset, size, user_buffer, buffer);
+}
+
+void
+ir3_emit_user_consts(struct fd_screen *screen, const struct ir3_shader_variant *v,
 		struct fd_ringbuffer *ring, struct fd_constbuf_stateobj *constbuf)
 {
-	const unsigned index = 0;     /* user consts are index 0 */
+	struct ir3_ubo_analysis_state *state;
+	state = &v->shader->ubo_state;
 
-	if (constbuf->enabled_mask & (1 << index)) {
-		struct pipe_constant_buffer *cb = &constbuf->cb[index];
-		unsigned size = align(cb->buffer_size, 4) / 4; /* size in dwords */
+	for (uint32_t i = 0; i < ARRAY_SIZE(state->range); i++) {
+		struct pipe_constant_buffer *cb = &constbuf->cb[i];
 
-		/* in particular, with binning shader we may end up with
-		 * unused consts, ie. we could end up w/ constlen that is
-		 * smaller than first_driver_param.  In that case truncate
-		 * the user consts early to avoid HLSQ lockup caused by
-		 * writing too many consts
-		 */
-		uint32_t max_const = MIN2(v->num_uniforms, v->constlen);
+		if (state->range[i].start < state->range[i].end &&
+			constbuf->enabled_mask & (1 << i)) {
 
-		// I expect that size should be a multiple of vec4's:
-		assert(size == align(size, 4));
+			uint32_t size = state->range[i].end - state->range[i].start;
+			uint32_t offset = cb->buffer_offset + state->range[i].start;
 
-		/* and even if the start of the const buffer is before
-		 * first_immediate, the end may not be:
-		 */
-		size = MIN2(size, 4 * max_const);
+			/* and even if the start of the const buffer is before
+			 * first_immediate, the end may not be:
+			 */
+			size = MIN2(size, (16 * v->constlen) - state->range[i].offset);
+
+			if (size == 0)
+				continue;
+
+			/* things should be aligned to vec4: */
+			debug_assert((state->range[i].offset % 16) == 0);
+			debug_assert((size % 16) == 0);
+			debug_assert((offset % 16) == 0);
 
-		if (size > 0) {
-			ring_wfi(ctx->batch, ring);
-			ctx->emit_const(ring, v->type, 0,
-					cb->buffer_offset, size,
-					cb->user_buffer, cb->buffer);
+			emit_const(screen, ring, v, state->range[i].offset / 4,
+							offset, size / 4, cb->user_buffer, cb->buffer);
 		}
 	}
 }
 
-static void
-emit_ubos(struct fd_context *ctx, const struct ir3_shader_variant *v,
+void
+ir3_emit_ubos(struct fd_screen *screen, const struct ir3_shader_variant *v,
 		struct fd_ringbuffer *ring, struct fd_constbuf_stateobj *constbuf)
 {
-	uint32_t offset = v->constbase.ubo;
+	const struct ir3_const_state *const_state = &v->shader->const_state;
+	uint32_t offset = const_state->offsets.ubo;
 	if (v->constlen > offset) {
-		uint32_t params = v->num_ubos;
+		uint32_t params = const_state->num_ubos;
 		uint32_t offsets[params];
 		struct pipe_resource *prscs[params];
 
@@ -265,46 +271,48 @@ emit_ubos(struct fd_context *ctx, const struct ir3_shader_variant *v,
 			}
 		}
 
-		ring_wfi(ctx->batch, ring);
-		ctx->emit_const_bo(ring, v->type, false, offset * 4, params, prscs, offsets);
+		assert(offset * 4 + params < v->constlen * 4);
+
+		screen->emit_const_bo(ring, v->type, false, offset * 4, params, prscs, offsets);
 	}
 }
 
-static void
-emit_ssbo_sizes(struct fd_context *ctx, const struct ir3_shader_variant *v,
+void
+ir3_emit_ssbo_sizes(struct fd_screen *screen, const struct ir3_shader_variant *v,
 		struct fd_ringbuffer *ring, struct fd_shaderbuf_stateobj *sb)
 {
-	uint32_t offset = v->constbase.ssbo_sizes;
+	const struct ir3_const_state *const_state = &v->shader->const_state;
+	uint32_t offset = const_state->offsets.ssbo_sizes;
 	if (v->constlen > offset) {
-		uint32_t sizes[align(v->const_layout.ssbo_size.count, 4)];
-		unsigned mask = v->const_layout.ssbo_size.mask;
+		uint32_t sizes[align(const_state->ssbo_size.count, 4)];
+		unsigned mask = const_state->ssbo_size.mask;
 
 		while (mask) {
 			unsigned index = u_bit_scan(&mask);
-			unsigned off = v->const_layout.ssbo_size.off[index];
+			unsigned off = const_state->ssbo_size.off[index];
 			sizes[off] = sb->sb[index].buffer_size;
 		}
 
-		ring_wfi(ctx->batch, ring);
-		ctx->emit_const(ring, v->type, offset * 4,
+		emit_const(screen, ring, v, offset * 4,
 			0, ARRAY_SIZE(sizes), sizes, NULL);
 	}
 }
 
-static void
-emit_image_dims(struct fd_context *ctx, const struct ir3_shader_variant *v,
+void
+ir3_emit_image_dims(struct fd_screen *screen, const struct ir3_shader_variant *v,
 		struct fd_ringbuffer *ring, struct fd_shaderimg_stateobj *si)
 {
-	uint32_t offset = v->constbase.image_dims;
+	const struct ir3_const_state *const_state = &v->shader->const_state;
+	uint32_t offset = const_state->offsets.image_dims;
 	if (v->constlen > offset) {
-		uint32_t dims[align(v->const_layout.image_dims.count, 4)];
-		unsigned mask = v->const_layout.image_dims.mask;
+		uint32_t dims[align(const_state->image_dims.count, 4)];
+		unsigned mask = const_state->image_dims.mask;
 
 		while (mask) {
 			struct pipe_image_view *img;
 			struct fd_resource *rsc;
 			unsigned index = u_bit_scan(&mask);
-			unsigned off = v->const_layout.image_dims.off[index];
+			unsigned off = const_state->image_dims.off[index];
 
 			img = &si->si[index];
 			rsc = fd_resource(img->resource);
@@ -336,19 +344,19 @@ emit_image_dims(struct fd_context *ctx, const struct ir3_shader_variant *v,
 				dims[off + 1] = ffs(dims[off + 0]) - 1;
 			}
 		}
+		uint32_t size = MIN2(ARRAY_SIZE(dims), v->constlen * 4 - offset * 4);
 
-		ring_wfi(ctx->batch, ring);
-		ctx->emit_const(ring, v->type, offset * 4,
-			0, ARRAY_SIZE(dims), dims, NULL);
+		emit_const(screen, ring, v, offset * 4, 0, size, dims, NULL);
 	}
 }
 
-static void
-emit_immediates(struct fd_context *ctx, const struct ir3_shader_variant *v,
+void
+ir3_emit_immediates(struct fd_screen *screen, const struct ir3_shader_variant *v,
 		struct fd_ringbuffer *ring)
 {
-	int size = v->immediates_count;
-	uint32_t base = v->constbase.immediate;
+	const struct ir3_const_state *const_state = &v->shader->const_state;
+	uint32_t base = const_state->offsets.immediate;
+	int size = const_state->immediates_count;
 
 	/* truncate size to avoid writing constants that shader
 	 * does not use:
@@ -360,9 +368,8 @@ emit_immediates(struct fd_context *ctx, const struct ir3_shader_variant *v,
 	size *= 4;
 
 	if (size > 0) {
-		ring_wfi(ctx->batch, ring);
-		ctx->emit_const(ring, v->type, base,
-			0, size, v->immediates[0].val, NULL);
+		emit_const(screen, ring, v, base,
+			0, size, const_state->immediates[0].val, NULL);
 	}
 }
 
@@ -372,7 +379,8 @@ emit_tfbos(struct fd_context *ctx, const struct ir3_shader_variant *v,
 		struct fd_ringbuffer *ring)
 {
 	/* streamout addresses after driver-params: */
-	uint32_t offset = v->constbase.tfbo;
+	const struct ir3_const_state *const_state = &v->shader->const_state;
+	uint32_t offset = const_state->offsets.tfbo;
 	if (v->constlen > offset) {
 		struct fd_streamout_stateobj *so = &ctx->streamout;
 		struct ir3_stream_output_info *info = &v->shader->stream_output;
@@ -393,8 +401,9 @@ emit_tfbos(struct fd_context *ctx, const struct ir3_shader_variant *v,
 			}
 		}
 
-		ring_wfi(ctx->batch, ring);
-		ctx->emit_const_bo(ring, v->type, true, offset * 4, params, prscs, offsets);
+		assert(offset * 4 + params < v->constlen * 4);
+
+		ctx->screen->emit_const_bo(ring, v->type, true, offset * 4, params, prscs, offsets);
 	}
 }
 
@@ -471,106 +480,119 @@ emit_common_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *rin
 		constbuf = &ctx->constbuf[t];
 		shader_dirty = !!(dirty & FD_DIRTY_SHADER_PROG);
 
-		emit_user_consts(ctx, v, ring, constbuf);
-		emit_ubos(ctx, v, ring, constbuf);
+		ring_wfi(ctx->batch, ring);
+
+		ir3_emit_user_consts(ctx->screen, v, ring, constbuf);
+		ir3_emit_ubos(ctx->screen, v, ring, constbuf);
 		if (shader_dirty)
-			emit_immediates(ctx, v, ring);
+			ir3_emit_immediates(ctx->screen, v, ring);
 	}
 
 	if (dirty & (FD_DIRTY_SHADER_PROG | FD_DIRTY_SHADER_SSBO)) {
 		struct fd_shaderbuf_stateobj *sb = &ctx->shaderbuf[t];
-		emit_ssbo_sizes(ctx, v, ring, sb);
+		ring_wfi(ctx->batch, ring);
+		ir3_emit_ssbo_sizes(ctx->screen, v, ring, sb);
 	}
 
 	if (dirty & (FD_DIRTY_SHADER_PROG | FD_DIRTY_SHADER_IMAGE)) {
 		struct fd_shaderimg_stateobj *si = &ctx->shaderimg[t];
-		emit_image_dims(ctx, v, ring, si);
+		ring_wfi(ctx->batch, ring);
+		ir3_emit_image_dims(ctx->screen, v, ring, si);
 	}
 }
 
 void
-ir3_emit_vs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
-		struct fd_context *ctx, const struct pipe_draw_info *info)
+ir3_emit_vs_driver_params(const struct ir3_shader_variant *v,
+		struct fd_ringbuffer *ring, struct fd_context *ctx,
+		const struct pipe_draw_info *info)
 {
-	debug_assert(v->type == MESA_SHADER_VERTEX);
-
-	emit_common_consts(v, ring, ctx, PIPE_SHADER_VERTEX);
-
-	/* emit driver params every time: */
-	/* TODO skip emit if shader doesn't use driver params to avoid WFI.. */
-	if (info) {
-		uint32_t offset = v->constbase.driver_param;
-		if (v->constlen > offset) {
-			uint32_t vertex_params[IR3_DP_VS_COUNT] = {
-				[IR3_DP_VTXID_BASE] = info->index_size ?
-						info->index_bias : info->start,
-				[IR3_DP_VTXCNT_MAX] = max_tf_vtx(ctx, v),
-			};
-			/* if no user-clip-planes, we don't need to emit the
-			 * entire thing:
-			 */
-			uint32_t vertex_params_size = 4;
-
-			if (v->key.ucp_enables) {
-				struct pipe_clip_state *ucp = &ctx->ucp;
-				unsigned pos = IR3_DP_UCP0_X;
-				for (unsigned i = 0; pos <= IR3_DP_UCP7_W; i++) {
-					for (unsigned j = 0; j < 4; j++) {
-						vertex_params[pos] = fui(ucp->ucp[i][j]);
-						pos++;
-					}
-				}
-				vertex_params_size = ARRAY_SIZE(vertex_params);
+	debug_assert(ir3_needs_vs_driver_params(v));
+
+	const struct ir3_const_state *const_state = &v->shader->const_state;
+	uint32_t offset = const_state->offsets.driver_param;
+	uint32_t vertex_params[IR3_DP_VS_COUNT] = {
+			[IR3_DP_VTXID_BASE] = info->index_size ?
+					info->index_bias : info->start,
+					[IR3_DP_VTXCNT_MAX] = max_tf_vtx(ctx, v),
+	};
+	/* if no user-clip-planes, we don't need to emit the
+	 * entire thing:
+	 */
+	uint32_t vertex_params_size = 4;
+
+	if (v->key.ucp_enables) {
+		struct pipe_clip_state *ucp = &ctx->ucp;
+		unsigned pos = IR3_DP_UCP0_X;
+		for (unsigned i = 0; pos <= IR3_DP_UCP7_W; i++) {
+			for (unsigned j = 0; j < 4; j++) {
+				vertex_params[pos] = fui(ucp->ucp[i][j]);
+				pos++;
 			}
+		}
+		vertex_params_size = ARRAY_SIZE(vertex_params);
+	}
 
-			ring_wfi(ctx->batch, ring);
+	vertex_params_size = MAX2(vertex_params_size, const_state->num_driver_params);
 
-			bool needs_vtxid_base =
-				ir3_find_sysval_regid(v, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) != regid(63, 0);
+	bool needs_vtxid_base =
+		ir3_find_sysval_regid(v, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) != regid(63, 0);
 
-			/* for indirect draw, we need to copy VTXID_BASE from
-			 * indirect-draw parameters buffer.. which is annoying
-			 * and means we can't easily emit these consts in cmd
-			 * stream so need to copy them to bo.
-			 */
-			if (info->indirect && needs_vtxid_base) {
-				struct pipe_draw_indirect_info *indirect = info->indirect;
-				struct pipe_resource *vertex_params_rsc =
-					pipe_buffer_create(&ctx->screen->base,
+	/* for indirect draw, we need to copy VTXID_BASE from
+	 * indirect-draw parameters buffer.. which is annoying
+	 * and means we can't easily emit these consts in cmd
+	 * stream so need to copy them to bo.
+	 */
+	if (info->indirect && needs_vtxid_base) {
+		struct pipe_draw_indirect_info *indirect = info->indirect;
+		struct pipe_resource *vertex_params_rsc =
+				pipe_buffer_create(&ctx->screen->base,
 						PIPE_BIND_CONSTANT_BUFFER, PIPE_USAGE_STREAM,
 						vertex_params_size * 4);
-				unsigned src_off = info->indirect->offset;;
-				void *ptr;
+		unsigned src_off = info->indirect->offset;;
+		void *ptr;
 
-				ptr = fd_bo_map(fd_resource(vertex_params_rsc)->bo);
-				memcpy(ptr, vertex_params, vertex_params_size * 4);
+		ptr = fd_bo_map(fd_resource(vertex_params_rsc)->bo);
+		memcpy(ptr, vertex_params, vertex_params_size * 4);
 
-				if (info->index_size) {
-					/* indexed draw, index_bias is 4th field: */
-					src_off += 3 * 4;
-				} else {
-					/* non-indexed draw, start is 3rd field: */
-					src_off += 2 * 4;
-				}
+		if (info->index_size) {
+			/* indexed draw, index_bias is 4th field: */
+			src_off += 3 * 4;
+		} else {
+			/* non-indexed draw, start is 3rd field: */
+			src_off += 2 * 4;
+		}
 
-				/* copy index_bias or start from draw params: */
-				ctx->mem_to_mem(ring, vertex_params_rsc, 0,
-						indirect->buffer, src_off, 1);
+		/* copy index_bias or start from draw params: */
+		ctx->screen->mem_to_mem(ring, vertex_params_rsc, 0,
+				indirect->buffer, src_off, 1);
 
-				ctx->emit_const(ring, MESA_SHADER_VERTEX, offset * 4, 0,
-						vertex_params_size, NULL, vertex_params_rsc);
+		emit_const(ctx->screen, ring, v, offset * 4, 0,
+				vertex_params_size, NULL, vertex_params_rsc);
 
-				pipe_resource_reference(&vertex_params_rsc, NULL);
-			} else {
-				ctx->emit_const(ring, MESA_SHADER_VERTEX, offset * 4, 0,
-						vertex_params_size, vertex_params, NULL);
-			}
+		pipe_resource_reference(&vertex_params_rsc, NULL);
+	} else {
+		emit_const(ctx->screen, ring, v, offset * 4, 0,
+				vertex_params_size, vertex_params, NULL);
+	}
 
-			/* if needed, emit stream-out buffer addresses: */
-			if (vertex_params[IR3_DP_VTXCNT_MAX] > 0) {
-				emit_tfbos(ctx, v, ring);
-			}
-		}
+	/* if needed, emit stream-out buffer addresses: */
+	if (vertex_params[IR3_DP_VTXCNT_MAX] > 0) {
+		emit_tfbos(ctx, v, ring);
+	}
+}
+
+void
+ir3_emit_vs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
+		struct fd_context *ctx, const struct pipe_draw_info *info)
+{
+	debug_assert(v->type == MESA_SHADER_VERTEX);
+
+	emit_common_consts(v, ring, ctx, PIPE_SHADER_VERTEX);
+
+	/* emit driver params every time: */
+	if (info && ir3_needs_vs_driver_params(v)) {
+		ring_wfi(ctx->batch, ring);
+		ir3_emit_vs_driver_params(v, ring, ctx, info);
 	}
 }
 
@@ -593,7 +615,8 @@ ir3_emit_cs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *rin
 	emit_common_consts(v, ring, ctx, PIPE_SHADER_COMPUTE);
 
 	/* emit compute-shader driver-params: */
-	uint32_t offset = v->constbase.driver_param;
+	const struct ir3_const_state *const_state = &v->shader->const_state;
+	uint32_t offset = const_state->offsets.driver_param;
 	if (v->constlen > offset) {
 		ring_wfi(ctx->batch, ring);
 
@@ -615,14 +638,14 @@ ir3_emit_cs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *rin
 					0x1000);
 				indirect_offset = 0;
 
-				ctx->mem_to_mem(ring, indirect, 0, info->indirect,
+				ctx->screen->mem_to_mem(ring, indirect, 0, info->indirect,
 						info->indirect_offset, 3);
 			} else {
 				pipe_resource_reference(&indirect, info->indirect);
 				indirect_offset = info->indirect_offset;
 			}
 
-			ctx->emit_const(ring, MESA_SHADER_COMPUTE, offset * 4,
+			emit_const(ctx->screen, ring, v, offset * 4,
 					indirect_offset, 4, NULL, indirect);
 
 			pipe_resource_reference(&indirect, NULL);
@@ -635,9 +658,11 @@ ir3_emit_cs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *rin
 				[IR3_DP_LOCAL_GROUP_SIZE_Y] = info->block[1],
 				[IR3_DP_LOCAL_GROUP_SIZE_Z] = info->block[2],
 			};
+			uint32_t size = MIN2(const_state->num_driver_params,
+					v->constlen * 4 - offset * 4);
 
-			ctx->emit_const(ring, MESA_SHADER_COMPUTE, offset * 4, 0,
-					ARRAY_SIZE(compute_params), compute_params, NULL);
+			emit_const(ctx->screen, ring, v, offset * 4, 0, size,
+					compute_params, NULL);
 		}
 	}
 }
diff --git a/lib/mesa/src/gallium/drivers/freedreno/ir3/ir3_gallium.h b/lib/mesa/src/gallium/drivers/freedreno/ir3/ir3_gallium.h
index 5fb745967..cc8ae4599 100644
--- a/lib/mesa/src/gallium/drivers/freedreno/ir3/ir3_gallium.h
+++ b/lib/mesa/src/gallium/drivers/freedreno/ir3/ir3_gallium.h
@@ -28,23 +28,52 @@
 #define IR3_GALLIUM_H_
 
 #include "pipe/p_state.h"
+#include "pipe/p_screen.h"
 #include "ir3/ir3_shader.h"
 
 struct ir3_shader * ir3_shader_create(struct ir3_compiler *compiler,
 		const struct pipe_shader_state *cso, gl_shader_stage type,
-		struct pipe_debug_callback *debug);
+		struct pipe_debug_callback *debug,
+		struct pipe_screen *screen);
 struct ir3_shader *
 ir3_shader_create_compute(struct ir3_compiler *compiler,
 		const struct pipe_compute_state *cso,
-		struct pipe_debug_callback *debug);
+		struct pipe_debug_callback *debug,
+		struct pipe_screen *screen);
 struct ir3_shader_variant * ir3_shader_variant(struct ir3_shader *shader,
 		struct ir3_shader_key key, bool binning_pass,
 		struct pipe_debug_callback *debug);
-struct nir_shader * ir3_tgsi_to_nir(struct ir3_compiler *compiler,
-		const struct tgsi_token *tokens);
 
 struct fd_ringbuffer;
 struct fd_context;
+struct fd_screen;
+struct fd_constbuf_stateobj;
+struct fd_shaderbuf_stateobj;
+struct fd_shaderimg_stateobj;
+
+void ir3_emit_user_consts(struct fd_screen *screen, const struct ir3_shader_variant *v,
+		struct fd_ringbuffer *ring, struct fd_constbuf_stateobj *constbuf);
+void ir3_emit_ubos(struct fd_screen *screen, const struct ir3_shader_variant *v,
+		struct fd_ringbuffer *ring, struct fd_constbuf_stateobj *constbuf);
+void ir3_emit_ssbo_sizes(struct fd_screen *screen, const struct ir3_shader_variant *v,
+		struct fd_ringbuffer *ring, struct fd_shaderbuf_stateobj *sb);
+void ir3_emit_image_dims(struct fd_screen *screen, const struct ir3_shader_variant *v,
+		struct fd_ringbuffer *ring, struct fd_shaderimg_stateobj *si);
+void ir3_emit_immediates(struct fd_screen *screen, const struct ir3_shader_variant *v,
+		struct fd_ringbuffer *ring);
+
+static inline bool
+ir3_needs_vs_driver_params(const struct ir3_shader_variant *v)
+{
+	const struct ir3_const_state *const_state = &v->shader->const_state;
+	uint32_t offset = const_state->offsets.driver_param;
+
+	return v->constlen > offset;
+}
+
+void ir3_emit_vs_driver_params(const struct ir3_shader_variant *v,
+		struct fd_ringbuffer *ring, struct fd_context *ctx,
+		const struct pipe_draw_info *info);
 void ir3_emit_vs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
 		struct fd_context *ctx, const struct pipe_draw_info *info);
 void ir3_emit_fs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,