Import Mesa 19.0.5

3 files changed, 42 insertions, 17 deletions

diff --git a/lib/mesa/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c b/lib/mesa/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c
index 496349387..28e163673 100644
--- a/lib/mesa/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c
+++ b/lib/mesa/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c
@@ -423,6 +423,7 @@ void
 nvc0_launch_grid(struct pipe_context *pipe, const struct pipe_grid_info *info)
 {
    struct nvc0_context *nvc0 = nvc0_context(pipe);
+   struct nvc0_screen *screen = nvc0->screen;
    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
    struct nvc0_program *cp = nvc0->compprog;
    int ret;
@@ -463,12 +464,14 @@ nvc0_launch_grid(struct pipe_context *pipe, const struct pipe_grid_info *info)
    PUSH_DATA (push, (info->block[1] << 16) | info->block[0]);
    PUSH_DATA (push, info->block[2]);
 
+   nouveau_pushbuf_space(push, 32, 2, 1);
+   PUSH_REFN(push, screen->text, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD);
+
    if (unlikely(info->indirect)) {
       struct nv04_resource *res = nv04_resource(info->indirect);
       uint32_t offset = res->offset + info->indirect_offset;
       unsigned macro = NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT;
 
-      nouveau_pushbuf_space(push, 16, 0, 1);
       PUSH_REFN(push, res->bo, NOUVEAU_BO_RD | res->domain);
       PUSH_DATA(push, NVC0_FIFO_PKHDR_1I(1, macro, 3));
       nouveau_pushbuf_data(push, res->bo, offset,
diff --git a/lib/mesa/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.h b/lib/mesa/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.h
index 8225755d8..5c8ad5eb2 100644
--- a/lib/mesa/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.h
+++ b/lib/mesa/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.h
@@ -6,6 +6,11 @@
 
 #include "nvc0_query.h"
 
+#define NVC0_HW_QUERY_STATE_READY   0
+#define NVC0_HW_QUERY_STATE_ACTIVE  1
+#define NVC0_HW_QUERY_STATE_ENDED   2
+#define NVC0_HW_QUERY_STATE_FLUSHED 3
+
 #define NVC0_HW_QUERY_TFB_BUFFER_OFFSET (PIPE_QUERY_TYPES + 0)
 
 struct nvc0_hw_query;
@@ -29,7 +34,6 @@ struct nvc0_hw_query {
    uint8_t state;
    boolean is64bit;
    uint8_t rotate;
-   int nesting; /* only used for occlusion queries */
    struct nouveau_mm_allocation *mm;
    struct nouveau_fence *fence;
 };
diff --git a/lib/mesa/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c b/lib/mesa/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
index f40600e48..8820b5aac 100644
--- a/lib/mesa/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
+++ b/lib/mesa/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
@@ -657,6 +657,19 @@ nvc0_validate_tsc(struct nvc0_context *nvc0, int s)
 
    nvc0->state.num_samplers[s] = nvc0->num_samplers[s];
 
+   // TXF, in unlinked tsc mode, will always use sampler 0. So we have to
+   // ensure that it remains bound. Its contents don't matter, all samplers we
+   // ever create have the SRGB_CONVERSION bit set, so as long as the first
+   // entry is initialized, we're good to go. This is the only bit that has
+   // any effect on what TXF does.
+   if ((nvc0->samplers_dirty[s] & 1) && !nvc0->samplers[s][0]) {
+      if (n == 0)
+         n = 1;
+      // We're guaranteed that the first command refers to the first slot, so
+      // we're not overwriting a valid entry.
+      commands[0] = (0 << 12) | (0 << 4) | 1;
+   }
+
    if (n) {
       if (unlikely(s == 5))
          BEGIN_NIC0(push, NVC0_CP(BIND_TSC), n);
@@ -728,6 +741,18 @@ void nvc0_validate_samplers(struct nvc0_context *nvc0)
    nvc0->dirty_cp |= NVC0_NEW_CP_SAMPLERS;
 }
 
+void
+nvc0_upload_tsc0(struct nvc0_context *nvc0)
+{
+   struct nouveau_pushbuf *push = nvc0->base.pushbuf;
+   u32 data[8] = { G80_TSC_0_SRGB_CONVERSION };
+   nvc0->base.push_data(&nvc0->base, nvc0->screen->txc,
+                        65536 /*+ tsc->id * 32*/,
+                        NV_VRAM_DOMAIN(&nvc0->screen->base), 32, data);
+   BEGIN_NVC0(push, NVC0_3D(TSC_FLUSH), 1);
+   PUSH_DATA (push, 0);
+}
+
 /* Upload the "diagonal" entries for the possible texture sources ($t == $s).
  * At some point we might want to get a list of the combinations used by a
  * shader and fill in those entries instead of having it extract the handles.
@@ -1026,21 +1051,13 @@ nve4_set_surface_info(struct nouveau_pushbuf *push,
    } else {
       struct nv50_miptree *mt = nv50_miptree(&res->base);
       struct nv50_miptree_level *lvl = &mt->level[view->u.tex.level];
-      const unsigned z = view->u.tex.first_layer;
-
-      if (z) {
-         if (mt->layout_3d) {
-            address += nvc0_mt_zslice_offset(mt, view->u.tex.level, z);
-            /* doesn't work if z passes z-tile boundary */
-            if (depth > 1) {
-               pipe_debug_message(&nvc0->base.debug, CONFORMANCE,
-                                  "3D images are not really supported!");
-               debug_printf("3D images are not really supported!\n");
-            }
-         } else {
-            address += mt->layer_stride * z;
-         }
+      unsigned z = view->u.tex.first_layer;
+
+      if (!mt->layout_3d) {
+         address += mt->layer_stride * z;
+         z = 0;
       }
+
       address += lvl->offset;
 
       info[0]  = address >> 8;
@@ -1055,7 +1072,8 @@ nve4_set_surface_info(struct nouveau_pushbuf *push,
       info[6]  = depth - 1;
       info[6] |= (lvl->tile_mode & 0xf00) << 21;
       info[6] |= NVC0_TILE_SHIFT_Z(lvl->tile_mode) << 22;
-      info[7]  = 0;
+      info[7]  = mt->layout_3d ? 1 : 0;
+      info[7] |= z << 16;
       info[14] = mt->ms_x;
       info[15] = mt->ms_y;
    }