Import Mesa 17.3.9

2 files changed, 33 insertions, 48 deletions

diff --git a/lib/mesa/src/gallium/drivers/radeon/r600_cs.h b/lib/mesa/src/gallium/drivers/radeon/r600_cs.h
index 28bdf15b8..5bfce1ca7 100644
--- a/lib/mesa/src/gallium/drivers/radeon/r600_cs.h
+++ b/lib/mesa/src/gallium/drivers/radeon/r600_cs.h
@@ -31,7 +31,7 @@
 #define R600_CS_H
 
 #include "r600_pipe_common.h"
-#include "amd/common/r600d_common.h"
+#include "amd/common/sid.h"
 
 /**
  * Return true if there is enough memory in VRAM and GTT for the buffers
@@ -113,27 +113,12 @@ radeon_add_to_buffer_list_check_mem(struct r600_common_context *rctx,
 	return radeon_add_to_buffer_list(rctx, ring, rbo, usage, priority);
 }
 
-static inline void r600_emit_reloc(struct r600_common_context *rctx,
-				   struct r600_ring *ring, struct r600_resource *rbo,
-				   enum radeon_bo_usage usage,
-				   enum radeon_bo_priority priority)
-{
-	struct radeon_winsys_cs *cs = ring->cs;
-	bool has_vm = ((struct r600_common_screen*)rctx->b.screen)->info.has_virtual_memory;
-	unsigned reloc = radeon_add_to_buffer_list(rctx, ring, rbo, usage, priority);
-
-	if (!has_vm) {
-		radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
-		radeon_emit(cs, reloc);
-	}
-}
-
 static inline void radeon_set_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 {
-	assert(reg < R600_CONTEXT_REG_OFFSET);
+	assert(reg < SI_CONTEXT_REG_OFFSET);
 	assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
 	radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0));
-	radeon_emit(cs, (reg - R600_CONFIG_REG_OFFSET) >> 2);
+	radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2);
 }
 
 static inline void radeon_set_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
@@ -144,10 +129,10 @@ static inline void radeon_set_config_reg(struct radeon_winsys_cs *cs, unsigned r
 
 static inline void radeon_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 {
-	assert(reg >= R600_CONTEXT_REG_OFFSET);
+	assert(reg >= SI_CONTEXT_REG_OFFSET);
 	assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
 	radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0));
-	radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2);
+	radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
 }
 
 static inline void radeon_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
@@ -160,10 +145,10 @@ static inline void radeon_set_context_reg_idx(struct radeon_winsys_cs *cs,
 					      unsigned reg, unsigned idx,
 					      unsigned value)
 {
-	assert(reg >= R600_CONTEXT_REG_OFFSET);
+	assert(reg >= SI_CONTEXT_REG_OFFSET);
 	assert(cs->current.cdw + 3 <= cs->current.max_dw);
 	radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0));
-	radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2 | (idx << 28));
+	radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2 | (idx << 28));
 	radeon_emit(cs, value);
 }
 
diff --git a/lib/mesa/src/gallium/drivers/radeon/radeon_vce.h b/lib/mesa/src/gallium/drivers/radeon/radeon_vce.h
index f79e65c9a..f34a8eaf8 100644
--- a/lib/mesa/src/gallium/drivers/radeon/radeon_vce.h
+++ b/lib/mesa/src/gallium/drivers/radeon/radeon_vce.h
@@ -40,9 +40,9 @@
 #define RVCE_BEGIN(cmd) { \
 	uint32_t *begin = &enc->cs->current.buf[enc->cs->current.cdw++]; \
 	RVCE_CS(cmd)
-#define RVCE_READ(buf, domain, off) rvce_add_buffer(enc, (buf), RADEON_USAGE_READ, (domain), (off))
-#define RVCE_WRITE(buf, domain, off) rvce_add_buffer(enc, (buf), RADEON_USAGE_WRITE, (domain), (off))
-#define RVCE_READWRITE(buf, domain, off) rvce_add_buffer(enc, (buf), RADEON_USAGE_READWRITE, (domain), (off))
+#define RVCE_READ(buf, domain, off) si_vce_add_buffer(enc, (buf), RADEON_USAGE_READ, (domain), (off))
+#define RVCE_WRITE(buf, domain, off) si_vce_add_buffer(enc, (buf), RADEON_USAGE_WRITE, (domain), (off))
+#define RVCE_READWRITE(buf, domain, off) si_vce_add_buffer(enc, (buf), RADEON_USAGE_READWRITE, (domain), (off))
 #define RVCE_END() *begin = (&enc->cs->current.buf[enc->cs->current.cdw] - begin) * 4; }
 
 #define RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE (4096 * 16 * 2.5)
@@ -417,46 +417,46 @@ struct rvce_encoder {
 };
 
 /* CPB handling functions */
-struct rvce_cpb_slot *current_slot(struct rvce_encoder *enc);
-struct rvce_cpb_slot *l0_slot(struct rvce_encoder *enc);
-struct rvce_cpb_slot *l1_slot(struct rvce_encoder *enc);
-void rvce_frame_offset(struct rvce_encoder *enc, struct rvce_cpb_slot *slot,
-		       signed *luma_offset, signed *chroma_offset);
+struct rvce_cpb_slot *si_current_slot(struct rvce_encoder *enc);
+struct rvce_cpb_slot *si_l0_slot(struct rvce_encoder *enc);
+struct rvce_cpb_slot *si_l1_slot(struct rvce_encoder *enc);
+void si_vce_frame_offset(struct rvce_encoder *enc, struct rvce_cpb_slot *slot,
+			 signed *luma_offset, signed *chroma_offset);
 
-struct pipe_video_codec *rvce_create_encoder(struct pipe_context *context,
-					     const struct pipe_video_codec *templat,
-					     struct radeon_winsys* ws,
-					     rvce_get_buffer get_buffer);
+struct pipe_video_codec *si_vce_create_encoder(struct pipe_context *context,
+					       const struct pipe_video_codec *templat,
+					       struct radeon_winsys* ws,
+					       rvce_get_buffer get_buffer);
 
-bool rvce_is_fw_version_supported(struct r600_common_screen *rscreen);
+bool si_vce_is_fw_version_supported(struct r600_common_screen *rscreen);
 
-void rvce_add_buffer(struct rvce_encoder *enc, struct pb_buffer *buf,
-		     enum radeon_bo_usage usage, enum radeon_bo_domain domain,
-		     signed offset);
+void si_vce_add_buffer(struct rvce_encoder *enc, struct pb_buffer *buf,
+		       enum radeon_bo_usage usage, enum radeon_bo_domain domain,
+		       signed offset);
 
 /* init vce fw 40.2.2 specific callbacks */
-void radeon_vce_40_2_2_init(struct rvce_encoder *enc);
+void si_vce_40_2_2_init(struct rvce_encoder *enc);
 
 /* init vce fw 50 specific callbacks */
-void radeon_vce_50_init(struct rvce_encoder *enc);
+void si_vce_50_init(struct rvce_encoder *enc);
 
 /* init vce fw 52 specific callbacks */
-void radeon_vce_52_init(struct rvce_encoder *enc);
+void si_vce_52_init(struct rvce_encoder *enc);
 
 /* version specific function for getting parameters */
-void (*get_pic_param)(struct rvce_encoder *enc,
+void (*si_get_pic_param)(struct rvce_encoder *enc,
                       struct pipe_h264_enc_picture_desc *pic);
 
 /* get parameters for vce 40.2.2 */
-void radeon_vce_40_2_2_get_param(struct rvce_encoder *enc,
-                                 struct pipe_h264_enc_picture_desc *pic);
+void si_vce_40_2_2_get_param(struct rvce_encoder *enc,
+			     struct pipe_h264_enc_picture_desc *pic);
 
 /* get parameters for vce 50 */
-void radeon_vce_50_get_param(struct rvce_encoder *enc,
-                             struct pipe_h264_enc_picture_desc *pic);
+void si_vce_50_get_param(struct rvce_encoder *enc,
+			 struct pipe_h264_enc_picture_desc *pic);
 
 /* get parameters for vce 52 */
-void radeon_vce_52_get_param(struct rvce_encoder *enc,
-                             struct pipe_h264_enc_picture_desc *pic);
+void si_vce_52_get_param(struct rvce_encoder *enc,
+			 struct pipe_h264_enc_picture_desc *pic);
 
 #endif