diff options
| author | Jonathan Gray <jsg@cvs.openbsd.org> | 2019-07-01 08:17:14 +0000 |
|---|---|---|
| committer | Jonathan Gray <jsg@cvs.openbsd.org> | 2019-07-01 08:17:14 +0000 |
| commit | 31e0cc54752847a9d3508fad08c8784666ba62cf (patch) | |
| tree | 664e5a21c48e149f1223e0eb259487fda4c0c4f0 /lib/mesa/src/gallium/drivers | |
| parent | 8299dd14c674896e0a62932905dc20f3a24a0093 (diff) | |
Import Mesa 19.0.8
Diffstat (limited to 'lib/mesa/src/gallium/drivers')
| -rw-r--r-- | lib/mesa/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/lib/mesa/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c b/lib/mesa/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c index cb5c58247..38825d0aa 100644 --- a/lib/mesa/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c +++ b/lib/mesa/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c @@ -588,6 +588,13 @@ set_blit_scissor(struct fd_batch *batch, struct fd_ringbuffer *ring) blit_scissor.maxx = MIN2(pfb->width, batch->max_scissor.maxx); blit_scissor.maxy = MIN2(pfb->height, batch->max_scissor.maxy); + /* NOTE: blob switches to CP_BLIT instead of CP_EVENT_WRITE:BLIT for + * small render targets. But since we align pitch to binw I think + * we can get away avoiding GPU hangs a simpler way, by just rounding + * up the blit scissor: + */ + blit_scissor.maxx = MAX2(blit_scissor.maxx, batch->ctx->screen->gmem_alignw); + OUT_PKT4(ring, REG_A6XX_RB_BLIT_SCISSOR_TL, 2); OUT_RING(ring, A6XX_RB_BLIT_SCISSOR_TL_X(blit_scissor.minx) | |