Merge Mesa 23.3.6

7 files changed, 533 insertions, 225 deletions

diff --git a/lib/mesa/src/gallium/include/pipe/p_compiler.h b/lib/mesa/src/gallium/include/pipe/p_compiler.h
deleted file mode 100644
index 3a0d8fecd..000000000
--- a/lib/mesa/src/gallium/include/pipe/p_compiler.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/**************************************************************************
- *
- * Copyright 2007-2008 VMware, Inc.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- **************************************************************************/
-
-#ifndef P_COMPILER_H
-#define P_COMPILER_H
-
-
-#include "util/compiler.h"
-#include "util/detect.h"
-#include "util/macros.h"
-
-#include <limits.h>
-#include <stdarg.h>
-#include <stdbool.h>
-#include <stddef.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <string.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-#if !defined(__HAIKU__) && !defined(__USE_MISC)
-#if !DETECT_OS_ANDROID
-typedef unsigned int       uint;
-#endif
-typedef unsigned short     ushort;
-#endif
-typedef unsigned char      ubyte;
-
-typedef unsigned char boolean;
-#ifndef TRUE
-#define TRUE  true
-#endif
-#ifndef FALSE
-#define FALSE false
-#endif
-
-#if defined(__cplusplus)
-}
-#endif
-
-
-#endif /* P_COMPILER_H */
diff --git a/lib/mesa/src/gallium/include/pipe/p_context.h b/lib/mesa/src/gallium/include/pipe/p_context.h
index dd4529f02..0c8d81cdf 100644
--- a/lib/mesa/src/gallium/include/pipe/p_context.h
+++ b/lib/mesa/src/gallium/include/pipe/p_context.h
@@ -28,7 +28,7 @@
 #ifndef PIPE_CONTEXT_H
 #define PIPE_CONTEXT_H
 
-#include "p_compiler.h"
+#include "util/compiler.h"
 #include "util/format/u_formats.h"
 #include "p_video_enums.h"
 #include "p_defines.h"
@@ -408,6 +408,15 @@ struct pipe_context {
    void   (*bind_vertex_elements_state)(struct pipe_context *, void *);
    void   (*delete_vertex_elements_state)(struct pipe_context *, void *);
 
+   void * (*create_ts_state)(struct pipe_context *,
+                             const struct pipe_shader_state *);
+   void   (*bind_ts_state)(struct pipe_context *, void *);
+   void   (*delete_ts_state)(struct pipe_context *, void *);
+
+   void * (*create_ms_state)(struct pipe_context *,
+                             const struct pipe_shader_state *);
+   void   (*bind_ms_state)(struct pipe_context *, void *);
+   void   (*delete_ms_state)(struct pipe_context *, void *);
    /*@}*/
 
    /**
@@ -595,7 +604,6 @@ struct pipe_context {
    /**
     * Bind an array of vertex buffers to the specified slots.
     *
-    * \param start_slot      first vertex buffer slot
     * \param count           number of consecutive vertex buffers to bind.
     * \param unbind_num_trailing_slots  unbind slots after the bound slots
     * \param take_ownership the caller holds buffer references and they
@@ -604,7 +612,6 @@ struct pipe_context {
     * \param buffers         array of the buffers to bind
     */
    void (*set_vertex_buffers)(struct pipe_context *,
-                              unsigned start_slot,
                               unsigned num_buffers,
                               unsigned unbind_num_trailing_slots,
                               bool take_ownership,
@@ -884,7 +891,7 @@ struct pipe_context {
                            const struct pipe_box *,
                            const void *data,
                            unsigned stride,
-                           unsigned layer_stride);
+                           uintptr_t layer_stride);
 
    /**
     * Flush any pending framebuffer writes and invalidate texture caches.
@@ -937,6 +944,9 @@ struct pipe_context {
    void (*get_compute_state_info)(struct pipe_context *, void *,
                                   struct pipe_compute_state_object_info *);
 
+   uint32_t (*get_compute_state_subgroup_size)(struct pipe_context *, void *,
+                                               const uint32_t block[3]);
+
    /**
     * Bind an array of shader resources that will be used by the
     * compute program.  Any resources that were previously bound to
@@ -995,6 +1005,9 @@ struct pipe_context {
     */
    void (*launch_grid)(struct pipe_context *context,
                        const struct pipe_grid_info *info);
+
+   void (*draw_mesh_tasks)(struct pipe_context *context,
+                           const struct pipe_grid_info *info);
    /*@}*/
 
    /**
@@ -1006,11 +1019,12 @@ struct pipe_context {
     *
     * \param to_device - true if the virtual memory is migrated to the device
     *                    false if the virtual memory is migrated to the host
-    * \param migrate_content - whether the content should be migrated as well
+    * \param content_undefined - whether the content of the migrated memory
+    *                            is undefined after migration
     */
    void (*svm_migrate)(struct pipe_context *context, unsigned num_ptrs,
                        const void* const* ptrs, const size_t *sizes,
-                       bool to_device, bool migrate_content);
+                       bool to_device, bool content_undefined);
    /*@}*/
 
    /**
diff --git a/lib/mesa/src/gallium/include/pipe/p_defines.h b/lib/mesa/src/gallium/include/pipe/p_defines.h
index 800e9015d..cefce408e 100644
--- a/lib/mesa/src/gallium/include/pipe/p_defines.h
+++ b/lib/mesa/src/gallium/include/pipe/p_defines.h
@@ -28,9 +28,13 @@
 #ifndef PIPE_DEFINES_H
 #define PIPE_DEFINES_H
 
-#include "p_compiler.h"
+/* For pipe_blend* and pipe_logicop enums */
+#include "util/blend.h"
+
+#include "util/compiler.h"
 
 #include "compiler/shader_enums.h"
+#include "util/os_time.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -53,68 +57,6 @@ enum pipe_error
    /* TODO */
 };
 
-enum pipe_blendfactor {
-   PIPE_BLENDFACTOR_ONE = 1,
-   PIPE_BLENDFACTOR_SRC_COLOR,
-   PIPE_BLENDFACTOR_SRC_ALPHA,
-   PIPE_BLENDFACTOR_DST_ALPHA,
-   PIPE_BLENDFACTOR_DST_COLOR,
-   PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE,
-   PIPE_BLENDFACTOR_CONST_COLOR,
-   PIPE_BLENDFACTOR_CONST_ALPHA,
-   PIPE_BLENDFACTOR_SRC1_COLOR,
-   PIPE_BLENDFACTOR_SRC1_ALPHA,
-
-   PIPE_BLENDFACTOR_ZERO = 0x11,
-   PIPE_BLENDFACTOR_INV_SRC_COLOR,
-   PIPE_BLENDFACTOR_INV_SRC_ALPHA,
-   PIPE_BLENDFACTOR_INV_DST_ALPHA,
-   PIPE_BLENDFACTOR_INV_DST_COLOR,
-
-   PIPE_BLENDFACTOR_INV_CONST_COLOR = 0x17,
-   PIPE_BLENDFACTOR_INV_CONST_ALPHA,
-   PIPE_BLENDFACTOR_INV_SRC1_COLOR,
-   PIPE_BLENDFACTOR_INV_SRC1_ALPHA,
-};
-
-enum pipe_blend_func {
-   PIPE_BLEND_ADD,
-   PIPE_BLEND_SUBTRACT,
-   PIPE_BLEND_REVERSE_SUBTRACT,
-   PIPE_BLEND_MIN,
-   PIPE_BLEND_MAX,
-};
-
-enum pipe_logicop {
-   PIPE_LOGICOP_CLEAR,
-   PIPE_LOGICOP_NOR,
-   PIPE_LOGICOP_AND_INVERTED,
-   PIPE_LOGICOP_COPY_INVERTED,
-   PIPE_LOGICOP_AND_REVERSE,
-   PIPE_LOGICOP_INVERT,
-   PIPE_LOGICOP_XOR,
-   PIPE_LOGICOP_NAND,
-   PIPE_LOGICOP_AND,
-   PIPE_LOGICOP_EQUIV,
-   PIPE_LOGICOP_NOOP,
-   PIPE_LOGICOP_OR_INVERTED,
-   PIPE_LOGICOP_COPY,
-   PIPE_LOGICOP_OR_REVERSE,
-   PIPE_LOGICOP_OR,
-   PIPE_LOGICOP_SET,
-};
-
-#define PIPE_MASK_R  0x1
-#define PIPE_MASK_G  0x2
-#define PIPE_MASK_B  0x4
-#define PIPE_MASK_A  0x8
-#define PIPE_MASK_RGBA 0xf
-#define PIPE_MASK_Z  0x10
-#define PIPE_MASK_S  0x20
-#define PIPE_MASK_ZS 0x30
-#define PIPE_MASK_RGBAZS (PIPE_MASK_RGBA|PIPE_MASK_ZS)
-
-
 /**
  * Inequality functions.  Used for depth test, stencil compare, alpha
  * test, shadow compare, etc.
@@ -244,6 +186,7 @@ enum pipe_tex_reduction_mode {
  */
 enum pipe_map_flags
 {
+   PIPE_MAP_NONE = 0,
    /**
     * Resource contents read back (or accessed directly) at transfer
     * create time.
@@ -452,6 +395,15 @@ enum pipe_flush_flags
 #define PIPE_CONTEXT_PROTECTED         (1 << 7)
 
 /**
+ * Create a context that does not use sampler LOD bias. If this is set, the
+ * frontend MUST set pipe_sampler_state::lod_bias to 0.0f for all samplers used
+ * with the context. Drivers MAY ignore lod_bias for such contexts.
+ *
+ * This may allow driver fast paths for GLES, which lacks sampler LOD bias.
+ */
+#define PIPE_CONTEXT_NO_LOD_BIAS (1 << 8)
+
+/**
  * Flags for pipe_context::memory_barrier.
  */
 #define PIPE_BARRIER_MAPPED_BUFFER     (1 << 0)
@@ -529,7 +481,7 @@ enum pipe_flush_flags
 /* Resource is the DRI_PRIME blit destination. Only set on on the render GPU. */
 #define PIPE_BIND_PRIME_BLIT_DST (1 << 24)
 #define PIPE_BIND_USE_FRONT_RENDERING (1 << 25) /* Resource may be used for frontbuffer rendering */
-
+#define PIPE_BIND_CONST_BW    (1 << 26) /* Avoid using a data dependent layout (AFBC, UBWC, etc) */
 
 /**
  * Flags for the driver about resource behaviour:
@@ -559,28 +511,6 @@ enum pipe_resource_usage {
 };
 
 /**
- * Primitive types:
- */
-enum PACKED pipe_prim_type {
-   PIPE_PRIM_POINTS,
-   PIPE_PRIM_LINES,
-   PIPE_PRIM_LINE_LOOP,
-   PIPE_PRIM_LINE_STRIP,
-   PIPE_PRIM_TRIANGLES,
-   PIPE_PRIM_TRIANGLE_STRIP,
-   PIPE_PRIM_TRIANGLE_FAN,
-   PIPE_PRIM_QUADS,
-   PIPE_PRIM_QUAD_STRIP,
-   PIPE_PRIM_POLYGON,
-   PIPE_PRIM_LINES_ADJACENCY,
-   PIPE_PRIM_LINE_STRIP_ADJACENCY,
-   PIPE_PRIM_TRIANGLES_ADJACENCY,
-   PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY,
-   PIPE_PRIM_PATCHES,
-   PIPE_PRIM_MAX,
-};
-
-/**
  * Tessellator spacing types
  */
 enum pipe_tess_spacing {
@@ -627,6 +557,8 @@ enum pipe_statistics_query_index {
    PIPE_STAT_QUERY_HS_INVOCATIONS,
    PIPE_STAT_QUERY_DS_INVOCATIONS,
    PIPE_STAT_QUERY_CS_INVOCATIONS,
+   PIPE_STAT_QUERY_TS_INVOCATIONS,
+   PIPE_STAT_QUERY_MS_INVOCATIONS,
 };
 
 /**
@@ -648,20 +580,6 @@ enum pipe_sprite_coord_mode {
 };
 
 /**
- * Texture & format swizzles
- */
-enum pipe_swizzle {
-   PIPE_SWIZZLE_X,
-   PIPE_SWIZZLE_Y,
-   PIPE_SWIZZLE_Z,
-   PIPE_SWIZZLE_W,
-   PIPE_SWIZZLE_0,
-   PIPE_SWIZZLE_1,
-   PIPE_SWIZZLE_NONE,
-   PIPE_SWIZZLE_MAX, /**< Number of enums counter (must be last) */
-};
-
-/**
  * Viewport swizzles
  */
 enum pipe_viewport_swizzle {
@@ -675,9 +593,6 @@ enum pipe_viewport_swizzle {
    PIPE_VIEWPORT_SWIZZLE_NEGATIVE_W,
 };
 
-#define PIPE_TIMEOUT_INFINITE 0xffffffffffffffffull
-
-
 /**
  * Device reset status.
  */
@@ -800,6 +715,7 @@ enum pipe_cap
    PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT,
    PIPE_CAP_START_INSTANCE,
    PIPE_CAP_QUERY_TIMESTAMP,
+   PIPE_CAP_TIMER_RESOLUTION,
    PIPE_CAP_TEXTURE_MULTISAMPLE,
    PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT,
    PIPE_CAP_CUBE_MAP_ARRAY,
@@ -854,7 +770,6 @@ enum pipe_cap
    PIPE_CAP_FORCE_PERSAMPLE_INTERP,
    PIPE_CAP_SHAREABLE_SHADERS,
    PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS,
-   PIPE_CAP_CLEAR_TEXTURE,
    PIPE_CAP_CLEAR_SCISSORED,
    PIPE_CAP_DRAW_PARAMETERS,
    PIPE_CAP_SHADER_PACK_HALF_FLOAT,
@@ -894,7 +809,6 @@ enum pipe_cap
    PIPE_CAP_LEGACY_MATH_RULES,
    PIPE_CAP_DOUBLES,
    PIPE_CAP_INT64,
-   PIPE_CAP_INT64_DIVMOD,
    PIPE_CAP_TGSI_TEX_TXF_LZ,
    PIPE_CAP_SHADER_CLOCK,
    PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE,
@@ -936,7 +850,6 @@ enum pipe_cap
    PIPE_CAP_SURFACE_SAMPLE_COUNT,
    PIPE_CAP_IMAGE_ATOMIC_FLOAT_ADD,
    PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE,
-   PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND,
    PIPE_CAP_DEST_SURFACE_SRGB_CONTROL,
    PIPE_CAP_NIR_COMPACT_ARRAYS,
    PIPE_CAP_MAX_VARYINGS,
@@ -1021,6 +934,7 @@ enum pipe_cap
    PIPE_CAP_ASTC_VOID_EXTENTS_NEED_DENORM_FLUSH,
 
    PIPE_CAP_VALIDATE_ALL_DIRTY_STATES,
+   PIPE_CAP_HAS_CONST_BW,
    PIPE_CAP_LAST,
    /* XXX do not add caps after PIPE_CAP_LAST! */
 };
@@ -1111,10 +1025,8 @@ enum pipe_shader_cap
    PIPE_SHADER_CAP_INT16,
    PIPE_SHADER_CAP_GLSL_16BIT_CONSTS,
    PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS,
-   PIPE_SHADER_CAP_PREFERRED_IR,
    PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED,
    PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS,
-   PIPE_SHADER_CAP_DROUND_SUPPORTED, /* all rounding modes */
    PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE,
    PIPE_SHADER_CAP_MAX_SHADER_BUFFERS,
    PIPE_SHADER_CAP_SUPPORTED_IRS,
@@ -1161,8 +1073,9 @@ enum pipe_compute_cap
    PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
    PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY,
    PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS,
+   PIPE_COMPUTE_CAP_MAX_SUBGROUPS,
    PIPE_COMPUTE_CAP_IMAGES_SUPPORTED,
-   PIPE_COMPUTE_CAP_SUBGROUP_SIZE,
+   PIPE_COMPUTE_CAP_SUBGROUP_SIZES,
    PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK,
 };
 
@@ -1236,8 +1149,10 @@ struct pipe_query_data_pipeline_statistics
          uint64_t hs_invocations; /**< Num hull shader invocations. */
          uint64_t ds_invocations; /**< Num domain shader invocations. */
          uint64_t cs_invocations; /**< Num compute shader invocations. */
+         uint64_t ts_invocations; /**< Num task shader invocations. */
+         uint64_t ms_invocations; /**< Num mesh shader invocations. */
       };
-      uint64_t counters[11];
+      uint64_t counters[13];
    };
 };
 
@@ -1308,13 +1223,6 @@ enum pipe_query_flags
    PIPE_QUERY_PARTIAL = (1 << 1),
 };
 
-union pipe_color_union
-{
-   float f[4];
-   int i[4];
-   unsigned int ui[4];
-};
-
 enum pipe_driver_query_type
 {
    PIPE_DRIVER_QUERY_TYPE_UINT64,
diff --git a/lib/mesa/src/gallium/include/pipe/p_screen.h b/lib/mesa/src/gallium/include/pipe/p_screen.h
index 9ee59c915..0c3c096bc 100644
--- a/lib/mesa/src/gallium/include/pipe/p_screen.h
+++ b/lib/mesa/src/gallium/include/pipe/p_screen.h
@@ -38,7 +38,7 @@
 #define P_SCREEN_H
 
 
-#include "pipe/p_compiler.h"
+#include "util/compiler.h"
 #include "util/format/u_formats.h"
 #include "pipe/p_defines.h"
 #include "pipe/p_video_enums.h"
@@ -408,7 +408,7 @@ struct pipe_screen {
     *
     * In all other cases, the ctx parameter has no effect.
     *
-    * \param timeout  in nanoseconds (may be PIPE_TIMEOUT_INFINITE).
+    * \param timeout  in nanoseconds (may be OS_TIMEOUT_INFINITE).
     */
    bool (*fence_finish)(struct pipe_screen *screen,
                         struct pipe_context *ctx,
diff --git a/lib/mesa/src/gallium/include/pipe/p_state.h b/lib/mesa/src/gallium/include/pipe/p_state.h
index b84a333f2..cd55ee04a 100644
--- a/lib/mesa/src/gallium/include/pipe/p_state.h
+++ b/lib/mesa/src/gallium/include/pipe/p_state.h
@@ -46,7 +46,7 @@
 
 #include "util/u_memory.h"
 
-#include "p_compiler.h"
+#include "util/compiler.h"
 #include "p_defines.h"
 #include "util/format/u_formats.h"
 
@@ -70,7 +70,7 @@ extern "C" {
 #define PIPE_MAX_SHADER_IMAGES    64
 #define PIPE_MAX_TEXTURE_LEVELS   16
 #define PIPE_MAX_SO_BUFFERS        4
-#define PIPE_MAX_SO_OUTPUTS       64
+#define PIPE_MAX_SO_OUTPUTS       128
 #define PIPE_MAX_VIEWPORTS        16
 #define PIPE_MAX_CLIP_OR_CULL_DISTANCE_COUNT 8
 #define PIPE_MAX_CLIP_OR_CULL_DISTANCE_ELEMENT_COUNT 2
@@ -109,7 +109,7 @@ struct pipe_rasterizer_state
    unsigned point_smooth:1;
    unsigned sprite_coord_mode:1;     /**< PIPE_SPRITE_COORD_ */
    unsigned point_quad_rasterization:1; /** points rasterized as quads or points */
-   unsigned point_tri_clip:1; /** large points clipped as tris or points */
+   unsigned point_line_tri_clip:1; /** large points/lines clipped as tris or points/lines */
    unsigned point_size_per_vertex:1; /**< size computed in vertex shader */
    unsigned multisample:1;         /* XXX maybe more ms state in future */
    unsigned no_ms_sample_mask_out:1;
@@ -282,12 +282,8 @@ struct pipe_stream_output_info
 };
 
 /**
- * The 'type' parameter identifies whether the shader state contains TGSI
- * tokens, etc.  If the driver returns 'PIPE_SHADER_IR_TGSI' for the
- * 'PIPE_SHADER_CAP_PREFERRED_IR' shader param, the ir will *always* be
- * 'PIPE_SHADER_IR_TGSI' and the tokens ptr will be valid.  If the driver
- * requests a different 'pipe_shader_ir' type, then it must check the 'type'
- * enum to see if it is getting TGSI tokens or its preferred IR.
+ * The 'type' parameter identifies whether the shader state contains NIR, TGSI
+ * tokens, etc.
  *
  * TODO pipe_compute_state should probably get similar treatment to handle
  * multiple IR's in a cleaner way..
@@ -318,6 +314,16 @@ pipe_shader_state_from_tgsi(struct pipe_shader_state *state,
    memset(&state->stream_output, 0, sizeof(state->stream_output));
 }
 
+static inline void
+pipe_shader_state_from_nir(struct pipe_shader_state *state,
+                           void *nir)
+{
+   state->type = PIPE_SHADER_IR_NIR;
+   state->ir.nir = nir;
+   state->tokens = NULL;
+   memset(&state->stream_output, 0, sizeof(state->stream_output));
+}
+
 
 struct pipe_stencil_state
 {
@@ -389,7 +395,7 @@ struct pipe_blend_color
 
 struct pipe_stencil_ref
 {
-   ubyte ref_value[2];
+   uint8_t ref_value[2];
 };
 
 
@@ -403,10 +409,10 @@ struct pipe_framebuffer_state
 {
    uint16_t width, height;
    uint16_t layers;  /**< Number of layers  in a no-attachment framebuffer */
-   ubyte samples; /**< Number of samples in a no-attachment framebuffer */
+   uint8_t samples; /**< Number of samples in a no-attachment framebuffer */
 
    /** multiple color buffers for multiple render targets */
-   ubyte nr_cbufs;
+   uint8_t nr_cbufs;
    struct pipe_surface *cbufs[PIPE_MAX_COLOR_BUFS];
 
    struct pipe_surface *zsbuf;      /**< Z/stencil buffer */
@@ -536,6 +542,7 @@ struct pipe_image_view
          unsigned first_layer:16;     /**< first layer to use for array textures */
          unsigned last_layer:16;      /**< last layer to use for array textures */
          unsigned level:8;            /**< mipmap level to use */
+         bool single_layer_view;      /**< single layer view of array */
       } tex;
       struct {
          unsigned offset;   /**< offset in bytes */
@@ -627,7 +634,7 @@ struct pipe_transfer
    unsigned level:8;               /**< texture mipmap level */
    struct pipe_box box;            /**< region of the resource to access */
    unsigned stride;                /**< row stride in bytes */
-   unsigned layer_stride;          /**< image/layer stride in bytes */
+   uintptr_t layer_stride;          /**< image/layer stride in bytes */
 
    /* Offset into a driver-internal staging buffer to make use of unused
     * padding in this structure.
@@ -643,7 +650,6 @@ struct pipe_transfer
  */
 struct pipe_vertex_buffer
 {
-   uint16_t stride;    /**< stride to same attrib in next vertex, in bytes */
    bool is_user_buffer;
    unsigned buffer_offset;  /**< offset to start of data in buffer, in bytes */
 
@@ -735,6 +741,9 @@ struct pipe_vertex_element
     */
    uint8_t src_format; /* low 8 bits of enum pipe_format. */
 
+   /**< stride to same attrib in next vertex, in bytes */
+   uint32_t src_stride; /* technically only uint16_t, expanded for struct padding */
+
    /** Instance data rate divisor. 0 means this is per-vertex data,
     *  n means per-instance data used for n consecutive instances (n > 0).
     */
@@ -843,7 +852,7 @@ struct pipe_draw_start_count_bias {
 struct pipe_draw_vertex_state_info {
 #if defined(__GNUC__)
    /* sizeof(mode) == 1 because it's a packed enum. */
-   enum pipe_prim_type mode;  /**< the mode of the primitive */
+   enum mesa_prim mode;  /**< the mode of the primitive */
 #else
    /* sizeof(mode) == 1 is required by draw merging in u_threaded_context. */
    uint8_t mode;              /**< the mode of the primitive */
@@ -858,7 +867,7 @@ struct pipe_draw_info
 {
 #if defined(__GNUC__)
    /* sizeof(mode) == 1 because it's a packed enum. */
-   enum pipe_prim_type mode;  /**< the mode of the primitive */
+   enum mesa_prim mode;  /**< the mode of the primitive */
 #else
    /* sizeof(mode) == 1 is required by draw merging in u_threaded_context. */
    uint8_t mode;              /**< the mode of the primitive */
@@ -873,7 +882,7 @@ struct pipe_draw_info
    bool take_index_buffer_ownership:1; /**< callee inherits caller's refcount
          (no need to reference indexbuf, but still needs to unreference it) */
    bool index_bias_varies:1;   /**< true if index_bias varies between draws */
-   bool was_line_loop:1; /**< true if pipe_prim_type was LINE_LOOP before translation */
+   bool was_line_loop:1; /**< true if mesa_prim was LINE_LOOP before translation */
    uint8_t _pad:1;
 
    unsigned start_instance; /**< first instance id */
@@ -1015,6 +1024,11 @@ struct pipe_grid_info
     */
    struct pipe_resource *indirect;
    unsigned indirect_offset; /**< must be 4 byte aligned */
+   unsigned indirect_stride;
+   /* draw related members are for task/mesh shaders */
+   unsigned draw_count;
+   unsigned indirect_draw_count_offset;
+   struct pipe_resource *indirect_draw_count;
 };
 
 /**
@@ -1050,6 +1064,11 @@ struct pipe_compute_state_object_info
    unsigned preferred_simd_size;
 
    /**
+    * Bitmask of supported SIMD sizes.
+    */
+   unsigned simd_sizes;
+
+   /**
     * How much private memory does this CSO require per thread (a.k.a. NIR scratch memory).
     */
    unsigned private_memory;
diff --git a/lib/mesa/src/gallium/include/pipe/p_video_enums.h b/lib/mesa/src/gallium/include/pipe/p_video_enums.h
index d37f7c6f4..657fce683 100644
--- a/lib/mesa/src/gallium/include/pipe/p_video_enums.h
+++ b/lib/mesa/src/gallium/include/pipe/p_video_enums.h
@@ -129,6 +129,35 @@ enum pipe_video_cap
       when it has reached its maximum async depth capacity
    */
    PIPE_VIDEO_CAP_ENC_SUPPORTS_ASYNC_OPERATION = 33,
+   PIPE_VIDEO_CAP_MIN_WIDTH = 34,
+   PIPE_VIDEO_CAP_MIN_HEIGHT = 35,
+   PIPE_VIDEO_CAP_ENC_RATE_CONTROL_QVBR = 36,
+   /*
+      AV1 encoding features list
+   */
+   PIPE_VIDEO_CAP_ENC_AV1_FEATURE = 37,
+   PIPE_VIDEO_CAP_ENC_AV1_FEATURE_EXT1 = 38,
+   PIPE_VIDEO_CAP_ENC_AV1_FEATURE_EXT2 = 39,
+   PIPE_VIDEO_CAP_ENC_SUPPORTS_TILE = 40,
+   PIPE_VIDEO_CAP_ENC_MAX_TILE_ROWS = 41,
+   PIPE_VIDEO_CAP_ENC_MAX_TILE_COLS = 42,
+};
+
+enum pipe_video_av1_enc_filter_mode
+{
+   PIPE_VIDEO_CAP_ENC_AV1_INTERPOLATION_FILTER_EIGHT_TAP = (1 << 0),
+   PIPE_VIDEO_CAP_ENC_AV1_INTERPOLATION_FILTER_EIGHT_TAP_SMOOTH = (1 << 1),
+   PIPE_VIDEO_CAP_ENC_AV1_INTERPOLATION_FILTER_EIGHT_TAP_SHARP = (1 << 2),
+   PIPE_VIDEO_CAP_ENC_AV1_INTERPOLATION_FILTER_BILINEAR = (1 << 3),
+   PIPE_VIDEO_CAP_ENC_AV1_INTERPOLATION_FILTER_SWITCHABLE = (1 << 4),
+
+};
+
+enum pipe_video_av1_enc_tx_mode
+{
+   PIPE_VIDEO_CAP_ENC_AV1_TX_MODE_ONLY_4X4 = (1 << 0),
+   PIPE_VIDEO_CAP_ENC_AV1_TX_MODE_LARGEST = (1 << 1),
+   PIPE_VIDEO_CAP_ENC_AV1_TX_MODE_SELECT = (1 << 2),
 };
 
 /* To be used with PIPE_VIDEO_CAP_VPP_ORIENTATION_MODES and for VPP state*/
@@ -184,7 +213,6 @@ enum pipe_video_cap_slice_structure
    PIPE_VIDEO_CAP_SLICE_STRUCTURE_EQUAL_MULTI_ROWS = 0x00000020,
 };
 
-
 enum pipe_video_entrypoint
 {
    PIPE_VIDEO_ENTRYPOINT_UNKNOWN,
diff --git a/lib/mesa/src/gallium/include/pipe/p_video_state.h b/lib/mesa/src/gallium/include/pipe/p_video_state.h
index 2ebc9d3fa..9cb34c55a 100644
--- a/lib/mesa/src/gallium/include/pipe/p_video_state.h
+++ b/lib/mesa/src/gallium/include/pipe/p_video_state.h
@@ -41,8 +41,10 @@ extern "C" {
 #endif
 
 #define PIPE_H265_MAX_REFERENCES      15
+#define PIPE_AV1_MAX_REFERENCES       8
 #define PIPE_DEFAULT_FRAME_RATE_DEN   1
 #define PIPE_DEFAULT_FRAME_RATE_NUM   30
+#define PIPE_DEFAULT_INTRA_IDR_PERIOD 30
 #define PIPE_H2645_EXTENDED_SAR       255
 #define PIPE_DEFAULT_DECODER_FEEDBACK_TIMEOUT_NS 1000000000
 
@@ -127,6 +129,14 @@ enum pipe_h265_slice_type
    PIPE_H265_SLICE_TYPE_I = 0x2,
 };
 
+/* To be used on each encoding feature bit field */
+enum pipe_enc_feature
+{
+   PIPE_ENC_FEATURE_NOT_SUPPORTED = 0x0,
+   PIPE_ENC_FEATURE_SUPPORTED = 0x1,
+   PIPE_ENC_FEATURE_REQUIRED = 0x2,
+};
+
 /* Same enum for h264/h265 */
 enum pipe_h2645_enc_picture_type
 {
@@ -137,13 +147,23 @@ enum pipe_h2645_enc_picture_type
    PIPE_H2645_ENC_PICTURE_TYPE_SKIP = 0x04
 };
 
+enum pipe_av1_enc_frame_type
+{
+   PIPE_AV1_ENC_FRAME_TYPE_KEY = 0x00,
+   PIPE_AV1_ENC_FRAME_TYPE_INTER = 0x01,
+   PIPE_AV1_ENC_FRAME_TYPE_INTRA_ONLY = 0x02,
+   PIPE_AV1_ENC_FRAME_TYPE_SWITCH = 0x03,
+   PIPE_AV1_ENC_FRAME_TYPE_SHOW_EXISTING = 0x04
+};
+
 enum pipe_h2645_enc_rate_control_method
 {
    PIPE_H2645_ENC_RATE_CONTROL_METHOD_DISABLE = 0x00,
    PIPE_H2645_ENC_RATE_CONTROL_METHOD_CONSTANT_SKIP = 0x01,
    PIPE_H2645_ENC_RATE_CONTROL_METHOD_VARIABLE_SKIP = 0x02,
    PIPE_H2645_ENC_RATE_CONTROL_METHOD_CONSTANT = 0x03,
-   PIPE_H2645_ENC_RATE_CONTROL_METHOD_VARIABLE = 0x04
+   PIPE_H2645_ENC_RATE_CONTROL_METHOD_VARIABLE = 0x04,
+   PIPE_H2645_ENC_RATE_CONTROL_METHOD_QUALITY_VARIABLE = 0x05
 };
 
 enum pipe_slice_buffer_placement_type
@@ -166,8 +186,9 @@ struct pipe_picture_desc
    uint8_t *decrypt_key;
    uint32_t key_size;
    enum pipe_format input_format;
+   bool input_full_range;
    enum pipe_format output_format;
-   /* A fence used on PIPE_VIDEO_ENTRYPOINT_DECODE to signal job completion */
+   /* A fence used on PIPE_VIDEO_ENTRYPOINT_DECODE/PROCESSING to signal job completion */
    struct pipe_fence_handle **fence;
 };
 
@@ -382,6 +403,15 @@ struct pipe_h264_picture_desc
    uint32_t frame_num_list[16];
 
    struct pipe_video_buffer *ref[16];
+
+   struct
+   {
+      bool slice_info_present;
+      uint32_t slice_count;
+      uint32_t slice_data_size[128];
+      uint32_t slice_data_offset[128];
+      enum pipe_slice_buffer_placement_type slice_data_flag[128];
+   } slice_parameter;
 };
 
 struct pipe_enc_quality_modes
@@ -401,6 +431,8 @@ struct pipe_h264_enc_rate_control
    unsigned frame_rate_den;
    unsigned vbv_buffer_size;
    unsigned vbv_buf_lv;
+   unsigned vbv_buf_initial_size;
+   bool app_requested_hrd_buffer;
    unsigned target_bits_picture;
    unsigned peak_bits_picture_integer;
    unsigned peak_bits_picture_fraction;
@@ -410,6 +442,10 @@ struct pipe_h264_enc_rate_control
    unsigned max_au_size;
    unsigned max_qp;
    unsigned min_qp;
+   bool app_requested_qp_range;
+
+   /* Used with PIPE_H2645_ENC_RATE_CONTROL_METHOD_QUALITY_VARIABLE */
+   unsigned vbr_quality_factor;
 };
 
 struct pipe_h264_enc_motion_estimation
@@ -476,12 +512,23 @@ struct pipe_h264_enc_seq_param
    struct {
       uint32_t aspect_ratio_info_present_flag: 1;
       uint32_t timing_info_present_flag: 1;
+      uint32_t video_signal_type_present_flag: 1;
+      uint32_t colour_description_present_flag: 1;
+      uint32_t chroma_loc_info_present_flag: 1;
    } vui_flags;
    uint32_t aspect_ratio_idc;
    uint32_t sar_width;
    uint32_t sar_height;
    uint32_t num_units_in_tick;
    uint32_t time_scale;
+   uint32_t video_format;
+   uint32_t video_full_range_flag;
+   uint32_t colour_primaries;
+   uint32_t transfer_characteristics;
+   uint32_t matrix_coefficients;
+   uint32_t chroma_sample_loc_type_top_field;
+   uint32_t chroma_sample_loc_type_bottom_field;
+   uint32_t max_num_reorder_frames;
 };
 
 struct pipe_h264_enc_picture_desc
@@ -560,12 +607,22 @@ struct pipe_h265_enc_seq_param
    struct {
       uint32_t aspect_ratio_info_present_flag: 1;
       uint32_t timing_info_present_flag: 1;
+      uint32_t video_signal_type_present_flag: 1;
+      uint32_t colour_description_present_flag: 1;
+      uint32_t chroma_loc_info_present_flag: 1;
    } vui_flags;
    uint32_t aspect_ratio_idc;
    uint32_t sar_width;
    uint32_t sar_height;
    uint32_t num_units_in_tick;
    uint32_t time_scale;
+   uint32_t video_format;
+   uint32_t video_full_range_flag;
+   uint32_t colour_primaries;
+   uint32_t transfer_characteristics;
+   uint32_t matrix_coefficients;
+   uint32_t chroma_sample_loc_type_top_field;
+   uint32_t chroma_sample_loc_type_bottom_field;
 };
 
 struct pipe_h265_enc_pic_param
@@ -601,6 +658,8 @@ struct pipe_h265_enc_rate_control
    unsigned quant_b_frames;
    unsigned vbv_buffer_size;
    unsigned vbv_buf_lv;
+   unsigned vbv_buf_initial_size;
+   bool app_requested_hrd_buffer;
    unsigned target_bits_picture;
    unsigned peak_bits_picture_integer;
    unsigned peak_bits_picture_fraction;
@@ -610,6 +669,10 @@ struct pipe_h265_enc_rate_control
    unsigned max_au_size;
    unsigned max_qp;
    unsigned min_qp;
+   bool app_requested_qp_range;
+
+   /* Used with PIPE_H2645_ENC_RATE_CONTROL_METHOD_QUALITY_VARIABLE */
+   unsigned vbr_quality_factor;
 };
 
 struct pipe_h265_enc_picture_desc
@@ -639,6 +702,214 @@ struct pipe_h265_enc_picture_desc
    struct h265_slice_descriptor slices_descriptors[128];
 };
 
+struct pipe_av1_enc_rate_control
+{
+   enum pipe_h2645_enc_rate_control_method rate_ctrl_method;
+   unsigned target_bitrate;
+   unsigned peak_bitrate;
+   unsigned frame_rate_num;
+   unsigned frame_rate_den;
+   unsigned vbv_buffer_size;
+   unsigned vbv_buf_lv;
+   unsigned vbv_buf_initial_size;
+   bool app_requested_hrd_buffer;
+   unsigned target_bits_picture;
+   unsigned peak_bits_picture_integer;
+   unsigned peak_bits_picture_fraction;
+   unsigned fill_data_enable;
+   unsigned skip_frame_enable;
+   unsigned enforce_hrd;
+   unsigned max_au_size;
+   unsigned qp; /* Initial QP */
+   unsigned max_qp;
+   unsigned min_qp;
+   bool app_requested_qp_range;
+   bool app_requested_initial_qp;
+
+   /* Used with PIPE_H2645_ENC_RATE_CONTROL_METHOD_QUALITY_VARIABLE */
+   unsigned vbr_quality_factor;
+};
+
+struct pipe_av1_enc_decoder_model_info
+{
+   uint32_t buffer_delay_length_minus1;
+   uint32_t num_units_in_decoding_tick;
+   uint32_t buffer_removal_time_length_minus1;
+   uint32_t frame_presentation_time_length_minus1;
+};
+
+struct pipe_av1_enc_color_description
+{
+   uint32_t color_primaries;
+   uint32_t transfer_characteristics;
+   uint32_t matrix_coefficients;
+   uint32_t color_range;
+   uint32_t chroma_sample_position;
+};
+struct pipe_av1_enc_seq_param
+{
+   uint32_t profile;
+   uint32_t level;
+   uint32_t tier;
+   uint32_t num_temporal_layers;
+   uint32_t intra_period;
+   uint32_t ip_period;
+   uint32_t bit_depth_minus8;
+   uint32_t pic_width_in_luma_samples;
+   uint32_t pic_height_in_luma_samples;
+   struct
+   {
+      uint32_t use_128x128_superblock:1;
+      uint32_t enable_filter_intra :1;
+      uint32_t enable_intra_edge_filter :1;
+      uint32_t enable_interintra_compound :1;
+      uint32_t enable_masked_compound :1;
+      uint32_t enable_warped_motion :1;
+      uint32_t enable_dual_filter :1;
+      uint32_t enable_cdef:1;
+      uint32_t enable_restoration:1;
+      uint32_t enable_superres:1;
+      uint32_t enable_order_hint:1;
+      uint32_t enable_jnt_comp:1;
+      uint32_t color_description_present_flag:1;
+      uint32_t enable_ref_frame_mvs:1;
+      uint32_t frame_id_number_present_flag:1;
+      uint32_t disable_screen_content_tools:1;
+      uint32_t timing_info_present_flag:1;
+      uint32_t equal_picture_interval:1;
+      uint32_t decoder_model_info_present_flag:1;
+      uint32_t force_screen_content_tools:2;
+      uint32_t force_integer_mv:2;
+   } seq_bits;
+
+   /* timing info params */
+   uint32_t num_units_in_display_tick;
+   uint32_t time_scale;
+   uint32_t num_tick_per_picture_minus1;
+   uint32_t delta_frame_id_length;
+   uint32_t additional_frame_id_length;
+   uint32_t order_hint_bits;
+   struct pipe_av1_enc_decoder_model_info decoder_model_info;
+   struct pipe_av1_enc_color_description color_config;
+   uint16_t frame_width_bits_minus1;
+   uint16_t frame_height_bits_minus1;
+   uint16_t operating_point_idc[32];
+   uint8_t decoder_model_present_for_this_op[32];
+};
+
+struct pipe_av1_tile_group {
+   uint8_t tile_group_start;
+   uint8_t tile_group_end;
+};
+
+struct pipe_av1_enc_picture_desc
+{
+   struct pipe_picture_desc base;
+   enum pipe_av1_enc_frame_type frame_type;
+   struct pipe_av1_enc_seq_param seq;
+   struct pipe_av1_enc_rate_control rc[4];
+   struct {
+      uint32_t enable_frame_obu:1;
+      uint32_t error_resilient_mode:1;
+      uint32_t disable_cdf_update:1;
+      uint32_t frame_size_override_flag:1;
+      uint32_t allow_screen_content_tools:1;
+      uint32_t allow_intrabc:1;
+      uint32_t force_integer_mv:1;
+      uint32_t disable_frame_end_update_cdf:1;
+      uint32_t palette_mode_enable:1;
+      uint32_t allow_high_precision_mv:1;
+      uint32_t use_ref_frame_mvs;
+      uint32_t show_existing_frame:1;
+      uint32_t enable_render_size:1;
+      uint32_t use_superres:1;
+      uint32_t reduced_tx_set:1;
+      uint32_t skip_mode_present:1;
+   };
+   struct pipe_enc_quality_modes quality_modes;
+   uint32_t num_tiles_in_pic; /* [1, 32], */
+   uint32_t tile_rows;
+   uint32_t tile_cols;
+   unsigned num_tile_groups;
+   struct pipe_av1_tile_group tile_groups[256];
+   uint32_t context_update_tile_id;
+   uint16_t width_in_sbs_minus_1[63];
+   uint16_t height_in_sbs_minus_1[63];
+   uint32_t frame_num;
+   uint32_t last_key_frame_num;
+   uint32_t number_of_skips;
+   uint32_t temporal_id;
+   uint32_t spatial_id;
+   uint16_t frame_width;
+   uint16_t frame_height;
+   uint16_t frame_width_sb;
+   uint16_t frame_height_sb;
+   uint16_t upscaled_width;
+   uint16_t render_width;
+   uint16_t render_height;
+   uint32_t interpolation_filter;
+   uint8_t tx_mode;
+   uint8_t compound_reference_mode;
+   uint32_t order_hint;
+   uint8_t superres_scale_denominator;
+   uint32_t primary_ref_frame;
+   uint8_t refresh_frame_flags;
+   uint8_t ref_frame_idx[7];
+
+   struct {
+      uint8_t cdef_damping_minus_3;
+      uint8_t cdef_bits;
+      uint8_t cdef_y_strengths[8];
+      uint8_t cdef_uv_strengths[8];
+   } cdef;
+
+   struct {
+      uint8_t yframe_restoration_type;
+      uint8_t cbframe_restoration_type;
+      uint8_t crframe_restoration_type;
+      uint8_t lr_unit_shift;
+      uint8_t lr_uv_shift;
+   } restoration;
+
+   struct {
+      uint8_t filter_level[2];
+      uint8_t filter_level_u;
+      uint8_t filter_level_v;
+      uint8_t sharpness_level;
+      uint8_t mode_ref_delta_enabled;
+      uint8_t mode_ref_delta_update;
+      int8_t  ref_deltas[8];
+      int8_t  mode_deltas[2];
+      uint8_t delta_lf_present;
+      uint8_t delta_lf_res;
+      uint8_t delta_lf_multi;
+   } loop_filter;
+
+   struct {
+      uint8_t base_qindex;
+      int8_t y_dc_delta_q;
+      int8_t u_dc_delta_q;
+      int8_t u_ac_delta_q;
+      int8_t v_dc_delta_q;
+      int8_t v_ac_delta_q;
+      uint8_t min_base_qindex;
+      uint8_t max_base_qindex;
+      uint8_t using_qmatrix;
+      uint8_t qm_y;
+      uint8_t qm_u;
+      uint8_t qm_v;
+      uint8_t delta_q_present;
+      uint8_t delta_q_res;
+   } quantization;
+
+   struct {
+      uint8_t obu_extension_flag;
+      uint8_t obu_has_size_field;
+      uint8_t temporal_id;
+      uint8_t spatial_id;
+   } tg_obu_header;
+};
+
 struct pipe_h265_sps
 {
    uint8_t chroma_format_idc;
@@ -1113,6 +1384,7 @@ struct pipe_av1_picture_desc
       uint16_t slice_data_row[256];
       uint16_t slice_data_col[256];
       uint8_t slice_data_anchor_frame_idx[256];
+      uint16_t slice_count;
    } slice_parameter;
 };
 
@@ -1130,6 +1402,9 @@ struct pipe_vpp_desc
    struct u_rect dst_region;
    enum pipe_video_vpp_orientation orientation;
    struct pipe_vpp_blend blend;
+
+   /* Fence to wait on for the src surface */
+   struct pipe_fence_handle *src_surface_fence;
 };
 
 
@@ -1146,16 +1421,6 @@ enum pipe_h265_enc_pred_direction
    PIPE_H265_PRED_DIRECTION_BI_NOT_EMPTY = 0x4,
 };
 
-/* To be used on each h265 feature bit field
-   defined in pipe_h265_enc_cap_features
-*/
-enum pipe_h265_enc_feature
-{
-   PIPE_H265_ENC_FEATURE_NOT_SUPPORTED = 0x0,
-   PIPE_H265_ENC_FEATURE_SUPPORTED = 0x1,
-   PIPE_H265_ENC_FEATURE_REQUIRED = 0x2,
-};
-
 /* To be used with PIPE_VIDEO_CAP_ENC_HEVC_FEATURE_FLAGS
    the config_supported bit is used to differenciate a supported
    config with all bits as zero and unsupported by driver with value=0
@@ -1347,6 +1612,150 @@ union pipe_h265_enc_cap_block_sizes {
       uint32_t value;
 };
 
+union pipe_av1_enc_cap_features {
+    struct {
+        /**
+         * Use 128x128 superblock.
+         *
+         * Allows setting use_128x128_superblock in the SPS.
+         */
+        uint32_t support_128x128_superblock     : 2;
+        /**
+         * Intra  filter.
+         * Allows setting enable_filter_intra in the SPS.
+         */
+        uint32_t support_filter_intra           : 2;
+        /**
+         *  Intra edge filter.
+         * Allows setting enable_intra_edge_filter in the SPS.
+         */
+        uint32_t support_intra_edge_filter      : 2;
+        /**
+         *  Interintra compound.
+         * Allows setting enable_interintra_compound in the SPS.
+         */
+        uint32_t support_interintra_compound    : 2;
+        /**
+         *  Masked compound.
+         * Allows setting enable_masked_compound in the SPS.
+         */
+        uint32_t support_masked_compound        : 2;
+        /**
+         *  Warped motion.
+         * Allows setting enable_warped_motion in the SPS.
+         */
+        uint32_t support_warped_motion          : 2;
+        /**
+         *  Palette mode.
+         * Allows setting palette_mode in the PPS.
+         */
+        uint32_t support_palette_mode           : 2;
+        /**
+         *  Dual filter.
+         * Allows setting enable_dual_filter in the SPS.
+         */
+        uint32_t support_dual_filter            : 2;
+        /**
+         *  Jnt compound.
+         * Allows setting enable_jnt_comp in the SPS.
+         */
+        uint32_t support_jnt_comp               : 2;
+        /**
+         *  Refrence frame mvs.
+         * Allows setting enable_ref_frame_mvs in the SPS.
+         */
+        uint32_t support_ref_frame_mvs          : 2;
+        /**
+         *  Super resolution.
+         * Allows setting enable_superres in the SPS.
+         */
+        uint32_t support_superres               : 2;
+        /**
+         *  Restoration.
+         * Allows setting enable_restoration in the SPS.
+         */
+        uint32_t support_restoration            : 2;
+        /**
+         *  Allow intraBC.
+         * Allows setting allow_intrabc in the PPS.
+         */
+        uint32_t support_allow_intrabc          : 2;
+        /**
+         *  Cdef channel strength.
+         * Allows setting cdef_y_strengths and cdef_uv_strengths in PPS.
+         */
+        uint32_t support_cdef_channel_strength  : 2;
+        /** Reserved bits for future, must be zero. */
+        uint32_t reserved                       : 4;
+    } bits;
+    uint32_t value;
+};
+
+union pipe_av1_enc_cap_features_ext1 {
+    struct {
+        /**
+         * Fields indicate which types of interpolation filter are supported.
+         * (interpolation_filter & 0x01) == 1: eight_tap filter is supported, 0: not.
+         * (interpolation_filter & 0x02) == 1: eight_tap_smooth filter is supported, 0: not.
+         * (interpolation_filter & 0x04) == 1: eight_sharp filter is supported, 0: not.
+         * (interpolation_filter & 0x08) == 1: bilinear filter is supported, 0: not.
+         * (interpolation_filter & 0x10) == 1: switchable filter is supported, 0: not.
+         */
+        uint32_t interpolation_filter          : 5;
+        /**
+         * Min segmentId block size accepted.
+         * Application need to send seg_id_block_size in PPS equal or larger than this value.
+         */
+        uint32_t min_segid_block_size_accepted : 8;
+        /**
+         * Type of segment feature supported.
+         * (segment_feature_support & 0x01) == 1: SEG_LVL_ALT_Q is supported, 0: not.
+         * (segment_feature_support & 0x02) == 1: SEG_LVL_ALT_LF_Y_V is supported, 0: not.
+         * (segment_feature_support & 0x04) == 1: SEG_LVL_ALT_LF_Y_H is supported, 0: not.
+         * (segment_feature_support & 0x08) == 1: SEG_LVL_ALT_LF_U is supported, 0: not.
+         * (segment_feature_support & 0x10) == 1: SEG_LVL_ALT_LF_V is supported, 0: not.
+         * (segment_feature_support & 0x20) == 1: SEG_LVL_REF_FRAME is supported, 0: not.
+         * (segment_feature_support & 0x40) == 1: SEG_LVL_SKIP is supported, 0: not.
+         * (segment_feature_support & 0x80) == 1: SEG_LVL_GLOBALMV is supported, 0: not.
+         */
+        uint32_t segment_feature_support       : 8;
+        /** Reserved bits for future, must be zero. */
+        uint32_t reserved                      : 11;
+    } bits;
+    uint32_t value;
+};
+
+union pipe_av1_enc_cap_features_ext2 {
+    struct {
+        /**
+        * Tile size bytes minus1.
+        * Specify the number of bytes needed to code tile size supported.
+        * This value need to be set in frame header obu.
+        */
+        uint32_t tile_size_bytes_minus1        : 2;
+        /**
+        * Tile size bytes minus1.
+        * Specify the fixed number of bytes needed to code syntax obu_size.
+        */
+        uint32_t obu_size_bytes_minus1         : 2;
+        /**
+         * tx_mode supported.
+         * (tx_mode_support & 0x01) == 1: ONLY_4X4 is supported, 0: not.
+         * (tx_mode_support & 0x02) == 1: TX_MODE_LARGEST is supported, 0: not.
+         * (tx_mode_support & 0x04) == 1: TX_MODE_SELECT is supported, 0: not.
+         */
+        uint32_t tx_mode_support               : 3;
+        /**
+         * Max tile num minus1.
+         * Specify the max number of tile supported by driver.
+         */
+        uint32_t max_tile_num_minus1           : 13;
+        /** Reserved bits for future, must be zero. */
+        uint32_t reserved                      : 12;
+    } bits;
+    uint32_t value;
+};
+
 #ifdef __cplusplus
 }
 #endif