Merge Mesa 20.0.8

With Mesa 20.1 even after the kernel change to do wbinvd on all cpus
sthen@ reported that hard hangs still occurred on his Haswell system
with inteldrm.

Mark Kane also reported seeing hangs on Ivy Bridge on bugs@.

Some systems/workloads seem to be more prone to triggering this than
others as I have not seen any hangs on Ivy Bridge and the only hangs
I saw on Haswell when running piglit went away with the wbinvd change.

It seems something is wrong with drm memory attributes or coherency in
the kernel and newer Mesa versions expect behaviour we don't have.

4 files changed, 30 insertions, 28 deletions

diff --git a/lib/mesa/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c b/lib/mesa/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index ec2fa3a56..ad746bd41 100644
--- a/lib/mesa/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/lib/mesa/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -31,7 +31,7 @@
 #include "util/os_time.h"
 #include "util/u_hash_table.h"
 #include "state_tracker/drm_driver.h"
-#include "drm-uapi/amdgpu_drm.h"
+#include <amdgpu_drm.h>
 #include <xf86drm.h>
 #include <stdio.h>
 #include <inttypes.h>
@@ -204,7 +204,7 @@ void amdgpu_bo_destroy(struct pb_buffer *_buf)
    simple_mtx_unlock(&ws->sws_list_lock);
 
    simple_mtx_lock(&ws->bo_export_table_lock);
-   _mesa_hash_table_remove_key(ws->bo_export_table, bo->bo);
+   util_hash_table_remove(ws->bo_export_table, bo->bo);
    simple_mtx_unlock(&ws->bo_export_table_lock);
 
    if (bo->initial_domain & RADEON_DOMAIN_VRAM_GTT) {
@@ -1223,10 +1223,6 @@ static unsigned eg_tile_split_rev(unsigned eg_tile_split)
    }
 }
 
-#define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT	44
-#define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK		0x1
-#define AMDGPU_TILING_DCC_MAX_COMPRESSED_BLOCK_SIZE_SHIFT  45
-#define AMDGPU_TILING_DCC_MAX_COMPRESSED_BLOCK_SIZE_MASK   0x3
 #define AMDGPU_TILING_SCANOUT_SHIFT		63
 #define AMDGPU_TILING_SCANOUT_MASK		0x1
 
@@ -1252,8 +1248,6 @@ static void amdgpu_buffer_get_metadata(struct pb_buffer *_buf,
       md->u.gfx9.dcc_offset_256B = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B);
       md->u.gfx9.dcc_pitch_max = AMDGPU_TILING_GET(tiling_flags, DCC_PITCH_MAX);
       md->u.gfx9.dcc_independent_64B = AMDGPU_TILING_GET(tiling_flags, DCC_INDEPENDENT_64B);
-      md->u.gfx9.dcc_independent_128B = AMDGPU_TILING_GET(tiling_flags, DCC_INDEPENDENT_128B);
-      md->u.gfx9.dcc_max_compressed_block_size = AMDGPU_TILING_GET(tiling_flags, DCC_MAX_COMPRESSED_BLOCK_SIZE);
       md->u.gfx9.scanout = AMDGPU_TILING_GET(tiling_flags, SCANOUT);
    } else {
       md->u.legacy.microtile = RADEON_LAYOUT_LINEAR;
@@ -1292,8 +1286,6 @@ static void amdgpu_buffer_set_metadata(struct pb_buffer *_buf,
       tiling_flags |= AMDGPU_TILING_SET(DCC_OFFSET_256B, md->u.gfx9.dcc_offset_256B);
       tiling_flags |= AMDGPU_TILING_SET(DCC_PITCH_MAX, md->u.gfx9.dcc_pitch_max);
       tiling_flags |= AMDGPU_TILING_SET(DCC_INDEPENDENT_64B, md->u.gfx9.dcc_independent_64B);
-      tiling_flags |= AMDGPU_TILING_SET(DCC_INDEPENDENT_128B, md->u.gfx9.dcc_independent_128B);
-      tiling_flags |= AMDGPU_TILING_SET(DCC_MAX_COMPRESSED_BLOCK_SIZE, md->u.gfx9.dcc_max_compressed_block_size);
       tiling_flags |= AMDGPU_TILING_SET(SCANOUT, md->u.gfx9.scanout);
    } else {
       if (md->u.legacy.macrotile == RADEON_LAYOUT_TILED)
@@ -1540,7 +1532,7 @@ static struct pb_buffer *amdgpu_bo_from_handle(struct radeon_winsys *rws,
 
    amdgpu_add_buffer_to_global_list(bo);
 
-   _mesa_hash_table_insert(ws->bo_export_table, bo->bo, bo);
+   util_hash_table_set(ws->bo_export_table, bo->bo, bo);
    simple_mtx_unlock(&ws->bo_export_table_lock);
 
    return &bo->base;
@@ -1623,7 +1615,7 @@ static bool amdgpu_bo_get_handle(struct radeon_winsys *rws,
 
  hash_table_set:
    simple_mtx_lock(&ws->bo_export_table_lock);
-   _mesa_hash_table_insert(ws->bo_export_table, bo->bo, bo);
+   util_hash_table_set(ws->bo_export_table, bo->bo, bo);
    simple_mtx_unlock(&ws->bo_export_table_lock);
 
    bo->is_shared = true;
diff --git a/lib/mesa/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h b/lib/mesa/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
index 26c14d8ec..507859c2d 100644
--- a/lib/mesa/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
+++ b/lib/mesa/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
@@ -30,7 +30,7 @@
 
 #include "amdgpu_bo.h"
 #include "util/u_memory.h"
-#include "drm-uapi/amdgpu_drm.h"
+#include <amdgpu_drm.h>
 
 struct amdgpu_ctx {
    struct amdgpu_winsys *ws;
diff --git a/lib/mesa/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c b/lib/mesa/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
index 7ac2a61bd..8b56f6956 100644
--- a/lib/mesa/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
+++ b/lib/mesa/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
@@ -36,7 +36,7 @@
 #include "util/u_hash_table.h"
 #include "util/hash_table.h"
 #include "util/xmlconfig.h"
-#include "drm-uapi/amdgpu_drm.h"
+#include <amdgpu_drm.h>
 #include <xf86drm.h>
 #include <stdio.h>
 #include <sys/stat.h>
@@ -48,7 +48,7 @@
 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS	0x1E
 #endif
 
-static struct hash_table *dev_tab = NULL;
+static struct util_hash_table *dev_tab = NULL;
 static simple_mtx_t dev_tab_mutex = _SIMPLE_MTX_INITIALIZER_NP;
 
 DEBUG_GET_ONCE_BOOL_OPTION(all_bos, "RADEON_ALL_BOS", false)
@@ -102,7 +102,7 @@ static bool do_winsys_init(struct amdgpu_winsys *ws,
 
    handle_env_var_force_family(ws);
 
-   ws->addrlib = ac_addrlib_create(&ws->info, &ws->amdinfo, &ws->info.max_alignment);
+   ws->addrlib = amdgpu_addr_create(&ws->info, &ws->amdinfo, &ws->info.max_alignment);
    if (!ws->addrlib) {
       fprintf(stderr, "amdgpu: Cannot create addrlib.\n");
       goto fail;
@@ -139,12 +139,12 @@ static void do_winsys_deinit(struct amdgpu_winsys *ws)
          pb_slabs_deinit(&ws->bo_slabs[i]);
    }
    pb_cache_deinit(&ws->bo_cache);
-   _mesa_hash_table_destroy(ws->bo_export_table, NULL);
+   util_hash_table_destroy(ws->bo_export_table);
    simple_mtx_destroy(&ws->sws_list_lock);
    simple_mtx_destroy(&ws->global_bo_list_lock);
    simple_mtx_destroy(&ws->bo_export_table_lock);
 
-   ac_addrlib_destroy(ws->addrlib);
+   AddrDestroy(ws->addrlib);
    amdgpu_device_deinitialize(ws->dev);
    FREE(ws);
 }
@@ -165,9 +165,9 @@ static void amdgpu_winsys_destroy(struct radeon_winsys *rws)
 
    destroy = pipe_reference(&ws->reference, NULL);
    if (destroy && dev_tab) {
-      _mesa_hash_table_remove_key(dev_tab, ws->dev);
-      if (_mesa_hash_table_num_entries(dev_tab) == 0) {
-         _mesa_hash_table_destroy(dev_tab, NULL);
+      util_hash_table_remove(dev_tab, ws->dev);
+      if (util_hash_table_count(dev_tab) == 0) {
+         util_hash_table_destroy(dev_tab);
          dev_tab = NULL;
       }
    }
@@ -269,6 +269,16 @@ static bool amdgpu_read_registers(struct radeon_winsys *rws,
                                    0xffffffff, 0, out) == 0;
 }
 
+static unsigned hash_pointer(void *key)
+{
+   return _mesa_hash_pointer(key);
+}
+
+static int compare_pointers(void *key1, void *key2)
+{
+   return key1 != key2;
+}
+
 static bool amdgpu_winsys_unref(struct radeon_winsys *rws)
 {
    struct amdgpu_screen_winsys *sws = amdgpu_screen_winsys(rws);
@@ -336,8 +346,7 @@ amdgpu_winsys_create(int fd, const struct pipe_screen_config *config,
    struct amdgpu_screen_winsys *ws;
    struct amdgpu_winsys *aws;
    amdgpu_device_handle dev;
-   uint32_t drm_major, drm_minor;
-   int r;
+   uint32_t drm_major, drm_minor, r;
 
    ws = CALLOC_STRUCT(amdgpu_screen_winsys);
    if (!ws)
@@ -349,7 +358,7 @@ amdgpu_winsys_create(int fd, const struct pipe_screen_config *config,
    /* Look up the winsys from the dev table. */
    simple_mtx_lock(&dev_tab_mutex);
    if (!dev_tab)
-      dev_tab = util_hash_table_create_ptr_keys();
+      dev_tab = util_hash_table_create(hash_pointer, compare_pointers);
 
    /* Initialize the amdgpu device. This should always return the same pointer
     * for the same fd. */
@@ -453,7 +462,7 @@ amdgpu_winsys_create(int fd, const struct pipe_screen_config *config,
       pipe_reference_init(&aws->reference, 1);
 
       list_inithead(&aws->global_bo_list);
-      aws->bo_export_table = util_hash_table_create_ptr_keys();
+      aws->bo_export_table = util_hash_table_create(hash_pointer, compare_pointers);
 
       (void) simple_mtx_init(&aws->sws_list_lock, mtx_plain);
       (void) simple_mtx_init(&aws->global_bo_list_lock, mtx_plain);
@@ -467,7 +476,7 @@ amdgpu_winsys_create(int fd, const struct pipe_screen_config *config,
          return NULL;
       }
 
-      _mesa_hash_table_insert(dev_tab, dev, aws);
+      util_hash_table_set(dev_tab, dev, aws);
 
       if (aws->reserve_vmid) {
          r = amdgpu_vm_reserve_vmid(dev, 0);
diff --git a/lib/mesa/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h b/lib/mesa/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
index 42bc8846d..a22be6086 100644
--- a/lib/mesa/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
+++ b/lib/mesa/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
@@ -31,6 +31,7 @@
 #include "pipebuffer/pb_cache.h"
 #include "pipebuffer/pb_slab.h"
 #include "gallium/drivers/radeon/radeon_winsys.h"
+#include "addrlib/inc/addrinterface.h"
 #include "util/simple_mtx.h"
 #include "util/u_queue.h"
 #include <amdgpu.h>
@@ -78,7 +79,7 @@ struct amdgpu_winsys {
    struct util_queue cs_queue;
 
    struct amdgpu_gpu_info amdinfo;
-   struct ac_addrlib *addrlib;
+   ADDR_HANDLE addrlib;
 
    bool check_vm;
    bool debug_all_bos;
@@ -98,7 +99,7 @@ struct amdgpu_winsys {
 
    /* For returning the same amdgpu_winsys_bo instance for exported
     * and re-imported buffers. */
-   struct hash_table *bo_export_table;
+   struct util_hash_table *bo_export_table;
    simple_mtx_t bo_export_table_lock;
 };