import Mesa 11.0.6

4 files changed, 4 insertions, 52 deletions

diff --git a/lib/mesa/src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.cpp b/lib/mesa/src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.cpp
index 570216241..7393953c1 100644
--- a/lib/mesa/src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.cpp
+++ b/lib/mesa/src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.cpp
@@ -896,49 +896,6 @@ BOOL_32 CIAddrLib::HwlOverrideTileMode(
 
 /**
 ***************************************************************************************************
-*   CiAddrLib::GetPrtSwitchP4Threshold
-*
-*   @brief
-*       Return the threshold of switching to P4_* instead of P16_* for PRT resources
-***************************************************************************************************
-*/
-UINT_32 CIAddrLib::GetPrtSwitchP4Threshold() const
-{
-    UINT_32 threshold;
-
-    switch (m_pipes)
-    {
-        case 8:
-            threshold = 32;
-            break;
-        case 16:
-            if (m_settings.isFiji)
-            {
-                threshold = 16;
-            }
-            else if (m_settings.isHawaii)
-            {
-                threshold = 8;
-            }
-            else
-            {
-                ///@todo add for possible new ASICs.
-                ADDR_ASSERT_ALWAYS();
-                threshold = 16;
-            }
-            break;
-        default:
-            ///@todo add for possible new ASICs.
-            ADDR_ASSERT_ALWAYS();
-            threshold = 32;
-            break;
-    }
-
-    return threshold;
-}
-
-/**
-***************************************************************************************************
 *   CIAddrLib::HwlSetupTileInfo
 *
 *   @brief
@@ -1166,7 +1123,7 @@ VOID CIAddrLib::HwlSetupTileInfo(
             {
                 UINT_32 bytesXSamples = bpp * numSamples / 8;
                 UINT_32 bytesXThickness = bpp * thickness / 8;
-                UINT_32 switchP4Threshold = GetPrtSwitchP4Threshold();
+                UINT_32 switchP4Threshold = (m_pipes == 16) ? 8 : 32;
 
                 if ((bytesXSamples > switchP4Threshold) || (bytesXThickness > switchP4Threshold))
                 {
diff --git a/lib/mesa/src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.h b/lib/mesa/src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.h
index 4cbe9706b..451508619 100644
--- a/lib/mesa/src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.h
+++ b/lib/mesa/src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.h
@@ -167,8 +167,6 @@ private:
     VOID ReadGbMacroTileCfg(
         UINT_32 regValue, ADDR_TILEINFO* pCfg) const;
 
-    UINT_32 GetPrtSwitchP4Threshold() const;
-
     BOOL_32 InitTileSettingTable(
         const UINT_32 *pSetting, UINT_32 noOfEntries);
 
diff --git a/lib/mesa/src/gallium/winsys/amdgpu/drm/addrlib/r800/egbaddrlib.cpp b/lib/mesa/src/gallium/winsys/amdgpu/drm/addrlib/r800/egbaddrlib.cpp
index 088b64593..b1e008b83 100644
--- a/lib/mesa/src/gallium/winsys/amdgpu/drm/addrlib/r800/egbaddrlib.cpp
+++ b/lib/mesa/src/gallium/winsys/amdgpu/drm/addrlib/r800/egbaddrlib.cpp
@@ -352,7 +352,6 @@ BOOL_32 EgBasedAddrLib::ComputeSurfaceInfoMicroTiled(
     ComputeSurfaceAlignmentsMicroTiled(expTileMode,
                                        pIn->bpp,
                                        pIn->flags,
-                                       pIn->mipLevel,
                                        numSamples,
                                        &pOut->baseAlign,
                                        &pOut->pitchAlign,
@@ -648,7 +647,6 @@ BOOL_32 EgBasedAddrLib::ComputeSurfaceAlignmentsMicroTiled(
     AddrTileMode        tileMode,          ///< [in] tile mode
     UINT_32             bpp,               ///< [in] bits per pixel
     ADDR_SURFACE_FLAGS  flags,             ///< [in] surface flags
-    UINT_32             mipLevel,          ///< [in] mip level
     UINT_32             numSamples,        ///< [in] number of samples
     UINT_32*            pBaseAlign,        ///< [out] base address alignment in bytes
     UINT_32*            pPitchAlign,       ///< [out] pitch alignment in pixels
@@ -671,10 +669,10 @@ BOOL_32 EgBasedAddrLib::ComputeSurfaceAlignmentsMicroTiled(
     // ECR#393489
     // Workaround 2 for 1D tiling -  There is HW bug for Carrizo
     // where it requires the following alignments for 1D tiling.
-    if (flags.czDispCompatible && (mipLevel == 0))
+    if (flags.czDispCompatible)
     {
         *pBaseAlign  = PowTwoAlign(*pBaseAlign, 4096);                         //Base address MOD 4096 = 0
-        *pPitchAlign = PowTwoAlign(*pPitchAlign, 512 / (BITS_TO_BYTES(bpp))); //(8 lines * pitch * bytes per pixel) MOD 4096 = 0
+        *pPitchAlign = PowTwoAlign(*pPitchAlign, 512 >> (BITS_TO_BYTES(bpp))); //(8 lines * pitch * bytes per pixel) MOD 4096 = 0
     }
     // end Carrizo workaround for 1D tilling
 
diff --git a/lib/mesa/src/gallium/winsys/amdgpu/drm/addrlib/r800/egbaddrlib.h b/lib/mesa/src/gallium/winsys/amdgpu/drm/addrlib/r800/egbaddrlib.h
index 25e38964b..84adb66ee 100644
--- a/lib/mesa/src/gallium/winsys/amdgpu/drm/addrlib/r800/egbaddrlib.h
+++ b/lib/mesa/src/gallium/winsys/amdgpu/drm/addrlib/r800/egbaddrlib.h
@@ -315,8 +315,7 @@ private:
         UINT_32* pBaseAlign, UINT_32* pPitchAlign, UINT_32* pHeightAlign) const;
 
     BOOL_32 ComputeSurfaceAlignmentsMicroTiled(
-        AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
-        UINT_32 mipLevel, UINT_32 numSamples,
+        AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, UINT_32 numSamples,
         UINT_32* pBaseAlign, UINT_32* pPitchAlign, UINT_32* pHeightAlign) const;
 
     BOOL_32 ComputeSurfaceAlignmentsMacroTiled(