diff options
author | Jonathan Gray <jsg@cvs.openbsd.org> | 2016-12-11 08:40:05 +0000 |
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committer | Jonathan Gray <jsg@cvs.openbsd.org> | 2016-12-11 08:40:05 +0000 |
commit | 21ab4c9f31674b113c24177398ed39f29b7cd8e6 (patch) | |
tree | 8be392d7a792d9663c2586396be77bfd506f5164 /lib/mesa/src/intel/isl | |
parent | a8f0a7916e26e550dd2a26e7188835c481978004 (diff) |
Import Mesa 13.0.2
Diffstat (limited to 'lib/mesa/src/intel/isl')
21 files changed, 12677 insertions, 0 deletions
diff --git a/lib/mesa/src/intel/isl/README b/lib/mesa/src/intel/isl/README new file mode 100644 index 000000000..1ab4313fc --- /dev/null +++ b/lib/mesa/src/intel/isl/README @@ -0,0 +1,113 @@ +Intel Surface Layout + +Introduction +============ +isl is a small library that calculates the layout of Intel GPU surfaces, queries +those layouts, and queries the properties of surface formats. + + +Independence from User APIs +=========================== +isl's API is independent of any user-facing graphics API, such as OpenGL and +Vulkan. This independence allows isl to be used a shared component by multiple +Intel drivers. + +Rather than mimic the user-facing APIs, the isl API attempts to reflect Intel +hardware: the actual memory layout of Intel GPU surfaces and how one programs +the GPU to use those surfaces. For example: + + - The tokens of `enum isl_format` (such as `ISL_FORMAT_R8G8B8A8_UNORM`) + match those of the hardware enum `SURFACE_FORMAT` rather than the OpenGL + or Vulkan format tokens. And the values of `isl_format` and + `SURFACE_FORMAT` are identical. + + - The OpenGL and Vulkan APIs contain depth and stencil formats. However the + hardware enum `SURFACE_FORMAT` does not, and therefore neither does `enum + isl_format`. Rather than define new pixel formats that have no hardware + counterpart, isl records the intent to use a surface as a depth or stencil + buffer with the usage flags `ISL_SURF_USAGE_DEPTH_BIT` and + `ISL_SURF_USAGE_STENCIL_BIT`. + + - `struct isl_surf` distinguishes between the surface's logical dimension + from the user API's perspective (`enum isl_surf_dim`, which may be 1D, 2D, + or 3D) and the layout of those dimensions in memory (`enum isl_dim_layout`). + + +Surface Units +============= + +Intro +----- +ISL takes care in its equations to correctly handle conversion among surface +units (such as pixels and compression blocks) and to carefully distinguish +between a surface's logical layout in the client API and its physical layout +in memory. + +Symbol names often explicitly declare their unit with a suffix: + + - px: logical pixels + - sa: physical surface samples + - el: physical surface elements + - sa_rows: rows of physical surface samples + - el_rows: rows of physical surface elements + +Logical units are independent of hardware generation and are closely related +to the user-facing API (OpenGL and Vulkan). Physical units are dependent on +hardware generation and reflect the surface's layout in memory. + +Definitions +----------- +- Logical Pixels (px): + + The surface's layout from the perspective of the client API (OpenGL and + Vulkan) is in units of logical pixels. Logical pixels are independent of the + surface's layout in memory. + + A surface's width and height, in units of logical pixels, is not affected by + the surface's sample count. For example, consider a VkImage created with + VkImageCreateInfo{width=w0, height=h0, samples=s0}. The surface's width and + height at level 0 is, in units of logical pixels, w0 and h0 regardless of + the value of s0. + + For example, the logical array length of a 3D surface is always 1, even on + Gen9 where the surface's memory layout is that of an array surface + (ISL_DIM_LAYOUT_GEN4_2D). + +- Physical Surface Samples (sa): + + For a multisampled surface, this unit has the obvious meaning. + A singlesampled surface, from ISL's perspective, is simply a multisampled + surface whose sample count is 1. + + For example, consider a 2D single-level non-array surface with samples=4, + width_px=64, and height_px=64 (note that the suffix 'px' indicates logical + pixels). If the surface's multisample layout is ISL_MSAA_LAYOUT_INTERLEAVED, + then the extent of level 0 is, in units of physical surface samples, + width_sa=128, height_sa=128, depth_sa=1, array_length_sa=1. If + ISL_MSAA_LAYOUT_ARRAY, then width_sa=64, height_sa=64, depth_sa=1, + array_length_sa=4. + +- Physical Surface Elements (el): + + This unit allows ISL to treat compressed and uncompressed formats + identically in many calculations. + + If the surface's pixel format is compressed, such as ETC2, then a surface + element is equivalent to a compression block. If uncompressed, then + a surface element is equivalent to a surface sample. As a corollary, for + a given surface a surface element is at least as large as a surface sample. + +Errata +------ +ISL acquired the term 'surface element' from the Broadwell PRM [1], which +defines it as follows: + + An element is defined as a pixel in uncompresed surface formats, and as + a compression block in compressed surface formats. For MSFMT_DEPTH_STENCIL + type multisampled surfaces, an element is a sample. + + +References +========== +[1]: Broadwell PRM >> Volume 2d: Command Reference: Structures >> + RENDER_SURFACE_STATE Surface Vertical Alignment (p325) diff --git a/lib/mesa/src/intel/isl/gen_format_layout.py b/lib/mesa/src/intel/isl/gen_format_layout.py new file mode 100644 index 000000000..f52e45499 --- /dev/null +++ b/lib/mesa/src/intel/isl/gen_format_layout.py @@ -0,0 +1,207 @@ +# encoding=utf-8 +# Copyright © 2016 Intel Corporation + +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: + +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. + +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. + +"""Generates isl_format_layout.c.""" + +from __future__ import absolute_import, division, print_function +import argparse +import csv +import re +import textwrap + +from mako import template + +# Load the template, ensure that __future__.division is imported, and set the +# bytes encoding to be utf-8. This last bit is important to getting simple +# consistent behavior for python 3 when we get there. +TEMPLATE = template.Template( + text=textwrap.dedent("""\ + /* This file is autogenerated by gen_format_layout.py. DO NOT EDIT! */ + + /* + * Copyright 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + + #include "isl/isl.h" + + const struct isl_format_layout + isl_format_layouts[] = { + % for format in formats: + [ISL_FORMAT_${format.name}] = { + .format = ISL_FORMAT_${format.name}, + .name = "ISL_FORMAT_${format.name}", + .bpb = ${format.bpb}, + .bw = ${format.bw}, + .bh = ${format.bh}, + .bd = ${format.bd}, + .channels = { + % for mask in ['r', 'g', 'b', 'a', 'l', 'i', 'p']: + <% channel = getattr(format, mask, None) %>\\ + % if channel.type is not None: + .${mask} = { ISL_${channel.type}, ${channel.size} }, + % else: + .${mask} = {}, + % endif + % endfor + }, + .colorspace = ISL_COLORSPACE_${format.colorspace}, + .txc = ISL_TXC_${format.txc}, + }, + + % endfor + }; + """), + future_imports=['division'], + output_encoding='utf-8') + + +class Channel(object): + """Class representing a Channel. + + Converts the csv encoded data into the format that the template (and thus + the consuming C code) expects. + + """ + # If the csv file grew very large this class could be put behind a factory + # to increase efficiency. Right now though it's fast enough that It didn't + # seem worthwhile to add all of the boilerplate + _types = { + 'x': 'void', + 'r': 'raw', + 'un': 'unorm', + 'sn': 'snorm', + 'uf': 'ufloat', + 'sf': 'sfloat', + 'ux': 'ufixed', + 'sx': 'sfixed', + 'ui': 'uint', + 'si': 'sint', + 'us': 'uscaled', + 'ss': 'sscaled', + } + _splitter = re.compile(r'\s*(?P<type>[a-z]+)(?P<size>[0-9]+)') + + def __init__(self, line): + # If the line is just whitespace then just set everything to None to + # save on the regex cost and let the template skip on None. + if line.isspace(): + self.size = None + self.type = None + else: + grouped = self._splitter.match(line) + self.type = self._types[grouped.group('type')].upper() + self.size = grouped.group('size') + + +class Format(object): + """Class taht contains all values needed by the template.""" + def __init__(self, line): + # pylint: disable=invalid-name + self.name = line[0].strip() + + # Future division makes this work in python 2. + self.bpb = int(line[1]) + self.bw = line[2].strip() + self.bh = line[3].strip() + self.bd = line[4].strip() + self.r = Channel(line[5]) + self.g = Channel(line[6]) + self.b = Channel(line[7]) + self.a = Channel(line[8]) + self.l = Channel(line[9]) + self.i = Channel(line[10]) + self.p = Channel(line[11]) + + # alpha doesn't have a colorspace of it's own. + self.colorspace = line[12].strip().upper() + if self.colorspace in ['', 'ALPHA']: + self.colorspace = 'NONE' + + # This sets it to the line value, or if it's an empty string 'NONE' + self.txc = line[13].strip().upper() or 'NONE' + + +def reader(csvfile): + """Wrapper around csv.reader that skips comments and blanks.""" + # csv.reader actually reads the file one line at a time (it was designed to + # open excel generated sheets), so hold the file until all of the lines are + # read. + with open(csvfile, 'r') as f: + for line in csv.reader(f): + if line and not line[0].startswith('#'): + yield line + + +def main(): + """Main function.""" + parser = argparse.ArgumentParser() + parser.add_argument('--csv', action='store', help='The CSV file to parse.') + parser.add_argument( + '--out', + action='store', + help='The location to put the generated C file.') + args = parser.parse_args() + + # This generator opens and writes the file itself, and it does so in bytes + # mode. This solves both python 2 vs 3 problems and solves the locale + # problem: Unicode can be rendered even if the shell calling this script + # doesn't. + with open(args.out, 'wb') as f: + try: + # This basically does lazy evaluation and initialization, which + # saves on memory and startup overhead. + f.write(TEMPLATE.render( + formats=(Format(l) for l in reader(args.csv)))) + except Exception: + # In the even there's an error this imports some helpers from mako + # to print a useful stack trace and prints it, then exits with + # status 1, if python is run with debug; otherwise it just raises + # the exception + if __debug__: + import sys + from mako import exceptions + print(exceptions.text_error_template().render(), + file=sys.stderr) + sys.exit(1) + raise + + +if __name__ == '__main__': + main() diff --git a/lib/mesa/src/intel/isl/isl.c b/lib/mesa/src/intel/isl/isl.c new file mode 100644 index 000000000..32463b129 --- /dev/null +++ b/lib/mesa/src/intel/isl/isl.c @@ -0,0 +1,1852 @@ +/* + * Copyright 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#include <assert.h> +#include <stdarg.h> +#include <stdio.h> + +#include "isl.h" +#include "isl_gen4.h" +#include "isl_gen6.h" +#include "isl_gen7.h" +#include "isl_gen8.h" +#include "isl_gen9.h" +#include "isl_priv.h" + +void PRINTFLIKE(3, 4) UNUSED +__isl_finishme(const char *file, int line, const char *fmt, ...) +{ + va_list ap; + char buf[512]; + + va_start(ap, fmt); + vsnprintf(buf, sizeof(buf), fmt, ap); + va_end(ap); + + fprintf(stderr, "%s:%d: FINISHME: %s\n", file, line, buf); +} + +void +isl_device_init(struct isl_device *dev, + const struct gen_device_info *info, + bool has_bit6_swizzling) +{ + dev->info = info; + dev->use_separate_stencil = ISL_DEV_GEN(dev) >= 6; + dev->has_bit6_swizzling = has_bit6_swizzling; + + /* The ISL_DEV macros may be defined in the CFLAGS, thus hardcoding some + * device properties at buildtime. Verify that the macros with the device + * properties chosen during runtime. + */ + ISL_DEV_GEN_SANITIZE(dev); + ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(dev); + + /* Did we break hiz or stencil? */ + if (ISL_DEV_USE_SEPARATE_STENCIL(dev)) + assert(info->has_hiz_and_separate_stencil); + if (info->must_use_separate_stencil) + assert(ISL_DEV_USE_SEPARATE_STENCIL(dev)); +} + +/** + * @brief Query the set of multisamples supported by the device. + * + * This function always returns non-zero, as ISL_SAMPLE_COUNT_1_BIT is always + * supported. + */ +isl_sample_count_mask_t ATTRIBUTE_CONST +isl_device_get_sample_counts(struct isl_device *dev) +{ + if (ISL_DEV_GEN(dev) >= 9) { + return ISL_SAMPLE_COUNT_1_BIT | + ISL_SAMPLE_COUNT_2_BIT | + ISL_SAMPLE_COUNT_4_BIT | + ISL_SAMPLE_COUNT_8_BIT | + ISL_SAMPLE_COUNT_16_BIT; + } else if (ISL_DEV_GEN(dev) >= 8) { + return ISL_SAMPLE_COUNT_1_BIT | + ISL_SAMPLE_COUNT_2_BIT | + ISL_SAMPLE_COUNT_4_BIT | + ISL_SAMPLE_COUNT_8_BIT; + } else if (ISL_DEV_GEN(dev) >= 7) { + return ISL_SAMPLE_COUNT_1_BIT | + ISL_SAMPLE_COUNT_4_BIT | + ISL_SAMPLE_COUNT_8_BIT; + } else if (ISL_DEV_GEN(dev) >= 6) { + return ISL_SAMPLE_COUNT_1_BIT | + ISL_SAMPLE_COUNT_4_BIT; + } else { + return ISL_SAMPLE_COUNT_1_BIT; + } +} + +/** + * @param[out] info is written only on success + */ +static bool +isl_tiling_get_info(const struct isl_device *dev, + enum isl_tiling tiling, + uint32_t format_bpb, + struct isl_tile_info *tile_info) +{ + const uint32_t bs = format_bpb / 8; + struct isl_extent2d logical_el, phys_B; + + if (tiling != ISL_TILING_LINEAR && !isl_is_pow2(format_bpb)) { + /* It is possible to have non-power-of-two formats in a tiled buffer. + * The easiest way to handle this is to treat the tile as if it is three + * times as wide. This way no pixel will ever cross a tile boundary. + * This really only works on legacy X and Y tiling formats. + */ + assert(tiling == ISL_TILING_X || tiling == ISL_TILING_Y0); + assert(bs % 3 == 0 && isl_is_pow2(format_bpb / 3)); + return isl_tiling_get_info(dev, tiling, format_bpb / 3, tile_info); + } + + switch (tiling) { + case ISL_TILING_LINEAR: + assert(bs > 0); + logical_el = isl_extent2d(1, 1); + phys_B = isl_extent2d(bs, 1); + break; + + case ISL_TILING_X: + assert(bs > 0); + logical_el = isl_extent2d(512 / bs, 8); + phys_B = isl_extent2d(512, 8); + break; + + case ISL_TILING_Y0: + assert(bs > 0); + logical_el = isl_extent2d(128 / bs, 32); + phys_B = isl_extent2d(128, 32); + break; + + case ISL_TILING_W: + assert(bs == 1); + logical_el = isl_extent2d(64, 64); + /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfacePitch: + * + * "If the surface is a stencil buffer (and thus has Tile Mode set + * to TILEMODE_WMAJOR), the pitch must be set to 2x the value + * computed based on width, as the stencil buffer is stored with two + * rows interleaved." + * + * This, together with the fact that stencil buffers are referred to as + * being Y-tiled in the PRMs for older hardware implies that the + * physical size of a W-tile is actually the same as for a Y-tile. + */ + phys_B = isl_extent2d(128, 32); + break; + + case ISL_TILING_Yf: + case ISL_TILING_Ys: { + if (ISL_DEV_GEN(dev) < 9) + return false; + + if (!isl_is_pow2(bs)) + return false; + + bool is_Ys = tiling == ISL_TILING_Ys; + + assert(bs > 0); + unsigned width = 1 << (6 + (ffs(bs) / 2) + (2 * is_Ys)); + unsigned height = 1 << (6 - (ffs(bs) / 2) + (2 * is_Ys)); + + logical_el = isl_extent2d(width / bs, height); + phys_B = isl_extent2d(width, height); + break; + } + + case ISL_TILING_HIZ: + /* HiZ buffers are required to have ISL_FORMAT_HIZ which is an 8x4 + * 128bpb format. The tiling has the same physical dimensions as + * Y-tiling but actually has two HiZ columns per Y-tiled column. + */ + assert(bs == 16); + logical_el = isl_extent2d(16, 16); + phys_B = isl_extent2d(128, 32); + break; + + case ISL_TILING_CCS: + /* CCS surfaces are required to have one of the GENX_CCS_* formats which + * have a block size of 1 or 2 bits per block and each CCS element + * corresponds to one cache-line pair in the main surface. From the Sky + * Lake PRM Vol. 12 in the section on planes: + * + * "The Color Control Surface (CCS) contains the compression status + * of the cache-line pairs. The compression state of the cache-line + * pair is specified by 2 bits in the CCS. Each CCS cache-line + * represents an area on the main surface of 16x16 sets of 128 byte + * Y-tiled cache-line-pairs. CCS is always Y tiled." + * + * The CCS being Y-tiled implies that it's an 8x8 grid of cache-lines. + * Since each cache line corresponds to a 16x16 set of cache-line pairs, + * that yields total tile area of 128x128 cache-line pairs or CCS + * elements. On older hardware, each CCS element is 1 bit and the tile + * is 128x256 elements. + */ + assert(format_bpb == 1 || format_bpb == 2); + logical_el = isl_extent2d(128, 256 / format_bpb); + phys_B = isl_extent2d(128, 32); + break; + + default: + unreachable("not reached"); + } /* end switch */ + + *tile_info = (struct isl_tile_info) { + .tiling = tiling, + .format_bpb = format_bpb, + .logical_extent_el = logical_el, + .phys_extent_B = phys_B, + }; + + return true; +} + +/** + * @param[out] tiling is set only on success + */ +static bool +isl_surf_choose_tiling(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + enum isl_tiling *tiling) +{ + isl_tiling_flags_t tiling_flags = info->tiling_flags; + + /* HiZ surfaces always use the HiZ tiling */ + if (info->usage & ISL_SURF_USAGE_HIZ_BIT) { + assert(info->format == ISL_FORMAT_HIZ); + assert(tiling_flags == ISL_TILING_HIZ_BIT); + *tiling = ISL_TILING_HIZ; + return true; + } + + /* CCS surfaces always use the CCS tiling */ + if (info->usage & ISL_SURF_USAGE_CCS_BIT) { + assert(isl_format_get_layout(info->format)->txc == ISL_TXC_CCS); + assert(tiling_flags == ISL_TILING_CCS_BIT); + *tiling = ISL_TILING_CCS; + return true; + } + + if (ISL_DEV_GEN(dev) >= 6) { + isl_gen6_filter_tiling(dev, info, &tiling_flags); + } else { + isl_finishme("%s: gen%u", __func__, ISL_DEV_GEN(dev)); + isl_gen6_filter_tiling(dev, info, &tiling_flags); + } + + #define CHOOSE(__tiling) \ + do { \ + if (tiling_flags & (1u << (__tiling))) { \ + *tiling = (__tiling); \ + return true; \ + } \ + } while (0) + + /* Of the tiling modes remaining, choose the one that offers the best + * performance. + */ + + if (info->dim == ISL_SURF_DIM_1D) { + /* Prefer linear for 1D surfaces because they do not benefit from + * tiling. To the contrary, tiling leads to wasted memory and poor + * memory locality due to the swizzling and alignment restrictions + * required in tiled surfaces. + */ + CHOOSE(ISL_TILING_LINEAR); + } + + CHOOSE(ISL_TILING_Ys); + CHOOSE(ISL_TILING_Yf); + CHOOSE(ISL_TILING_Y0); + CHOOSE(ISL_TILING_X); + CHOOSE(ISL_TILING_W); + CHOOSE(ISL_TILING_LINEAR); + + #undef CHOOSE + + /* No tiling mode accomodates the inputs. */ + return false; +} + +static bool +isl_choose_msaa_layout(const struct isl_device *dev, + const struct isl_surf_init_info *info, + enum isl_tiling tiling, + enum isl_msaa_layout *msaa_layout) +{ + if (ISL_DEV_GEN(dev) >= 8) { + return isl_gen8_choose_msaa_layout(dev, info, tiling, msaa_layout); + } else if (ISL_DEV_GEN(dev) >= 7) { + return isl_gen7_choose_msaa_layout(dev, info, tiling, msaa_layout); + } else if (ISL_DEV_GEN(dev) >= 6) { + return isl_gen6_choose_msaa_layout(dev, info, tiling, msaa_layout); + } else { + return isl_gen4_choose_msaa_layout(dev, info, tiling, msaa_layout); + } +} + +struct isl_extent2d +isl_get_interleaved_msaa_px_size_sa(uint32_t samples) +{ + assert(isl_is_pow2(samples)); + + /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level + * Sizes (p133): + * + * If the surface is multisampled and it is a depth or stencil surface + * or Multisampled Surface StorageFormat in SURFACE_STATE is + * MSFMT_DEPTH_STENCIL, W_L and H_L must be adjusted as follows before + * proceeding: [...] + */ + return (struct isl_extent2d) { + .width = 1 << ((ffs(samples) - 0) / 2), + .height = 1 << ((ffs(samples) - 1) / 2), + }; +} + +static void +isl_msaa_interleaved_scale_px_to_sa(uint32_t samples, + uint32_t *width, uint32_t *height) +{ + const struct isl_extent2d px_size_sa = + isl_get_interleaved_msaa_px_size_sa(samples); + + if (width) + *width = isl_align(*width, 2) * px_size_sa.width; + if (height) + *height = isl_align(*height, 2) * px_size_sa.height; +} + +static enum isl_array_pitch_span +isl_choose_array_pitch_span(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + enum isl_dim_layout dim_layout, + const struct isl_extent4d *phys_level0_sa) +{ + switch (dim_layout) { + case ISL_DIM_LAYOUT_GEN9_1D: + case ISL_DIM_LAYOUT_GEN4_2D: + if (ISL_DEV_GEN(dev) >= 8) { + /* QPitch becomes programmable in Broadwell. So choose the + * most compact QPitch possible in order to conserve memory. + * + * From the Broadwell PRM >> Volume 2d: Command Reference: Structures + * >> RENDER_SURFACE_STATE Surface QPitch (p325): + * + * - Software must ensure that this field is set to a value + * sufficiently large such that the array slices in the surface + * do not overlap. Refer to the Memory Data Formats section for + * information on how surfaces are stored in memory. + * + * - This field specifies the distance in rows between array + * slices. It is used only in the following cases: + * + * - Surface Array is enabled OR + * - Number of Mulitsamples is not NUMSAMPLES_1 and + * Multisampled Surface Storage Format set to MSFMT_MSS OR + * - Surface Type is SURFTYPE_CUBE + */ + return ISL_ARRAY_PITCH_SPAN_COMPACT; + } else if (ISL_DEV_GEN(dev) >= 7) { + /* Note that Ivybridge introduces + * RENDER_SURFACE_STATE.SurfaceArraySpacing, which provides the + * driver more control over the QPitch. + */ + + if (phys_level0_sa->array_len == 1) { + /* The hardware will never use the QPitch. So choose the most + * compact QPitch possible in order to conserve memory. + */ + return ISL_ARRAY_PITCH_SPAN_COMPACT; + } + + if (isl_surf_usage_is_depth_or_stencil(info->usage) || + (info->usage & ISL_SURF_USAGE_HIZ_BIT)) { + /* From the Ivybridge PRM >> Volume 1 Part 1: Graphics Core >> + * Section 6.18.4.7: Surface Arrays (p112): + * + * If Surface Array Spacing is set to ARYSPC_FULL (note that + * the depth buffer and stencil buffer have an implied value of + * ARYSPC_FULL): + */ + return ISL_ARRAY_PITCH_SPAN_FULL; + } + + if (info->levels == 1) { + /* We are able to set RENDER_SURFACE_STATE.SurfaceArraySpacing + * to ARYSPC_LOD0. + */ + return ISL_ARRAY_PITCH_SPAN_COMPACT; + } + + return ISL_ARRAY_PITCH_SPAN_FULL; + } else if ((ISL_DEV_GEN(dev) == 5 || ISL_DEV_GEN(dev) == 6) && + ISL_DEV_USE_SEPARATE_STENCIL(dev) && + isl_surf_usage_is_stencil(info->usage)) { + /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1: + * Graphics Core >> Section 7.18.3.7: Surface Arrays: + * + * The separate stencil buffer does not support mip mapping, thus + * the storage for LODs other than LOD 0 is not needed. + */ + assert(info->levels == 1); + assert(phys_level0_sa->array_len == 1); + return ISL_ARRAY_PITCH_SPAN_COMPACT; + } else { + if ((ISL_DEV_GEN(dev) == 5 || ISL_DEV_GEN(dev) == 6) && + ISL_DEV_USE_SEPARATE_STENCIL(dev) && + isl_surf_usage_is_stencil(info->usage)) { + /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1: + * Graphics Core >> Section 7.18.3.7: Surface Arrays: + * + * The separate stencil buffer does not support mip mapping, + * thus the storage for LODs other than LOD 0 is not needed. + */ + assert(info->levels == 1); + assert(phys_level0_sa->array_len == 1); + return ISL_ARRAY_PITCH_SPAN_COMPACT; + } + + if (phys_level0_sa->array_len == 1) { + /* The hardware will never use the QPitch. So choose the most + * compact QPitch possible in order to conserve memory. + */ + return ISL_ARRAY_PITCH_SPAN_COMPACT; + } + + return ISL_ARRAY_PITCH_SPAN_FULL; + } + + case ISL_DIM_LAYOUT_GEN4_3D: + /* The hardware will never use the QPitch. So choose the most + * compact QPitch possible in order to conserve memory. + */ + return ISL_ARRAY_PITCH_SPAN_COMPACT; + } + + unreachable("bad isl_dim_layout"); + return ISL_ARRAY_PITCH_SPAN_FULL; +} + +static void +isl_choose_image_alignment_el(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + enum isl_tiling tiling, + enum isl_dim_layout dim_layout, + enum isl_msaa_layout msaa_layout, + struct isl_extent3d *image_align_el) +{ + if (info->format == ISL_FORMAT_HIZ) { + assert(ISL_DEV_GEN(dev) >= 6); + /* HiZ surfaces are always aligned to 16x8 pixels in the primary surface + * which works out to 2x2 HiZ elments. + */ + *image_align_el = isl_extent3d(2, 2, 1); + return; + } + + if (ISL_DEV_GEN(dev) >= 9) { + isl_gen9_choose_image_alignment_el(dev, info, tiling, dim_layout, + msaa_layout, image_align_el); + } else if (ISL_DEV_GEN(dev) >= 8) { + isl_gen8_choose_image_alignment_el(dev, info, tiling, dim_layout, + msaa_layout, image_align_el); + } else if (ISL_DEV_GEN(dev) >= 7) { + isl_gen7_choose_image_alignment_el(dev, info, tiling, dim_layout, + msaa_layout, image_align_el); + } else if (ISL_DEV_GEN(dev) >= 6) { + isl_gen6_choose_image_alignment_el(dev, info, tiling, dim_layout, + msaa_layout, image_align_el); + } else { + isl_gen4_choose_image_alignment_el(dev, info, tiling, dim_layout, + msaa_layout, image_align_el); + } +} + +static enum isl_dim_layout +isl_surf_choose_dim_layout(const struct isl_device *dev, + enum isl_surf_dim logical_dim, + enum isl_tiling tiling) +{ + if (ISL_DEV_GEN(dev) >= 9) { + switch (logical_dim) { + case ISL_SURF_DIM_1D: + /* From the Sky Lake PRM Vol. 5, "1D Surfaces": + * + * One-dimensional surfaces use a tiling mode of linear. + * Technically, they are not tiled resources, but the Tiled + * Resource Mode field in RENDER_SURFACE_STATE is still used to + * indicate the alignment requirements for this linear surface + * (See 1D Alignment requirements for how 4K and 64KB Tiled + * Resource Modes impact alignment). Alternatively, a 1D surface + * can be defined as a 2D tiled surface (e.g. TileY or TileX) with + * a height of 0. + * + * In other words, ISL_DIM_LAYOUT_GEN9_1D is only used for linear + * surfaces and, for tiled surfaces, ISL_DIM_LAYOUT_GEN4_2D is used. + */ + if (tiling == ISL_TILING_LINEAR) + return ISL_DIM_LAYOUT_GEN9_1D; + else + return ISL_DIM_LAYOUT_GEN4_2D; + case ISL_SURF_DIM_2D: + case ISL_SURF_DIM_3D: + return ISL_DIM_LAYOUT_GEN4_2D; + } + } else { + switch (logical_dim) { + case ISL_SURF_DIM_1D: + case ISL_SURF_DIM_2D: + return ISL_DIM_LAYOUT_GEN4_2D; + case ISL_SURF_DIM_3D: + return ISL_DIM_LAYOUT_GEN4_3D; + } + } + + unreachable("bad isl_surf_dim"); + return ISL_DIM_LAYOUT_GEN4_2D; +} + +/** + * Calculate the physical extent of the surface's first level, in units of + * surface samples. The result is aligned to the format's compression block. + */ +static void +isl_calc_phys_level0_extent_sa(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + enum isl_dim_layout dim_layout, + enum isl_tiling tiling, + enum isl_msaa_layout msaa_layout, + struct isl_extent4d *phys_level0_sa) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); + + if (isl_format_is_yuv(info->format)) + isl_finishme("%s:%s: YUV format", __FILE__, __func__); + + switch (info->dim) { + case ISL_SURF_DIM_1D: + assert(info->height == 1); + assert(info->depth == 1); + assert(info->samples == 1); + + switch (dim_layout) { + case ISL_DIM_LAYOUT_GEN4_3D: + unreachable("bad isl_dim_layout"); + + case ISL_DIM_LAYOUT_GEN9_1D: + case ISL_DIM_LAYOUT_GEN4_2D: + *phys_level0_sa = (struct isl_extent4d) { + .w = isl_align_npot(info->width, fmtl->bw), + .h = fmtl->bh, + .d = 1, + .a = info->array_len, + }; + break; + } + break; + + case ISL_SURF_DIM_2D: + assert(dim_layout == ISL_DIM_LAYOUT_GEN4_2D); + + if (tiling == ISL_TILING_Ys && info->samples > 1) + isl_finishme("%s:%s: multisample TileYs layout", __FILE__, __func__); + + switch (msaa_layout) { + case ISL_MSAA_LAYOUT_NONE: + assert(info->depth == 1); + assert(info->samples == 1); + + *phys_level0_sa = (struct isl_extent4d) { + .w = isl_align_npot(info->width, fmtl->bw), + .h = isl_align_npot(info->height, fmtl->bh), + .d = 1, + .a = info->array_len, + }; + break; + + case ISL_MSAA_LAYOUT_ARRAY: + assert(info->depth == 1); + assert(info->levels == 1); + assert(isl_format_supports_multisampling(dev->info, info->format)); + assert(fmtl->bw == 1 && fmtl->bh == 1); + + *phys_level0_sa = (struct isl_extent4d) { + .w = info->width, + .h = info->height, + .d = 1, + .a = info->array_len * info->samples, + }; + break; + + case ISL_MSAA_LAYOUT_INTERLEAVED: + assert(info->depth == 1); + assert(info->levels == 1); + assert(isl_format_supports_multisampling(dev->info, info->format)); + + *phys_level0_sa = (struct isl_extent4d) { + .w = info->width, + .h = info->height, + .d = 1, + .a = info->array_len, + }; + + isl_msaa_interleaved_scale_px_to_sa(info->samples, + &phys_level0_sa->w, + &phys_level0_sa->h); + + phys_level0_sa->w = isl_align(phys_level0_sa->w, fmtl->bw); + phys_level0_sa->h = isl_align(phys_level0_sa->h, fmtl->bh); + break; + } + break; + + case ISL_SURF_DIM_3D: + assert(info->array_len == 1); + assert(info->samples == 1); + + if (fmtl->bd > 1) { + isl_finishme("%s:%s: compression block with depth > 1", + __FILE__, __func__); + } + + switch (dim_layout) { + case ISL_DIM_LAYOUT_GEN9_1D: + unreachable("bad isl_dim_layout"); + + case ISL_DIM_LAYOUT_GEN4_2D: + assert(ISL_DEV_GEN(dev) >= 9); + + *phys_level0_sa = (struct isl_extent4d) { + .w = isl_align_npot(info->width, fmtl->bw), + .h = isl_align_npot(info->height, fmtl->bh), + .d = 1, + .a = info->depth, + }; + break; + + case ISL_DIM_LAYOUT_GEN4_3D: + assert(ISL_DEV_GEN(dev) < 9); + *phys_level0_sa = (struct isl_extent4d) { + .w = isl_align(info->width, fmtl->bw), + .h = isl_align(info->height, fmtl->bh), + .d = info->depth, + .a = 1, + }; + break; + } + break; + } +} + +/** + * A variant of isl_calc_phys_slice0_extent_sa() specific to + * ISL_DIM_LAYOUT_GEN4_2D. + */ +static void +isl_calc_phys_slice0_extent_sa_gen4_2d( + const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + enum isl_msaa_layout msaa_layout, + const struct isl_extent3d *image_align_sa, + const struct isl_extent4d *phys_level0_sa, + struct isl_extent2d *phys_slice0_sa) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); + + assert(phys_level0_sa->depth == 1); + + if (info->levels == 1) { + /* Do not pad the surface to the image alignment. Instead, pad it only + * to the pixel format's block alignment. + * + * For tiled surfaces, using a reduced alignment here avoids wasting CPU + * cycles on the below mipmap layout caluclations. Reducing the + * alignment here is safe because we later align the row pitch and array + * pitch to the tile boundary. It is safe even for + * ISL_MSAA_LAYOUT_INTERLEAVED, because phys_level0_sa is already scaled + * to accomodate the interleaved samples. + * + * For linear surfaces, reducing the alignment here permits us to later + * choose an arbitrary, non-aligned row pitch. If the surface backs + * a VkBuffer, then an arbitrary pitch may be needed to accomodate + * VkBufferImageCopy::bufferRowLength. + */ + *phys_slice0_sa = (struct isl_extent2d) { + .w = isl_align_npot(phys_level0_sa->w, fmtl->bw), + .h = isl_align_npot(phys_level0_sa->h, fmtl->bh), + }; + return; + } + + uint32_t slice_top_w = 0; + uint32_t slice_bottom_w = 0; + uint32_t slice_left_h = 0; + uint32_t slice_right_h = 0; + + uint32_t W0 = phys_level0_sa->w; + uint32_t H0 = phys_level0_sa->h; + + for (uint32_t l = 0; l < info->levels; ++l) { + uint32_t W = isl_minify(W0, l); + uint32_t H = isl_minify(H0, l); + + uint32_t w = isl_align_npot(W, image_align_sa->w); + uint32_t h = isl_align_npot(H, image_align_sa->h); + + if (l == 0) { + slice_top_w = w; + slice_left_h = h; + slice_right_h = h; + } else if (l == 1) { + slice_bottom_w = w; + slice_left_h += h; + } else if (l == 2) { + slice_bottom_w += w; + slice_right_h += h; + } else { + slice_right_h += h; + } + } + + *phys_slice0_sa = (struct isl_extent2d) { + .w = MAX(slice_top_w, slice_bottom_w), + .h = MAX(slice_left_h, slice_right_h), + }; +} + +/** + * A variant of isl_calc_phys_slice0_extent_sa() specific to + * ISL_DIM_LAYOUT_GEN4_3D. + */ +static void +isl_calc_phys_slice0_extent_sa_gen4_3d( + const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + const struct isl_extent3d *image_align_sa, + const struct isl_extent4d *phys_level0_sa, + struct isl_extent2d *phys_slice0_sa) +{ + assert(info->samples == 1); + assert(phys_level0_sa->array_len == 1); + + uint32_t slice_w = 0; + uint32_t slice_h = 0; + + uint32_t W0 = phys_level0_sa->w; + uint32_t H0 = phys_level0_sa->h; + uint32_t D0 = phys_level0_sa->d; + + for (uint32_t l = 0; l < info->levels; ++l) { + uint32_t level_w = isl_align_npot(isl_minify(W0, l), image_align_sa->w); + uint32_t level_h = isl_align_npot(isl_minify(H0, l), image_align_sa->h); + uint32_t level_d = isl_align_npot(isl_minify(D0, l), image_align_sa->d); + + uint32_t max_layers_horiz = MIN(level_d, 1u << l); + uint32_t max_layers_vert = isl_align(level_d, 1u << l) / (1u << l); + + slice_w = MAX(slice_w, level_w * max_layers_horiz); + slice_h += level_h * max_layers_vert; + } + + *phys_slice0_sa = (struct isl_extent2d) { + .w = slice_w, + .h = slice_h, + }; +} + +/** + * A variant of isl_calc_phys_slice0_extent_sa() specific to + * ISL_DIM_LAYOUT_GEN9_1D. + */ +static void +isl_calc_phys_slice0_extent_sa_gen9_1d( + const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + const struct isl_extent3d *image_align_sa, + const struct isl_extent4d *phys_level0_sa, + struct isl_extent2d *phys_slice0_sa) +{ + MAYBE_UNUSED const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); + + assert(phys_level0_sa->height == 1); + assert(phys_level0_sa->depth == 1); + assert(info->samples == 1); + assert(image_align_sa->w >= fmtl->bw); + + uint32_t slice_w = 0; + const uint32_t W0 = phys_level0_sa->w; + + for (uint32_t l = 0; l < info->levels; ++l) { + uint32_t W = isl_minify(W0, l); + uint32_t w = isl_align_npot(W, image_align_sa->w); + + slice_w += w; + } + + *phys_slice0_sa = isl_extent2d(slice_w, 1); +} + +/** + * Calculate the physical extent of the surface's first array slice, in units + * of surface samples. If the surface is multi-leveled, then the result will + * be aligned to \a image_align_sa. + */ +static void +isl_calc_phys_slice0_extent_sa(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + enum isl_dim_layout dim_layout, + enum isl_msaa_layout msaa_layout, + const struct isl_extent3d *image_align_sa, + const struct isl_extent4d *phys_level0_sa, + struct isl_extent2d *phys_slice0_sa) +{ + switch (dim_layout) { + case ISL_DIM_LAYOUT_GEN9_1D: + isl_calc_phys_slice0_extent_sa_gen9_1d(dev, info, + image_align_sa, phys_level0_sa, + phys_slice0_sa); + return; + case ISL_DIM_LAYOUT_GEN4_2D: + isl_calc_phys_slice0_extent_sa_gen4_2d(dev, info, msaa_layout, + image_align_sa, phys_level0_sa, + phys_slice0_sa); + return; + case ISL_DIM_LAYOUT_GEN4_3D: + isl_calc_phys_slice0_extent_sa_gen4_3d(dev, info, image_align_sa, + phys_level0_sa, phys_slice0_sa); + return; + } +} + +/** + * Calculate the pitch between physical array slices, in units of rows of + * surface elements. + */ +static uint32_t +isl_calc_array_pitch_el_rows(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + const struct isl_tile_info *tile_info, + enum isl_dim_layout dim_layout, + enum isl_array_pitch_span array_pitch_span, + const struct isl_extent3d *image_align_sa, + const struct isl_extent4d *phys_level0_sa, + const struct isl_extent2d *phys_slice0_sa) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); + uint32_t pitch_sa_rows = 0; + + switch (dim_layout) { + case ISL_DIM_LAYOUT_GEN9_1D: + /* Each row is an array slice */ + pitch_sa_rows = 1; + break; + case ISL_DIM_LAYOUT_GEN4_2D: + switch (array_pitch_span) { + case ISL_ARRAY_PITCH_SPAN_COMPACT: + pitch_sa_rows = isl_align_npot(phys_slice0_sa->h, image_align_sa->h); + break; + case ISL_ARRAY_PITCH_SPAN_FULL: { + /* The QPitch equation is found in the Broadwell PRM >> Volume 5: + * Memory Views >> Common Surface Formats >> Surface Layout >> 2D + * Surfaces >> Surface Arrays. + */ + uint32_t H0_sa = phys_level0_sa->h; + uint32_t H1_sa = isl_minify(H0_sa, 1); + + uint32_t h0_sa = isl_align_npot(H0_sa, image_align_sa->h); + uint32_t h1_sa = isl_align_npot(H1_sa, image_align_sa->h); + + uint32_t m; + if (ISL_DEV_GEN(dev) >= 7) { + /* The QPitch equation changed slightly in Ivybridge. */ + m = 12; + } else { + m = 11; + } + + pitch_sa_rows = h0_sa + h1_sa + (m * image_align_sa->h); + + if (ISL_DEV_GEN(dev) == 6 && info->samples > 1 && + (info->height % 4 == 1)) { + /* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1: + * Graphics Core >> Section 7.18.3.7: Surface Arrays: + * + * [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than + * the value calculated in the equation above , for every + * other odd Surface Height starting from 1 i.e. 1,5,9,13. + * + * XXX(chadv): Is the errata natural corollary of the physical + * layout of interleaved samples? + */ + pitch_sa_rows += 4; + } + + pitch_sa_rows = isl_align_npot(pitch_sa_rows, fmtl->bh); + } /* end case */ + break; + } + break; + case ISL_DIM_LAYOUT_GEN4_3D: + assert(array_pitch_span == ISL_ARRAY_PITCH_SPAN_COMPACT); + pitch_sa_rows = isl_align_npot(phys_slice0_sa->h, image_align_sa->h); + break; + default: + unreachable("bad isl_dim_layout"); + break; + } + + assert(pitch_sa_rows % fmtl->bh == 0); + uint32_t pitch_el_rows = pitch_sa_rows / fmtl->bh; + + if (ISL_DEV_GEN(dev) >= 9 && fmtl->txc == ISL_TXC_CCS) { + /* + * From the Sky Lake PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 632): + * + * "Mip-mapped and arrayed surfaces are supported with MCS buffer + * layout with these alignments in the RT space: Horizontal + * Alignment = 128 and Vertical Alignment = 64." + * + * From the Sky Lake PRM Vol. 2d, "RENDER_SURFACE_STATE" (p. 435): + * + * "For non-multisampled render target's CCS auxiliary surface, + * QPitch must be computed with Horizontal Alignment = 128 and + * Surface Vertical Alignment = 256. These alignments are only for + * CCS buffer and not for associated render target." + * + * The first restriction is already handled by isl_choose_image_alignment_el + * but the second restriction, which is an extension of the first, only + * applies to qpitch and must be applied here. + */ + assert(fmtl->bh == 4); + pitch_el_rows = isl_align(pitch_el_rows, 256 / 4); + } + + if (ISL_DEV_GEN(dev) >= 9 && + info->dim == ISL_SURF_DIM_3D && + tile_info->tiling != ISL_TILING_LINEAR) { + /* From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch: + * + * Tile Mode != Linear: This field must be set to an integer multiple + * of the tile height + */ + pitch_el_rows = isl_align(pitch_el_rows, tile_info->logical_extent_el.height); + } + + return pitch_el_rows; +} + +/** + * Calculate the pitch of each surface row, in bytes. + */ +static uint32_t +isl_calc_linear_row_pitch(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + const struct isl_extent2d *phys_slice0_sa) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); + + uint32_t row_pitch = info->min_pitch; + + /* First, align the surface to a cache line boundary, as the PRM explains + * below. + * + * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface + * Formats >> Surface Padding Requirements >> Render Target and Media + * Surfaces: + * + * The data port accesses data (pixels) outside of the surface if they + * are contained in the same cache request as pixels that are within the + * surface. These pixels will not be returned by the requesting message, + * however if these pixels lie outside of defined pages in the GTT, + * a GTT error will result when the cache request is processed. In order + * to avoid these GTT errors, “padding” at the bottom of the surface is + * sometimes necessary. + * + * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface + * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces: + * + * The sampling engine accesses texels outside of the surface if they + * are contained in the same cache line as texels that are within the + * surface. These texels will not participate in any calculation + * performed by the sampling engine and will not affect the result of + * any sampling engine operation, however if these texels lie outside of + * defined pages in the GTT, a GTT error will result when the cache line + * is accessed. In order to avoid these GTT errors, “padding” at the + * bottom and right side of a sampling engine surface is sometimes + * necessary. + * + * It is possible that a cache line will straddle a page boundary if the + * base address or pitch is not aligned. All pages included in the cache + * lines that are part of the surface must map to valid GTT entries to + * avoid errors. To determine the necessary padding on the bottom and + * right side of the surface, refer to the table in Alignment Unit Size + * section for the i and j parameters for the surface format in use. The + * surface must then be extended to the next multiple of the alignment + * unit size in each dimension, and all texels contained in this + * extended surface must have valid GTT entries. + * + * For example, suppose the surface size is 15 texels by 10 texels and + * the alignment parameters are i=4 and j=2. In this case, the extended + * surface would be 16 by 10. Note that these calculations are done in + * texels, and must be converted to bytes based on the surface format + * being used to determine whether additional pages need to be defined. + */ + assert(phys_slice0_sa->w % fmtl->bw == 0); + const uint32_t bs = fmtl->bpb / 8; + row_pitch = MAX(row_pitch, bs * (phys_slice0_sa->w / fmtl->bw)); + + /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >> + * RENDER_SURFACE_STATE Surface Pitch (p349): + * + * - For linear render target surfaces and surfaces accessed with the + * typed data port messages, the pitch must be a multiple of the + * element size for non-YUV surface formats. Pitch must be + * a multiple of 2 * element size for YUV surface formats. + * + * - [Requirements for SURFTYPE_BUFFER and SURFTYPE_STRBUF, which we + * ignore because isl doesn't do buffers.] + * + * - For other linear surfaces, the pitch can be any multiple of + * bytes. + */ + if (info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) { + if (isl_format_is_yuv(info->format)) { + row_pitch = isl_align_npot(row_pitch, 2 * bs); + } else { + row_pitch = isl_align_npot(row_pitch, bs); + } + } + + return row_pitch; +} + +/** + * Calculate and apply any padding required for the surface. + * + * @param[inout] total_h_el is updated with the new height + * @param[out] pad_bytes is overwritten with additional padding requirements. + */ +static void +isl_apply_surface_padding(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + const struct isl_tile_info *tile_info, + uint32_t *total_h_el, + uint32_t *pad_bytes) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); + + *pad_bytes = 0; + + /* From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface + * Formats >> Surface Padding Requirements >> Render Target and Media + * Surfaces: + * + * The data port accesses data (pixels) outside of the surface if they + * are contained in the same cache request as pixels that are within the + * surface. These pixels will not be returned by the requesting message, + * however if these pixels lie outside of defined pages in the GTT, + * a GTT error will result when the cache request is processed. In + * order to avoid these GTT errors, “padding” at the bottom of the + * surface is sometimes necessary. + * + * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface + * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces: + * + * ... Lots of padding requirements, all listed separately below. + */ + + /* We can safely ignore the first padding requirement, quoted below, + * because isl doesn't do buffers. + * + * - [pre-BDW] For buffers, which have no inherent “height,” padding + * requirements are different. A buffer must be padded to the next + * multiple of 256 array elements, with an additional 16 bytes added + * beyond that to account for the L1 cache line. + */ + + /* + * - For compressed textures [...], padding at the bottom of the surface + * is to an even compressed row. + */ + if (isl_format_is_compressed(info->format)) + *total_h_el = isl_align(*total_h_el, 2); + + /* + * - For cube surfaces, an additional two rows of padding are required + * at the bottom of the surface. + */ + if (info->usage & ISL_SURF_USAGE_CUBE_BIT) + *total_h_el += 2; + + /* + * - For packed YUV, 96 bpt, 48 bpt, and 24 bpt surface formats, + * additional padding is required. These surfaces require an extra row + * plus 16 bytes of padding at the bottom in addition to the general + * padding requirements. + */ + if (isl_format_is_yuv(info->format) && + (fmtl->bpb == 96 || fmtl->bpb == 48|| fmtl->bpb == 24)) { + *total_h_el += 1; + *pad_bytes += 16; + } + + /* + * - For linear surfaces, additional padding of 64 bytes is required at + * the bottom of the surface. This is in addition to the padding + * required above. + */ + if (tile_info->tiling == ISL_TILING_LINEAR) + *pad_bytes += 64; + + /* The below text weakens, not strengthens, the padding requirements for + * linear surfaces. Therefore we can safely ignore it. + * + * - [BDW+] For SURFTYPE_BUFFER, SURFTYPE_1D, and SURFTYPE_2D non-array, + * non-MSAA, non-mip-mapped surfaces in linear memory, the only + * padding requirement is to the next aligned 64-byte boundary beyond + * the end of the surface. The rest of the padding requirements + * documented above do not apply to these surfaces. + */ + + /* + * - [SKL+] For SURFTYPE_2D and SURFTYPE_3D with linear mode and + * height % 4 != 0, the surface must be padded with + * 4-(height % 4)*Surface Pitch # of bytes. + */ + if (ISL_DEV_GEN(dev) >= 9 && + tile_info->tiling == ISL_TILING_LINEAR && + (info->dim == ISL_SURF_DIM_2D || info->dim == ISL_SURF_DIM_3D)) { + *total_h_el = isl_align(*total_h_el, 4); + } + + /* + * - [SKL+] For SURFTYPE_1D with linear mode, the surface must be padded + * to 4 times the Surface Pitch # of bytes + */ + if (ISL_DEV_GEN(dev) >= 9 && + tile_info->tiling == ISL_TILING_LINEAR && + info->dim == ISL_SURF_DIM_1D) { + *total_h_el += 4; + } +} + +bool +isl_surf_init_s(const struct isl_device *dev, + struct isl_surf *surf, + const struct isl_surf_init_info *restrict info) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); + + const struct isl_extent4d logical_level0_px = { + .w = info->width, + .h = info->height, + .d = info->depth, + .a = info->array_len, + }; + + enum isl_tiling tiling; + if (!isl_surf_choose_tiling(dev, info, &tiling)) + return false; + + struct isl_tile_info tile_info; + if (!isl_tiling_get_info(dev, tiling, fmtl->bpb, &tile_info)) + return false; + + const enum isl_dim_layout dim_layout = + isl_surf_choose_dim_layout(dev, info->dim, tiling); + + enum isl_msaa_layout msaa_layout; + if (!isl_choose_msaa_layout(dev, info, tiling, &msaa_layout)) + return false; + + struct isl_extent3d image_align_el; + isl_choose_image_alignment_el(dev, info, tiling, dim_layout, msaa_layout, + &image_align_el); + + struct isl_extent3d image_align_sa = + isl_extent3d_el_to_sa(info->format, image_align_el); + + struct isl_extent4d phys_level0_sa; + isl_calc_phys_level0_extent_sa(dev, info, dim_layout, tiling, msaa_layout, + &phys_level0_sa); + assert(phys_level0_sa.w % fmtl->bw == 0); + assert(phys_level0_sa.h % fmtl->bh == 0); + + enum isl_array_pitch_span array_pitch_span = + isl_choose_array_pitch_span(dev, info, dim_layout, &phys_level0_sa); + + struct isl_extent2d phys_slice0_sa; + isl_calc_phys_slice0_extent_sa(dev, info, dim_layout, msaa_layout, + &image_align_sa, &phys_level0_sa, + &phys_slice0_sa); + assert(phys_slice0_sa.w % fmtl->bw == 0); + assert(phys_slice0_sa.h % fmtl->bh == 0); + + const uint32_t array_pitch_el_rows = + isl_calc_array_pitch_el_rows(dev, info, &tile_info, dim_layout, + array_pitch_span, &image_align_sa, + &phys_level0_sa, &phys_slice0_sa); + + uint32_t total_h_el = phys_level0_sa.array_len * array_pitch_el_rows; + + uint32_t pad_bytes; + isl_apply_surface_padding(dev, info, &tile_info, &total_h_el, &pad_bytes); + + uint32_t row_pitch, size, base_alignment; + if (tiling == ISL_TILING_LINEAR) { + row_pitch = isl_calc_linear_row_pitch(dev, info, &phys_slice0_sa); + size = row_pitch * total_h_el + pad_bytes; + + /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfaceBaseAddress: + * + * "The Base Address for linear render target surfaces and surfaces + * accessed with the typed surface read/write data port messages must + * be element-size aligned, for non-YUV surface formats, or a + * multiple of 2 element-sizes for YUV surface formats. Other linear + * surfaces have no alignment requirements (byte alignment is + * sufficient.)" + */ + base_alignment = MAX(1, info->min_alignment); + if (info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) { + if (isl_format_is_yuv(info->format)) { + base_alignment = MAX(base_alignment, fmtl->bpb / 4); + } else { + base_alignment = MAX(base_alignment, fmtl->bpb / 8); + } + } + base_alignment = isl_round_up_to_power_of_two(base_alignment); + } else { + assert(fmtl->bpb % tile_info.format_bpb == 0); + const uint32_t tile_el_scale = fmtl->bpb / tile_info.format_bpb; + + assert(phys_slice0_sa.w % fmtl->bw == 0); + const uint32_t total_w_el = phys_slice0_sa.width / fmtl->bw; + const uint32_t total_w_tl = + isl_align_div(total_w_el * tile_el_scale, + tile_info.logical_extent_el.width); + + row_pitch = total_w_tl * tile_info.phys_extent_B.width; + if (row_pitch < info->min_pitch) { + row_pitch = isl_align_npot(info->min_pitch, + tile_info.phys_extent_B.width); + } + + total_h_el += isl_align_div_npot(pad_bytes, row_pitch); + const uint32_t total_h_tl = + isl_align_div(total_h_el, tile_info.logical_extent_el.height); + + size = total_h_tl * tile_info.phys_extent_B.height * row_pitch; + + const uint32_t tile_size = tile_info.phys_extent_B.width * + tile_info.phys_extent_B.height; + assert(isl_is_pow2(info->min_alignment) && isl_is_pow2(tile_size)); + base_alignment = MAX(info->min_alignment, tile_size); + } + + *surf = (struct isl_surf) { + .dim = info->dim, + .dim_layout = dim_layout, + .msaa_layout = msaa_layout, + .tiling = tiling, + .format = info->format, + + .levels = info->levels, + .samples = info->samples, + + .image_alignment_el = image_align_el, + .logical_level0_px = logical_level0_px, + .phys_level0_sa = phys_level0_sa, + + .size = size, + .alignment = base_alignment, + .row_pitch = row_pitch, + .array_pitch_el_rows = array_pitch_el_rows, + .array_pitch_span = array_pitch_span, + + .usage = info->usage, + }; + + return true; +} + +void +isl_surf_get_tile_info(const struct isl_device *dev, + const struct isl_surf *surf, + struct isl_tile_info *tile_info) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format); + isl_tiling_get_info(dev, surf->tiling, fmtl->bpb, tile_info); +} + +void +isl_surf_get_hiz_surf(const struct isl_device *dev, + const struct isl_surf *surf, + struct isl_surf *hiz_surf) +{ + assert(ISL_DEV_GEN(dev) >= 5 && ISL_DEV_USE_SEPARATE_STENCIL(dev)); + + /* Multisampled depth is always interleaved */ + assert(surf->msaa_layout == ISL_MSAA_LAYOUT_NONE || + surf->msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED); + + /* From the Broadwell PRM Vol. 7, "Hierarchical Depth Buffer": + * + * "The Surface Type, Height, Width, Depth, Minimum Array Element, Render + * Target View Extent, and Depth Coordinate Offset X/Y of the + * hierarchical depth buffer are inherited from the depth buffer. The + * height and width of the hierarchical depth buffer that must be + * allocated are computed by the following formulas, where HZ is the + * hierarchical depth buffer and Z is the depth buffer. The Z_Height, + * Z_Width, and Z_Depth values given in these formulas are those present + * in 3DSTATE_DEPTH_BUFFER incremented by one. + * + * "The value of Z_Height and Z_Width must each be multiplied by 2 before + * being applied to the table below if Number of Multisamples is set to + * NUMSAMPLES_4. The value of Z_Height must be multiplied by 2 and + * Z_Width must be multiplied by 4 before being applied to the table + * below if Number of Multisamples is set to NUMSAMPLES_8." + * + * In the Sky Lake PRM, the second paragraph is replaced with this: + * + * "The Z_Height and Z_Width values must equal those present in + * 3DSTATE_DEPTH_BUFFER incremented by one." + * + * In other words, on Sandy Bridge through Broadwell, each 128-bit HiZ + * block corresponds to a region of 8x4 samples in the primary depth + * surface. On Sky Lake, on the other hand, each HiZ block corresponds to + * a region of 8x4 pixels in the primary depth surface regardless of the + * number of samples. The dimensions of a HiZ block in both pixels and + * samples are given in the table below: + * + * | SNB - BDW | SKL+ + * ------+-----------+------------- + * 1x | 8 x 4 sa | 8 x 4 sa + * MSAA | 8 x 4 px | 8 x 4 px + * ------+-----------+------------- + * 2x | 8 x 4 sa | 16 x 4 sa + * MSAA | 4 x 4 px | 8 x 4 px + * ------+-----------+------------- + * 4x | 8 x 4 sa | 16 x 8 sa + * MSAA | 4 x 2 px | 8 x 4 px + * ------+-----------+------------- + * 8x | 8 x 4 sa | 32 x 8 sa + * MSAA | 2 x 2 px | 8 x 4 px + * ------+-----------+------------- + * 16x | N/A | 32 x 16 sa + * MSAA | N/A | 8 x 4 px + * ------+-----------+------------- + * + * There are a number of different ways that this discrepency could be + * handled. The way we have chosen is to simply make MSAA HiZ have the + * same number of samples as the parent surface pre-Sky Lake and always be + * single-sampled on Sky Lake and above. Since the block sizes of + * compressed formats are given in samples, this neatly handles everything + * without the need for additional HiZ formats with different block sizes + * on SKL+. + */ + const unsigned samples = ISL_DEV_GEN(dev) >= 9 ? 1 : surf->samples; + + isl_surf_init(dev, hiz_surf, + .dim = surf->dim, + .format = ISL_FORMAT_HIZ, + .width = surf->logical_level0_px.width, + .height = surf->logical_level0_px.height, + .depth = surf->logical_level0_px.depth, + .levels = surf->levels, + .array_len = surf->logical_level0_px.array_len, + .samples = samples, + .usage = ISL_SURF_USAGE_HIZ_BIT, + .tiling_flags = ISL_TILING_HIZ_BIT); +} + +void +isl_surf_get_mcs_surf(const struct isl_device *dev, + const struct isl_surf *surf, + struct isl_surf *mcs_surf) +{ + /* It must be multisampled with an array layout */ + assert(surf->samples > 1 && surf->msaa_layout == ISL_MSAA_LAYOUT_ARRAY); + + /* The following are true of all multisampled surfaces */ + assert(surf->dim == ISL_SURF_DIM_2D); + assert(surf->levels == 1); + assert(surf->logical_level0_px.depth == 1); + + enum isl_format mcs_format; + switch (surf->samples) { + case 2: mcs_format = ISL_FORMAT_MCS_2X; break; + case 4: mcs_format = ISL_FORMAT_MCS_4X; break; + case 8: mcs_format = ISL_FORMAT_MCS_8X; break; + case 16: mcs_format = ISL_FORMAT_MCS_16X; break; + default: + unreachable("Invalid sample count"); + } + + isl_surf_init(dev, mcs_surf, + .dim = ISL_SURF_DIM_2D, + .format = mcs_format, + .width = surf->logical_level0_px.width, + .height = surf->logical_level0_px.height, + .depth = 1, + .levels = 1, + .array_len = surf->logical_level0_px.array_len, + .samples = 1, /* MCS surfaces are really single-sampled */ + .usage = ISL_SURF_USAGE_MCS_BIT, + .tiling_flags = ISL_TILING_Y0_BIT); +} + +bool +isl_surf_get_ccs_surf(const struct isl_device *dev, + const struct isl_surf *surf, + struct isl_surf *ccs_surf) +{ + assert(surf->samples == 1 && surf->msaa_layout == ISL_MSAA_LAYOUT_NONE); + assert(ISL_DEV_GEN(dev) >= 7); + + assert(ISL_DEV_GEN(dev) >= 8 || surf->dim == ISL_SURF_DIM_2D); + + assert(surf->logical_level0_px.depth == 1); + + /* TODO: More conditions where it can fail. */ + + enum isl_format ccs_format; + if (ISL_DEV_GEN(dev) >= 9) { + if (!isl_tiling_is_any_y(surf->tiling)) + return false; + + switch (isl_format_get_layout(surf->format)->bpb) { + case 32: ccs_format = ISL_FORMAT_GEN9_CCS_32BPP; break; + case 64: ccs_format = ISL_FORMAT_GEN9_CCS_64BPP; break; + case 128: ccs_format = ISL_FORMAT_GEN9_CCS_128BPP; break; + default: + return false; + } + } else if (surf->tiling == ISL_TILING_Y0) { + switch (isl_format_get_layout(surf->format)->bpb) { + case 32: ccs_format = ISL_FORMAT_GEN7_CCS_32BPP_Y; break; + case 64: ccs_format = ISL_FORMAT_GEN7_CCS_64BPP_Y; break; + case 128: ccs_format = ISL_FORMAT_GEN7_CCS_128BPP_Y; break; + default: + return false; + } + } else if (surf->tiling == ISL_TILING_X) { + switch (isl_format_get_layout(surf->format)->bpb) { + case 32: ccs_format = ISL_FORMAT_GEN7_CCS_32BPP_X; break; + case 64: ccs_format = ISL_FORMAT_GEN7_CCS_64BPP_X; break; + case 128: ccs_format = ISL_FORMAT_GEN7_CCS_128BPP_X; break; + default: + return false; + } + } else { + return false; + } + + isl_surf_init(dev, ccs_surf, + .dim = ISL_SURF_DIM_2D, + .format = ccs_format, + .width = surf->logical_level0_px.width, + .height = surf->logical_level0_px.height, + .depth = 1, + .levels = surf->levels, + .array_len = surf->logical_level0_px.array_len, + .samples = 1, + .usage = ISL_SURF_USAGE_CCS_BIT, + .tiling_flags = ISL_TILING_CCS_BIT); + + return true; +} + +void +isl_surf_fill_state_s(const struct isl_device *dev, void *state, + const struct isl_surf_fill_state_info *restrict info) +{ +#ifndef NDEBUG + isl_surf_usage_flags_t _base_usage = + info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT | + ISL_SURF_USAGE_TEXTURE_BIT | + ISL_SURF_USAGE_STORAGE_BIT); + /* They may only specify one of the above bits at a time */ + assert(__builtin_popcount(_base_usage) == 1); + /* The only other allowed bit is ISL_SURF_USAGE_CUBE_BIT */ + assert((info->view->usage & ~ISL_SURF_USAGE_CUBE_BIT) == _base_usage); +#endif + + if (info->surf->dim == ISL_SURF_DIM_3D) { + assert(info->view->base_array_layer + info->view->array_len <= + info->surf->logical_level0_px.depth); + } else { + assert(info->view->base_array_layer + info->view->array_len <= + info->surf->logical_level0_px.array_len); + } + + switch (ISL_DEV_GEN(dev)) { + case 4: + if (ISL_DEV_IS_G4X(dev)) { + /* G45 surface state is the same as gen5 */ + isl_gen5_surf_fill_state_s(dev, state, info); + } else { + isl_gen4_surf_fill_state_s(dev, state, info); + } + break; + case 5: + isl_gen5_surf_fill_state_s(dev, state, info); + break; + case 6: + isl_gen6_surf_fill_state_s(dev, state, info); + break; + case 7: + if (ISL_DEV_IS_HASWELL(dev)) { + isl_gen75_surf_fill_state_s(dev, state, info); + } else { + isl_gen7_surf_fill_state_s(dev, state, info); + } + break; + case 8: + isl_gen8_surf_fill_state_s(dev, state, info); + break; + case 9: + isl_gen9_surf_fill_state_s(dev, state, info); + break; + default: + assert(!"Cannot fill surface state for this gen"); + } +} + +void +isl_buffer_fill_state_s(const struct isl_device *dev, void *state, + const struct isl_buffer_fill_state_info *restrict info) +{ + switch (ISL_DEV_GEN(dev)) { + case 4: + case 5: + /* Gen 4-5 are all the same when it comes to buffer surfaces */ + isl_gen5_buffer_fill_state_s(state, info); + break; + case 6: + isl_gen6_buffer_fill_state_s(state, info); + break; + case 7: + if (ISL_DEV_IS_HASWELL(dev)) { + isl_gen75_buffer_fill_state_s(state, info); + } else { + isl_gen7_buffer_fill_state_s(state, info); + } + break; + case 8: + isl_gen8_buffer_fill_state_s(state, info); + break; + case 9: + isl_gen9_buffer_fill_state_s(state, info); + break; + default: + assert(!"Cannot fill surface state for this gen"); + } +} + +/** + * A variant of isl_surf_get_image_offset_sa() specific to + * ISL_DIM_LAYOUT_GEN4_2D. + */ +static void +get_image_offset_sa_gen4_2d(const struct isl_surf *surf, + uint32_t level, uint32_t logical_array_layer, + uint32_t *x_offset_sa, + uint32_t *y_offset_sa) +{ + assert(level < surf->levels); + if (surf->dim == ISL_SURF_DIM_3D) + assert(logical_array_layer < surf->logical_level0_px.depth); + else + assert(logical_array_layer < surf->logical_level0_px.array_len); + + const struct isl_extent3d image_align_sa = + isl_surf_get_image_alignment_sa(surf); + + const uint32_t W0 = surf->phys_level0_sa.width; + const uint32_t H0 = surf->phys_level0_sa.height; + + const uint32_t phys_layer = logical_array_layer * + (surf->msaa_layout == ISL_MSAA_LAYOUT_ARRAY ? surf->samples : 1); + + uint32_t x = 0; + uint32_t y = phys_layer * isl_surf_get_array_pitch_sa_rows(surf); + + for (uint32_t l = 0; l < level; ++l) { + if (l == 1) { + uint32_t W = isl_minify(W0, l); + x += isl_align_npot(W, image_align_sa.w); + } else { + uint32_t H = isl_minify(H0, l); + y += isl_align_npot(H, image_align_sa.h); + } + } + + *x_offset_sa = x; + *y_offset_sa = y; +} + +/** + * A variant of isl_surf_get_image_offset_sa() specific to + * ISL_DIM_LAYOUT_GEN4_3D. + */ +static void +get_image_offset_sa_gen4_3d(const struct isl_surf *surf, + uint32_t level, uint32_t logical_z_offset_px, + uint32_t *x_offset_sa, + uint32_t *y_offset_sa) +{ + assert(level < surf->levels); + assert(logical_z_offset_px < isl_minify(surf->phys_level0_sa.depth, level)); + assert(surf->phys_level0_sa.array_len == 1); + + const struct isl_extent3d image_align_sa = + isl_surf_get_image_alignment_sa(surf); + + const uint32_t W0 = surf->phys_level0_sa.width; + const uint32_t H0 = surf->phys_level0_sa.height; + const uint32_t D0 = surf->phys_level0_sa.depth; + + uint32_t x = 0; + uint32_t y = 0; + + for (uint32_t l = 0; l < level; ++l) { + const uint32_t level_h = isl_align_npot(isl_minify(H0, l), image_align_sa.h); + const uint32_t level_d = isl_align_npot(isl_minify(D0, l), image_align_sa.d); + const uint32_t max_layers_vert = isl_align(level_d, 1u << l) / (1u << l); + + y += level_h * max_layers_vert; + } + + const uint32_t level_w = isl_align_npot(isl_minify(W0, level), image_align_sa.w); + const uint32_t level_h = isl_align_npot(isl_minify(H0, level), image_align_sa.h); + const uint32_t level_d = isl_align_npot(isl_minify(D0, level), image_align_sa.d); + + const uint32_t max_layers_horiz = MIN(level_d, 1u << level); + + x += level_w * (logical_z_offset_px % max_layers_horiz); + y += level_h * (logical_z_offset_px / max_layers_horiz); + + *x_offset_sa = x; + *y_offset_sa = y; +} + +/** + * A variant of isl_surf_get_image_offset_sa() specific to + * ISL_DIM_LAYOUT_GEN9_1D. + */ +static void +get_image_offset_sa_gen9_1d(const struct isl_surf *surf, + uint32_t level, uint32_t layer, + uint32_t *x_offset_sa, + uint32_t *y_offset_sa) +{ + assert(level < surf->levels); + assert(layer < surf->phys_level0_sa.array_len); + assert(surf->phys_level0_sa.height == 1); + assert(surf->phys_level0_sa.depth == 1); + assert(surf->samples == 1); + + const uint32_t W0 = surf->phys_level0_sa.width; + const struct isl_extent3d image_align_sa = + isl_surf_get_image_alignment_sa(surf); + + uint32_t x = 0; + + for (uint32_t l = 0; l < level; ++l) { + uint32_t W = isl_minify(W0, l); + uint32_t w = isl_align_npot(W, image_align_sa.w); + + x += w; + } + + *x_offset_sa = x; + *y_offset_sa = layer * isl_surf_get_array_pitch_sa_rows(surf); +} + +/** + * Calculate the offset, in units of surface samples, to a subimage in the + * surface. + * + * @invariant level < surface levels + * @invariant logical_array_layer < logical array length of surface + * @invariant logical_z_offset_px < logical depth of surface at level + */ +void +isl_surf_get_image_offset_sa(const struct isl_surf *surf, + uint32_t level, + uint32_t logical_array_layer, + uint32_t logical_z_offset_px, + uint32_t *x_offset_sa, + uint32_t *y_offset_sa) +{ + assert(level < surf->levels); + assert(logical_array_layer < surf->logical_level0_px.array_len); + assert(logical_z_offset_px + < isl_minify(surf->logical_level0_px.depth, level)); + + switch (surf->dim_layout) { + case ISL_DIM_LAYOUT_GEN9_1D: + get_image_offset_sa_gen9_1d(surf, level, logical_array_layer, + x_offset_sa, y_offset_sa); + break; + case ISL_DIM_LAYOUT_GEN4_2D: + get_image_offset_sa_gen4_2d(surf, level, logical_array_layer + + logical_z_offset_px, + x_offset_sa, y_offset_sa); + break; + case ISL_DIM_LAYOUT_GEN4_3D: + get_image_offset_sa_gen4_3d(surf, level, logical_z_offset_px, + x_offset_sa, y_offset_sa); + break; + + default: + unreachable("not reached"); + } +} + +void +isl_surf_get_image_offset_el(const struct isl_surf *surf, + uint32_t level, + uint32_t logical_array_layer, + uint32_t logical_z_offset_px, + uint32_t *x_offset_el, + uint32_t *y_offset_el) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format); + + assert(level < surf->levels); + assert(logical_array_layer < surf->logical_level0_px.array_len); + assert(logical_z_offset_px + < isl_minify(surf->logical_level0_px.depth, level)); + + uint32_t x_offset_sa, y_offset_sa; + isl_surf_get_image_offset_sa(surf, level, + logical_array_layer, + logical_z_offset_px, + &x_offset_sa, + &y_offset_sa); + + *x_offset_el = x_offset_sa / fmtl->bw; + *y_offset_el = y_offset_sa / fmtl->bh; +} + +void +isl_tiling_get_intratile_offset_el(const struct isl_device *dev, + enum isl_tiling tiling, + uint8_t bs, + uint32_t row_pitch, + uint32_t total_x_offset_el, + uint32_t total_y_offset_el, + uint32_t *base_address_offset, + uint32_t *x_offset_el, + uint32_t *y_offset_el) +{ + if (tiling == ISL_TILING_LINEAR) { + *base_address_offset = total_y_offset_el * row_pitch + + total_x_offset_el * bs; + *x_offset_el = 0; + *y_offset_el = 0; + return; + } + + const uint32_t bpb = bs * 8; + + struct isl_tile_info tile_info; + isl_tiling_get_info(dev, tiling, bpb, &tile_info); + + assert(row_pitch % tile_info.phys_extent_B.width == 0); + + /* For non-power-of-two formats, we need the address to be both tile and + * element-aligned. The easiest way to achieve this is to work with a tile + * that is three times as wide as the regular tile. + * + * The tile info returned by get_tile_info has a logical size that is an + * integer number of tile_info.format_bpb size elements. To scale the + * tile, we scale up the physical width and then treat the logical tile + * size as if it has bpb size elements. + */ + const uint32_t tile_el_scale = bpb / tile_info.format_bpb; + tile_info.phys_extent_B.width *= tile_el_scale; + + /* Compute the offset into the tile */ + *x_offset_el = total_x_offset_el % tile_info.logical_extent_el.w; + *y_offset_el = total_y_offset_el % tile_info.logical_extent_el.h; + + /* Compute the offset of the tile in units of whole tiles */ + uint32_t x_offset_tl = total_x_offset_el / tile_info.logical_extent_el.w; + uint32_t y_offset_tl = total_y_offset_el / tile_info.logical_extent_el.h; + + *base_address_offset = + y_offset_tl * tile_info.phys_extent_B.h * row_pitch + + x_offset_tl * tile_info.phys_extent_B.h * tile_info.phys_extent_B.w; +} + +uint32_t +isl_surf_get_depth_format(const struct isl_device *dev, + const struct isl_surf *surf) +{ + /* Support for separate stencil buffers began in gen5. Support for + * interleaved depthstencil buffers ceased in gen7. The intermediate gens, + * those that supported separate and interleaved stencil, were gen5 and + * gen6. + * + * For a list of all available formats, see the Sandybridge PRM >> Volume + * 2 Part 1: 3D/Media - 3D Pipeline >> 3DSTATE_DEPTH_BUFFER >> Surface + * Format (p321). + */ + + bool has_stencil = surf->usage & ISL_SURF_USAGE_STENCIL_BIT; + + assert(surf->usage & ISL_SURF_USAGE_DEPTH_BIT); + + if (has_stencil) + assert(ISL_DEV_GEN(dev) < 7); + + switch (surf->format) { + default: + unreachable("bad isl depth format"); + case ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS: + assert(ISL_DEV_GEN(dev) < 7); + return 0; /* D32_FLOAT_S8X24_UINT */ + case ISL_FORMAT_R32_FLOAT: + assert(!has_stencil); + return 1; /* D32_FLOAT */ + case ISL_FORMAT_R24_UNORM_X8_TYPELESS: + if (has_stencil) { + assert(ISL_DEV_GEN(dev) < 7); + return 2; /* D24_UNORM_S8_UINT */ + } else { + assert(ISL_DEV_GEN(dev) >= 5); + return 3; /* D24_UNORM_X8_UINT */ + } + case ISL_FORMAT_R16_UNORM: + assert(!has_stencil); + return 5; /* D16_UNORM */ + } +} diff --git a/lib/mesa/src/intel/isl/isl.h b/lib/mesa/src/intel/isl/isl.h new file mode 100644 index 000000000..11ad8919e --- /dev/null +++ b/lib/mesa/src/intel/isl/isl.h @@ -0,0 +1,1482 @@ +/* + * Copyright 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +/** + * @file + * @brief Intel Surface Layout + * + * Header Layout + * ------------- + * The header is ordered as: + * - forward declarations + * - macros that may be overridden at compile-time for specific gens + * - enums and constants + * - structs and unions + * - functions + */ + +#ifndef ISL_H +#define ISL_H + +#include <assert.h> +#include <stdbool.h> +#include <stdint.h> + +#include "c99_compat.h" +#include "util/macros.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct gen_device_info; +struct brw_image_param; + +#ifndef ISL_DEV_GEN +/** + * @brief Get the hardware generation of isl_device. + * + * You can define this as a compile-time constant in the CFLAGS. For example, + * `gcc -DISL_DEV_GEN(dev)=9 ...`. + */ +#define ISL_DEV_GEN(__dev) ((__dev)->info->gen) +#define ISL_DEV_GEN_SANITIZE(__dev) +#else +#define ISL_DEV_GEN_SANITIZE(__dev) \ + (assert(ISL_DEV_GEN(__dev) == (__dev)->info->gen)) +#endif + +#ifndef ISL_DEV_IS_G4X +#define ISL_DEV_IS_G4X(__dev) ((__dev)->info->is_g4x) +#endif + +#ifndef ISL_DEV_IS_HASWELL +/** + * @brief Get the hardware generation of isl_device. + * + * You can define this as a compile-time constant in the CFLAGS. For example, + * `gcc -DISL_DEV_GEN(dev)=9 ...`. + */ +#define ISL_DEV_IS_HASWELL(__dev) ((__dev)->info->is_haswell) +#endif + +#ifndef ISL_DEV_IS_BAYTRAIL +#define ISL_DEV_IS_BAYTRAIL(__dev) ((__dev)->info->is_baytrail) +#endif + +#ifndef ISL_DEV_USE_SEPARATE_STENCIL +/** + * You can define this as a compile-time constant in the CFLAGS. For example, + * `gcc -DISL_DEV_USE_SEPARATE_STENCIL(dev)=1 ...`. + */ +#define ISL_DEV_USE_SEPARATE_STENCIL(__dev) ((__dev)->use_separate_stencil) +#define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev) +#else +#define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev) \ + (assert(ISL_DEV_USE_SEPARATE_STENCIL(__dev) == (__dev)->use_separate_stencil)) +#endif + +/** + * Hardware enumeration SURFACE_FORMAT. + * + * For the official list, see Broadwell PRM: Volume 2b: Command Reference: + * Enumerations: SURFACE_FORMAT. + */ +enum isl_format { + ISL_FORMAT_R32G32B32A32_FLOAT = 0, + ISL_FORMAT_R32G32B32A32_SINT = 1, + ISL_FORMAT_R32G32B32A32_UINT = 2, + ISL_FORMAT_R32G32B32A32_UNORM = 3, + ISL_FORMAT_R32G32B32A32_SNORM = 4, + ISL_FORMAT_R64G64_FLOAT = 5, + ISL_FORMAT_R32G32B32X32_FLOAT = 6, + ISL_FORMAT_R32G32B32A32_SSCALED = 7, + ISL_FORMAT_R32G32B32A32_USCALED = 8, + ISL_FORMAT_R32G32B32A32_SFIXED = 32, + ISL_FORMAT_R64G64_PASSTHRU = 33, + ISL_FORMAT_R32G32B32_FLOAT = 64, + ISL_FORMAT_R32G32B32_SINT = 65, + ISL_FORMAT_R32G32B32_UINT = 66, + ISL_FORMAT_R32G32B32_UNORM = 67, + ISL_FORMAT_R32G32B32_SNORM = 68, + ISL_FORMAT_R32G32B32_SSCALED = 69, + ISL_FORMAT_R32G32B32_USCALED = 70, + ISL_FORMAT_R32G32B32_SFIXED = 80, + ISL_FORMAT_R16G16B16A16_UNORM = 128, + ISL_FORMAT_R16G16B16A16_SNORM = 129, + ISL_FORMAT_R16G16B16A16_SINT = 130, + ISL_FORMAT_R16G16B16A16_UINT = 131, + ISL_FORMAT_R16G16B16A16_FLOAT = 132, + ISL_FORMAT_R32G32_FLOAT = 133, + ISL_FORMAT_R32G32_SINT = 134, + ISL_FORMAT_R32G32_UINT = 135, + ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS = 136, + ISL_FORMAT_X32_TYPELESS_G8X24_UINT = 137, + ISL_FORMAT_L32A32_FLOAT = 138, + ISL_FORMAT_R32G32_UNORM = 139, + ISL_FORMAT_R32G32_SNORM = 140, + ISL_FORMAT_R64_FLOAT = 141, + ISL_FORMAT_R16G16B16X16_UNORM = 142, + ISL_FORMAT_R16G16B16X16_FLOAT = 143, + ISL_FORMAT_A32X32_FLOAT = 144, + ISL_FORMAT_L32X32_FLOAT = 145, + ISL_FORMAT_I32X32_FLOAT = 146, + ISL_FORMAT_R16G16B16A16_SSCALED = 147, + ISL_FORMAT_R16G16B16A16_USCALED = 148, + ISL_FORMAT_R32G32_SSCALED = 149, + ISL_FORMAT_R32G32_USCALED = 150, + ISL_FORMAT_R32G32_FLOAT_LD = 151, + ISL_FORMAT_R32G32_SFIXED = 160, + ISL_FORMAT_R64_PASSTHRU = 161, + ISL_FORMAT_B8G8R8A8_UNORM = 192, + ISL_FORMAT_B8G8R8A8_UNORM_SRGB = 193, + ISL_FORMAT_R10G10B10A2_UNORM = 194, + ISL_FORMAT_R10G10B10A2_UNORM_SRGB = 195, + ISL_FORMAT_R10G10B10A2_UINT = 196, + ISL_FORMAT_R10G10B10_SNORM_A2_UNORM = 197, + ISL_FORMAT_R8G8B8A8_UNORM = 199, + ISL_FORMAT_R8G8B8A8_UNORM_SRGB = 200, + ISL_FORMAT_R8G8B8A8_SNORM = 201, + ISL_FORMAT_R8G8B8A8_SINT = 202, + ISL_FORMAT_R8G8B8A8_UINT = 203, + ISL_FORMAT_R16G16_UNORM = 204, + ISL_FORMAT_R16G16_SNORM = 205, + ISL_FORMAT_R16G16_SINT = 206, + ISL_FORMAT_R16G16_UINT = 207, + ISL_FORMAT_R16G16_FLOAT = 208, + ISL_FORMAT_B10G10R10A2_UNORM = 209, + ISL_FORMAT_B10G10R10A2_UNORM_SRGB = 210, + ISL_FORMAT_R11G11B10_FLOAT = 211, + ISL_FORMAT_R32_SINT = 214, + ISL_FORMAT_R32_UINT = 215, + ISL_FORMAT_R32_FLOAT = 216, + ISL_FORMAT_R24_UNORM_X8_TYPELESS = 217, + ISL_FORMAT_X24_TYPELESS_G8_UINT = 218, + ISL_FORMAT_L32_UNORM = 221, + ISL_FORMAT_A32_UNORM = 222, + ISL_FORMAT_L16A16_UNORM = 223, + ISL_FORMAT_I24X8_UNORM = 224, + ISL_FORMAT_L24X8_UNORM = 225, + ISL_FORMAT_A24X8_UNORM = 226, + ISL_FORMAT_I32_FLOAT = 227, + ISL_FORMAT_L32_FLOAT = 228, + ISL_FORMAT_A32_FLOAT = 229, + ISL_FORMAT_X8B8_UNORM_G8R8_SNORM = 230, + ISL_FORMAT_A8X8_UNORM_G8R8_SNORM = 231, + ISL_FORMAT_B8X8_UNORM_G8R8_SNORM = 232, + ISL_FORMAT_B8G8R8X8_UNORM = 233, + ISL_FORMAT_B8G8R8X8_UNORM_SRGB = 234, + ISL_FORMAT_R8G8B8X8_UNORM = 235, + ISL_FORMAT_R8G8B8X8_UNORM_SRGB = 236, + ISL_FORMAT_R9G9B9E5_SHAREDEXP = 237, + ISL_FORMAT_B10G10R10X2_UNORM = 238, + ISL_FORMAT_L16A16_FLOAT = 240, + ISL_FORMAT_R32_UNORM = 241, + ISL_FORMAT_R32_SNORM = 242, + ISL_FORMAT_R10G10B10X2_USCALED = 243, + ISL_FORMAT_R8G8B8A8_SSCALED = 244, + ISL_FORMAT_R8G8B8A8_USCALED = 245, + ISL_FORMAT_R16G16_SSCALED = 246, + ISL_FORMAT_R16G16_USCALED = 247, + ISL_FORMAT_R32_SSCALED = 248, + ISL_FORMAT_R32_USCALED = 249, + ISL_FORMAT_B5G6R5_UNORM = 256, + ISL_FORMAT_B5G6R5_UNORM_SRGB = 257, + ISL_FORMAT_B5G5R5A1_UNORM = 258, + ISL_FORMAT_B5G5R5A1_UNORM_SRGB = 259, + ISL_FORMAT_B4G4R4A4_UNORM = 260, + ISL_FORMAT_B4G4R4A4_UNORM_SRGB = 261, + ISL_FORMAT_R8G8_UNORM = 262, + ISL_FORMAT_R8G8_SNORM = 263, + ISL_FORMAT_R8G8_SINT = 264, + ISL_FORMAT_R8G8_UINT = 265, + ISL_FORMAT_R16_UNORM = 266, + ISL_FORMAT_R16_SNORM = 267, + ISL_FORMAT_R16_SINT = 268, + ISL_FORMAT_R16_UINT = 269, + ISL_FORMAT_R16_FLOAT = 270, + ISL_FORMAT_A8P8_UNORM_PALETTE0 = 271, + ISL_FORMAT_A8P8_UNORM_PALETTE1 = 272, + ISL_FORMAT_I16_UNORM = 273, + ISL_FORMAT_L16_UNORM = 274, + ISL_FORMAT_A16_UNORM = 275, + ISL_FORMAT_L8A8_UNORM = 276, + ISL_FORMAT_I16_FLOAT = 277, + ISL_FORMAT_L16_FLOAT = 278, + ISL_FORMAT_A16_FLOAT = 279, + ISL_FORMAT_L8A8_UNORM_SRGB = 280, + ISL_FORMAT_R5G5_SNORM_B6_UNORM = 281, + ISL_FORMAT_B5G5R5X1_UNORM = 282, + ISL_FORMAT_B5G5R5X1_UNORM_SRGB = 283, + ISL_FORMAT_R8G8_SSCALED = 284, + ISL_FORMAT_R8G8_USCALED = 285, + ISL_FORMAT_R16_SSCALED = 286, + ISL_FORMAT_R16_USCALED = 287, + ISL_FORMAT_P8A8_UNORM_PALETTE0 = 290, + ISL_FORMAT_P8A8_UNORM_PALETTE1 = 291, + ISL_FORMAT_A1B5G5R5_UNORM = 292, + ISL_FORMAT_A4B4G4R4_UNORM = 293, + ISL_FORMAT_L8A8_UINT = 294, + ISL_FORMAT_L8A8_SINT = 295, + ISL_FORMAT_R8_UNORM = 320, + ISL_FORMAT_R8_SNORM = 321, + ISL_FORMAT_R8_SINT = 322, + ISL_FORMAT_R8_UINT = 323, + ISL_FORMAT_A8_UNORM = 324, + ISL_FORMAT_I8_UNORM = 325, + ISL_FORMAT_L8_UNORM = 326, + ISL_FORMAT_P4A4_UNORM_PALETTE0 = 327, + ISL_FORMAT_A4P4_UNORM_PALETTE0 = 328, + ISL_FORMAT_R8_SSCALED = 329, + ISL_FORMAT_R8_USCALED = 330, + ISL_FORMAT_P8_UNORM_PALETTE0 = 331, + ISL_FORMAT_L8_UNORM_SRGB = 332, + ISL_FORMAT_P8_UNORM_PALETTE1 = 333, + ISL_FORMAT_P4A4_UNORM_PALETTE1 = 334, + ISL_FORMAT_A4P4_UNORM_PALETTE1 = 335, + ISL_FORMAT_Y8_UNORM = 336, + ISL_FORMAT_L8_UINT = 338, + ISL_FORMAT_L8_SINT = 339, + ISL_FORMAT_I8_UINT = 340, + ISL_FORMAT_I8_SINT = 341, + ISL_FORMAT_DXT1_RGB_SRGB = 384, + ISL_FORMAT_R1_UNORM = 385, + ISL_FORMAT_YCRCB_NORMAL = 386, + ISL_FORMAT_YCRCB_SWAPUVY = 387, + ISL_FORMAT_P2_UNORM_PALETTE0 = 388, + ISL_FORMAT_P2_UNORM_PALETTE1 = 389, + ISL_FORMAT_BC1_UNORM = 390, + ISL_FORMAT_BC2_UNORM = 391, + ISL_FORMAT_BC3_UNORM = 392, + ISL_FORMAT_BC4_UNORM = 393, + ISL_FORMAT_BC5_UNORM = 394, + ISL_FORMAT_BC1_UNORM_SRGB = 395, + ISL_FORMAT_BC2_UNORM_SRGB = 396, + ISL_FORMAT_BC3_UNORM_SRGB = 397, + ISL_FORMAT_MONO8 = 398, + ISL_FORMAT_YCRCB_SWAPUV = 399, + ISL_FORMAT_YCRCB_SWAPY = 400, + ISL_FORMAT_DXT1_RGB = 401, + ISL_FORMAT_FXT1 = 402, + ISL_FORMAT_R8G8B8_UNORM = 403, + ISL_FORMAT_R8G8B8_SNORM = 404, + ISL_FORMAT_R8G8B8_SSCALED = 405, + ISL_FORMAT_R8G8B8_USCALED = 406, + ISL_FORMAT_R64G64B64A64_FLOAT = 407, + ISL_FORMAT_R64G64B64_FLOAT = 408, + ISL_FORMAT_BC4_SNORM = 409, + ISL_FORMAT_BC5_SNORM = 410, + ISL_FORMAT_R16G16B16_FLOAT = 411, + ISL_FORMAT_R16G16B16_UNORM = 412, + ISL_FORMAT_R16G16B16_SNORM = 413, + ISL_FORMAT_R16G16B16_SSCALED = 414, + ISL_FORMAT_R16G16B16_USCALED = 415, + ISL_FORMAT_BC6H_SF16 = 417, + ISL_FORMAT_BC7_UNORM = 418, + ISL_FORMAT_BC7_UNORM_SRGB = 419, + ISL_FORMAT_BC6H_UF16 = 420, + ISL_FORMAT_PLANAR_420_8 = 421, + ISL_FORMAT_R8G8B8_UNORM_SRGB = 424, + ISL_FORMAT_ETC1_RGB8 = 425, + ISL_FORMAT_ETC2_RGB8 = 426, + ISL_FORMAT_EAC_R11 = 427, + ISL_FORMAT_EAC_RG11 = 428, + ISL_FORMAT_EAC_SIGNED_R11 = 429, + ISL_FORMAT_EAC_SIGNED_RG11 = 430, + ISL_FORMAT_ETC2_SRGB8 = 431, + ISL_FORMAT_R16G16B16_UINT = 432, + ISL_FORMAT_R16G16B16_SINT = 433, + ISL_FORMAT_R32_SFIXED = 434, + ISL_FORMAT_R10G10B10A2_SNORM = 435, + ISL_FORMAT_R10G10B10A2_USCALED = 436, + ISL_FORMAT_R10G10B10A2_SSCALED = 437, + ISL_FORMAT_R10G10B10A2_SINT = 438, + ISL_FORMAT_B10G10R10A2_SNORM = 439, + ISL_FORMAT_B10G10R10A2_USCALED = 440, + ISL_FORMAT_B10G10R10A2_SSCALED = 441, + ISL_FORMAT_B10G10R10A2_UINT = 442, + ISL_FORMAT_B10G10R10A2_SINT = 443, + ISL_FORMAT_R64G64B64A64_PASSTHRU = 444, + ISL_FORMAT_R64G64B64_PASSTHRU = 445, + ISL_FORMAT_ETC2_RGB8_PTA = 448, + ISL_FORMAT_ETC2_SRGB8_PTA = 449, + ISL_FORMAT_ETC2_EAC_RGBA8 = 450, + ISL_FORMAT_ETC2_EAC_SRGB8_A8 = 451, + ISL_FORMAT_R8G8B8_UINT = 456, + ISL_FORMAT_R8G8B8_SINT = 457, + ISL_FORMAT_RAW = 511, + ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB = 512, + ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB = 520, + ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB = 521, + ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB = 529, + ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB = 530, + ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB = 545, + ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB = 546, + ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB = 548, + ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB = 561, + ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB = 562, + ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB = 564, + ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB = 566, + ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB = 574, + ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB = 575, + ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16 = 576, + ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16 = 584, + ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16 = 585, + ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16 = 593, + ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16 = 594, + ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16 = 609, + ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16 = 610, + ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16 = 612, + ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16 = 625, + ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16 = 626, + ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16 = 628, + ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16 = 630, + ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16 = 638, + ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16 = 639, + + /* The formats that follow are internal to ISL and as such don't have an + * explicit number. We'll just let the C compiler assign it for us. Any + * actual hardware formats *must* come before these in the list. + */ + + /* Formats for auxiliary surfaces */ + ISL_FORMAT_HIZ, + ISL_FORMAT_MCS_2X, + ISL_FORMAT_MCS_4X, + ISL_FORMAT_MCS_8X, + ISL_FORMAT_MCS_16X, + ISL_FORMAT_GEN7_CCS_32BPP_X, + ISL_FORMAT_GEN7_CCS_64BPP_X, + ISL_FORMAT_GEN7_CCS_128BPP_X, + ISL_FORMAT_GEN7_CCS_32BPP_Y, + ISL_FORMAT_GEN7_CCS_64BPP_Y, + ISL_FORMAT_GEN7_CCS_128BPP_Y, + ISL_FORMAT_GEN9_CCS_32BPP, + ISL_FORMAT_GEN9_CCS_64BPP, + ISL_FORMAT_GEN9_CCS_128BPP, + + /* Hardware doesn't understand this out-of-band value */ + ISL_FORMAT_UNSUPPORTED = UINT16_MAX, +}; + +/** + * Numerical base type for channels of isl_format. + */ +enum isl_base_type { + ISL_VOID, + ISL_RAW, + ISL_UNORM, + ISL_SNORM, + ISL_UFLOAT, + ISL_SFLOAT, + ISL_UFIXED, + ISL_SFIXED, + ISL_UINT, + ISL_SINT, + ISL_USCALED, + ISL_SSCALED, +}; + +/** + * Colorspace of isl_format. + */ +enum isl_colorspace { + ISL_COLORSPACE_NONE = 0, + ISL_COLORSPACE_LINEAR, + ISL_COLORSPACE_SRGB, + ISL_COLORSPACE_YUV, +}; + +/** + * Texture compression mode of isl_format. + */ +enum isl_txc { + ISL_TXC_NONE = 0, + ISL_TXC_DXT1, + ISL_TXC_DXT3, + ISL_TXC_DXT5, + ISL_TXC_FXT1, + ISL_TXC_RGTC1, + ISL_TXC_RGTC2, + ISL_TXC_BPTC, + ISL_TXC_ETC1, + ISL_TXC_ETC2, + ISL_TXC_ASTC, + + /* Used for auxiliary surface formats */ + ISL_TXC_HIZ, + ISL_TXC_MCS, + ISL_TXC_CCS, +}; + +/** + * @brief Hardware tile mode + * + * WARNING: These values differ from the hardware enum values, which are + * unstable across hardware generations. + * + * Note that legacy Y tiling is ISL_TILING_Y0 instead of ISL_TILING_Y, to + * clearly distinguish it from Yf and Ys. + */ +enum isl_tiling { + ISL_TILING_LINEAR = 0, + ISL_TILING_W, + ISL_TILING_X, + ISL_TILING_Y0, /**< Legacy Y tiling */ + ISL_TILING_Yf, /**< Standard 4K tiling. The 'f' means "four". */ + ISL_TILING_Ys, /**< Standard 64K tiling. The 's' means "sixty-four". */ + ISL_TILING_HIZ, /**< Tiling format for HiZ surfaces */ + ISL_TILING_CCS, /**< Tiling format for CCS surfaces */ +}; + +/** + * @defgroup Tiling Flags + * @{ + */ +typedef uint32_t isl_tiling_flags_t; +#define ISL_TILING_LINEAR_BIT (1u << ISL_TILING_LINEAR) +#define ISL_TILING_W_BIT (1u << ISL_TILING_W) +#define ISL_TILING_X_BIT (1u << ISL_TILING_X) +#define ISL_TILING_Y0_BIT (1u << ISL_TILING_Y0) +#define ISL_TILING_Yf_BIT (1u << ISL_TILING_Yf) +#define ISL_TILING_Ys_BIT (1u << ISL_TILING_Ys) +#define ISL_TILING_HIZ_BIT (1u << ISL_TILING_HIZ) +#define ISL_TILING_CCS_BIT (1u << ISL_TILING_CCS) +#define ISL_TILING_ANY_MASK (~0u) +#define ISL_TILING_NON_LINEAR_MASK (~ISL_TILING_LINEAR_BIT) + +/** Any Y tiling, including legacy Y tiling. */ +#define ISL_TILING_ANY_Y_MASK (ISL_TILING_Y0_BIT | \ + ISL_TILING_Yf_BIT | \ + ISL_TILING_Ys_BIT) + +/** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */ +#define ISL_TILING_STD_Y_MASK (ISL_TILING_Yf_BIT | \ + ISL_TILING_Ys_BIT) +/** @} */ + +/** + * @brief Logical dimension of surface. + * + * Note: There is no dimension for cube map surfaces. ISL interprets cube maps + * as 2D array surfaces. + */ +enum isl_surf_dim { + ISL_SURF_DIM_1D, + ISL_SURF_DIM_2D, + ISL_SURF_DIM_3D, +}; + +/** + * @brief Physical layout of the surface's dimensions. + */ +enum isl_dim_layout { + /** + * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section + * 6.17.3: 2D Surfaces. + * + * On many gens, 1D surfaces share the same layout as 2D surfaces. From + * the G35 PRM >> Volume 1: Graphics Core >> Section 6.17.2: 1D Surfaces: + * + * One-dimensional surfaces are identical to 2D surfaces with height of + * one. + * + * @invariant isl_surf::phys_level0_sa::depth == 1 + */ + ISL_DIM_LAYOUT_GEN4_2D, + + /** + * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section + * 6.17.5: 3D Surfaces. + * + * @invariant isl_surf::phys_level0_sa::array_len == 1 + */ + ISL_DIM_LAYOUT_GEN4_3D, + + /** + * For details, see the Skylake BSpec >> Memory Views >> Common Surface + * Formats >> Surface Layout and Tiling >> » 1D Surfaces. + */ + ISL_DIM_LAYOUT_GEN9_1D, +}; + +enum isl_aux_usage { + /** No Auxiliary surface is used */ + ISL_AUX_USAGE_NONE, + + /** The primary surface is a depth surface and the auxiliary surface is HiZ */ + ISL_AUX_USAGE_HIZ, + + /** The auxiliary surface is an MCS + * + * @invariant isl_surf::samples > 1 + */ + ISL_AUX_USAGE_MCS, + + /** The auxiliary surface is a fast-clear-only compression surface + * + * @invariant isl_surf::samples == 1 + */ + ISL_AUX_USAGE_CCS_D, + + /** The auxiliary surface provides full lossless color compression + * + * @invariant isl_surf::samples == 1 + */ + ISL_AUX_USAGE_CCS_E, +}; + +/* TODO(chadv): Explain */ +enum isl_array_pitch_span { + ISL_ARRAY_PITCH_SPAN_FULL, + ISL_ARRAY_PITCH_SPAN_COMPACT, +}; + +/** + * @defgroup Surface Usage + * @{ + */ +typedef uint64_t isl_surf_usage_flags_t; +#define ISL_SURF_USAGE_RENDER_TARGET_BIT (1u << 0) +#define ISL_SURF_USAGE_DEPTH_BIT (1u << 1) +#define ISL_SURF_USAGE_STENCIL_BIT (1u << 2) +#define ISL_SURF_USAGE_TEXTURE_BIT (1u << 3) +#define ISL_SURF_USAGE_CUBE_BIT (1u << 4) +#define ISL_SURF_USAGE_DISABLE_AUX_BIT (1u << 5) +#define ISL_SURF_USAGE_DISPLAY_BIT (1u << 6) +#define ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT (1u << 7) +#define ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT (1u << 8) +#define ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT (1u << 9) +#define ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT (1u << 10) +#define ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT (1u << 11) +#define ISL_SURF_USAGE_STORAGE_BIT (1u << 12) +#define ISL_SURF_USAGE_HIZ_BIT (1u << 13) +#define ISL_SURF_USAGE_MCS_BIT (1u << 14) +#define ISL_SURF_USAGE_CCS_BIT (1u << 15) +/** @} */ + +/** + * @brief A channel select (also known as texture swizzle) value + */ +enum isl_channel_select { + ISL_CHANNEL_SELECT_ZERO = 0, + ISL_CHANNEL_SELECT_ONE = 1, + ISL_CHANNEL_SELECT_RED = 4, + ISL_CHANNEL_SELECT_GREEN = 5, + ISL_CHANNEL_SELECT_BLUE = 6, + ISL_CHANNEL_SELECT_ALPHA = 7, +}; + +/** + * Identical to VkSampleCountFlagBits. + */ +enum isl_sample_count { + ISL_SAMPLE_COUNT_1_BIT = 1u, + ISL_SAMPLE_COUNT_2_BIT = 2u, + ISL_SAMPLE_COUNT_4_BIT = 4u, + ISL_SAMPLE_COUNT_8_BIT = 8u, + ISL_SAMPLE_COUNT_16_BIT = 16u, +}; +typedef uint32_t isl_sample_count_mask_t; + +/** + * @brief Multisample Format + */ +enum isl_msaa_layout { + /** + * @brief Suface is single-sampled. + */ + ISL_MSAA_LAYOUT_NONE, + + /** + * @brief [SNB+] Interleaved Multisample Format + * + * In this format, multiple samples are interleaved into each cacheline. + * In other words, the sample index is swizzled into the low 6 bits of the + * surface's virtual address space. + * + * For example, suppose the surface is legacy Y tiled, is 4x multisampled, + * and its pixel format is 32bpp. Then the first cacheline is arranged + * thus: + * + * (0,0,0) (0,1,0) (0,0,1) (1,0,1) + * (1,0,0) (1,1,0) (0,1,1) (1,1,1) + * + * (0,0,2) (1,0,2) (0,0,3) (1,0,3) + * (0,1,2) (1,1,2) (0,1,3) (1,1,3) + * + * The hardware docs refer to this format with multiple terms. In + * Sandybridge, this is the only multisample format; so no term is used. + * The Ivybridge docs refer to surfaces in this format as IMS (Interleaved + * Multisample Surface). Later hardware docs additionally refer to this + * format as MSFMT_DEPTH_STENCIL (because the format is deprecated for + * color surfaces). + * + * See the Sandybridge PRM, Volume 4, Part 1, Section 2.7 "Multisampled + * Surface Behavior". + * + * See the Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.1 "Interleaved + * Multisampled Surfaces". + */ + ISL_MSAA_LAYOUT_INTERLEAVED, + + /** + * @brief [IVB+] Array Multisample Format + * + * In this format, the surface's physical layout resembles that of a + * 2D array surface. + * + * Suppose the multisample surface's logical extent is (w, h) and its + * sample count is N. Then surface's physical extent is the same as + * a singlesample 2D surface whose logical extent is (w, h) and array + * length is N. Array slice `i` contains the pixel values for sample + * index `i`. + * + * The Ivybridge docs refer to surfaces in this format as UMS + * (Uncompressed Multsample Layout) and CMS (Compressed Multisample + * Surface). The Broadwell docs additionally refer to this format as + * MSFMT_MSS (MSS=Multisample Surface Storage). + * + * See the Broadwell PRM, Volume 5 "Memory Views", Section "Uncompressed + * Multisample Surfaces". + * + * See the Broadwell PRM, Volume 5 "Memory Views", Section "Compressed + * Multisample Surfaces". + */ + ISL_MSAA_LAYOUT_ARRAY, +}; + + +struct isl_device { + const struct gen_device_info *info; + bool use_separate_stencil; + bool has_bit6_swizzling; +}; + +struct isl_extent2d { + union { uint32_t w, width; }; + union { uint32_t h, height; }; +}; + +struct isl_extent3d { + union { uint32_t w, width; }; + union { uint32_t h, height; }; + union { uint32_t d, depth; }; +}; + +struct isl_extent4d { + union { uint32_t w, width; }; + union { uint32_t h, height; }; + union { uint32_t d, depth; }; + union { uint32_t a, array_len; }; +}; + +struct isl_channel_layout { + enum isl_base_type type; + uint8_t bits; /**< Size in bits */ +}; + +/** + * Each format has 3D block extent (width, height, depth). The block extent of + * compressed formats is that of the format's compression block. For example, + * the block extent of ISL_FORMAT_ETC2_RGB8 is (w=4, h=4, d=1). The block + * extent of uncompressed pixel formats, such as ISL_FORMAT_R8G8B8A8_UNORM, is + * is (w=1, h=1, d=1). + */ +struct isl_format_layout { + enum isl_format format; + const char *name; + + uint16_t bpb; /**< Bits per block */ + uint8_t bw; /**< Block width, in pixels */ + uint8_t bh; /**< Block height, in pixels */ + uint8_t bd; /**< Block depth, in pixels */ + + struct { + struct isl_channel_layout r; /**< Red channel */ + struct isl_channel_layout g; /**< Green channel */ + struct isl_channel_layout b; /**< Blue channel */ + struct isl_channel_layout a; /**< Alpha channel */ + struct isl_channel_layout l; /**< Luminance channel */ + struct isl_channel_layout i; /**< Intensity channel */ + struct isl_channel_layout p; /**< Palette channel */ + } channels; + + enum isl_colorspace colorspace; + enum isl_txc txc; +}; + +struct isl_tile_info { + enum isl_tiling tiling; + + /* The size (in bits per block) of a single surface element + * + * For surfaces with power-of-two formats, this is the same as + * isl_format_layout::bpb. For non-power-of-two formats it may be smaller. + * The logical_extent_el field is in terms of elements of this size. + * + * For example, consider ISL_FORMAT_R32G32B32_FLOAT for which + * isl_format_layout::bpb is 96 (a non-power-of-two). In this case, none + * of the tiling formats can actually hold an integer number of 96-bit + * surface elements so isl_tiling_get_info returns an isl_tile_info for a + * 32-bit element size. It is the responsibility of the caller to + * recognize that 32 != 96 ad adjust accordingly. For instance, to compute + * the width of a surface in tiles, you would do: + * + * width_tl = DIV_ROUND_UP(width_el * (format_bpb / tile_info.format_bpb), + * tile_info.logical_extent_el.width); + */ + uint32_t format_bpb; + + /** The logical size of the tile in units of format_bpb size elements + * + * This field determines how a given surface is cut up into tiles. It is + * used to compute the size of a surface in tiles and can be used to + * determine the location of the tile containing any given surface element. + * The exact value of this field depends heavily on the bits-per-block of + * the format being used. + */ + struct isl_extent2d logical_extent_el; + + /** The physical size of the tile in bytes and rows of bytes + * + * This field determines how the tiles of a surface are physically layed + * out in memory. The logical and physical tile extent are frequently the + * same but this is not always the case. For instance, a W-tile (which is + * always used with ISL_FORMAT_R8) has a logical size of 64el x 64el but + * its physical size is 128B x 32rows, the same as a Y-tile. + * + * @see isl_surf::row_pitch + */ + struct isl_extent2d phys_extent_B; +}; + +/** + * @brief Input to surface initialization + * + * @invariant width >= 1 + * @invariant height >= 1 + * @invariant depth >= 1 + * @invariant levels >= 1 + * @invariant samples >= 1 + * @invariant array_len >= 1 + * + * @invariant if 1D then height == 1 and depth == 1 and samples == 1 + * @invariant if 2D then depth == 1 + * @invariant if 3D then array_len == 1 and samples == 1 + */ +struct isl_surf_init_info { + enum isl_surf_dim dim; + enum isl_format format; + + uint32_t width; + uint32_t height; + uint32_t depth; + uint32_t levels; + uint32_t array_len; + uint32_t samples; + + /** Lower bound for isl_surf::alignment, in bytes. */ + uint32_t min_alignment; + + /** Lower bound for isl_surf::pitch, in bytes. */ + uint32_t min_pitch; + + isl_surf_usage_flags_t usage; + + /** Flags that alter how ISL selects isl_surf::tiling. */ + isl_tiling_flags_t tiling_flags; +}; + +struct isl_surf { + enum isl_surf_dim dim; + enum isl_dim_layout dim_layout; + enum isl_msaa_layout msaa_layout; + enum isl_tiling tiling; + enum isl_format format; + + /** + * Alignment of the upper-left sample of each subimage, in units of surface + * elements. + */ + struct isl_extent3d image_alignment_el; + + /** + * Logical extent of the surface's base level, in units of pixels. This is + * identical to the extent defined in isl_surf_init_info. + */ + struct isl_extent4d logical_level0_px; + + /** + * Physical extent of the surface's base level, in units of physical + * surface samples and aligned to the format's compression block. + * + * Consider isl_dim_layout as an operator that transforms a logical surface + * layout to a physical surface layout. Then + * + * logical_layout := (isl_surf::dim, isl_surf::logical_level0_px) + * isl_surf::phys_level0_sa := isl_surf::dim_layout * logical_layout + */ + struct isl_extent4d phys_level0_sa; + + uint32_t levels; + uint32_t samples; + + /** Total size of the surface, in bytes. */ + uint32_t size; + + /** Required alignment for the surface's base address. */ + uint32_t alignment; + + /** + * The interpretation of this field depends on the value of + * isl_tile_info::physical_extent_B. In particular, the width of the + * surface in tiles is row_pitch / isl_tile_info::physical_extent_B.width + * and the distance in bytes between vertically adjacent tiles in the image + * is given by row_pitch * isl_tile_info::physical_extent_B.height. + * + * For linear images where isl_tile_info::physical_extent_B.height == 1, + * this cleanly reduces to being the distance, in bytes, between vertically + * adjacent surface elements. + * + * @see isl_tile_info::phys_extent_B; + */ + uint32_t row_pitch; + + /** + * Pitch between physical array slices, in rows of surface elements. + */ + uint32_t array_pitch_el_rows; + + enum isl_array_pitch_span array_pitch_span; + + /** Copy of isl_surf_init_info::usage. */ + isl_surf_usage_flags_t usage; +}; + +struct isl_swizzle { + enum isl_channel_select r:4; + enum isl_channel_select g:4; + enum isl_channel_select b:4; + enum isl_channel_select a:4; +}; + +#define ISL_SWIZZLE(R, G, B, A) ((struct isl_swizzle) { \ + .r = ISL_CHANNEL_SELECT_##R, \ + .g = ISL_CHANNEL_SELECT_##G, \ + .b = ISL_CHANNEL_SELECT_##B, \ + .a = ISL_CHANNEL_SELECT_##A, \ + }) + +#define ISL_SWIZZLE_IDENTITY ISL_SWIZZLE(RED, GREEN, BLUE, ALPHA) + +struct isl_view { + /** + * Indicates the usage of the particular view + * + * Normally, this is one bit. However, for a cube map texture, it + * should be ISL_SURF_USAGE_TEXTURE_BIT | ISL_SURF_USAGE_CUBE_BIT. + */ + isl_surf_usage_flags_t usage; + + /** + * The format to use in the view + * + * This may differ from the format of the actual isl_surf but must have + * the same block size. + */ + enum isl_format format; + + uint32_t base_level; + uint32_t levels; + + /** + * Base array layer + * + * For cube maps, both base_array_layer and array_len should be + * specified in terms of 2-D layers and must be a multiple of 6. + * + * 3-D textures are effectively treated as 2-D arrays when used as a + * storage image or render target. If `usage` contains + * ISL_SURF_USAGE_RENDER_TARGET_BIT or ISL_SURF_USAGE_STORAGE_BIT then + * base_array_layer and array_len are applied. If the surface is only used + * for texturing, they are ignored. + */ + uint32_t base_array_layer; + uint32_t array_len; + + struct isl_swizzle swizzle; +}; + +union isl_color_value { + float f32[4]; + uint32_t u32[4]; + int32_t i32[4]; +}; + +struct isl_surf_fill_state_info { + const struct isl_surf *surf; + const struct isl_view *view; + + /** + * The address of the surface in GPU memory. + */ + uint64_t address; + + /** + * The Memory Object Control state for the filled surface state. + * + * The exact format of this value depends on hardware generation. + */ + uint32_t mocs; + + /** + * The auxilary surface or NULL if no auxilary surface is to be used. + */ + const struct isl_surf *aux_surf; + enum isl_aux_usage aux_usage; + uint64_t aux_address; + + /** + * The clear color for this surface + * + * Valid values depend on hardware generation. + */ + union isl_color_value clear_color; + + /* Intra-tile offset */ + uint16_t x_offset_sa, y_offset_sa; +}; + +struct isl_buffer_fill_state_info { + /** + * The address of the surface in GPU memory. + */ + uint64_t address; + + /** + * The size of the buffer + */ + uint64_t size; + + /** + * The Memory Object Control state for the filled surface state. + * + * The exact format of this value depends on hardware generation. + */ + uint32_t mocs; + + /** + * The format to use in the surface state + * + * This may differ from the format of the actual isl_surf but have the + * same block size. + */ + enum isl_format format; + + uint32_t stride; +}; + +extern const struct isl_format_layout isl_format_layouts[]; + +void +isl_device_init(struct isl_device *dev, + const struct gen_device_info *info, + bool has_bit6_swizzling); + +isl_sample_count_mask_t ATTRIBUTE_CONST +isl_device_get_sample_counts(struct isl_device *dev); + +static inline const struct isl_format_layout * ATTRIBUTE_CONST +isl_format_get_layout(enum isl_format fmt) +{ + return &isl_format_layouts[fmt]; +} + +static inline const char * ATTRIBUTE_CONST +isl_format_get_name(enum isl_format fmt) +{ + return isl_format_layouts[fmt].name; +} + +bool isl_format_supports_rendering(const struct gen_device_info *devinfo, + enum isl_format format); +bool isl_format_supports_alpha_blending(const struct gen_device_info *devinfo, + enum isl_format format); +bool isl_format_supports_sampling(const struct gen_device_info *devinfo, + enum isl_format format); +bool isl_format_supports_filtering(const struct gen_device_info *devinfo, + enum isl_format format); +bool isl_format_supports_vertex_fetch(const struct gen_device_info *devinfo, + enum isl_format format); +bool isl_format_supports_lossless_compression(const struct gen_device_info *devinfo, + enum isl_format format); +bool isl_format_supports_multisampling(const struct gen_device_info *devinfo, + enum isl_format format); + +bool isl_format_has_unorm_channel(enum isl_format fmt) ATTRIBUTE_CONST; +bool isl_format_has_snorm_channel(enum isl_format fmt) ATTRIBUTE_CONST; +bool isl_format_has_ufloat_channel(enum isl_format fmt) ATTRIBUTE_CONST; +bool isl_format_has_sfloat_channel(enum isl_format fmt) ATTRIBUTE_CONST; +bool isl_format_has_uint_channel(enum isl_format fmt) ATTRIBUTE_CONST; +bool isl_format_has_sint_channel(enum isl_format fmt) ATTRIBUTE_CONST; + +static inline bool +isl_format_has_normalized_channel(enum isl_format fmt) +{ + return isl_format_has_unorm_channel(fmt) || + isl_format_has_snorm_channel(fmt); +} + +static inline bool +isl_format_has_float_channel(enum isl_format fmt) +{ + return isl_format_has_ufloat_channel(fmt) || + isl_format_has_sfloat_channel(fmt); +} + +static inline bool +isl_format_has_int_channel(enum isl_format fmt) +{ + return isl_format_has_uint_channel(fmt) || + isl_format_has_sint_channel(fmt); +} + +unsigned isl_format_get_num_channels(enum isl_format fmt); + +uint32_t isl_format_get_depth_format(enum isl_format fmt, bool has_stencil); + +static inline bool +isl_format_is_compressed(enum isl_format fmt) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(fmt); + + return fmtl->txc != ISL_TXC_NONE; +} + +static inline bool +isl_format_has_bc_compression(enum isl_format fmt) +{ + switch (isl_format_get_layout(fmt)->txc) { + case ISL_TXC_DXT1: + case ISL_TXC_DXT3: + case ISL_TXC_DXT5: + return true; + case ISL_TXC_NONE: + case ISL_TXC_FXT1: + case ISL_TXC_RGTC1: + case ISL_TXC_RGTC2: + case ISL_TXC_BPTC: + case ISL_TXC_ETC1: + case ISL_TXC_ETC2: + case ISL_TXC_ASTC: + return false; + + case ISL_TXC_HIZ: + case ISL_TXC_MCS: + case ISL_TXC_CCS: + unreachable("Should not be called on an aux surface"); + } + + unreachable("bad texture compression mode"); + return false; +} + +static inline bool +isl_format_is_yuv(enum isl_format fmt) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(fmt); + + return fmtl->colorspace == ISL_COLORSPACE_YUV; +} + +static inline bool +isl_format_block_is_1x1x1(enum isl_format fmt) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(fmt); + + return fmtl->bw == 1 && fmtl->bh == 1 && fmtl->bd == 1; +} + +static inline bool +isl_format_is_rgb(enum isl_format fmt) +{ + return isl_format_layouts[fmt].channels.r.bits > 0 && + isl_format_layouts[fmt].channels.g.bits > 0 && + isl_format_layouts[fmt].channels.b.bits > 0 && + isl_format_layouts[fmt].channels.a.bits == 0; +} + +enum isl_format isl_format_rgb_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST; +enum isl_format isl_format_rgb_to_rgbx(enum isl_format rgb) ATTRIBUTE_CONST; + +bool isl_is_storage_image_format(enum isl_format fmt); + +enum isl_format +isl_lower_storage_image_format(const struct gen_device_info *devinfo, + enum isl_format fmt); + +/* Returns true if this hardware supports typed load/store on a format with + * the same size as the given format. + */ +bool +isl_has_matching_typed_storage_image_format(const struct gen_device_info *devinfo, + enum isl_format fmt); + +static inline bool +isl_tiling_is_any_y(enum isl_tiling tiling) +{ + return (1u << tiling) & ISL_TILING_ANY_Y_MASK; +} + +static inline bool +isl_tiling_is_std_y(enum isl_tiling tiling) +{ + return (1u << tiling) & ISL_TILING_STD_Y_MASK; +} + +struct isl_extent2d ATTRIBUTE_CONST +isl_get_interleaved_msaa_px_size_sa(uint32_t samples); + +static inline bool +isl_surf_usage_is_display(isl_surf_usage_flags_t usage) +{ + return usage & ISL_SURF_USAGE_DISPLAY_BIT; +} + +static inline bool +isl_surf_usage_is_depth(isl_surf_usage_flags_t usage) +{ + return usage & ISL_SURF_USAGE_DEPTH_BIT; +} + +static inline bool +isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage) +{ + return usage & ISL_SURF_USAGE_STENCIL_BIT; +} + +static inline bool +isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage) +{ + return (usage & ISL_SURF_USAGE_DEPTH_BIT) && + (usage & ISL_SURF_USAGE_STENCIL_BIT); +} + +static inline bool +isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage) +{ + return usage & (ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_STENCIL_BIT); +} + +static inline bool +isl_surf_info_is_z16(const struct isl_surf_init_info *info) +{ + return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) && + (info->format == ISL_FORMAT_R16_UNORM); +} + +static inline bool +isl_surf_info_is_z32_float(const struct isl_surf_init_info *info) +{ + return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) && + (info->format == ISL_FORMAT_R32_FLOAT); +} + +static inline struct isl_extent2d +isl_extent2d(uint32_t width, uint32_t height) +{ + struct isl_extent2d e = { { 0 } }; + + e.width = width; + e.height = height; + + return e; +} + +static inline struct isl_extent3d +isl_extent3d(uint32_t width, uint32_t height, uint32_t depth) +{ + struct isl_extent3d e = { { 0 } }; + + e.width = width; + e.height = height; + e.depth = depth; + + return e; +} + +static inline struct isl_extent4d +isl_extent4d(uint32_t width, uint32_t height, uint32_t depth, + uint32_t array_len) +{ + struct isl_extent4d e = { { 0 } }; + + e.width = width; + e.height = height; + e.depth = depth; + e.array_len = array_len; + + return e; +} + +#define isl_surf_init(dev, surf, ...) \ + isl_surf_init_s((dev), (surf), \ + &(struct isl_surf_init_info) { __VA_ARGS__ }); + +bool +isl_surf_init_s(const struct isl_device *dev, + struct isl_surf *surf, + const struct isl_surf_init_info *restrict info); + +void +isl_surf_get_tile_info(const struct isl_device *dev, + const struct isl_surf *surf, + struct isl_tile_info *tile_info); + +void +isl_surf_get_hiz_surf(const struct isl_device *dev, + const struct isl_surf *surf, + struct isl_surf *hiz_surf); + +void +isl_surf_get_mcs_surf(const struct isl_device *dev, + const struct isl_surf *surf, + struct isl_surf *mcs_surf); + +bool +isl_surf_get_ccs_surf(const struct isl_device *dev, + const struct isl_surf *surf, + struct isl_surf *ccs_surf); + +#define isl_surf_fill_state(dev, state, ...) \ + isl_surf_fill_state_s((dev), (state), \ + &(struct isl_surf_fill_state_info) { __VA_ARGS__ }); + +void +isl_surf_fill_state_s(const struct isl_device *dev, void *state, + const struct isl_surf_fill_state_info *restrict info); + +#define isl_buffer_fill_state(dev, state, ...) \ + isl_buffer_fill_state_s((dev), (state), \ + &(struct isl_buffer_fill_state_info) { __VA_ARGS__ }); + +void +isl_buffer_fill_state_s(const struct isl_device *dev, void *state, + const struct isl_buffer_fill_state_info *restrict info); + +void +isl_surf_fill_image_param(const struct isl_device *dev, + struct brw_image_param *param, + const struct isl_surf *surf, + const struct isl_view *view); + +void +isl_buffer_fill_image_param(const struct isl_device *dev, + struct brw_image_param *param, + enum isl_format format, + uint64_t size); + +/** + * Alignment of the upper-left sample of each subimage, in units of surface + * elements. + */ +static inline struct isl_extent3d +isl_surf_get_image_alignment_el(const struct isl_surf *surf) +{ + return surf->image_alignment_el; +} + +/** + * Alignment of the upper-left sample of each subimage, in units of surface + * samples. + */ +static inline struct isl_extent3d +isl_surf_get_image_alignment_sa(const struct isl_surf *surf) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format); + + return isl_extent3d(fmtl->bw * surf->image_alignment_el.w, + fmtl->bh * surf->image_alignment_el.h, + fmtl->bd * surf->image_alignment_el.d); +} + +/** + * Pitch between vertically adjacent surface elements, in bytes. + */ +static inline uint32_t +isl_surf_get_row_pitch(const struct isl_surf *surf) +{ + return surf->row_pitch; +} + +/** + * Pitch between vertically adjacent surface elements, in units of surface elements. + */ +static inline uint32_t +isl_surf_get_row_pitch_el(const struct isl_surf *surf) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format); + + assert(surf->row_pitch % (fmtl->bpb / 8) == 0); + return surf->row_pitch / (fmtl->bpb / 8); +} + +/** + * Pitch between physical array slices, in rows of surface elements. + */ +static inline uint32_t +isl_surf_get_array_pitch_el_rows(const struct isl_surf *surf) +{ + return surf->array_pitch_el_rows; +} + +/** + * Pitch between physical array slices, in units of surface elements. + */ +static inline uint32_t +isl_surf_get_array_pitch_el(const struct isl_surf *surf) +{ + return isl_surf_get_array_pitch_el_rows(surf) * + isl_surf_get_row_pitch_el(surf); +} + +/** + * Pitch between physical array slices, in rows of surface samples. + */ +static inline uint32_t +isl_surf_get_array_pitch_sa_rows(const struct isl_surf *surf) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format); + return fmtl->bh * isl_surf_get_array_pitch_el_rows(surf); +} + +/** + * Pitch between physical array slices, in bytes. + */ +static inline uint32_t +isl_surf_get_array_pitch(const struct isl_surf *surf) +{ + return isl_surf_get_array_pitch_sa_rows(surf) * surf->row_pitch; +} + +/** + * Calculate the offset, in units of surface samples, to a subimage in the + * surface. + * + * @invariant level < surface levels + * @invariant logical_array_layer < logical array length of surface + * @invariant logical_z_offset_px < logical depth of surface at level + */ +void +isl_surf_get_image_offset_sa(const struct isl_surf *surf, + uint32_t level, + uint32_t logical_array_layer, + uint32_t logical_z_offset_px, + uint32_t *x_offset_sa, + uint32_t *y_offset_sa); + +/** + * Calculate the offset, in units of surface elements, to a subimage in the + * surface. + * + * @invariant level < surface levels + * @invariant logical_array_layer < logical array length of surface + * @invariant logical_z_offset_px < logical depth of surface at level + */ +void +isl_surf_get_image_offset_el(const struct isl_surf *surf, + uint32_t level, + uint32_t logical_array_layer, + uint32_t logical_z_offset_px, + uint32_t *x_offset_el, + uint32_t *y_offset_el); + +/** + * @brief Calculate the intratile offsets to a surface. + * + * In @a base_address_offset return the offset from the base of the surface to + * the base address of the first tile of the subimage. In @a x_offset_B and + * @a y_offset_rows, return the offset, in units of bytes and rows, from the + * tile's base to the subimage's first surface element. The x and y offsets + * are intratile offsets; that is, they do not exceed the boundary of the + * surface's tiling format. + */ +void +isl_tiling_get_intratile_offset_el(const struct isl_device *dev, + enum isl_tiling tiling, + uint8_t bs, + uint32_t row_pitch, + uint32_t total_x_offset_el, + uint32_t total_y_offset_el, + uint32_t *base_address_offset, + uint32_t *x_offset_el, + uint32_t *y_offset_el); + +static inline void +isl_tiling_get_intratile_offset_sa(const struct isl_device *dev, + enum isl_tiling tiling, + enum isl_format format, + uint32_t row_pitch, + uint32_t total_x_offset_sa, + uint32_t total_y_offset_sa, + uint32_t *base_address_offset, + uint32_t *x_offset_sa, + uint32_t *y_offset_sa) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(format); + + assert(fmtl->bpb % 8 == 0); + + /* For computing the intratile offsets, we actually want a strange unit + * which is samples for multisampled surfaces but elements for compressed + * surfaces. + */ + assert(total_x_offset_sa % fmtl->bw == 0); + assert(total_y_offset_sa % fmtl->bh == 0); + const uint32_t total_x_offset = total_x_offset_sa / fmtl->bw; + const uint32_t total_y_offset = total_y_offset_sa / fmtl->bh; + + isl_tiling_get_intratile_offset_el(dev, tiling, fmtl->bpb / 8, row_pitch, + total_x_offset, total_y_offset, + base_address_offset, + x_offset_sa, y_offset_sa); + *x_offset_sa *= fmtl->bw; + *y_offset_sa *= fmtl->bh; +} + +/** + * @brief Get value of 3DSTATE_DEPTH_BUFFER.SurfaceFormat + * + * @pre surf->usage has ISL_SURF_USAGE_DEPTH_BIT + * @pre surf->format must be a valid format for depth surfaces + */ +uint32_t +isl_surf_get_depth_format(const struct isl_device *dev, + const struct isl_surf *surf); + +#ifdef __cplusplus +} +#endif + +#endif /* ISL_H */ diff --git a/lib/mesa/src/intel/isl/isl_format.c b/lib/mesa/src/intel/isl/isl_format.c new file mode 100644 index 000000000..daf2d8134 --- /dev/null +++ b/lib/mesa/src/intel/isl/isl_format.c @@ -0,0 +1,608 @@ +/* + * Copyright 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#include <assert.h> + +#include "isl.h" +#include "common/gen_device_info.h" + +struct surface_format_info { + bool exists; + uint8_t sampling; + uint8_t filtering; + uint8_t shadow_compare; + uint8_t chroma_key; + uint8_t render_target; + uint8_t alpha_blend; + uint8_t input_vb; + uint8_t streamed_output_vb; + uint8_t color_processing; + uint8_t lossless_compression; +}; + +/* This macro allows us to write the table almost as it appears in the PRM, + * while restructuring it to turn it into the C code we want. + */ +#define SF(sampl, filt, shad, ck, rt, ab, vb, so, color, ccs_e, sf) \ + [ISL_FORMAT_##sf] = { true, sampl, filt, shad, ck, rt, ab, vb, so, color, ccs_e}, + +#define Y 0 +#define x 255 +/** + * This is the table of support for surface (texture, renderbuffer, and vertex + * buffer, but not depthbuffer) formats across the various hardware generations. + * + * The table is formatted to match the documentation, except that the docs have + * this ridiculous mapping of Y[*+~^#&] for "supported on DevWhatever". To put + * it in our table, here's the mapping: + * + * Y*: 45 + * Y+: 45 (g45/gm45) + * Y~: 50 (gen5) + * Y^: 60 (gen6) + * Y#: 70 (gen7) + * + * The abbreviations in the header below are: + * smpl - Sampling Engine + * filt - Sampling Engine Filtering + * shad - Sampling Engine Shadow Map + * CK - Sampling Engine Chroma Key + * RT - Render Target + * AB - Alpha Blend Render Target + * VB - Input Vertex Buffer + * SO - Steamed Output Vertex Buffers (transform feedback) + * color - Color Processing + * ccs_e - Lossless Compression Support (gen9+ only) + * sf - Surface Format + * + * See page 88 of the Sandybridge PRM VOL4_Part1 PDF. + * + * As of Ivybridge, the columns are no longer in that table and the + * information can be found spread across: + * + * - VOL2_Part1 section 2.5.11 Format Conversion (vertex fetch). + * - VOL4_Part1 section 2.12.2.1.2 Sampler Output Channel Mapping. + * - VOL4_Part1 section 3.9.11 Render Target Write. + * - Render Target Surface Types [SKL+] + */ +static const struct surface_format_info format_info[] = { +/* smpl filt shad CK RT AB VB SO color ccs_e */ + SF( Y, 50, x, x, Y, Y, Y, Y, x, 90, R32G32B32A32_FLOAT) + SF( Y, x, x, x, Y, x, Y, Y, x, 90, R32G32B32A32_SINT) + SF( Y, x, x, x, Y, x, Y, Y, x, 90, R32G32B32A32_UINT) + SF( x, x, x, x, x, x, Y, x, x, x, R32G32B32A32_UNORM) + SF( x, x, x, x, x, x, Y, x, x, x, R32G32B32A32_SNORM) + SF( x, x, x, x, x, x, Y, x, x, x, R64G64_FLOAT) + SF( Y, 50, x, x, x, x, x, x, x, x, R32G32B32X32_FLOAT) + SF( x, x, x, x, x, x, Y, x, x, x, R32G32B32A32_SSCALED) + SF( x, x, x, x, x, x, Y, x, x, x, R32G32B32A32_USCALED) + SF( x, x, x, x, x, x, 75, x, x, x, R32G32B32A32_SFIXED) + SF( x, x, x, x, x, x, x, x, x, x, R64G64_PASSTHRU) + SF( Y, 50, x, x, x, x, Y, Y, x, x, R32G32B32_FLOAT) + SF( Y, x, x, x, x, x, Y, Y, x, x, R32G32B32_SINT) + SF( Y, x, x, x, x, x, Y, Y, x, x, R32G32B32_UINT) + SF( x, x, x, x, x, x, Y, x, x, x, R32G32B32_UNORM) + SF( x, x, x, x, x, x, Y, x, x, x, R32G32B32_SNORM) + SF( x, x, x, x, x, x, Y, x, x, x, R32G32B32_SSCALED) + SF( x, x, x, x, x, x, Y, x, x, x, R32G32B32_USCALED) + SF( x, x, x, x, x, x, 75, x, x, x, R32G32B32_SFIXED) + SF( Y, Y, x, x, Y, 45, Y, x, 60, 90, R16G16B16A16_UNORM) + SF( Y, Y, x, x, Y, 60, Y, x, x, 90, R16G16B16A16_SNORM) + SF( Y, x, x, x, Y, x, Y, x, x, 90, R16G16B16A16_SINT) + SF( Y, x, x, x, Y, x, Y, x, x, 90, R16G16B16A16_UINT) + SF( Y, Y, x, x, Y, Y, Y, x, x, 90, R16G16B16A16_FLOAT) + SF( Y, 50, x, x, Y, Y, Y, Y, x, 90, R32G32_FLOAT) + SF( Y, 70, x, x, Y, Y, Y, Y, x, x, R32G32_FLOAT_LD) + SF( Y, x, x, x, Y, x, Y, Y, x, 90, R32G32_SINT) + SF( Y, x, x, x, Y, x, Y, Y, x, 90, R32G32_UINT) + SF( Y, 50, Y, x, x, x, x, x, x, x, R32_FLOAT_X8X24_TYPELESS) + SF( Y, x, x, x, x, x, x, x, x, x, X32_TYPELESS_G8X24_UINT) + SF( Y, 50, x, x, x, x, x, x, x, x, L32A32_FLOAT) + SF( x, x, x, x, x, x, Y, x, x, x, R32G32_UNORM) + SF( x, x, x, x, x, x, Y, x, x, x, R32G32_SNORM) + SF( x, x, x, x, x, x, Y, x, x, x, R64_FLOAT) + SF( Y, Y, x, x, x, x, x, x, x, x, R16G16B16X16_UNORM) + SF( Y, Y, x, x, x, x, x, x, x, 90, R16G16B16X16_FLOAT) + SF( Y, 50, x, x, x, x, x, x, x, x, A32X32_FLOAT) + SF( Y, 50, x, x, x, x, x, x, x, x, L32X32_FLOAT) + SF( Y, 50, x, x, x, x, x, x, x, x, I32X32_FLOAT) + SF( x, x, x, x, x, x, Y, x, x, x, R16G16B16A16_SSCALED) + SF( x, x, x, x, x, x, Y, x, x, x, R16G16B16A16_USCALED) + SF( x, x, x, x, x, x, Y, x, x, x, R32G32_SSCALED) + SF( x, x, x, x, x, x, Y, x, x, x, R32G32_USCALED) + SF( x, x, x, x, x, x, 75, x, x, x, R32G32_SFIXED) + SF( x, x, x, x, x, x, x, x, x, x, R64_PASSTHRU) + SF( Y, Y, x, Y, Y, Y, Y, x, 60, 90, B8G8R8A8_UNORM) + SF( Y, Y, x, x, Y, Y, x, x, x, x, B8G8R8A8_UNORM_SRGB) +/* smpl filt shad CK RT AB VB SO color ccs_e */ + SF( Y, Y, x, x, Y, Y, Y, x, 60, x, R10G10B10A2_UNORM) + SF( Y, Y, x, x, x, x, x, x, 60, x, R10G10B10A2_UNORM_SRGB) + SF( Y, x, x, x, Y, x, Y, x, x, x, R10G10B10A2_UINT) + SF( Y, Y, x, x, x, x, Y, x, x, x, R10G10B10_SNORM_A2_UNORM) + SF( Y, Y, x, x, Y, Y, Y, x, 60, 90, R8G8B8A8_UNORM) + SF( Y, Y, x, x, Y, Y, x, x, 60, x, R8G8B8A8_UNORM_SRGB) + SF( Y, Y, x, x, Y, 60, Y, x, x, 90, R8G8B8A8_SNORM) + SF( Y, x, x, x, Y, x, Y, x, x, 90, R8G8B8A8_SINT) + SF( Y, x, x, x, Y, x, Y, x, x, 90, R8G8B8A8_UINT) + SF( Y, Y, x, x, Y, 45, Y, x, x, 90, R16G16_UNORM) + SF( Y, Y, x, x, Y, 60, Y, x, x, 90, R16G16_SNORM) + SF( Y, x, x, x, Y, x, Y, x, x, 90, R16G16_SINT) + SF( Y, x, x, x, Y, x, Y, x, x, 90, R16G16_UINT) + SF( Y, Y, x, x, Y, Y, Y, x, x, 90, R16G16_FLOAT) + SF( Y, Y, x, x, Y, Y, 75, x, 60, x, B10G10R10A2_UNORM) + SF( Y, Y, x, x, Y, Y, x, x, 60, x, B10G10R10A2_UNORM_SRGB) + SF( Y, Y, x, x, Y, Y, Y, x, x, x, R11G11B10_FLOAT) + SF( Y, x, x, x, Y, x, Y, Y, x, 90, R32_SINT) + SF( Y, x, x, x, Y, x, Y, Y, x, 90, R32_UINT) + SF( Y, 50, Y, x, Y, Y, Y, Y, x, 90, R32_FLOAT) + SF( Y, 50, Y, x, x, x, x, x, x, x, R24_UNORM_X8_TYPELESS) + SF( Y, x, x, x, x, x, x, x, x, x, X24_TYPELESS_G8_UINT) + SF( Y, Y, x, x, x, x, x, x, x, x, L16A16_UNORM) + SF( Y, 50, Y, x, x, x, x, x, x, x, I24X8_UNORM) + SF( Y, 50, Y, x, x, x, x, x, x, x, L24X8_UNORM) + SF( Y, 50, Y, x, x, x, x, x, x, x, A24X8_UNORM) + SF( Y, 50, Y, x, x, x, x, x, x, x, I32_FLOAT) + SF( Y, 50, Y, x, x, x, x, x, x, x, L32_FLOAT) + SF( Y, 50, Y, x, x, x, x, x, x, x, A32_FLOAT) + SF( Y, Y, x, Y, 80, 80, x, x, 60, 90, B8G8R8X8_UNORM) + SF( Y, Y, x, x, 80, 80, x, x, x, x, B8G8R8X8_UNORM_SRGB) + SF( Y, Y, x, x, x, x, x, x, x, x, R8G8B8X8_UNORM) + SF( Y, Y, x, x, x, x, x, x, x, x, R8G8B8X8_UNORM_SRGB) + SF( Y, Y, x, x, x, x, x, x, x, x, R9G9B9E5_SHAREDEXP) + SF( Y, Y, x, x, x, x, x, x, x, x, B10G10R10X2_UNORM) + SF( Y, Y, x, x, x, x, x, x, x, x, L16A16_FLOAT) + SF( x, x, x, x, x, x, Y, x, x, x, R32_UNORM) + SF( x, x, x, x, x, x, Y, x, x, x, R32_SNORM) +/* smpl filt shad CK RT AB VB SO color ccs_e */ + SF( x, x, x, x, x, x, Y, x, x, x, R10G10B10X2_USCALED) + SF( x, x, x, x, x, x, Y, x, x, x, R8G8B8A8_SSCALED) + SF( x, x, x, x, x, x, Y, x, x, x, R8G8B8A8_USCALED) + SF( x, x, x, x, x, x, Y, x, x, x, R16G16_SSCALED) + SF( x, x, x, x, x, x, Y, x, x, x, R16G16_USCALED) + SF( x, x, x, x, x, x, Y, x, x, x, R32_SSCALED) + SF( x, x, x, x, x, x, Y, x, x, x, R32_USCALED) + SF( Y, Y, x, Y, Y, Y, x, x, x, x, B5G6R5_UNORM) + SF( Y, Y, x, x, Y, Y, x, x, x, x, B5G6R5_UNORM_SRGB) + SF( Y, Y, x, Y, Y, Y, x, x, x, x, B5G5R5A1_UNORM) + SF( Y, Y, x, x, Y, Y, x, x, x, x, B5G5R5A1_UNORM_SRGB) + SF( Y, Y, x, Y, Y, Y, x, x, x, x, B4G4R4A4_UNORM) + SF( Y, Y, x, x, Y, Y, x, x, x, x, B4G4R4A4_UNORM_SRGB) + SF( Y, Y, x, x, Y, Y, Y, x, x, x, R8G8_UNORM) + SF( Y, Y, x, Y, Y, 60, Y, x, x, x, R8G8_SNORM) + SF( Y, x, x, x, Y, x, Y, x, x, x, R8G8_SINT) + SF( Y, x, x, x, Y, x, Y, x, x, x, R8G8_UINT) + SF( Y, Y, Y, x, Y, 45, Y, x, 70, x, R16_UNORM) + SF( Y, Y, x, x, Y, 60, Y, x, x, x, R16_SNORM) + SF( Y, x, x, x, Y, x, Y, x, x, x, R16_SINT) + SF( Y, x, x, x, Y, x, Y, x, x, x, R16_UINT) + SF( Y, Y, x, x, Y, Y, Y, x, x, x, R16_FLOAT) + SF(50, 50, x, x, x, x, x, x, x, x, A8P8_UNORM_PALETTE0) + SF(50, 50, x, x, x, x, x, x, x, x, A8P8_UNORM_PALETTE1) + SF( Y, Y, Y, x, x, x, x, x, x, x, I16_UNORM) + SF( Y, Y, Y, x, x, x, x, x, x, x, L16_UNORM) + SF( Y, Y, Y, x, x, x, x, x, x, x, A16_UNORM) + SF( Y, Y, x, Y, x, x, x, x, x, x, L8A8_UNORM) + SF( Y, Y, Y, x, x, x, x, x, x, x, I16_FLOAT) + SF( Y, Y, Y, x, x, x, x, x, x, x, L16_FLOAT) + SF( Y, Y, Y, x, x, x, x, x, x, x, A16_FLOAT) + SF(45, 45, x, x, x, x, x, x, x, x, L8A8_UNORM_SRGB) + SF( Y, Y, x, Y, x, x, x, x, x, x, R5G5_SNORM_B6_UNORM) + SF( x, x, x, x, Y, Y, x, x, x, x, B5G5R5X1_UNORM) + SF( x, x, x, x, Y, Y, x, x, x, x, B5G5R5X1_UNORM_SRGB) + SF( x, x, x, x, x, x, Y, x, x, x, R8G8_SSCALED) + SF( x, x, x, x, x, x, Y, x, x, x, R8G8_USCALED) +/* smpl filt shad CK RT AB VB SO color ccs_e */ + SF( x, x, x, x, x, x, Y, x, x, x, R16_SSCALED) + SF( x, x, x, x, x, x, Y, x, x, x, R16_USCALED) + SF(50, 50, x, x, x, x, x, x, x, x, P8A8_UNORM_PALETTE0) + SF(50, 50, x, x, x, x, x, x, x, x, P8A8_UNORM_PALETTE1) + SF( x, x, x, x, x, x, x, x, x, x, A1B5G5R5_UNORM) + SF(90, 90, x, x, 90, x, x, x, x, x, A4B4G4R4_UNORM) + SF(90, x, x, x, x, x, x, x, x, x, L8A8_UINT) + SF(90, x, x, x, x, x, x, x, x, x, L8A8_SINT) + SF( Y, Y, x, 45, Y, Y, Y, x, x, x, R8_UNORM) + SF( Y, Y, x, x, Y, 60, Y, x, x, x, R8_SNORM) + SF( Y, x, x, x, Y, x, Y, x, x, x, R8_SINT) + SF( Y, x, x, x, Y, x, Y, x, x, x, R8_UINT) + SF( Y, Y, x, Y, Y, Y, x, x, x, x, A8_UNORM) + SF( Y, Y, x, x, x, x, x, x, x, x, I8_UNORM) + SF( Y, Y, x, Y, x, x, x, x, x, x, L8_UNORM) + SF( Y, Y, x, x, x, x, x, x, x, x, P4A4_UNORM_PALETTE0) + SF( Y, Y, x, x, x, x, x, x, x, x, A4P4_UNORM_PALETTE0) + SF( x, x, x, x, x, x, Y, x, x, x, R8_SSCALED) + SF( x, x, x, x, x, x, Y, x, x, x, R8_USCALED) + SF(45, 45, x, x, x, x, x, x, x, x, P8_UNORM_PALETTE0) + SF(45, 45, x, x, x, x, x, x, x, x, L8_UNORM_SRGB) + SF(45, 45, x, x, x, x, x, x, x, x, P8_UNORM_PALETTE1) + SF(45, 45, x, x, x, x, x, x, x, x, P4A4_UNORM_PALETTE1) + SF(45, 45, x, x, x, x, x, x, x, x, A4P4_UNORM_PALETTE1) + SF( x, x, x, x, x, x, x, x, x, x, Y8_UNORM) + SF(90, x, x, x, x, x, x, x, x, x, L8_UINT) + SF(90, x, x, x, x, x, x, x, x, x, L8_SINT) + SF(90, x, x, x, x, x, x, x, x, x, I8_UINT) + SF(90, x, x, x, x, x, x, x, x, x, I8_SINT) + SF(45, 45, x, x, x, x, x, x, x, x, DXT1_RGB_SRGB) + SF( Y, Y, x, x, x, x, x, x, x, x, R1_UNORM) + SF( Y, Y, x, Y, Y, x, x, x, 60, x, YCRCB_NORMAL) + SF( Y, Y, x, Y, Y, x, x, x, 60, x, YCRCB_SWAPUVY) + SF(45, 45, x, x, x, x, x, x, x, x, P2_UNORM_PALETTE0) + SF(45, 45, x, x, x, x, x, x, x, x, P2_UNORM_PALETTE1) + SF( Y, Y, x, Y, x, x, x, x, x, x, BC1_UNORM) + SF( Y, Y, x, Y, x, x, x, x, x, x, BC2_UNORM) + SF( Y, Y, x, Y, x, x, x, x, x, x, BC3_UNORM) + SF( Y, Y, x, x, x, x, x, x, x, x, BC4_UNORM) + SF( Y, Y, x, x, x, x, x, x, x, x, BC5_UNORM) + SF( Y, Y, x, x, x, x, x, x, x, x, BC1_UNORM_SRGB) + SF( Y, Y, x, x, x, x, x, x, x, x, BC2_UNORM_SRGB) + SF( Y, Y, x, x, x, x, x, x, x, x, BC3_UNORM_SRGB) + SF( Y, x, x, x, x, x, x, x, x, x, MONO8) + SF( Y, Y, x, x, Y, x, x, x, 60, x, YCRCB_SWAPUV) + SF( Y, Y, x, x, Y, x, x, x, 60, x, YCRCB_SWAPY) + SF( Y, Y, x, x, x, x, x, x, x, x, DXT1_RGB) +/* smpl filt shad CK RT AB VB SO color ccs_e */ + SF( Y, Y, x, x, x, x, x, x, x, x, FXT1) + SF(75, 75, x, x, x, x, Y, x, x, x, R8G8B8_UNORM) + SF(75, 75, x, x, x, x, Y, x, x, x, R8G8B8_SNORM) + SF( x, x, x, x, x, x, Y, x, x, x, R8G8B8_SSCALED) + SF( x, x, x, x, x, x, Y, x, x, x, R8G8B8_USCALED) + SF( x, x, x, x, x, x, Y, x, x, x, R64G64B64A64_FLOAT) + SF( x, x, x, x, x, x, Y, x, x, x, R64G64B64_FLOAT) + SF( Y, Y, x, x, x, x, x, x, x, x, BC4_SNORM) + SF( Y, Y, x, x, x, x, x, x, x, x, BC5_SNORM) + SF(50, 50, x, x, x, x, 60, x, x, x, R16G16B16_FLOAT) + SF(75, 75, x, x, x, x, Y, x, x, x, R16G16B16_UNORM) + SF(75, 75, x, x, x, x, Y, x, x, x, R16G16B16_SNORM) + SF( x, x, x, x, x, x, Y, x, x, x, R16G16B16_SSCALED) + SF( x, x, x, x, x, x, Y, x, x, x, R16G16B16_USCALED) + SF(70, 70, x, x, x, x, x, x, x, x, BC6H_SF16) + SF(70, 70, x, x, x, x, x, x, x, x, BC7_UNORM) + SF(70, 70, x, x, x, x, x, x, x, x, BC7_UNORM_SRGB) + SF(70, 70, x, x, x, x, x, x, x, x, BC6H_UF16) + SF( x, x, x, x, x, x, x, x, x, x, PLANAR_420_8) + SF(75, 75, x, x, x, x, x, x, x, x, R8G8B8_UNORM_SRGB) + SF(80, 80, x, x, x, x, x, x, x, x, ETC1_RGB8) + SF(80, 80, x, x, x, x, x, x, x, x, ETC2_RGB8) + SF(80, 80, x, x, x, x, x, x, x, x, EAC_R11) + SF(80, 80, x, x, x, x, x, x, x, x, EAC_RG11) + SF(80, 80, x, x, x, x, x, x, x, x, EAC_SIGNED_R11) + SF(80, 80, x, x, x, x, x, x, x, x, EAC_SIGNED_RG11) + SF(80, 80, x, x, x, x, x, x, x, x, ETC2_SRGB8) + SF(90, x, x, x, x, x, 75, x, x, x, R16G16B16_UINT) + SF(90, x, x, x, x, x, 75, x, x, x, R16G16B16_SINT) + SF( x, x, x, x, x, x, 75, x, x, x, R32_SFIXED) + SF( x, x, x, x, x, x, 75, x, x, x, R10G10B10A2_SNORM) + SF( x, x, x, x, x, x, 75, x, x, x, R10G10B10A2_USCALED) + SF( x, x, x, x, x, x, 75, x, x, x, R10G10B10A2_SSCALED) + SF( x, x, x, x, x, x, 75, x, x, x, R10G10B10A2_SINT) + SF( x, x, x, x, x, x, 75, x, x, x, B10G10R10A2_SNORM) + SF( x, x, x, x, x, x, 75, x, x, x, B10G10R10A2_USCALED) + SF( x, x, x, x, x, x, 75, x, x, x, B10G10R10A2_SSCALED) + SF( x, x, x, x, x, x, 75, x, x, x, B10G10R10A2_UINT) + SF( x, x, x, x, x, x, 75, x, x, x, B10G10R10A2_SINT) + SF( x, x, x, x, x, x, 80, x, x, x, R64G64B64A64_PASSTHRU) + SF( x, x, x, x, x, x, 80, x, x, x, R64G64B64_PASSTHRU) + SF(80, 80, x, x, x, x, x, x, x, x, ETC2_RGB8_PTA) + SF(80, 80, x, x, x, x, x, x, x, x, ETC2_SRGB8_PTA) + SF(80, 80, x, x, x, x, x, x, x, x, ETC2_EAC_RGBA8) + SF(80, 80, x, x, x, x, x, x, x, x, ETC2_EAC_SRGB8_A8) + SF(90, x, x, x, x, x, 75, x, x, x, R8G8B8_UINT) + SF(90, x, x, x, x, x, 75, x, x, x, R8G8B8_SINT) + SF(80, 80, x, x, x, x, x, x, x, x, ASTC_LDR_2D_4X4_FLT16) + SF(80, 80, x, x, x, x, x, x, x, x, ASTC_LDR_2D_5X4_FLT16) + SF(80, 80, x, x, x, x, x, x, x, x, ASTC_LDR_2D_5X5_FLT16) + SF(80, 80, x, x, x, x, x, x, x, x, ASTC_LDR_2D_6X5_FLT16) + SF(80, 80, x, x, x, x, x, x, x, x, ASTC_LDR_2D_6X6_FLT16) + SF(80, 80, x, x, x, x, x, x, x, x, ASTC_LDR_2D_8X5_FLT16) + SF(80, 80, x, x, x, x, x, x, x, x, ASTC_LDR_2D_8X6_FLT16) + SF(80, 80, x, x, x, x, x, x, x, x, ASTC_LDR_2D_8X8_FLT16) + SF(80, 80, x, x, x, x, x, x, x, x, ASTC_LDR_2D_10X5_FLT16) + SF(80, 80, x, x, x, x, x, x, x, x, ASTC_LDR_2D_10X6_FLT16) + SF(80, 80, x, x, x, x, x, x, x, x, ASTC_LDR_2D_10X8_FLT16) + SF(80, 80, x, x, x, x, x, x, x, x, ASTC_LDR_2D_10X10_FLT16) + SF(80, 80, x, x, x, x, x, x, x, x, ASTC_LDR_2D_12X10_FLT16) + SF(80, 80, x, x, x, x, x, x, x, x, ASTC_LDR_2D_12X12_FLT16) + SF(80, 80, x, x, x, x, x, x, x, x, ASTC_LDR_2D_4X4_U8SRGB) + SF(80, 80, x, x, x, x, x, x, x, x, ASTC_LDR_2D_5X4_U8SRGB) + SF(80, 80, x, x, x, x, x, x, x, x, ASTC_LDR_2D_5X5_U8SRGB) + SF(80, 80, x, x, x, x, x, x, x, x, ASTC_LDR_2D_6X5_U8SRGB) + SF(80, 80, x, x, x, x, x, x, x, x, ASTC_LDR_2D_6X6_U8SRGB) + SF(80, 80, x, x, x, x, x, x, x, x, ASTC_LDR_2D_8X5_U8SRGB) + SF(80, 80, x, x, x, x, x, x, x, x, ASTC_LDR_2D_8X6_U8SRGB) + SF(80, 80, x, x, x, x, x, x, x, x, ASTC_LDR_2D_8X8_U8SRGB) + SF(80, 80, x, x, x, x, x, x, x, x, ASTC_LDR_2D_10X5_U8SRGB) + SF(80, 80, x, x, x, x, x, x, x, x, ASTC_LDR_2D_10X6_U8SRGB) + SF(80, 80, x, x, x, x, x, x, x, x, ASTC_LDR_2D_10X8_U8SRGB) + SF(80, 80, x, x, x, x, x, x, x, x, ASTC_LDR_2D_10X10_U8SRGB) + SF(80, 80, x, x, x, x, x, x, x, x, ASTC_LDR_2D_12X10_U8SRGB) + SF(80, 80, x, x, x, x, x, x, x, x, ASTC_LDR_2D_12X12_U8SRGB) +}; +#undef x +#undef Y + +static unsigned +format_gen(const struct gen_device_info *devinfo) +{ + return devinfo->gen * 10 + (devinfo->is_g4x || devinfo->is_haswell) * 5; +} + +bool +isl_format_supports_rendering(const struct gen_device_info *devinfo, + enum isl_format format) +{ + if (!format_info[format].exists) + return false; + + return format_gen(devinfo) >= format_info[format].render_target; +} + +bool +isl_format_supports_alpha_blending(const struct gen_device_info *devinfo, + enum isl_format format) +{ + if (!format_info[format].exists) + return false; + + return format_gen(devinfo) >= format_info[format].alpha_blend; +} + +bool +isl_format_supports_sampling(const struct gen_device_info *devinfo, + enum isl_format format) +{ + if (!format_info[format].exists) + return false; + + if (devinfo->is_baytrail) { + const struct isl_format_layout *fmtl = isl_format_get_layout(format); + /* Support for ETC1 and ETC2 exists on Bay Trail even though big-core + * GPUs didn't get it until Broadwell. + */ + if (fmtl->txc == ISL_TXC_ETC1 || fmtl->txc == ISL_TXC_ETC2) + return true; + } + + return format_gen(devinfo) >= format_info[format].sampling; +} + +bool +isl_format_supports_filtering(const struct gen_device_info *devinfo, + enum isl_format format) +{ + if (!format_info[format].exists) + return false; + + if (devinfo->is_baytrail) { + const struct isl_format_layout *fmtl = isl_format_get_layout(format); + /* Support for ETC1 and ETC2 exists on Bay Trail even though big-core + * GPUs didn't get it until Broadwell. + */ + if (fmtl->txc == ISL_TXC_ETC1 || fmtl->txc == ISL_TXC_ETC2) + return true; + } + + return format_gen(devinfo) >= format_info[format].filtering; +} + +bool +isl_format_supports_vertex_fetch(const struct gen_device_info *devinfo, + enum isl_format format) +{ + if (!format_info[format].exists) + return false; + + /* For vertex fetch, Bay Trail supports the same set of formats as Haswell + * but is a superset of Ivy Bridge. + */ + if (devinfo->is_baytrail) + return 75 >= format_info[format].input_vb; + + return format_gen(devinfo) >= format_info[format].input_vb; +} + +bool +isl_format_supports_lossless_compression(const struct gen_device_info *devinfo, + enum isl_format format) +{ + if (!format_info[format].exists) + return false; + + return format_gen(devinfo) >= format_info[format].lossless_compression; +} + +bool +isl_format_supports_multisampling(const struct gen_device_info *devinfo, + enum isl_format format) +{ + /* From the Sandybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Surface + * Format: + * + * If Number of Multisamples is set to a value other than + * MULTISAMPLECOUNT_1, this field cannot be set to the following + * formats: + * + * - any format with greater than 64 bits per element + * - any compressed texture format (BC*) + * - any YCRCB* format + * + * The restriction on the format's size is removed on Broadwell. Also, + * there is an exception for HiZ which we treat as a compressed format and + * is allowed to be multisampled on Broadwell and earlier. + */ + if (format == ISL_FORMAT_HIZ) { + /* On SKL+, HiZ is always single-sampled even when the primary surface + * is multisampled. See also isl_surf_get_hiz_surf(). + */ + return devinfo->gen <= 8; + } else if (devinfo->gen < 8 && isl_format_get_layout(format)->bpb > 64) { + return false; + } else if (isl_format_is_compressed(format)) { + return false; + } else if (isl_format_is_yuv(format)) { + return false; + } else { + return true; + } +} + +static inline bool +isl_format_has_channel_type(enum isl_format fmt, enum isl_base_type type) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(fmt); + + return fmtl->channels.r.type == type || + fmtl->channels.g.type == type || + fmtl->channels.b.type == type || + fmtl->channels.a.type == type || + fmtl->channels.l.type == type || + fmtl->channels.i.type == type || + fmtl->channels.p.type == type; +} + +bool +isl_format_has_unorm_channel(enum isl_format fmt) +{ + return isl_format_has_channel_type(fmt, ISL_UNORM); +} + +bool +isl_format_has_snorm_channel(enum isl_format fmt) +{ + return isl_format_has_channel_type(fmt, ISL_SNORM); +} + +bool +isl_format_has_ufloat_channel(enum isl_format fmt) +{ + return isl_format_has_channel_type(fmt, ISL_UFLOAT); +} + +bool +isl_format_has_sfloat_channel(enum isl_format fmt) +{ + return isl_format_has_channel_type(fmt, ISL_SFLOAT); +} + +bool +isl_format_has_uint_channel(enum isl_format fmt) +{ + return isl_format_has_channel_type(fmt, ISL_UINT); +} + +bool +isl_format_has_sint_channel(enum isl_format fmt) +{ + return isl_format_has_channel_type(fmt, ISL_SINT); +} + +unsigned +isl_format_get_num_channels(enum isl_format fmt) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(fmt); + + assert(fmtl->channels.p.bits == 0); + + return (fmtl->channels.r.bits > 0) + + (fmtl->channels.g.bits > 0) + + (fmtl->channels.b.bits > 0) + + (fmtl->channels.a.bits > 0) + + (fmtl->channels.l.bits > 0) + + (fmtl->channels.i.bits > 0); +} + +uint32_t +isl_format_get_depth_format(enum isl_format fmt, bool has_stencil) +{ + switch (fmt) { + default: + unreachable("bad isl depth format"); + case ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS: + assert(has_stencil); + return 0; /* D32_FLOAT_S8X24_UINT */ + case ISL_FORMAT_R32_FLOAT: + assert(!has_stencil); + return 1; /* D32_FLOAT */ + case ISL_FORMAT_R24_UNORM_X8_TYPELESS: + if (has_stencil) { + return 2; /* D24_UNORM_S8_UINT */ + } else { + return 3; /* D24_UNORM_X8_UINT */ + } + case ISL_FORMAT_R16_UNORM: + assert(!has_stencil); + return 5; /* D16_UNORM */ + } +} + +enum isl_format +isl_format_rgb_to_rgba(enum isl_format rgb) +{ + assert(isl_format_is_rgb(rgb)); + + switch (rgb) { + case ISL_FORMAT_R32G32B32_FLOAT: return ISL_FORMAT_R32G32B32A32_FLOAT; + case ISL_FORMAT_R32G32B32_SINT: return ISL_FORMAT_R32G32B32A32_SINT; + case ISL_FORMAT_R32G32B32_UINT: return ISL_FORMAT_R32G32B32A32_UINT; + case ISL_FORMAT_R32G32B32_UNORM: return ISL_FORMAT_R32G32B32A32_UNORM; + case ISL_FORMAT_R32G32B32_SNORM: return ISL_FORMAT_R32G32B32A32_SNORM; + case ISL_FORMAT_R32G32B32_SSCALED: return ISL_FORMAT_R32G32B32A32_SSCALED; + case ISL_FORMAT_R32G32B32_USCALED: return ISL_FORMAT_R32G32B32A32_USCALED; + case ISL_FORMAT_R32G32B32_SFIXED: return ISL_FORMAT_R32G32B32A32_SFIXED; + case ISL_FORMAT_R8G8B8_UNORM: return ISL_FORMAT_R8G8B8A8_UNORM; + case ISL_FORMAT_R8G8B8_SNORM: return ISL_FORMAT_R8G8B8A8_SNORM; + case ISL_FORMAT_R8G8B8_SSCALED: return ISL_FORMAT_R8G8B8A8_SSCALED; + case ISL_FORMAT_R8G8B8_USCALED: return ISL_FORMAT_R8G8B8A8_USCALED; + case ISL_FORMAT_R16G16B16_FLOAT: return ISL_FORMAT_R16G16B16A16_FLOAT; + case ISL_FORMAT_R16G16B16_UNORM: return ISL_FORMAT_R16G16B16A16_UNORM; + case ISL_FORMAT_R16G16B16_SNORM: return ISL_FORMAT_R16G16B16A16_SNORM; + case ISL_FORMAT_R16G16B16_SSCALED: return ISL_FORMAT_R16G16B16A16_SSCALED; + case ISL_FORMAT_R16G16B16_USCALED: return ISL_FORMAT_R16G16B16A16_USCALED; + case ISL_FORMAT_R8G8B8_UNORM_SRGB: return ISL_FORMAT_R8G8B8A8_UNORM_SRGB; + case ISL_FORMAT_R16G16B16_UINT: return ISL_FORMAT_R16G16B16A16_UINT; + case ISL_FORMAT_R16G16B16_SINT: return ISL_FORMAT_R16G16B16A16_SINT; + case ISL_FORMAT_R8G8B8_UINT: return ISL_FORMAT_R8G8B8A8_UINT; + case ISL_FORMAT_R8G8B8_SINT: return ISL_FORMAT_R8G8B8A8_SINT; + default: + return ISL_FORMAT_UNSUPPORTED; + } +} + +enum isl_format +isl_format_rgb_to_rgbx(enum isl_format rgb) +{ + assert(isl_format_is_rgb(rgb)); + + switch (rgb) { + case ISL_FORMAT_R32G32B32_FLOAT: + return ISL_FORMAT_R32G32B32X32_FLOAT; + case ISL_FORMAT_R16G16B16_UNORM: + return ISL_FORMAT_R16G16B16X16_UNORM; + case ISL_FORMAT_R16G16B16_FLOAT: + return ISL_FORMAT_R16G16B16X16_FLOAT; + case ISL_FORMAT_R8G8B8_UNORM: + return ISL_FORMAT_R8G8B8X8_UNORM; + case ISL_FORMAT_R8G8B8_UNORM_SRGB: + return ISL_FORMAT_R8G8B8X8_UNORM_SRGB; + default: + return ISL_FORMAT_UNSUPPORTED; + } +} diff --git a/lib/mesa/src/intel/isl/isl_format_layout.c b/lib/mesa/src/intel/isl/isl_format_layout.c new file mode 100644 index 000000000..c05152163 --- /dev/null +++ b/lib/mesa/src/intel/isl/isl_format_layout.c @@ -0,0 +1,5310 @@ +/* This file is autogenerated by gen_format_layout.py. DO NOT EDIT! */ + +/* + * Copyright 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#include "isl/isl.h" + +const struct isl_format_layout +isl_format_layouts[] = { + [ISL_FORMAT_R32G32B32A32_FLOAT] = { + .format = ISL_FORMAT_R32G32B32A32_FLOAT, + .name = "ISL_FORMAT_R32G32B32A32_FLOAT", + .bpb = 128, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 32 }, + .g = { ISL_SFLOAT, 32 }, + .b = { ISL_SFLOAT, 32 }, + .a = { ISL_SFLOAT, 32 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32B32A32_SINT] = { + .format = ISL_FORMAT_R32G32B32A32_SINT, + .name = "ISL_FORMAT_R32G32B32A32_SINT", + .bpb = 128, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SINT, 32 }, + .g = { ISL_SINT, 32 }, + .b = { ISL_SINT, 32 }, + .a = { ISL_SINT, 32 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32B32A32_UINT] = { + .format = ISL_FORMAT_R32G32B32A32_UINT, + .name = "ISL_FORMAT_R32G32B32A32_UINT", + .bpb = 128, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UINT, 32 }, + .g = { ISL_UINT, 32 }, + .b = { ISL_UINT, 32 }, + .a = { ISL_UINT, 32 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32B32A32_UNORM] = { + .format = ISL_FORMAT_R32G32B32A32_UNORM, + .name = "ISL_FORMAT_R32G32B32A32_UNORM", + .bpb = 128, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 32 }, + .g = { ISL_UNORM, 32 }, + .b = { ISL_UNORM, 32 }, + .a = { ISL_UNORM, 32 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32B32A32_SNORM] = { + .format = ISL_FORMAT_R32G32B32A32_SNORM, + .name = "ISL_FORMAT_R32G32B32A32_SNORM", + .bpb = 128, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SNORM, 32 }, + .g = { ISL_SNORM, 32 }, + .b = { ISL_SNORM, 32 }, + .a = { ISL_SNORM, 32 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R64G64_FLOAT] = { + .format = ISL_FORMAT_R64G64_FLOAT, + .name = "ISL_FORMAT_R64G64_FLOAT", + .bpb = 128, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 64 }, + .g = { ISL_SFLOAT, 64 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32B32X32_FLOAT] = { + .format = ISL_FORMAT_R32G32B32X32_FLOAT, + .name = "ISL_FORMAT_R32G32B32X32_FLOAT", + .bpb = 128, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 32 }, + .g = { ISL_SFLOAT, 32 }, + .b = { ISL_SFLOAT, 32 }, + .a = { ISL_VOID, 32 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32B32A32_SSCALED] = { + .format = ISL_FORMAT_R32G32B32A32_SSCALED, + .name = "ISL_FORMAT_R32G32B32A32_SSCALED", + .bpb = 128, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SSCALED, 32 }, + .g = { ISL_SSCALED, 32 }, + .b = { ISL_SSCALED, 32 }, + .a = { ISL_SSCALED, 32 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32B32A32_USCALED] = { + .format = ISL_FORMAT_R32G32B32A32_USCALED, + .name = "ISL_FORMAT_R32G32B32A32_USCALED", + .bpb = 128, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_USCALED, 32 }, + .g = { ISL_USCALED, 32 }, + .b = { ISL_USCALED, 32 }, + .a = { ISL_USCALED, 32 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32B32A32_SFIXED] = { + .format = ISL_FORMAT_R32G32B32A32_SFIXED, + .name = "ISL_FORMAT_R32G32B32A32_SFIXED", + .bpb = 128, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SFIXED, 32 }, + .g = { ISL_SFIXED, 32 }, + .b = { ISL_SFIXED, 32 }, + .a = { ISL_SFIXED, 32 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R64G64_PASSTHRU] = { + .format = ISL_FORMAT_R64G64_PASSTHRU, + .name = "ISL_FORMAT_R64G64_PASSTHRU", + .bpb = 128, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_RAW, 64 }, + .g = { ISL_RAW, 64 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32B32_FLOAT] = { + .format = ISL_FORMAT_R32G32B32_FLOAT, + .name = "ISL_FORMAT_R32G32B32_FLOAT", + .bpb = 96, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 32 }, + .g = { ISL_SFLOAT, 32 }, + .b = { ISL_SFLOAT, 32 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32B32_SINT] = { + .format = ISL_FORMAT_R32G32B32_SINT, + .name = "ISL_FORMAT_R32G32B32_SINT", + .bpb = 96, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SINT, 32 }, + .g = { ISL_SINT, 32 }, + .b = { ISL_SINT, 32 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32B32_UINT] = { + .format = ISL_FORMAT_R32G32B32_UINT, + .name = "ISL_FORMAT_R32G32B32_UINT", + .bpb = 96, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UINT, 32 }, + .g = { ISL_UINT, 32 }, + .b = { ISL_UINT, 32 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32B32_UNORM] = { + .format = ISL_FORMAT_R32G32B32_UNORM, + .name = "ISL_FORMAT_R32G32B32_UNORM", + .bpb = 96, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 32 }, + .g = { ISL_UNORM, 32 }, + .b = { ISL_UNORM, 32 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32B32_SNORM] = { + .format = ISL_FORMAT_R32G32B32_SNORM, + .name = "ISL_FORMAT_R32G32B32_SNORM", + .bpb = 96, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SNORM, 32 }, + .g = { ISL_SNORM, 32 }, + .b = { ISL_SNORM, 32 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32B32_SSCALED] = { + .format = ISL_FORMAT_R32G32B32_SSCALED, + .name = "ISL_FORMAT_R32G32B32_SSCALED", + .bpb = 96, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SSCALED, 32 }, + .g = { ISL_SSCALED, 32 }, + .b = { ISL_SSCALED, 32 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32B32_USCALED] = { + .format = ISL_FORMAT_R32G32B32_USCALED, + .name = "ISL_FORMAT_R32G32B32_USCALED", + .bpb = 96, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_USCALED, 32 }, + .g = { ISL_USCALED, 32 }, + .b = { ISL_USCALED, 32 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32B32_SFIXED] = { + .format = ISL_FORMAT_R32G32B32_SFIXED, + .name = "ISL_FORMAT_R32G32B32_SFIXED", + .bpb = 96, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SFIXED, 32 }, + .g = { ISL_SFIXED, 32 }, + .b = { ISL_SFIXED, 32 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16G16B16A16_UNORM] = { + .format = ISL_FORMAT_R16G16B16A16_UNORM, + .name = "ISL_FORMAT_R16G16B16A16_UNORM", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 16 }, + .g = { ISL_UNORM, 16 }, + .b = { ISL_UNORM, 16 }, + .a = { ISL_UNORM, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16G16B16A16_SNORM] = { + .format = ISL_FORMAT_R16G16B16A16_SNORM, + .name = "ISL_FORMAT_R16G16B16A16_SNORM", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SNORM, 16 }, + .g = { ISL_SNORM, 16 }, + .b = { ISL_SNORM, 16 }, + .a = { ISL_SNORM, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16G16B16A16_SINT] = { + .format = ISL_FORMAT_R16G16B16A16_SINT, + .name = "ISL_FORMAT_R16G16B16A16_SINT", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SINT, 16 }, + .g = { ISL_SINT, 16 }, + .b = { ISL_SINT, 16 }, + .a = { ISL_SINT, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16G16B16A16_UINT] = { + .format = ISL_FORMAT_R16G16B16A16_UINT, + .name = "ISL_FORMAT_R16G16B16A16_UINT", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UINT, 16 }, + .g = { ISL_UINT, 16 }, + .b = { ISL_UINT, 16 }, + .a = { ISL_UINT, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16G16B16A16_FLOAT] = { + .format = ISL_FORMAT_R16G16B16A16_FLOAT, + .name = "ISL_FORMAT_R16G16B16A16_FLOAT", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 16 }, + .g = { ISL_SFLOAT, 16 }, + .b = { ISL_SFLOAT, 16 }, + .a = { ISL_SFLOAT, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32_FLOAT] = { + .format = ISL_FORMAT_R32G32_FLOAT, + .name = "ISL_FORMAT_R32G32_FLOAT", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 32 }, + .g = { ISL_SFLOAT, 32 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32_SINT] = { + .format = ISL_FORMAT_R32G32_SINT, + .name = "ISL_FORMAT_R32G32_SINT", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SINT, 32 }, + .g = { ISL_SINT, 32 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32_UINT] = { + .format = ISL_FORMAT_R32G32_UINT, + .name = "ISL_FORMAT_R32G32_UINT", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UINT, 32 }, + .g = { ISL_UINT, 32 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS] = { + .format = ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS, + .name = "ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 32 }, + .g = { ISL_VOID, 8 }, + .b = { ISL_VOID, 24 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_X32_TYPELESS_G8X24_UINT] = { + .format = ISL_FORMAT_X32_TYPELESS_G8X24_UINT, + .name = "ISL_FORMAT_X32_TYPELESS_G8X24_UINT", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_VOID, 32 }, + .g = { ISL_UINT, 8 }, + .b = { ISL_VOID, 24 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_L32A32_FLOAT] = { + .format = ISL_FORMAT_L32A32_FLOAT, + .name = "ISL_FORMAT_L32A32_FLOAT", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_SFLOAT, 32 }, + .l = { ISL_SFLOAT, 32 }, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32_UNORM] = { + .format = ISL_FORMAT_R32G32_UNORM, + .name = "ISL_FORMAT_R32G32_UNORM", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 32 }, + .g = { ISL_UNORM, 32 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32_SNORM] = { + .format = ISL_FORMAT_R32G32_SNORM, + .name = "ISL_FORMAT_R32G32_SNORM", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SNORM, 32 }, + .g = { ISL_SNORM, 32 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R64_FLOAT] = { + .format = ISL_FORMAT_R64_FLOAT, + .name = "ISL_FORMAT_R64_FLOAT", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 64 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16G16B16X16_UNORM] = { + .format = ISL_FORMAT_R16G16B16X16_UNORM, + .name = "ISL_FORMAT_R16G16B16X16_UNORM", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 16 }, + .g = { ISL_UNORM, 16 }, + .b = { ISL_UNORM, 16 }, + .a = { ISL_VOID, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16G16B16X16_FLOAT] = { + .format = ISL_FORMAT_R16G16B16X16_FLOAT, + .name = "ISL_FORMAT_R16G16B16X16_FLOAT", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 16 }, + .g = { ISL_SFLOAT, 16 }, + .b = { ISL_SFLOAT, 16 }, + .a = { ISL_VOID, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_A32X32_FLOAT] = { + .format = ISL_FORMAT_A32X32_FLOAT, + .name = "ISL_FORMAT_A32X32_FLOAT", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_SFLOAT, 32 }, + .l = { ISL_VOID, 32 }, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_L32X32_FLOAT] = { + .format = ISL_FORMAT_L32X32_FLOAT, + .name = "ISL_FORMAT_L32X32_FLOAT", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_VOID, 32 }, + .l = { ISL_SFLOAT, 32 }, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_I32X32_FLOAT] = { + .format = ISL_FORMAT_I32X32_FLOAT, + .name = "ISL_FORMAT_I32X32_FLOAT", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_VOID, 32 }, + .l = {}, + .i = { ISL_SFLOAT, 32 }, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16G16B16A16_SSCALED] = { + .format = ISL_FORMAT_R16G16B16A16_SSCALED, + .name = "ISL_FORMAT_R16G16B16A16_SSCALED", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SSCALED, 16 }, + .g = { ISL_SSCALED, 16 }, + .b = { ISL_SSCALED, 16 }, + .a = { ISL_SSCALED, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16G16B16A16_USCALED] = { + .format = ISL_FORMAT_R16G16B16A16_USCALED, + .name = "ISL_FORMAT_R16G16B16A16_USCALED", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_USCALED, 16 }, + .g = { ISL_USCALED, 16 }, + .b = { ISL_USCALED, 16 }, + .a = { ISL_USCALED, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32_SSCALED] = { + .format = ISL_FORMAT_R32G32_SSCALED, + .name = "ISL_FORMAT_R32G32_SSCALED", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SSCALED, 32 }, + .g = { ISL_SSCALED, 32 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32_USCALED] = { + .format = ISL_FORMAT_R32G32_USCALED, + .name = "ISL_FORMAT_R32G32_USCALED", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_USCALED, 32 }, + .g = { ISL_USCALED, 32 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32_FLOAT_LD] = { + .format = ISL_FORMAT_R32G32_FLOAT_LD, + .name = "ISL_FORMAT_R32G32_FLOAT_LD", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 32 }, + .g = { ISL_SFLOAT, 32 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32_SFIXED] = { + .format = ISL_FORMAT_R32G32_SFIXED, + .name = "ISL_FORMAT_R32G32_SFIXED", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SFIXED, 32 }, + .g = { ISL_SFIXED, 32 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R64_PASSTHRU] = { + .format = ISL_FORMAT_R64_PASSTHRU, + .name = "ISL_FORMAT_R64_PASSTHRU", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_RAW, 64 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_B8G8R8A8_UNORM] = { + .format = ISL_FORMAT_B8G8R8A8_UNORM, + .name = "ISL_FORMAT_B8G8R8A8_UNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 8 }, + .g = { ISL_UNORM, 8 }, + .b = { ISL_UNORM, 8 }, + .a = { ISL_UNORM, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_B8G8R8A8_UNORM_SRGB] = { + .format = ISL_FORMAT_B8G8R8A8_UNORM_SRGB, + .name = "ISL_FORMAT_B8G8R8A8_UNORM_SRGB", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 8 }, + .g = { ISL_UNORM, 8 }, + .b = { ISL_UNORM, 8 }, + .a = { ISL_UNORM, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R10G10B10A2_UNORM] = { + .format = ISL_FORMAT_R10G10B10A2_UNORM, + .name = "ISL_FORMAT_R10G10B10A2_UNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 10 }, + .g = { ISL_UNORM, 10 }, + .b = { ISL_UNORM, 10 }, + .a = { ISL_UNORM, 2 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R10G10B10A2_UNORM_SRGB] = { + .format = ISL_FORMAT_R10G10B10A2_UNORM_SRGB, + .name = "ISL_FORMAT_R10G10B10A2_UNORM_SRGB", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 10 }, + .g = { ISL_UNORM, 10 }, + .b = { ISL_UNORM, 10 }, + .a = { ISL_UNORM, 2 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R10G10B10A2_UINT] = { + .format = ISL_FORMAT_R10G10B10A2_UINT, + .name = "ISL_FORMAT_R10G10B10A2_UINT", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UINT, 10 }, + .g = { ISL_UINT, 10 }, + .b = { ISL_UINT, 10 }, + .a = { ISL_UINT, 2 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R10G10B10_SNORM_A2_UNORM] = { + .format = ISL_FORMAT_R10G10B10_SNORM_A2_UNORM, + .name = "ISL_FORMAT_R10G10B10_SNORM_A2_UNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SNORM, 10 }, + .g = { ISL_SNORM, 10 }, + .b = { ISL_SNORM, 10 }, + .a = { ISL_UNORM, 2 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8G8B8A8_UNORM] = { + .format = ISL_FORMAT_R8G8B8A8_UNORM, + .name = "ISL_FORMAT_R8G8B8A8_UNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 8 }, + .g = { ISL_UNORM, 8 }, + .b = { ISL_UNORM, 8 }, + .a = { ISL_UNORM, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8G8B8A8_UNORM_SRGB] = { + .format = ISL_FORMAT_R8G8B8A8_UNORM_SRGB, + .name = "ISL_FORMAT_R8G8B8A8_UNORM_SRGB", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 8 }, + .g = { ISL_UNORM, 8 }, + .b = { ISL_UNORM, 8 }, + .a = { ISL_UNORM, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8G8B8A8_SNORM] = { + .format = ISL_FORMAT_R8G8B8A8_SNORM, + .name = "ISL_FORMAT_R8G8B8A8_SNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SNORM, 8 }, + .g = { ISL_SNORM, 8 }, + .b = { ISL_SNORM, 8 }, + .a = { ISL_SNORM, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8G8B8A8_SINT] = { + .format = ISL_FORMAT_R8G8B8A8_SINT, + .name = "ISL_FORMAT_R8G8B8A8_SINT", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SINT, 8 }, + .g = { ISL_SINT, 8 }, + .b = { ISL_SINT, 8 }, + .a = { ISL_SINT, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8G8B8A8_UINT] = { + .format = ISL_FORMAT_R8G8B8A8_UINT, + .name = "ISL_FORMAT_R8G8B8A8_UINT", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UINT, 8 }, + .g = { ISL_UINT, 8 }, + .b = { ISL_UINT, 8 }, + .a = { ISL_UINT, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16G16_UNORM] = { + .format = ISL_FORMAT_R16G16_UNORM, + .name = "ISL_FORMAT_R16G16_UNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 16 }, + .g = { ISL_UNORM, 16 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16G16_SNORM] = { + .format = ISL_FORMAT_R16G16_SNORM, + .name = "ISL_FORMAT_R16G16_SNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SNORM, 16 }, + .g = { ISL_SNORM, 16 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16G16_SINT] = { + .format = ISL_FORMAT_R16G16_SINT, + .name = "ISL_FORMAT_R16G16_SINT", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SINT, 16 }, + .g = { ISL_SINT, 16 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16G16_UINT] = { + .format = ISL_FORMAT_R16G16_UINT, + .name = "ISL_FORMAT_R16G16_UINT", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UINT, 16 }, + .g = { ISL_UINT, 16 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16G16_FLOAT] = { + .format = ISL_FORMAT_R16G16_FLOAT, + .name = "ISL_FORMAT_R16G16_FLOAT", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 16 }, + .g = { ISL_SFLOAT, 16 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_B10G10R10A2_UNORM] = { + .format = ISL_FORMAT_B10G10R10A2_UNORM, + .name = "ISL_FORMAT_B10G10R10A2_UNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 10 }, + .g = { ISL_UNORM, 10 }, + .b = { ISL_UNORM, 10 }, + .a = { ISL_UNORM, 2 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_B10G10R10A2_UNORM_SRGB] = { + .format = ISL_FORMAT_B10G10R10A2_UNORM_SRGB, + .name = "ISL_FORMAT_B10G10R10A2_UNORM_SRGB", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 10 }, + .g = { ISL_UNORM, 10 }, + .b = { ISL_UNORM, 10 }, + .a = { ISL_UNORM, 2 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R11G11B10_FLOAT] = { + .format = ISL_FORMAT_R11G11B10_FLOAT, + .name = "ISL_FORMAT_R11G11B10_FLOAT", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UFLOAT, 11 }, + .g = { ISL_UFLOAT, 11 }, + .b = { ISL_UFLOAT, 10 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32_SINT] = { + .format = ISL_FORMAT_R32_SINT, + .name = "ISL_FORMAT_R32_SINT", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SINT, 32 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32_UINT] = { + .format = ISL_FORMAT_R32_UINT, + .name = "ISL_FORMAT_R32_UINT", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UINT, 32 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32_FLOAT] = { + .format = ISL_FORMAT_R32_FLOAT, + .name = "ISL_FORMAT_R32_FLOAT", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 32 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R24_UNORM_X8_TYPELESS] = { + .format = ISL_FORMAT_R24_UNORM_X8_TYPELESS, + .name = "ISL_FORMAT_R24_UNORM_X8_TYPELESS", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 24 }, + .g = { ISL_VOID, 8 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_X24_TYPELESS_G8_UINT] = { + .format = ISL_FORMAT_X24_TYPELESS_G8_UINT, + .name = "ISL_FORMAT_X24_TYPELESS_G8_UINT", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_VOID, 24 }, + .g = { ISL_UINT, 8 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_L32_UNORM] = { + .format = ISL_FORMAT_L32_UNORM, + .name = "ISL_FORMAT_L32_UNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = { ISL_UNORM, 32 }, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_A32_UNORM] = { + .format = ISL_FORMAT_A32_UNORM, + .name = "ISL_FORMAT_A32_UNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_UNORM, 32 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_L16A16_UNORM] = { + .format = ISL_FORMAT_L16A16_UNORM, + .name = "ISL_FORMAT_L16A16_UNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_UNORM, 16 }, + .l = { ISL_UNORM, 16 }, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_I24X8_UNORM] = { + .format = ISL_FORMAT_I24X8_UNORM, + .name = "ISL_FORMAT_I24X8_UNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_VOID, 8 }, + .l = {}, + .i = { ISL_UNORM, 24 }, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_L24X8_UNORM] = { + .format = ISL_FORMAT_L24X8_UNORM, + .name = "ISL_FORMAT_L24X8_UNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_VOID, 8 }, + .l = { ISL_UNORM, 24 }, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_A24X8_UNORM] = { + .format = ISL_FORMAT_A24X8_UNORM, + .name = "ISL_FORMAT_A24X8_UNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_UNORM, 24 }, + .l = { ISL_VOID, 8 }, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_I32_FLOAT] = { + .format = ISL_FORMAT_I32_FLOAT, + .name = "ISL_FORMAT_I32_FLOAT", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = { ISL_SFLOAT, 32 }, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_L32_FLOAT] = { + .format = ISL_FORMAT_L32_FLOAT, + .name = "ISL_FORMAT_L32_FLOAT", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = { ISL_SFLOAT, 32 }, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_A32_FLOAT] = { + .format = ISL_FORMAT_A32_FLOAT, + .name = "ISL_FORMAT_A32_FLOAT", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_SFLOAT, 32 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_X8B8_UNORM_G8R8_SNORM] = { + .format = ISL_FORMAT_X8B8_UNORM_G8R8_SNORM, + .name = "ISL_FORMAT_X8B8_UNORM_G8R8_SNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SNORM, 8 }, + .g = { ISL_SNORM, 8 }, + .b = { ISL_UNORM, 8 }, + .a = { ISL_VOID, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_A8X8_UNORM_G8R8_SNORM] = { + .format = ISL_FORMAT_A8X8_UNORM_G8R8_SNORM, + .name = "ISL_FORMAT_A8X8_UNORM_G8R8_SNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SNORM, 8 }, + .g = { ISL_SNORM, 8 }, + .b = { ISL_VOID, 8 }, + .a = { ISL_UNORM, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_B8X8_UNORM_G8R8_SNORM] = { + .format = ISL_FORMAT_B8X8_UNORM_G8R8_SNORM, + .name = "ISL_FORMAT_B8X8_UNORM_G8R8_SNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SNORM, 8 }, + .g = { ISL_SNORM, 8 }, + .b = { ISL_UNORM, 8 }, + .a = { ISL_VOID, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_B8G8R8X8_UNORM] = { + .format = ISL_FORMAT_B8G8R8X8_UNORM, + .name = "ISL_FORMAT_B8G8R8X8_UNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 8 }, + .g = { ISL_UNORM, 8 }, + .b = { ISL_UNORM, 8 }, + .a = { ISL_VOID, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_B8G8R8X8_UNORM_SRGB] = { + .format = ISL_FORMAT_B8G8R8X8_UNORM_SRGB, + .name = "ISL_FORMAT_B8G8R8X8_UNORM_SRGB", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 8 }, + .g = { ISL_UNORM, 8 }, + .b = { ISL_UNORM, 8 }, + .a = { ISL_VOID, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8G8B8X8_UNORM] = { + .format = ISL_FORMAT_R8G8B8X8_UNORM, + .name = "ISL_FORMAT_R8G8B8X8_UNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 8 }, + .g = { ISL_UNORM, 8 }, + .b = { ISL_UNORM, 8 }, + .a = { ISL_VOID, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8G8B8X8_UNORM_SRGB] = { + .format = ISL_FORMAT_R8G8B8X8_UNORM_SRGB, + .name = "ISL_FORMAT_R8G8B8X8_UNORM_SRGB", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 8 }, + .g = { ISL_UNORM, 8 }, + .b = { ISL_UNORM, 8 }, + .a = { ISL_VOID, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R9G9B9E5_SHAREDEXP] = { + .format = ISL_FORMAT_R9G9B9E5_SHAREDEXP, + .name = "ISL_FORMAT_R9G9B9E5_SHAREDEXP", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UFLOAT, 9 }, + .g = { ISL_UFLOAT, 9 }, + .b = { ISL_UFLOAT, 9 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_B10G10R10X2_UNORM] = { + .format = ISL_FORMAT_B10G10R10X2_UNORM, + .name = "ISL_FORMAT_B10G10R10X2_UNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 10 }, + .g = { ISL_UNORM, 10 }, + .b = { ISL_UNORM, 10 }, + .a = { ISL_VOID, 2 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_L16A16_FLOAT] = { + .format = ISL_FORMAT_L16A16_FLOAT, + .name = "ISL_FORMAT_L16A16_FLOAT", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_SFLOAT, 16 }, + .l = { ISL_SFLOAT, 16 }, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32_UNORM] = { + .format = ISL_FORMAT_R32_UNORM, + .name = "ISL_FORMAT_R32_UNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 32 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32_SNORM] = { + .format = ISL_FORMAT_R32_SNORM, + .name = "ISL_FORMAT_R32_SNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SNORM, 32 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R10G10B10X2_USCALED] = { + .format = ISL_FORMAT_R10G10B10X2_USCALED, + .name = "ISL_FORMAT_R10G10B10X2_USCALED", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_USCALED, 10 }, + .g = { ISL_USCALED, 10 }, + .b = { ISL_USCALED, 10 }, + .a = { ISL_VOID, 2 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8G8B8A8_SSCALED] = { + .format = ISL_FORMAT_R8G8B8A8_SSCALED, + .name = "ISL_FORMAT_R8G8B8A8_SSCALED", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SSCALED, 8 }, + .g = { ISL_SSCALED, 8 }, + .b = { ISL_SSCALED, 8 }, + .a = { ISL_SSCALED, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8G8B8A8_USCALED] = { + .format = ISL_FORMAT_R8G8B8A8_USCALED, + .name = "ISL_FORMAT_R8G8B8A8_USCALED", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_USCALED, 8 }, + .g = { ISL_USCALED, 8 }, + .b = { ISL_USCALED, 8 }, + .a = { ISL_USCALED, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16G16_SSCALED] = { + .format = ISL_FORMAT_R16G16_SSCALED, + .name = "ISL_FORMAT_R16G16_SSCALED", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SSCALED, 16 }, + .g = { ISL_SSCALED, 6 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16G16_USCALED] = { + .format = ISL_FORMAT_R16G16_USCALED, + .name = "ISL_FORMAT_R16G16_USCALED", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_USCALED, 16 }, + .g = { ISL_USCALED, 16 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32_SSCALED] = { + .format = ISL_FORMAT_R32_SSCALED, + .name = "ISL_FORMAT_R32_SSCALED", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SSCALED, 32 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32_USCALED] = { + .format = ISL_FORMAT_R32_USCALED, + .name = "ISL_FORMAT_R32_USCALED", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_USCALED, 32 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_B5G6R5_UNORM] = { + .format = ISL_FORMAT_B5G6R5_UNORM, + .name = "ISL_FORMAT_B5G6R5_UNORM", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 5 }, + .g = { ISL_UNORM, 6 }, + .b = { ISL_UNORM, 5 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_B5G6R5_UNORM_SRGB] = { + .format = ISL_FORMAT_B5G6R5_UNORM_SRGB, + .name = "ISL_FORMAT_B5G6R5_UNORM_SRGB", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 5 }, + .g = { ISL_UNORM, 6 }, + .b = { ISL_UNORM, 5 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_B5G5R5A1_UNORM] = { + .format = ISL_FORMAT_B5G5R5A1_UNORM, + .name = "ISL_FORMAT_B5G5R5A1_UNORM", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 5 }, + .g = { ISL_UNORM, 5 }, + .b = { ISL_UNORM, 5 }, + .a = { ISL_UNORM, 1 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_B5G5R5A1_UNORM_SRGB] = { + .format = ISL_FORMAT_B5G5R5A1_UNORM_SRGB, + .name = "ISL_FORMAT_B5G5R5A1_UNORM_SRGB", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 5 }, + .g = { ISL_UNORM, 5 }, + .b = { ISL_UNORM, 5 }, + .a = { ISL_UNORM, 1 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_B4G4R4A4_UNORM] = { + .format = ISL_FORMAT_B4G4R4A4_UNORM, + .name = "ISL_FORMAT_B4G4R4A4_UNORM", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 4 }, + .g = { ISL_UNORM, 4 }, + .b = { ISL_UNORM, 4 }, + .a = { ISL_UNORM, 4 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_B4G4R4A4_UNORM_SRGB] = { + .format = ISL_FORMAT_B4G4R4A4_UNORM_SRGB, + .name = "ISL_FORMAT_B4G4R4A4_UNORM_SRGB", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 4 }, + .g = { ISL_UNORM, 4 }, + .b = { ISL_UNORM, 4 }, + .a = { ISL_UNORM, 4 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8G8_UNORM] = { + .format = ISL_FORMAT_R8G8_UNORM, + .name = "ISL_FORMAT_R8G8_UNORM", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 8 }, + .g = { ISL_UNORM, 8 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8G8_SNORM] = { + .format = ISL_FORMAT_R8G8_SNORM, + .name = "ISL_FORMAT_R8G8_SNORM", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SNORM, 8 }, + .g = { ISL_SNORM, 8 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8G8_SINT] = { + .format = ISL_FORMAT_R8G8_SINT, + .name = "ISL_FORMAT_R8G8_SINT", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SINT, 8 }, + .g = { ISL_SINT, 8 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8G8_UINT] = { + .format = ISL_FORMAT_R8G8_UINT, + .name = "ISL_FORMAT_R8G8_UINT", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UINT, 8 }, + .g = { ISL_UINT, 8 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16_UNORM] = { + .format = ISL_FORMAT_R16_UNORM, + .name = "ISL_FORMAT_R16_UNORM", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 16 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16_SNORM] = { + .format = ISL_FORMAT_R16_SNORM, + .name = "ISL_FORMAT_R16_SNORM", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SNORM, 16 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16_SINT] = { + .format = ISL_FORMAT_R16_SINT, + .name = "ISL_FORMAT_R16_SINT", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SINT, 16 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16_UINT] = { + .format = ISL_FORMAT_R16_UINT, + .name = "ISL_FORMAT_R16_UINT", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UINT, 16 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16_FLOAT] = { + .format = ISL_FORMAT_R16_FLOAT, + .name = "ISL_FORMAT_R16_FLOAT", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 16 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_A8P8_UNORM_PALETTE0] = { + .format = ISL_FORMAT_A8P8_UNORM_PALETTE0, + .name = "ISL_FORMAT_A8P8_UNORM_PALETTE0", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_UNORM, 8 }, + .l = {}, + .i = {}, + .p = { ISL_UNORM, 8 }, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_A8P8_UNORM_PALETTE1] = { + .format = ISL_FORMAT_A8P8_UNORM_PALETTE1, + .name = "ISL_FORMAT_A8P8_UNORM_PALETTE1", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_UNORM, 8 }, + .l = {}, + .i = {}, + .p = { ISL_UNORM, 8 }, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_I16_UNORM] = { + .format = ISL_FORMAT_I16_UNORM, + .name = "ISL_FORMAT_I16_UNORM", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = { ISL_UNORM, 16 }, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_L16_UNORM] = { + .format = ISL_FORMAT_L16_UNORM, + .name = "ISL_FORMAT_L16_UNORM", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = { ISL_UNORM, 16 }, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_A16_UNORM] = { + .format = ISL_FORMAT_A16_UNORM, + .name = "ISL_FORMAT_A16_UNORM", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_UNORM, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_L8A8_UNORM] = { + .format = ISL_FORMAT_L8A8_UNORM, + .name = "ISL_FORMAT_L8A8_UNORM", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_UNORM, 8 }, + .l = { ISL_UNORM, 8 }, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_I16_FLOAT] = { + .format = ISL_FORMAT_I16_FLOAT, + .name = "ISL_FORMAT_I16_FLOAT", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = { ISL_SFLOAT, 16 }, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_L16_FLOAT] = { + .format = ISL_FORMAT_L16_FLOAT, + .name = "ISL_FORMAT_L16_FLOAT", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = { ISL_SFLOAT, 16 }, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_A16_FLOAT] = { + .format = ISL_FORMAT_A16_FLOAT, + .name = "ISL_FORMAT_A16_FLOAT", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_SFLOAT, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_L8A8_UNORM_SRGB] = { + .format = ISL_FORMAT_L8A8_UNORM_SRGB, + .name = "ISL_FORMAT_L8A8_UNORM_SRGB", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_UNORM, 8 }, + .l = { ISL_UNORM, 8 }, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R5G5_SNORM_B6_UNORM] = { + .format = ISL_FORMAT_R5G5_SNORM_B6_UNORM, + .name = "ISL_FORMAT_R5G5_SNORM_B6_UNORM", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SNORM, 5 }, + .g = { ISL_SNORM, 5 }, + .b = { ISL_UNORM, 6 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_B5G5R5X1_UNORM] = { + .format = ISL_FORMAT_B5G5R5X1_UNORM, + .name = "ISL_FORMAT_B5G5R5X1_UNORM", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 5 }, + .g = { ISL_UNORM, 5 }, + .b = { ISL_UNORM, 5 }, + .a = { ISL_VOID, 1 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_B5G5R5X1_UNORM_SRGB] = { + .format = ISL_FORMAT_B5G5R5X1_UNORM_SRGB, + .name = "ISL_FORMAT_B5G5R5X1_UNORM_SRGB", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 5 }, + .g = { ISL_UNORM, 5 }, + .b = { ISL_UNORM, 5 }, + .a = { ISL_VOID, 1 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8G8_SSCALED] = { + .format = ISL_FORMAT_R8G8_SSCALED, + .name = "ISL_FORMAT_R8G8_SSCALED", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SSCALED, 8 }, + .g = { ISL_SSCALED, 8 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8G8_USCALED] = { + .format = ISL_FORMAT_R8G8_USCALED, + .name = "ISL_FORMAT_R8G8_USCALED", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_USCALED, 8 }, + .g = { ISL_USCALED, 8 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16_SSCALED] = { + .format = ISL_FORMAT_R16_SSCALED, + .name = "ISL_FORMAT_R16_SSCALED", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SSCALED, 16 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16_USCALED] = { + .format = ISL_FORMAT_R16_USCALED, + .name = "ISL_FORMAT_R16_USCALED", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_USCALED, 16 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_P8A8_UNORM_PALETTE0] = { + .format = ISL_FORMAT_P8A8_UNORM_PALETTE0, + .name = "ISL_FORMAT_P8A8_UNORM_PALETTE0", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_UNORM, 8 }, + .l = {}, + .i = {}, + .p = { ISL_UNORM, 8 }, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_P8A8_UNORM_PALETTE1] = { + .format = ISL_FORMAT_P8A8_UNORM_PALETTE1, + .name = "ISL_FORMAT_P8A8_UNORM_PALETTE1", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_UNORM, 8 }, + .l = {}, + .i = {}, + .p = { ISL_UNORM, 8 }, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_A1B5G5R5_UNORM] = { + .format = ISL_FORMAT_A1B5G5R5_UNORM, + .name = "ISL_FORMAT_A1B5G5R5_UNORM", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 5 }, + .g = { ISL_UNORM, 5 }, + .b = { ISL_UNORM, 5 }, + .a = { ISL_UNORM, 1 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_A4B4G4R4_UNORM] = { + .format = ISL_FORMAT_A4B4G4R4_UNORM, + .name = "ISL_FORMAT_A4B4G4R4_UNORM", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 4 }, + .g = { ISL_UNORM, 4 }, + .b = { ISL_UNORM, 4 }, + .a = { ISL_UNORM, 4 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_L8A8_UINT] = { + .format = ISL_FORMAT_L8A8_UINT, + .name = "ISL_FORMAT_L8A8_UINT", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_UINT, 8 }, + .l = { ISL_UINT, 8 }, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_L8A8_SINT] = { + .format = ISL_FORMAT_L8A8_SINT, + .name = "ISL_FORMAT_L8A8_SINT", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_SINT, 8 }, + .l = { ISL_SINT, 8 }, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8_UNORM] = { + .format = ISL_FORMAT_R8_UNORM, + .name = "ISL_FORMAT_R8_UNORM", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 8 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8_SNORM] = { + .format = ISL_FORMAT_R8_SNORM, + .name = "ISL_FORMAT_R8_SNORM", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SNORM, 8 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8_SINT] = { + .format = ISL_FORMAT_R8_SINT, + .name = "ISL_FORMAT_R8_SINT", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SINT, 8 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8_UINT] = { + .format = ISL_FORMAT_R8_UINT, + .name = "ISL_FORMAT_R8_UINT", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UINT, 8 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_A8_UNORM] = { + .format = ISL_FORMAT_A8_UNORM, + .name = "ISL_FORMAT_A8_UNORM", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_UNORM, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_I8_UNORM] = { + .format = ISL_FORMAT_I8_UNORM, + .name = "ISL_FORMAT_I8_UNORM", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = { ISL_UNORM, 8 }, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_L8_UNORM] = { + .format = ISL_FORMAT_L8_UNORM, + .name = "ISL_FORMAT_L8_UNORM", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = { ISL_UNORM, 8 }, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_P4A4_UNORM_PALETTE0] = { + .format = ISL_FORMAT_P4A4_UNORM_PALETTE0, + .name = "ISL_FORMAT_P4A4_UNORM_PALETTE0", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_UNORM, 4 }, + .l = {}, + .i = {}, + .p = { ISL_UNORM, 4 }, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_A4P4_UNORM_PALETTE0] = { + .format = ISL_FORMAT_A4P4_UNORM_PALETTE0, + .name = "ISL_FORMAT_A4P4_UNORM_PALETTE0", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_UNORM, 4 }, + .l = {}, + .i = {}, + .p = { ISL_UNORM, 4 }, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8_SSCALED] = { + .format = ISL_FORMAT_R8_SSCALED, + .name = "ISL_FORMAT_R8_SSCALED", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SSCALED, 8 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8_USCALED] = { + .format = ISL_FORMAT_R8_USCALED, + .name = "ISL_FORMAT_R8_USCALED", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_USCALED, 8 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_P8_UNORM_PALETTE0] = { + .format = ISL_FORMAT_P8_UNORM_PALETTE0, + .name = "ISL_FORMAT_P8_UNORM_PALETTE0", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = { ISL_UNORM, 8 }, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_L8_UNORM_SRGB] = { + .format = ISL_FORMAT_L8_UNORM_SRGB, + .name = "ISL_FORMAT_L8_UNORM_SRGB", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = { ISL_UNORM, 8 }, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_P8_UNORM_PALETTE1] = { + .format = ISL_FORMAT_P8_UNORM_PALETTE1, + .name = "ISL_FORMAT_P8_UNORM_PALETTE1", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = { ISL_UNORM, 8 }, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_P4A4_UNORM_PALETTE1] = { + .format = ISL_FORMAT_P4A4_UNORM_PALETTE1, + .name = "ISL_FORMAT_P4A4_UNORM_PALETTE1", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_UNORM, 4 }, + .l = {}, + .i = {}, + .p = { ISL_UNORM, 4 }, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_A4P4_UNORM_PALETTE1] = { + .format = ISL_FORMAT_A4P4_UNORM_PALETTE1, + .name = "ISL_FORMAT_A4P4_UNORM_PALETTE1", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_UNORM, 4 }, + .l = {}, + .i = {}, + .p = { ISL_UNORM, 4 }, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_Y8_UNORM] = { + .format = ISL_FORMAT_Y8_UNORM, + .name = "ISL_FORMAT_Y8_UNORM", + .bpb = 0, + .bw = 0, + .bh = 0, + .bd = 0, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_YUV, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_L8_UINT] = { + .format = ISL_FORMAT_L8_UINT, + .name = "ISL_FORMAT_L8_UINT", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = { ISL_UINT, 8 }, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_L8_SINT] = { + .format = ISL_FORMAT_L8_SINT, + .name = "ISL_FORMAT_L8_SINT", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = { ISL_SINT, 8 }, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_I8_UINT] = { + .format = ISL_FORMAT_I8_UINT, + .name = "ISL_FORMAT_I8_UINT", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = { ISL_UINT, 8 }, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_I8_SINT] = { + .format = ISL_FORMAT_I8_SINT, + .name = "ISL_FORMAT_I8_SINT", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = { ISL_SINT, 8 }, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_DXT1_RGB_SRGB] = { + .format = ISL_FORMAT_DXT1_RGB_SRGB, + .name = "ISL_FORMAT_DXT1_RGB_SRGB", + .bpb = 64, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 4 }, + .g = { ISL_UNORM, 4 }, + .b = { ISL_UNORM, 4 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_DXT1, + }, + + [ISL_FORMAT_R1_UNORM] = { + .format = ISL_FORMAT_R1_UNORM, + .name = "ISL_FORMAT_R1_UNORM", + .bpb = 1, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 1 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_YCRCB_NORMAL] = { + .format = ISL_FORMAT_YCRCB_NORMAL, + .name = "ISL_FORMAT_YCRCB_NORMAL", + .bpb = 0, + .bw = 0, + .bh = 0, + .bd = 0, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_YUV, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_YCRCB_SWAPUVY] = { + .format = ISL_FORMAT_YCRCB_SWAPUVY, + .name = "ISL_FORMAT_YCRCB_SWAPUVY", + .bpb = 0, + .bw = 0, + .bh = 0, + .bd = 0, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_YUV, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_P2_UNORM_PALETTE0] = { + .format = ISL_FORMAT_P2_UNORM_PALETTE0, + .name = "ISL_FORMAT_P2_UNORM_PALETTE0", + .bpb = 2, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = { ISL_UNORM, 2 }, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_P2_UNORM_PALETTE1] = { + .format = ISL_FORMAT_P2_UNORM_PALETTE1, + .name = "ISL_FORMAT_P2_UNORM_PALETTE1", + .bpb = 2, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = { ISL_UNORM, 2 }, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_BC1_UNORM] = { + .format = ISL_FORMAT_BC1_UNORM, + .name = "ISL_FORMAT_BC1_UNORM", + .bpb = 64, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 4 }, + .g = { ISL_UNORM, 4 }, + .b = { ISL_UNORM, 4 }, + .a = { ISL_UNORM, 4 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_DXT1, + }, + + [ISL_FORMAT_BC2_UNORM] = { + .format = ISL_FORMAT_BC2_UNORM, + .name = "ISL_FORMAT_BC2_UNORM", + .bpb = 128, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 4 }, + .g = { ISL_UNORM, 4 }, + .b = { ISL_UNORM, 4 }, + .a = { ISL_UNORM, 4 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_DXT3, + }, + + [ISL_FORMAT_BC3_UNORM] = { + .format = ISL_FORMAT_BC3_UNORM, + .name = "ISL_FORMAT_BC3_UNORM", + .bpb = 128, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 4 }, + .g = { ISL_UNORM, 4 }, + .b = { ISL_UNORM, 4 }, + .a = { ISL_UNORM, 4 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_DXT5, + }, + + [ISL_FORMAT_BC4_UNORM] = { + .format = ISL_FORMAT_BC4_UNORM, + .name = "ISL_FORMAT_BC4_UNORM", + .bpb = 64, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 8 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_RGTC1, + }, + + [ISL_FORMAT_BC5_UNORM] = { + .format = ISL_FORMAT_BC5_UNORM, + .name = "ISL_FORMAT_BC5_UNORM", + .bpb = 128, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 8 }, + .g = { ISL_UNORM, 8 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_RGTC2, + }, + + [ISL_FORMAT_BC1_UNORM_SRGB] = { + .format = ISL_FORMAT_BC1_UNORM_SRGB, + .name = "ISL_FORMAT_BC1_UNORM_SRGB", + .bpb = 64, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 4 }, + .g = { ISL_UNORM, 4 }, + .b = { ISL_UNORM, 4 }, + .a = { ISL_UNORM, 4 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_DXT1, + }, + + [ISL_FORMAT_BC2_UNORM_SRGB] = { + .format = ISL_FORMAT_BC2_UNORM_SRGB, + .name = "ISL_FORMAT_BC2_UNORM_SRGB", + .bpb = 128, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 4 }, + .g = { ISL_UNORM, 4 }, + .b = { ISL_UNORM, 4 }, + .a = { ISL_UNORM, 4 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_DXT3, + }, + + [ISL_FORMAT_BC3_UNORM_SRGB] = { + .format = ISL_FORMAT_BC3_UNORM_SRGB, + .name = "ISL_FORMAT_BC3_UNORM_SRGB", + .bpb = 128, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 4 }, + .g = { ISL_UNORM, 4 }, + .b = { ISL_UNORM, 4 }, + .a = { ISL_UNORM, 4 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_DXT5, + }, + + [ISL_FORMAT_MONO8] = { + .format = ISL_FORMAT_MONO8, + .name = "ISL_FORMAT_MONO8", + .bpb = 1, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_YCRCB_SWAPUV] = { + .format = ISL_FORMAT_YCRCB_SWAPUV, + .name = "ISL_FORMAT_YCRCB_SWAPUV", + .bpb = 0, + .bw = 0, + .bh = 0, + .bd = 0, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_YUV, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_YCRCB_SWAPY] = { + .format = ISL_FORMAT_YCRCB_SWAPY, + .name = "ISL_FORMAT_YCRCB_SWAPY", + .bpb = 0, + .bw = 0, + .bh = 0, + .bd = 0, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_YUV, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_DXT1_RGB] = { + .format = ISL_FORMAT_DXT1_RGB, + .name = "ISL_FORMAT_DXT1_RGB", + .bpb = 64, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 4 }, + .g = { ISL_UNORM, 4 }, + .b = { ISL_UNORM, 4 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_DXT1, + }, + + [ISL_FORMAT_FXT1] = { + .format = ISL_FORMAT_FXT1, + .name = "ISL_FORMAT_FXT1", + .bpb = 128, + .bw = 8, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 4 }, + .g = { ISL_UNORM, 4 }, + .b = { ISL_UNORM, 4 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_FXT1, + }, + + [ISL_FORMAT_R8G8B8_UNORM] = { + .format = ISL_FORMAT_R8G8B8_UNORM, + .name = "ISL_FORMAT_R8G8B8_UNORM", + .bpb = 24, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 8 }, + .g = { ISL_UNORM, 8 }, + .b = { ISL_UNORM, 8 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8G8B8_SNORM] = { + .format = ISL_FORMAT_R8G8B8_SNORM, + .name = "ISL_FORMAT_R8G8B8_SNORM", + .bpb = 24, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SNORM, 8 }, + .g = { ISL_SNORM, 8 }, + .b = { ISL_SNORM, 8 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8G8B8_SSCALED] = { + .format = ISL_FORMAT_R8G8B8_SSCALED, + .name = "ISL_FORMAT_R8G8B8_SSCALED", + .bpb = 24, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SSCALED, 8 }, + .g = { ISL_SSCALED, 8 }, + .b = { ISL_SSCALED, 8 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8G8B8_USCALED] = { + .format = ISL_FORMAT_R8G8B8_USCALED, + .name = "ISL_FORMAT_R8G8B8_USCALED", + .bpb = 24, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_USCALED, 8 }, + .g = { ISL_USCALED, 8 }, + .b = { ISL_USCALED, 8 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R64G64B64A64_FLOAT] = { + .format = ISL_FORMAT_R64G64B64A64_FLOAT, + .name = "ISL_FORMAT_R64G64B64A64_FLOAT", + .bpb = 256, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 64 }, + .g = { ISL_SFLOAT, 64 }, + .b = { ISL_SFLOAT, 64 }, + .a = { ISL_SFLOAT, 64 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R64G64B64_FLOAT] = { + .format = ISL_FORMAT_R64G64B64_FLOAT, + .name = "ISL_FORMAT_R64G64B64_FLOAT", + .bpb = 196, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 64 }, + .g = { ISL_SFLOAT, 64 }, + .b = { ISL_SFLOAT, 64 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_BC4_SNORM] = { + .format = ISL_FORMAT_BC4_SNORM, + .name = "ISL_FORMAT_BC4_SNORM", + .bpb = 64, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_SNORM, 8 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_RGTC1, + }, + + [ISL_FORMAT_BC5_SNORM] = { + .format = ISL_FORMAT_BC5_SNORM, + .name = "ISL_FORMAT_BC5_SNORM", + .bpb = 128, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_SNORM, 8 }, + .g = { ISL_SNORM, 8 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_RGTC2, + }, + + [ISL_FORMAT_R16G16B16_FLOAT] = { + .format = ISL_FORMAT_R16G16B16_FLOAT, + .name = "ISL_FORMAT_R16G16B16_FLOAT", + .bpb = 48, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 16 }, + .g = { ISL_SFLOAT, 16 }, + .b = { ISL_SFLOAT, 16 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16G16B16_UNORM] = { + .format = ISL_FORMAT_R16G16B16_UNORM, + .name = "ISL_FORMAT_R16G16B16_UNORM", + .bpb = 48, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 16 }, + .g = { ISL_UNORM, 16 }, + .b = { ISL_UNORM, 16 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16G16B16_SNORM] = { + .format = ISL_FORMAT_R16G16B16_SNORM, + .name = "ISL_FORMAT_R16G16B16_SNORM", + .bpb = 48, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SNORM, 16 }, + .g = { ISL_SNORM, 16 }, + .b = { ISL_SNORM, 16 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16G16B16_SSCALED] = { + .format = ISL_FORMAT_R16G16B16_SSCALED, + .name = "ISL_FORMAT_R16G16B16_SSCALED", + .bpb = 48, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SSCALED, 16 }, + .g = { ISL_SSCALED, 16 }, + .b = { ISL_SSCALED, 16 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16G16B16_USCALED] = { + .format = ISL_FORMAT_R16G16B16_USCALED, + .name = "ISL_FORMAT_R16G16B16_USCALED", + .bpb = 48, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_USCALED, 16 }, + .g = { ISL_USCALED, 16 }, + .b = { ISL_USCALED, 16 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_BC6H_SF16] = { + .format = ISL_FORMAT_BC6H_SF16, + .name = "ISL_FORMAT_BC6H_SF16", + .bpb = 128, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 16 }, + .g = { ISL_SFLOAT, 16 }, + .b = { ISL_SFLOAT, 16 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_BPTC, + }, + + [ISL_FORMAT_BC7_UNORM] = { + .format = ISL_FORMAT_BC7_UNORM, + .name = "ISL_FORMAT_BC7_UNORM", + .bpb = 128, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 8 }, + .g = { ISL_UNORM, 8 }, + .b = { ISL_UNORM, 8 }, + .a = { ISL_UNORM, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_BPTC, + }, + + [ISL_FORMAT_BC7_UNORM_SRGB] = { + .format = ISL_FORMAT_BC7_UNORM_SRGB, + .name = "ISL_FORMAT_BC7_UNORM_SRGB", + .bpb = 128, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 8 }, + .g = { ISL_UNORM, 8 }, + .b = { ISL_UNORM, 8 }, + .a = { ISL_UNORM, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_BPTC, + }, + + [ISL_FORMAT_BC6H_UF16] = { + .format = ISL_FORMAT_BC6H_UF16, + .name = "ISL_FORMAT_BC6H_UF16", + .bpb = 128, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UFLOAT, 16 }, + .g = { ISL_UFLOAT, 16 }, + .b = { ISL_UFLOAT, 16 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_BPTC, + }, + + [ISL_FORMAT_PLANAR_420_8] = { + .format = ISL_FORMAT_PLANAR_420_8, + .name = "ISL_FORMAT_PLANAR_420_8", + .bpb = 0, + .bw = 0, + .bh = 0, + .bd = 0, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_YUV, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8G8B8_UNORM_SRGB] = { + .format = ISL_FORMAT_R8G8B8_UNORM_SRGB, + .name = "ISL_FORMAT_R8G8B8_UNORM_SRGB", + .bpb = 24, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 8 }, + .g = { ISL_UNORM, 8 }, + .b = { ISL_UNORM, 8 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_ETC1_RGB8] = { + .format = ISL_FORMAT_ETC1_RGB8, + .name = "ISL_FORMAT_ETC1_RGB8", + .bpb = 64, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 8 }, + .g = { ISL_UNORM, 8 }, + .b = { ISL_UNORM, 8 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ETC1, + }, + + [ISL_FORMAT_ETC2_RGB8] = { + .format = ISL_FORMAT_ETC2_RGB8, + .name = "ISL_FORMAT_ETC2_RGB8", + .bpb = 64, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 8 }, + .g = { ISL_UNORM, 8 }, + .b = { ISL_UNORM, 8 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ETC2, + }, + + [ISL_FORMAT_EAC_R11] = { + .format = ISL_FORMAT_EAC_R11, + .name = "ISL_FORMAT_EAC_R11", + .bpb = 64, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 11 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ETC2, + }, + + [ISL_FORMAT_EAC_RG11] = { + .format = ISL_FORMAT_EAC_RG11, + .name = "ISL_FORMAT_EAC_RG11", + .bpb = 128, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 11 }, + .g = { ISL_UNORM, 11 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ETC2, + }, + + [ISL_FORMAT_EAC_SIGNED_R11] = { + .format = ISL_FORMAT_EAC_SIGNED_R11, + .name = "ISL_FORMAT_EAC_SIGNED_R11", + .bpb = 64, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_SNORM, 11 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ETC2, + }, + + [ISL_FORMAT_EAC_SIGNED_RG11] = { + .format = ISL_FORMAT_EAC_SIGNED_RG11, + .name = "ISL_FORMAT_EAC_SIGNED_RG11", + .bpb = 128, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_SNORM, 11 }, + .g = { ISL_SNORM, 11 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ETC2, + }, + + [ISL_FORMAT_ETC2_SRGB8] = { + .format = ISL_FORMAT_ETC2_SRGB8, + .name = "ISL_FORMAT_ETC2_SRGB8", + .bpb = 64, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 8 }, + .g = { ISL_UNORM, 8 }, + .b = { ISL_UNORM, 8 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_ETC2, + }, + + [ISL_FORMAT_R16G16B16_UINT] = { + .format = ISL_FORMAT_R16G16B16_UINT, + .name = "ISL_FORMAT_R16G16B16_UINT", + .bpb = 48, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UINT, 16 }, + .g = { ISL_UINT, 16 }, + .b = { ISL_UINT, 16 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16G16B16_SINT] = { + .format = ISL_FORMAT_R16G16B16_SINT, + .name = "ISL_FORMAT_R16G16B16_SINT", + .bpb = 48, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SINT, 16 }, + .g = { ISL_SINT, 16 }, + .b = { ISL_SINT, 16 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32_SFIXED] = { + .format = ISL_FORMAT_R32_SFIXED, + .name = "ISL_FORMAT_R32_SFIXED", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SFIXED, 16 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R10G10B10A2_SNORM] = { + .format = ISL_FORMAT_R10G10B10A2_SNORM, + .name = "ISL_FORMAT_R10G10B10A2_SNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SNORM, 10 }, + .g = { ISL_SNORM, 10 }, + .b = { ISL_SNORM, 10 }, + .a = { ISL_SNORM, 2 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R10G10B10A2_USCALED] = { + .format = ISL_FORMAT_R10G10B10A2_USCALED, + .name = "ISL_FORMAT_R10G10B10A2_USCALED", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_USCALED, 10 }, + .g = { ISL_USCALED, 10 }, + .b = { ISL_USCALED, 10 }, + .a = { ISL_USCALED, 2 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R10G10B10A2_SSCALED] = { + .format = ISL_FORMAT_R10G10B10A2_SSCALED, + .name = "ISL_FORMAT_R10G10B10A2_SSCALED", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SSCALED, 10 }, + .g = { ISL_SSCALED, 10 }, + .b = { ISL_SSCALED, 10 }, + .a = { ISL_SSCALED, 2 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R10G10B10A2_SINT] = { + .format = ISL_FORMAT_R10G10B10A2_SINT, + .name = "ISL_FORMAT_R10G10B10A2_SINT", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SINT, 10 }, + .g = { ISL_SINT, 10 }, + .b = { ISL_SINT, 10 }, + .a = { ISL_SINT, 2 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_B10G10R10A2_SNORM] = { + .format = ISL_FORMAT_B10G10R10A2_SNORM, + .name = "ISL_FORMAT_B10G10R10A2_SNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SNORM, 10 }, + .g = { ISL_SNORM, 10 }, + .b = { ISL_SNORM, 10 }, + .a = { ISL_SNORM, 2 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_B10G10R10A2_USCALED] = { + .format = ISL_FORMAT_B10G10R10A2_USCALED, + .name = "ISL_FORMAT_B10G10R10A2_USCALED", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_USCALED, 10 }, + .g = { ISL_USCALED, 10 }, + .b = { ISL_USCALED, 10 }, + .a = { ISL_USCALED, 2 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_B10G10R10A2_SSCALED] = { + .format = ISL_FORMAT_B10G10R10A2_SSCALED, + .name = "ISL_FORMAT_B10G10R10A2_SSCALED", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SSCALED, 10 }, + .g = { ISL_SSCALED, 10 }, + .b = { ISL_SSCALED, 10 }, + .a = { ISL_SSCALED, 2 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_B10G10R10A2_UINT] = { + .format = ISL_FORMAT_B10G10R10A2_UINT, + .name = "ISL_FORMAT_B10G10R10A2_UINT", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UINT, 10 }, + .g = { ISL_UINT, 10 }, + .b = { ISL_UINT, 10 }, + .a = { ISL_UINT, 2 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_B10G10R10A2_SINT] = { + .format = ISL_FORMAT_B10G10R10A2_SINT, + .name = "ISL_FORMAT_B10G10R10A2_SINT", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SINT, 10 }, + .g = { ISL_SINT, 10 }, + .b = { ISL_SINT, 10 }, + .a = { ISL_SINT, 2 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R64G64B64A64_PASSTHRU] = { + .format = ISL_FORMAT_R64G64B64A64_PASSTHRU, + .name = "ISL_FORMAT_R64G64B64A64_PASSTHRU", + .bpb = 256, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_RAW, 64 }, + .g = { ISL_RAW, 64 }, + .b = { ISL_RAW, 64 }, + .a = { ISL_RAW, 64 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R64G64B64_PASSTHRU] = { + .format = ISL_FORMAT_R64G64B64_PASSTHRU, + .name = "ISL_FORMAT_R64G64B64_PASSTHRU", + .bpb = 192, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_RAW, 64 }, + .g = { ISL_RAW, 64 }, + .b = { ISL_RAW, 64 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_ETC2_RGB8_PTA] = { + .format = ISL_FORMAT_ETC2_RGB8_PTA, + .name = "ISL_FORMAT_ETC2_RGB8_PTA", + .bpb = 64, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 8 }, + .g = { ISL_UNORM, 8 }, + .b = { ISL_UNORM, 8 }, + .a = { ISL_UNORM, 1 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ETC2, + }, + + [ISL_FORMAT_ETC2_SRGB8_PTA] = { + .format = ISL_FORMAT_ETC2_SRGB8_PTA, + .name = "ISL_FORMAT_ETC2_SRGB8_PTA", + .bpb = 64, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 8 }, + .g = { ISL_UNORM, 8 }, + .b = { ISL_UNORM, 8 }, + .a = { ISL_UNORM, 1 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_ETC2, + }, + + [ISL_FORMAT_ETC2_EAC_RGBA8] = { + .format = ISL_FORMAT_ETC2_EAC_RGBA8, + .name = "ISL_FORMAT_ETC2_EAC_RGBA8", + .bpb = 128, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 8 }, + .g = { ISL_UNORM, 8 }, + .b = { ISL_UNORM, 8 }, + .a = { ISL_UNORM, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ETC2, + }, + + [ISL_FORMAT_ETC2_EAC_SRGB8_A8] = { + .format = ISL_FORMAT_ETC2_EAC_SRGB8_A8, + .name = "ISL_FORMAT_ETC2_EAC_SRGB8_A8", + .bpb = 128, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 8 }, + .g = { ISL_UNORM, 8 }, + .b = { ISL_UNORM, 8 }, + .a = { ISL_UNORM, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_ETC2, + }, + + [ISL_FORMAT_R8G8B8_UINT] = { + .format = ISL_FORMAT_R8G8B8_UINT, + .name = "ISL_FORMAT_R8G8B8_UINT", + .bpb = 24, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UINT, 8 }, + .g = { ISL_UINT, 8 }, + .b = { ISL_UINT, 8 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8G8B8_SINT] = { + .format = ISL_FORMAT_R8G8B8_SINT, + .name = "ISL_FORMAT_R8G8B8_SINT", + .bpb = 24, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SINT, 8 }, + .g = { ISL_SINT, 8 }, + .b = { ISL_SINT, 8 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_RAW] = { + .format = ISL_FORMAT_RAW, + .name = "ISL_FORMAT_RAW", + .bpb = 0, + .bw = 0, + .bh = 0, + .bd = 0, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB] = { + .format = ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB, + .name = "ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB", + .bpb = 128, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 8 }, + .g = { ISL_UNORM, 8 }, + .b = { ISL_UNORM, 8 }, + .a = { ISL_UNORM, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB] = { + .format = ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB, + .name = "ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB", + .bpb = 128, + .bw = 5, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 8 }, + .g = { ISL_UNORM, 8 }, + .b = { ISL_UNORM, 8 }, + .a = { ISL_UNORM, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB] = { + .format = ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB, + .name = "ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB", + .bpb = 128, + .bw = 5, + .bh = 5, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 8 }, + .g = { ISL_UNORM, 8 }, + .b = { ISL_UNORM, 8 }, + .a = { ISL_UNORM, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB] = { + .format = ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB, + .name = "ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB", + .bpb = 128, + .bw = 6, + .bh = 5, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 8 }, + .g = { ISL_UNORM, 8 }, + .b = { ISL_UNORM, 8 }, + .a = { ISL_UNORM, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB] = { + .format = ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB, + .name = "ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB", + .bpb = 128, + .bw = 6, + .bh = 6, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 8 }, + .g = { ISL_UNORM, 8 }, + .b = { ISL_UNORM, 8 }, + .a = { ISL_UNORM, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB] = { + .format = ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB, + .name = "ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB", + .bpb = 128, + .bw = 8, + .bh = 5, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 8 }, + .g = { ISL_UNORM, 8 }, + .b = { ISL_UNORM, 8 }, + .a = { ISL_UNORM, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB] = { + .format = ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB, + .name = "ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB", + .bpb = 128, + .bw = 8, + .bh = 6, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 8 }, + .g = { ISL_UNORM, 8 }, + .b = { ISL_UNORM, 8 }, + .a = { ISL_UNORM, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB] = { + .format = ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB, + .name = "ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB", + .bpb = 128, + .bw = 8, + .bh = 8, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 8 }, + .g = { ISL_UNORM, 8 }, + .b = { ISL_UNORM, 8 }, + .a = { ISL_UNORM, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB] = { + .format = ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB, + .name = "ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB", + .bpb = 128, + .bw = 10, + .bh = 5, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 8 }, + .g = { ISL_UNORM, 8 }, + .b = { ISL_UNORM, 8 }, + .a = { ISL_UNORM, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB] = { + .format = ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB, + .name = "ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB", + .bpb = 128, + .bw = 10, + .bh = 6, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 8 }, + .g = { ISL_UNORM, 8 }, + .b = { ISL_UNORM, 8 }, + .a = { ISL_UNORM, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB] = { + .format = ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB, + .name = "ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB", + .bpb = 128, + .bw = 10, + .bh = 8, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 8 }, + .g = { ISL_UNORM, 8 }, + .b = { ISL_UNORM, 8 }, + .a = { ISL_UNORM, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB] = { + .format = ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB, + .name = "ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB", + .bpb = 128, + .bw = 10, + .bh = 10, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 8 }, + .g = { ISL_UNORM, 8 }, + .b = { ISL_UNORM, 8 }, + .a = { ISL_UNORM, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB] = { + .format = ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB, + .name = "ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB", + .bpb = 128, + .bw = 12, + .bh = 10, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 8 }, + .g = { ISL_UNORM, 8 }, + .b = { ISL_UNORM, 8 }, + .a = { ISL_UNORM, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB] = { + .format = ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB, + .name = "ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB", + .bpb = 128, + .bw = 12, + .bh = 12, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 8 }, + .g = { ISL_UNORM, 8 }, + .b = { ISL_UNORM, 8 }, + .a = { ISL_UNORM, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16] = { + .format = ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16, + .name = "ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16", + .bpb = 128, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 16 }, + .g = { ISL_SFLOAT, 16 }, + .b = { ISL_SFLOAT, 16 }, + .a = { ISL_SFLOAT, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16] = { + .format = ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16, + .name = "ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16", + .bpb = 128, + .bw = 5, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 16 }, + .g = { ISL_SFLOAT, 16 }, + .b = { ISL_SFLOAT, 16 }, + .a = { ISL_SFLOAT, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16] = { + .format = ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16, + .name = "ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16", + .bpb = 128, + .bw = 5, + .bh = 5, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 16 }, + .g = { ISL_SFLOAT, 16 }, + .b = { ISL_SFLOAT, 16 }, + .a = { ISL_SFLOAT, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16] = { + .format = ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16, + .name = "ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16", + .bpb = 128, + .bw = 6, + .bh = 5, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 16 }, + .g = { ISL_SFLOAT, 16 }, + .b = { ISL_SFLOAT, 16 }, + .a = { ISL_SFLOAT, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16] = { + .format = ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16, + .name = "ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16", + .bpb = 128, + .bw = 6, + .bh = 6, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 16 }, + .g = { ISL_SFLOAT, 16 }, + .b = { ISL_SFLOAT, 16 }, + .a = { ISL_SFLOAT, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16] = { + .format = ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16, + .name = "ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16", + .bpb = 128, + .bw = 8, + .bh = 5, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 16 }, + .g = { ISL_SFLOAT, 16 }, + .b = { ISL_SFLOAT, 16 }, + .a = { ISL_SFLOAT, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16] = { + .format = ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16, + .name = "ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16", + .bpb = 128, + .bw = 8, + .bh = 6, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 16 }, + .g = { ISL_SFLOAT, 16 }, + .b = { ISL_SFLOAT, 16 }, + .a = { ISL_SFLOAT, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16] = { + .format = ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16, + .name = "ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16", + .bpb = 128, + .bw = 8, + .bh = 8, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 16 }, + .g = { ISL_SFLOAT, 16 }, + .b = { ISL_SFLOAT, 16 }, + .a = { ISL_SFLOAT, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16] = { + .format = ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16, + .name = "ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16", + .bpb = 128, + .bw = 10, + .bh = 5, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 16 }, + .g = { ISL_SFLOAT, 16 }, + .b = { ISL_SFLOAT, 16 }, + .a = { ISL_SFLOAT, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16] = { + .format = ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16, + .name = "ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16", + .bpb = 128, + .bw = 10, + .bh = 6, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 16 }, + .g = { ISL_SFLOAT, 16 }, + .b = { ISL_SFLOAT, 16 }, + .a = { ISL_SFLOAT, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16] = { + .format = ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16, + .name = "ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16", + .bpb = 128, + .bw = 10, + .bh = 8, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 16 }, + .g = { ISL_SFLOAT, 16 }, + .b = { ISL_SFLOAT, 16 }, + .a = { ISL_SFLOAT, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16] = { + .format = ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16, + .name = "ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16", + .bpb = 128, + .bw = 10, + .bh = 10, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 16 }, + .g = { ISL_SFLOAT, 16 }, + .b = { ISL_SFLOAT, 16 }, + .a = { ISL_SFLOAT, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16] = { + .format = ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16, + .name = "ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16", + .bpb = 128, + .bw = 12, + .bh = 10, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 16 }, + .g = { ISL_SFLOAT, 16 }, + .b = { ISL_SFLOAT, 16 }, + .a = { ISL_SFLOAT, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16] = { + .format = ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16, + .name = "ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16", + .bpb = 128, + .bw = 12, + .bh = 12, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 16 }, + .g = { ISL_SFLOAT, 16 }, + .b = { ISL_SFLOAT, 16 }, + .a = { ISL_SFLOAT, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_HIZ] = { + .format = ISL_FORMAT_HIZ, + .name = "ISL_FORMAT_HIZ", + .bpb = 128, + .bw = 8, + .bh = 4, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_HIZ, + }, + + [ISL_FORMAT_MCS_2X] = { + .format = ISL_FORMAT_MCS_2X, + .name = "ISL_FORMAT_MCS_2X", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_MCS, + }, + + [ISL_FORMAT_MCS_4X] = { + .format = ISL_FORMAT_MCS_4X, + .name = "ISL_FORMAT_MCS_4X", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_MCS, + }, + + [ISL_FORMAT_MCS_8X] = { + .format = ISL_FORMAT_MCS_8X, + .name = "ISL_FORMAT_MCS_8X", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_MCS, + }, + + [ISL_FORMAT_MCS_16X] = { + .format = ISL_FORMAT_MCS_16X, + .name = "ISL_FORMAT_MCS_16X", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_MCS, + }, + + [ISL_FORMAT_GEN7_CCS_32BPP_X] = { + .format = ISL_FORMAT_GEN7_CCS_32BPP_X, + .name = "ISL_FORMAT_GEN7_CCS_32BPP_X", + .bpb = 1, + .bw = 16, + .bh = 2, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_CCS, + }, + + [ISL_FORMAT_GEN7_CCS_64BPP_X] = { + .format = ISL_FORMAT_GEN7_CCS_64BPP_X, + .name = "ISL_FORMAT_GEN7_CCS_64BPP_X", + .bpb = 1, + .bw = 8, + .bh = 2, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_CCS, + }, + + [ISL_FORMAT_GEN7_CCS_128BPP_X] = { + .format = ISL_FORMAT_GEN7_CCS_128BPP_X, + .name = "ISL_FORMAT_GEN7_CCS_128BPP_X", + .bpb = 1, + .bw = 4, + .bh = 2, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_CCS, + }, + + [ISL_FORMAT_GEN7_CCS_32BPP_Y] = { + .format = ISL_FORMAT_GEN7_CCS_32BPP_Y, + .name = "ISL_FORMAT_GEN7_CCS_32BPP_Y", + .bpb = 1, + .bw = 8, + .bh = 4, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_CCS, + }, + + [ISL_FORMAT_GEN7_CCS_64BPP_Y] = { + .format = ISL_FORMAT_GEN7_CCS_64BPP_Y, + .name = "ISL_FORMAT_GEN7_CCS_64BPP_Y", + .bpb = 1, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_CCS, + }, + + [ISL_FORMAT_GEN7_CCS_128BPP_Y] = { + .format = ISL_FORMAT_GEN7_CCS_128BPP_Y, + .name = "ISL_FORMAT_GEN7_CCS_128BPP_Y", + .bpb = 1, + .bw = 2, + .bh = 4, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_CCS, + }, + + [ISL_FORMAT_GEN9_CCS_32BPP] = { + .format = ISL_FORMAT_GEN9_CCS_32BPP, + .name = "ISL_FORMAT_GEN9_CCS_32BPP", + .bpb = 2, + .bw = 8, + .bh = 4, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_CCS, + }, + + [ISL_FORMAT_GEN9_CCS_64BPP] = { + .format = ISL_FORMAT_GEN9_CCS_64BPP, + .name = "ISL_FORMAT_GEN9_CCS_64BPP", + .bpb = 2, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_CCS, + }, + + [ISL_FORMAT_GEN9_CCS_128BPP] = { + .format = ISL_FORMAT_GEN9_CCS_128BPP, + .name = "ISL_FORMAT_GEN9_CCS_128BPP", + .bpb = 2, + .bw = 2, + .bh = 4, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_CCS, + }, + +}; diff --git a/lib/mesa/src/intel/isl/isl_format_layout.csv b/lib/mesa/src/intel/isl/isl_format_layout.csv new file mode 100644 index 000000000..f0f31c72f --- /dev/null +++ b/lib/mesa/src/intel/isl/isl_format_layout.csv @@ -0,0 +1,330 @@ +# Copyright 2015 Intel Corporation +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice (including the next +# paragraph) shall be included in all copies or substantial portions of the +# Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +# IN THE SOFTWARE. + +# +# @file +# @brief Layout of all hardware surface formats +# +# For the official list, see Broadwell PRM: Volume 2b: Command Reference: +# Enumerations: SURFACE_FORMAT. +# + + +# Columns: +# name: format name in PRM +# bpb: bits per block +# bw: block width, in pixels +# bh: block height, in pixels +# bd: block depth, in pixels +# r: red channel, data type and bitwidth +# g: green channel +# b: blue channel +# a: alpha channel +# l: luminance channel +# i: intensity channel +# p: palette channel +# space: colorspace +# txc: texture compression +# +# Data Types: +# x: void +# r: raw +# un: unorm +# sn: snorm +# uf: ufloat +# sf: sfloat +# ux: ufixed +# sx: sfixed +# ui: uint +# si: sint +# us: uscaled +# ss: sscaled + + +# Table is aligned with the Vim commands below, using the Align plugin: +# :AlignCtrl lr+ p8000000000000P1 +# /^# name/,$ Align, + +# name , bpb, bw, bh, bd, r, g, b, a, l, i, p, space, txc +R32G32B32A32_FLOAT , 128, 1, 1, 1, sf32, sf32, sf32, sf32, , , , linear, +R32G32B32A32_SINT , 128, 1, 1, 1, si32, si32, si32, si32, , , , linear, +R32G32B32A32_UINT , 128, 1, 1, 1, ui32, ui32, ui32, ui32, , , , linear, +R32G32B32A32_UNORM , 128, 1, 1, 1, un32, un32, un32, un32, , , , linear, +R32G32B32A32_SNORM , 128, 1, 1, 1, sn32, sn32, sn32, sn32, , , , linear, +R64G64_FLOAT , 128, 1, 1, 1, sf64, sf64, , , , , , linear, +R32G32B32X32_FLOAT , 128, 1, 1, 1, sf32, sf32, sf32, x32, , , , linear, +R32G32B32A32_SSCALED , 128, 1, 1, 1, ss32, ss32, ss32, ss32, , , , linear, +R32G32B32A32_USCALED , 128, 1, 1, 1, us32, us32, us32, us32, , , , linear, +R32G32B32A32_SFIXED , 128, 1, 1, 1, sx32, sx32, sx32, sx32, , , , linear, +R64G64_PASSTHRU , 128, 1, 1, 1, r64, r64, , , , , , , +R32G32B32_FLOAT , 96, 1, 1, 1, sf32, sf32, sf32, , , , , linear, +R32G32B32_SINT , 96, 1, 1, 1, si32, si32, si32, , , , , linear, +R32G32B32_UINT , 96, 1, 1, 1, ui32, ui32, ui32, , , , , linear, +R32G32B32_UNORM , 96, 1, 1, 1, un32, un32, un32, , , , , linear, +R32G32B32_SNORM , 96, 1, 1, 1, sn32, sn32, sn32, , , , , linear, +R32G32B32_SSCALED , 96, 1, 1, 1, ss32, ss32, ss32, , , , , linear, +R32G32B32_USCALED , 96, 1, 1, 1, us32, us32, us32, , , , , linear, +R32G32B32_SFIXED , 96, 1, 1, 1, sx32, sx32, sx32, , , , , linear, +R16G16B16A16_UNORM , 64, 1, 1, 1, un16, un16, un16, un16, , , , linear, +R16G16B16A16_SNORM , 64, 1, 1, 1, sn16, sn16, sn16, sn16, , , , linear, +R16G16B16A16_SINT , 64, 1, 1, 1, si16, si16, si16, si16, , , , linear, +R16G16B16A16_UINT , 64, 1, 1, 1, ui16, ui16, ui16, ui16, , , , linear, +R16G16B16A16_FLOAT , 64, 1, 1, 1, sf16, sf16, sf16, sf16, , , , linear, +R32G32_FLOAT , 64, 1, 1, 1, sf32, sf32, , , , , , linear, +R32G32_SINT , 64, 1, 1, 1, si32, si32, , , , , , linear, +R32G32_UINT , 64, 1, 1, 1, ui32, ui32, , , , , , linear, +R32_FLOAT_X8X24_TYPELESS , 64, 1, 1, 1, sf32, x8, x24, , , , , linear, +X32_TYPELESS_G8X24_UINT , 64, 1, 1, 1, x32, ui8, x24, , , , , linear, +L32A32_FLOAT , 64, 1, 1, 1, , , , sf32, sf32, , , linear, +R32G32_UNORM , 64, 1, 1, 1, un32, un32, , , , , , linear, +R32G32_SNORM , 64, 1, 1, 1, sn32, sn32, , , , , , linear, +R64_FLOAT , 64, 1, 1, 1, sf64, , , , , , , linear, +R16G16B16X16_UNORM , 64, 1, 1, 1, un16, un16, un16, x16, , , , linear, +R16G16B16X16_FLOAT , 64, 1, 1, 1, sf16, sf16, sf16, x16, , , , linear, +A32X32_FLOAT , 64, 1, 1, 1, , , , sf32, x32, , , alpha, +L32X32_FLOAT , 64, 1, 1, 1, , , , x32, sf32, , , linear, +I32X32_FLOAT , 64, 1, 1, 1, , , , x32, , sf32, , linear, +R16G16B16A16_SSCALED , 64, 1, 1, 1, ss16, ss16, ss16, ss16, , , , linear, +R16G16B16A16_USCALED , 64, 1, 1, 1, us16, us16, us16, us16, , , , linear, +R32G32_SSCALED , 64, 1, 1, 1, ss32, ss32, , , , , , linear, +R32G32_USCALED , 64, 1, 1, 1, us32, us32, , , , , , linear, +R32G32_FLOAT_LD , 64, 1, 1, 1, sf32, sf32, , , , , , linear, +R32G32_SFIXED , 64, 1, 1, 1, sx32, sx32, , , , , , linear, +R64_PASSTHRU , 64, 1, 1, 1, r64, , , , , , , , +B8G8R8A8_UNORM , 32, 1, 1, 1, un8, un8, un8, un8, , , , linear, +B8G8R8A8_UNORM_SRGB , 32, 1, 1, 1, un8, un8, un8, un8, , , , srgb, +R10G10B10A2_UNORM , 32, 1, 1, 1, un10, un10, un10, un2, , , , linear, +R10G10B10A2_UNORM_SRGB , 32, 1, 1, 1, un10, un10, un10, un2, , , , srgb, +R10G10B10A2_UINT , 32, 1, 1, 1, ui10, ui10, ui10, ui2, , , , linear, +R10G10B10_SNORM_A2_UNORM , 32, 1, 1, 1, sn10, sn10, sn10, un2, , , , linear, +R8G8B8A8_UNORM , 32, 1, 1, 1, un8, un8, un8, un8, , , , linear, +R8G8B8A8_UNORM_SRGB , 32, 1, 1, 1, un8, un8, un8, un8, , , , srgb, +R8G8B8A8_SNORM , 32, 1, 1, 1, sn8, sn8, sn8, sn8, , , , linear, +R8G8B8A8_SINT , 32, 1, 1, 1, si8, si8, si8, si8, , , , linear, +R8G8B8A8_UINT , 32, 1, 1, 1, ui8, ui8, ui8, ui8, , , , linear, +R16G16_UNORM , 32, 1, 1, 1, un16, un16, , , , , , linear, +R16G16_SNORM , 32, 1, 1, 1, sn16, sn16, , , , , , linear, +R16G16_SINT , 32, 1, 1, 1, si16, si16, , , , , , linear, +R16G16_UINT , 32, 1, 1, 1, ui16, ui16, , , , , , linear, +R16G16_FLOAT , 32, 1, 1, 1, sf16, sf16, , , , , , linear, +B10G10R10A2_UNORM , 32, 1, 1, 1, un10, un10, un10, un2, , , , linear, +B10G10R10A2_UNORM_SRGB , 32, 1, 1, 1, un10, un10, un10, un2, , , , srgb, +R11G11B10_FLOAT , 32, 1, 1, 1, uf11, uf11, uf10, , , , , linear, +R32_SINT , 32, 1, 1, 1, si32, , , , , , , linear, +R32_UINT , 32, 1, 1, 1, ui32, , , , , , , linear, +R32_FLOAT , 32, 1, 1, 1, sf32, , , , , , , linear, +R24_UNORM_X8_TYPELESS , 32, 1, 1, 1, un24, x8, , , , , , linear, +X24_TYPELESS_G8_UINT , 32, 1, 1, 1, x24, ui8, , , , , , linear, +L32_UNORM , 32, 1, 1, 1, , , , , un32, , , linear, +A32_UNORM , 32, 1, 1, 1, , , , un32, , , , alpha, +L16A16_UNORM , 32, 1, 1, 1, , , , un16, un16, , , linear, +I24X8_UNORM , 32, 1, 1, 1, , , , x8, , un24, , linear, +L24X8_UNORM , 32, 1, 1, 1, , , , x8, un24, , , linear, +A24X8_UNORM , 32, 1, 1, 1, , , , un24, x8, , , alpha, +I32_FLOAT , 32, 1, 1, 1, , , , , , sf32, , linear, +L32_FLOAT , 32, 1, 1, 1, , , , , sf32, , , linear, +A32_FLOAT , 32, 1, 1, 1, , , , sf32, , , , alpha, +X8B8_UNORM_G8R8_SNORM , 32, 1, 1, 1, sn8, sn8, un8, x8, , , , linear, +A8X8_UNORM_G8R8_SNORM , 32, 1, 1, 1, sn8, sn8, x8, un8, , , , linear, +B8X8_UNORM_G8R8_SNORM , 32, 1, 1, 1, sn8, sn8, un8, x8, , , , linear, +B8G8R8X8_UNORM , 32, 1, 1, 1, un8, un8, un8, x8, , , , linear, +B8G8R8X8_UNORM_SRGB , 32, 1, 1, 1, un8, un8, un8, x8, , , , srgb, +R8G8B8X8_UNORM , 32, 1, 1, 1, un8, un8, un8, x8, , , , linear, +R8G8B8X8_UNORM_SRGB , 32, 1, 1, 1, un8, un8, un8, x8, , , , srgb, +R9G9B9E5_SHAREDEXP , 32, 1, 1, 1, uf9, uf9, uf9, , , , , linear, +B10G10R10X2_UNORM , 32, 1, 1, 1, un10, un10, un10, x2, , , , linear, +L16A16_FLOAT , 32, 1, 1, 1, , , , sf16, sf16, , , linear, +R32_UNORM , 32, 1, 1, 1, un32, , , , , , , linear, +R32_SNORM , 32, 1, 1, 1, sn32, , , , , , , linear, +R10G10B10X2_USCALED , 32, 1, 1, 1, us10, us10, us10, x2, , , , linear, +R8G8B8A8_SSCALED , 32, 1, 1, 1, ss8, ss8, ss8, ss8, , , , linear, +R8G8B8A8_USCALED , 32, 1, 1, 1, us8, us8, us8, us8, , , , linear, +R16G16_SSCALED , 32, 1, 1, 1, ss16, ss6, , , , , , linear, +R16G16_USCALED , 32, 1, 1, 1, us16, us16, , , , , , linear, +R32_SSCALED , 32, 1, 1, 1, ss32, , , , , , , linear, +R32_USCALED , 32, 1, 1, 1, us32, , , , , , , linear, +B5G6R5_UNORM , 16, 1, 1, 1, un5, un6, un5, , , , , linear, +B5G6R5_UNORM_SRGB , 16, 1, 1, 1, un5, un6, un5, , , , , srgb, +B5G5R5A1_UNORM , 16, 1, 1, 1, un5, un5, un5, un1, , , , linear, +B5G5R5A1_UNORM_SRGB , 16, 1, 1, 1, un5, un5, un5, un1, , , , srgb, +B4G4R4A4_UNORM , 16, 1, 1, 1, un4, un4, un4, un4, , , , linear, +B4G4R4A4_UNORM_SRGB , 16, 1, 1, 1, un4, un4, un4, un4, , , , srgb, +R8G8_UNORM , 16, 1, 1, 1, un8, un8, , , , , , linear, +R8G8_SNORM , 16, 1, 1, 1, sn8, sn8, , , , , , linear, +R8G8_SINT , 16, 1, 1, 1, si8, si8, , , , , , linear, +R8G8_UINT , 16, 1, 1, 1, ui8, ui8, , , , , , linear, +R16_UNORM , 16, 1, 1, 1, un16, , , , , , , linear, +R16_SNORM , 16, 1, 1, 1, sn16, , , , , , , linear, +R16_SINT , 16, 1, 1, 1, si16, , , , , , , linear, +R16_UINT , 16, 1, 1, 1, ui16, , , , , , , linear, +R16_FLOAT , 16, 1, 1, 1, sf16, , , , , , , linear, +A8P8_UNORM_PALETTE0 , 16, 1, 1, 1, , , , un8, , , un8, linear, +A8P8_UNORM_PALETTE1 , 16, 1, 1, 1, , , , un8, , , un8, linear, +I16_UNORM , 16, 1, 1, 1, , , , , , un16, , linear, +L16_UNORM , 16, 1, 1, 1, , , , , un16, , , linear, +A16_UNORM , 16, 1, 1, 1, , , , un16, , , , alpha, +L8A8_UNORM , 16, 1, 1, 1, , , , un8, un8, , , linear, +I16_FLOAT , 16, 1, 1, 1, , , , , , sf16, , linear, +L16_FLOAT , 16, 1, 1, 1, , , , , sf16, , , linear, +A16_FLOAT , 16, 1, 1, 1, , , , sf16, , , , alpha, +L8A8_UNORM_SRGB , 16, 1, 1, 1, , , , un8, un8, , , srgb, +R5G5_SNORM_B6_UNORM , 16, 1, 1, 1, sn5, sn5, un6, , , , , linear, +B5G5R5X1_UNORM , 16, 1, 1, 1, un5, un5, un5, x1, , , , linear, +B5G5R5X1_UNORM_SRGB , 16, 1, 1, 1, un5, un5, un5, x1, , , , srgb, +R8G8_SSCALED , 16, 1, 1, 1, ss8, ss8, , , , , , linear, +R8G8_USCALED , 16, 1, 1, 1, us8, us8, , , , , , linear, +R16_SSCALED , 16, 1, 1, 1, ss16, , , , , , , linear, +R16_USCALED , 16, 1, 1, 1, us16, , , , , , , linear, +P8A8_UNORM_PALETTE0 , 16, 1, 1, 1, , , , un8, , , un8, linear, +P8A8_UNORM_PALETTE1 , 16, 1, 1, 1, , , , un8, , , un8, linear, +A1B5G5R5_UNORM , 16, 1, 1, 1, un5, un5, un5, un1, , , , linear, +A4B4G4R4_UNORM , 16, 1, 1, 1, un4, un4, un4, un4, , , , linear, +L8A8_UINT , 16, 1, 1, 1, , , , ui8, ui8, , , linear, +L8A8_SINT , 16, 1, 1, 1, , , , si8, si8, , , linear, +R8_UNORM , 8, 1, 1, 1, un8, , , , , , , linear, +R8_SNORM , 8, 1, 1, 1, sn8, , , , , , , linear, +R8_SINT , 8, 1, 1, 1, si8, , , , , , , linear, +R8_UINT , 8, 1, 1, 1, ui8, , , , , , , linear, +A8_UNORM , 8, 1, 1, 1, , , , un8, , , , alpha, +I8_UNORM , 8, 1, 1, 1, , , , , , un8, , linear, +L8_UNORM , 8, 1, 1, 1, , , , , un8, , , linear, +P4A4_UNORM_PALETTE0 , 8, 1, 1, 1, , , , un4, , , un4, linear, +A4P4_UNORM_PALETTE0 , 8, 1, 1, 1, , , , un4, , , un4, linear, +R8_SSCALED , 8, 1, 1, 1, ss8, , , , , , , linear, +R8_USCALED , 8, 1, 1, 1, us8, , , , , , , linear, +P8_UNORM_PALETTE0 , 8, 1, 1, 1, , , , , , , un8, linear, +L8_UNORM_SRGB , 8, 1, 1, 1, , , , , un8, , , linear, +P8_UNORM_PALETTE1 , 8, 1, 1, 1, , , , , , , un8, linear, +P4A4_UNORM_PALETTE1 , 8, 1, 1, 1, , , , un4, , , un4, linear, +A4P4_UNORM_PALETTE1 , 8, 1, 1, 1, , , , un4, , , un4, linear, +Y8_UNORM , 0, 0, 0, 0, , , , , , , , yuv, +L8_UINT , 8, 1, 1, 1, , , , , ui8, , , linear, +L8_SINT , 8, 1, 1, 1, , , , , si8, , , linear, +I8_UINT , 8, 1, 1, 1, , , , , , ui8, , linear, +I8_SINT , 8, 1, 1, 1, , , , , , si8, , linear, +DXT1_RGB_SRGB , 64, 4, 4, 1, un4, un4, un4, , , , , srgb, dxt1 +R1_UNORM , 1, 1, 1, 1, un1, , , , , , , linear, +YCRCB_NORMAL , 0, 0, 0, 0, , , , , , , , yuv, +YCRCB_SWAPUVY , 0, 0, 0, 0, , , , , , , , yuv, +P2_UNORM_PALETTE0 , 2, 1, 1, 1, , , , , , , un2, linear, +P2_UNORM_PALETTE1 , 2, 1, 1, 1, , , , , , , un2, linear, +BC1_UNORM , 64, 4, 4, 1, un4, un4, un4, un4, , , , linear, dxt1 +BC2_UNORM , 128, 4, 4, 1, un4, un4, un4, un4, , , , linear, dxt3 +BC3_UNORM , 128, 4, 4, 1, un4, un4, un4, un4, , , , linear, dxt5 +BC4_UNORM , 64, 4, 4, 1, un8, , , , , , , linear, rgtc1 +BC5_UNORM , 128, 4, 4, 1, un8, un8, , , , , , linear, rgtc2 +BC1_UNORM_SRGB , 64, 4, 4, 1, un4, un4, un4, un4, , , , srgb, dxt1 +BC2_UNORM_SRGB , 128, 4, 4, 1, un4, un4, un4, un4, , , , srgb, dxt3 +BC3_UNORM_SRGB , 128, 4, 4, 1, un4, un4, un4, un4, , , , srgb, dxt5 +MONO8 , 1, 1, 1, 1, , , , , , , , , +YCRCB_SWAPUV , 0, 0, 0, 0, , , , , , , , yuv, +YCRCB_SWAPY , 0, 0, 0, 0, , , , , , , , yuv, +DXT1_RGB , 64, 4, 4, 1, un4, un4, un4, , , , , linear, dxt1 +FXT1 , 128, 8, 4, 1, un4, un4, un4, , , , , linear, fxt1 +R8G8B8_UNORM , 24, 1, 1, 1, un8, un8, un8, , , , , linear, +R8G8B8_SNORM , 24, 1, 1, 1, sn8, sn8, sn8, , , , , linear, +R8G8B8_SSCALED , 24, 1, 1, 1, ss8, ss8, ss8, , , , , linear, +R8G8B8_USCALED , 24, 1, 1, 1, us8, us8, us8, , , , , linear, +R64G64B64A64_FLOAT , 256, 1, 1, 1, sf64, sf64, sf64, sf64, , , , linear, +R64G64B64_FLOAT , 196, 1, 1, 1, sf64, sf64, sf64, , , , , linear, +BC4_SNORM , 64, 4, 4, 1, sn8, , , , , , , linear, rgtc1 +BC5_SNORM , 128, 4, 4, 1, sn8, sn8, , , , , , linear, rgtc2 +R16G16B16_FLOAT , 48, 1, 1, 1, sf16, sf16, sf16, , , , , linear, +R16G16B16_UNORM , 48, 1, 1, 1, un16, un16, un16, , , , , linear, +R16G16B16_SNORM , 48, 1, 1, 1, sn16, sn16, sn16, , , , , linear, +R16G16B16_SSCALED , 48, 1, 1, 1, ss16, ss16, ss16, , , , , linear, +R16G16B16_USCALED , 48, 1, 1, 1, us16, us16, us16, , , , , linear, +BC6H_SF16 , 128, 4, 4, 1, sf16, sf16, sf16, , , , , linear, bptc +BC7_UNORM , 128, 4, 4, 1, un8, un8, un8, un8, , , , linear, bptc +BC7_UNORM_SRGB , 128, 4, 4, 1, un8, un8, un8, un8, , , , srgb, bptc +BC6H_UF16 , 128, 4, 4, 1, uf16, uf16, uf16, , , , , linear, bptc +PLANAR_420_8 , 0, 0, 0, 0, , , , , , , , yuv, +R8G8B8_UNORM_SRGB , 24, 1, 1, 1, un8, un8, un8, , , , , srgb, +ETC1_RGB8 , 64, 4, 4, 1, un8, un8, un8, , , , , linear, etc1 +ETC2_RGB8 , 64, 4, 4, 1, un8, un8, un8, , , , , linear, etc2 +EAC_R11 , 64, 4, 4, 1, un11, , , , , , , linear, etc2 +EAC_RG11 , 128, 4, 4, 1, un11, un11, , , , , , linear, etc2 +EAC_SIGNED_R11 , 64, 4, 4, 1, sn11, , , , , , , linear, etc2 +EAC_SIGNED_RG11 , 128, 4, 4, 1, sn11, sn11, , , , , , linear, etc2 +ETC2_SRGB8 , 64, 4, 4, 1, un8, un8, un8, , , , , srgb, etc2 +R16G16B16_UINT , 48, 1, 1, 1, ui16, ui16, ui16, , , , , linear, +R16G16B16_SINT , 48, 1, 1, 1, si16, si16, si16, , , , , linear, +R32_SFIXED , 32, 1, 1, 1, sx16, , , , , , , linear, +R10G10B10A2_SNORM , 32, 1, 1, 1, sn10, sn10, sn10, sn2, , , , linear, +R10G10B10A2_USCALED , 32, 1, 1, 1, us10, us10, us10, us2, , , , linear, +R10G10B10A2_SSCALED , 32, 1, 1, 1, ss10, ss10, ss10, ss2, , , , linear, +R10G10B10A2_SINT , 32, 1, 1, 1, si10, si10, si10, si2, , , , linear, +B10G10R10A2_SNORM , 32, 1, 1, 1, sn10, sn10, sn10, sn2, , , , linear, +B10G10R10A2_USCALED , 32, 1, 1, 1, us10, us10, us10, us2, , , , linear, +B10G10R10A2_SSCALED , 32, 1, 1, 1, ss10, ss10, ss10, ss2, , , , linear, +B10G10R10A2_UINT , 32, 1, 1, 1, ui10, ui10, ui10, ui2, , , , linear, +B10G10R10A2_SINT , 32, 1, 1, 1, si10, si10, si10, si2, , , , linear, +R64G64B64A64_PASSTHRU , 256, 1, 1, 1, r64, r64, r64, r64, , , , , +R64G64B64_PASSTHRU , 192, 1, 1, 1, r64, r64, r64, , , , , , +ETC2_RGB8_PTA , 64, 4, 4, 1, un8, un8, un8, un1, , , , linear, etc2 +ETC2_SRGB8_PTA , 64, 4, 4, 1, un8, un8, un8, un1, , , , srgb, etc2 +ETC2_EAC_RGBA8 , 128, 4, 4, 1, un8, un8, un8, un8, , , , linear, etc2 +ETC2_EAC_SRGB8_A8 , 128, 4, 4, 1, un8, un8, un8, un8, , , , srgb, etc2 +R8G8B8_UINT , 24, 1, 1, 1, ui8, ui8, ui8, , , , , linear, +R8G8B8_SINT , 24, 1, 1, 1, si8, si8, si8, , , , , linear, +RAW , 0, 0, 0, 0, , , , , , , , , +ASTC_LDR_2D_4X4_U8SRGB , 128, 4, 4, 1, un8, un8, un8, un8, , , , srgb, astc +ASTC_LDR_2D_5X4_U8SRGB , 128, 5, 4, 1, un8, un8, un8, un8, , , , srgb, astc +ASTC_LDR_2D_5X5_U8SRGB , 128, 5, 5, 1, un8, un8, un8, un8, , , , srgb, astc +ASTC_LDR_2D_6X5_U8SRGB , 128, 6, 5, 1, un8, un8, un8, un8, , , , srgb, astc +ASTC_LDR_2D_6X6_U8SRGB , 128, 6, 6, 1, un8, un8, un8, un8, , , , srgb, astc +ASTC_LDR_2D_8X5_U8SRGB , 128, 8, 5, 1, un8, un8, un8, un8, , , , srgb, astc +ASTC_LDR_2D_8X6_U8SRGB , 128, 8, 6, 1, un8, un8, un8, un8, , , , srgb, astc +ASTC_LDR_2D_8X8_U8SRGB , 128, 8, 8, 1, un8, un8, un8, un8, , , , srgb, astc +ASTC_LDR_2D_10X5_U8SRGB , 128, 10, 5, 1, un8, un8, un8, un8, , , , srgb, astc +ASTC_LDR_2D_10X6_U8SRGB , 128, 10, 6, 1, un8, un8, un8, un8, , , , srgb, astc +ASTC_LDR_2D_10X8_U8SRGB , 128, 10, 8, 1, un8, un8, un8, un8, , , , srgb, astc +ASTC_LDR_2D_10X10_U8SRGB , 128, 10, 10, 1, un8, un8, un8, un8, , , , srgb, astc +ASTC_LDR_2D_12X10_U8SRGB , 128, 12, 10, 1, un8, un8, un8, un8, , , , srgb, astc +ASTC_LDR_2D_12X12_U8SRGB , 128, 12, 12, 1, un8, un8, un8, un8, , , , srgb, astc +ASTC_LDR_2D_4X4_FLT16 , 128, 4, 4, 1, sf16, sf16, sf16, sf16, , , , linear, astc +ASTC_LDR_2D_5X4_FLT16 , 128, 5, 4, 1, sf16, sf16, sf16, sf16, , , , linear, astc +ASTC_LDR_2D_5X5_FLT16 , 128, 5, 5, 1, sf16, sf16, sf16, sf16, , , , linear, astc +ASTC_LDR_2D_6X5_FLT16 , 128, 6, 5, 1, sf16, sf16, sf16, sf16, , , , linear, astc +ASTC_LDR_2D_6X6_FLT16 , 128, 6, 6, 1, sf16, sf16, sf16, sf16, , , , linear, astc +ASTC_LDR_2D_8X5_FLT16 , 128, 8, 5, 1, sf16, sf16, sf16, sf16, , , , linear, astc +ASTC_LDR_2D_8X6_FLT16 , 128, 8, 6, 1, sf16, sf16, sf16, sf16, , , , linear, astc +ASTC_LDR_2D_8X8_FLT16 , 128, 8, 8, 1, sf16, sf16, sf16, sf16, , , , linear, astc +ASTC_LDR_2D_10X5_FLT16 , 128, 10, 5, 1, sf16, sf16, sf16, sf16, , , , linear, astc +ASTC_LDR_2D_10X6_FLT16 , 128, 10, 6, 1, sf16, sf16, sf16, sf16, , , , linear, astc +ASTC_LDR_2D_10X8_FLT16 , 128, 10, 8, 1, sf16, sf16, sf16, sf16, , , , linear, astc +ASTC_LDR_2D_10X10_FLT16 , 128, 10, 10, 1, sf16, sf16, sf16, sf16, , , , linear, astc +ASTC_LDR_2D_12X10_FLT16 , 128, 12, 10, 1, sf16, sf16, sf16, sf16, , , , linear, astc +ASTC_LDR_2D_12X12_FLT16 , 128, 12, 12, 1, sf16, sf16, sf16, sf16, , , , linear, astc +HIZ , 128, 8, 4, 1, , , , , , , , , hiz +MCS_2X , 8, 1, 1, 1, , , , , , , , , mcs +MCS_4X , 8, 1, 1, 1, , , , , , , , , mcs +MCS_8X , 32, 1, 1, 1, , , , , , , , , mcs +MCS_16X , 64, 1, 1, 1, , , , , , , , , mcs +GEN7_CCS_32BPP_X , 1, 16, 2, 1, , , , , , , , , ccs +GEN7_CCS_64BPP_X , 1, 8, 2, 1, , , , , , , , , ccs +GEN7_CCS_128BPP_X , 1, 4, 2, 1, , , , , , , , , ccs +GEN7_CCS_32BPP_Y , 1, 8, 4, 1, , , , , , , , , ccs +GEN7_CCS_64BPP_Y , 1, 4, 4, 1, , , , , , , , , ccs +GEN7_CCS_128BPP_Y , 1, 2, 4, 1, , , , , , , , , ccs +GEN9_CCS_32BPP , 2, 8, 4, 1, , , , , , , , , ccs +GEN9_CCS_64BPP , 2, 4, 4, 1, , , , , , , , , ccs +GEN9_CCS_128BPP , 2, 2, 4, 1, , , , , , , , , ccs diff --git a/lib/mesa/src/intel/isl/isl_gen4.c b/lib/mesa/src/intel/isl/isl_gen4.c new file mode 100644 index 000000000..9fed45410 --- /dev/null +++ b/lib/mesa/src/intel/isl/isl_gen4.c @@ -0,0 +1,75 @@ +/* + * Copyright 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#include "isl_gen4.h" +#include "isl_priv.h" + +bool +isl_gen4_choose_msaa_layout(const struct isl_device *dev, + const struct isl_surf_init_info *info, + enum isl_tiling tiling, + enum isl_msaa_layout *msaa_layout) +{ + /* Gen4 and Gen5 do not support MSAA */ + assert(info->samples >= 1); + + *msaa_layout = ISL_MSAA_LAYOUT_NONE; + return true; +} + +void +isl_gen4_choose_image_alignment_el(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + enum isl_tiling tiling, + enum isl_dim_layout dim_layout, + enum isl_msaa_layout msaa_layout, + struct isl_extent3d *image_align_el) +{ + assert(info->samples == 1); + assert(msaa_layout == ISL_MSAA_LAYOUT_NONE); + assert(!isl_tiling_is_std_y(tiling)); + + /* Note that neither the surface's horizontal nor vertical image alignment + * is programmable on gen4 nor gen5. + * + * From the G35 PRM (2008-01), Volume 1 Graphics Core, Section 6.17.3.4 + * Alignment Unit Size: + * + * Note that the compressed formats are padded to a full compression + * cell. + * + * +------------------------+--------+--------+ + * | format | halign | valign | + * +------------------------+--------+--------+ + * | YUV 4:2:2 formats | 4 | 2 | + * | uncompressed formats | 4 | 2 | + * +------------------------+--------+--------+ + */ + + if (isl_format_is_compressed(info->format)) { + *image_align_el = isl_extent3d(1, 1, 1); + return; + } + + *image_align_el = isl_extent3d(4, 2, 1); +} diff --git a/lib/mesa/src/intel/isl/isl_gen4.h b/lib/mesa/src/intel/isl/isl_gen4.h new file mode 100644 index 000000000..dc6102bdf --- /dev/null +++ b/lib/mesa/src/intel/isl/isl_gen4.h @@ -0,0 +1,51 @@ +/* + * Copyright 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#ifndef ISL_GEN4_H +#define ISL_GEN4_H + +#include "isl.h" + +#ifdef __cplusplus +extern "C" { +#endif + +bool +isl_gen4_choose_msaa_layout(const struct isl_device *dev, + const struct isl_surf_init_info *info, + enum isl_tiling tiling, + enum isl_msaa_layout *msaa_layout); + +void +isl_gen4_choose_image_alignment_el(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + enum isl_tiling tiling, + enum isl_dim_layout dim_layout, + enum isl_msaa_layout msaa_layout, + struct isl_extent3d *image_align_el); + +#ifdef __cplusplus +} +#endif + +#endif /* ISL_GEN4_H */ diff --git a/lib/mesa/src/intel/isl/isl_gen6.c b/lib/mesa/src/intel/isl/isl_gen6.c new file mode 100644 index 000000000..b74690319 --- /dev/null +++ b/lib/mesa/src/intel/isl/isl_gen6.c @@ -0,0 +1,147 @@ +/* + * Copyright 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#include "isl_gen6.h" +#include "isl_priv.h" + +bool +isl_gen6_choose_msaa_layout(const struct isl_device *dev, + const struct isl_surf_init_info *info, + enum isl_tiling tiling, + enum isl_msaa_layout *msaa_layout) +{ + assert(ISL_DEV_GEN(dev) == 6); + assert(info->samples >= 1); + + if (info->samples == 1) { + *msaa_layout = ISL_MSAA_LAYOUT_NONE; + return true; + } + + if (!isl_format_supports_multisampling(dev->info, info->format)) + return false; + + /* From the Sandybridge PRM, Volume 4 Part 1 p85, SURFACE_STATE, Number of + * Multisamples: + * + * If this field is any value other than MULTISAMPLECOUNT_1 the + * following restrictions apply: + * + * - the Surface Type must be SURFTYPE_2D + * - [...] + */ + if (info->dim != ISL_SURF_DIM_2D) + return false; + + /* More obvious restrictions */ + if (isl_surf_usage_is_display(info->usage)) + return false; + if (tiling == ISL_TILING_LINEAR) + return false; + if (info->levels > 1) + return false; + + *msaa_layout = ISL_MSAA_LAYOUT_INTERLEAVED; + return true; +} + +void +isl_gen6_choose_image_alignment_el(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + enum isl_tiling tiling, + enum isl_dim_layout dim_layout, + enum isl_msaa_layout msaa_layout, + struct isl_extent3d *image_align_el) +{ + /* Handled by isl_choose_image_alignment_el */ + assert(info->format != ISL_FORMAT_HIZ); + + /* Note that the surface's horizontal image alignment is not programmable + * on Sandybridge. + * + * From the Sandybridge PRM (2011-05), Volume 1, Part 1, Section 7.18.3.4 + * Alignment Unit Size: + * + * Note that the compressed formats are padded to a full compression cell. + * + * +------------------------+--------+--------+ + * | format | halign | valign | + * +------------------------+--------+--------+ + * | YUV 4:2:2 formats | 4 | * | + * | uncompressed formats | 4 | * | + * +------------------------+--------+--------+ + * + * * For these formats, the vertical alignment factor “j” is determined + * as follows: + * - j = 4 for any depth buffer + * - j = 2 for separate stencil buffer + * - j = 4 for any render target surface is multisampled (4x) + * - j = 2 for all other render target surface + * + * From the Sandrybridge PRM (2011-05), Volume 4, Part 1, Section 2.11.2 + * SURFACE_STATE, Surface Vertical Alignment: + * + * - This field must be set to VALIGN_2 if the Surface Format is 96 bits + * per element (BPE). + * + * - Value of 1 [VALIGN_4] is not supported for format YCRCB_NORMAL + * (0x182), YCRCB_SWAPUVY (0x183), YCRCB_SWAPUV (0x18f), YCRCB_SWAPY + * (0x190) + */ + + if (isl_format_is_compressed(info->format)) { + *image_align_el = isl_extent3d(1, 1, 1); + return; + } + + if (isl_format_is_yuv(info->format)) { + *image_align_el = isl_extent3d(4, 2, 1); + return; + } + + if (info->samples > 1) { + *image_align_el = isl_extent3d(4, 4, 1); + return; + } + + if (isl_surf_usage_is_depth_or_stencil(info->usage) && + !ISL_DEV_USE_SEPARATE_STENCIL(dev)) { + /* interleaved depthstencil buffer */ + *image_align_el = isl_extent3d(4, 4, 1); + return; + } + + if (isl_surf_usage_is_depth(info->usage)) { + /* separate depth buffer */ + *image_align_el = isl_extent3d(4, 4, 1); + return; + } + + if (isl_surf_usage_is_stencil(info->usage)) { + /* separate stencil buffer */ + *image_align_el = isl_extent3d(4, 2, 1); + return; + } + + *image_align_el = isl_extent3d(4, 2, 1); +} diff --git a/lib/mesa/src/intel/isl/isl_gen6.h b/lib/mesa/src/intel/isl/isl_gen6.h new file mode 100644 index 000000000..c954026ef --- /dev/null +++ b/lib/mesa/src/intel/isl/isl_gen6.h @@ -0,0 +1,51 @@ +/* + * Copyright 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#ifndef ISL_GEN6_H +#define ISL_GEN6_H + +#include "isl.h" + +#ifdef __cplusplus +extern "C" { +#endif + +bool +isl_gen6_choose_msaa_layout(const struct isl_device *dev, + const struct isl_surf_init_info *info, + enum isl_tiling tiling, + enum isl_msaa_layout *msaa_layout); + +void +isl_gen6_choose_image_alignment_el(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + enum isl_tiling tiling, + enum isl_dim_layout dim_layout, + enum isl_msaa_layout msaa_layout, + struct isl_extent3d *image_align_el); + +#ifdef __cplusplus +} +#endif + +#endif /* ISL_GEN6_H */ diff --git a/lib/mesa/src/intel/isl/isl_gen7.c b/lib/mesa/src/intel/isl/isl_gen7.c new file mode 100644 index 000000000..b6a86d23f --- /dev/null +++ b/lib/mesa/src/intel/isl/isl_gen7.c @@ -0,0 +1,405 @@ +/* + * Copyright 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#include "isl_gen7.h" +#include "isl_priv.h" + +bool +isl_gen7_choose_msaa_layout(const struct isl_device *dev, + const struct isl_surf_init_info *info, + enum isl_tiling tiling, + enum isl_msaa_layout *msaa_layout) +{ + bool require_array = false; + bool require_interleaved = false; + + assert(ISL_DEV_GEN(dev) == 7); + assert(info->samples >= 1); + + if (info->samples == 1) { + *msaa_layout = ISL_MSAA_LAYOUT_NONE; + return true; + } + + if (!isl_format_supports_multisampling(dev->info, info->format)) + return false; + + /* From the Ivybridge PRM, Volume 4 Part 1 p73, SURFACE_STATE, Number of + * Multisamples: + * + * - If this field is any value other than MULTISAMPLECOUNT_1, the + * Surface Type must be SURFTYPE_2D. + * + * - If this field is any value other than MULTISAMPLECOUNT_1, Surface + * Min LOD, Mip Count / LOD, and Resource Min LOD must be set to zero + */ + if (info->dim != ISL_SURF_DIM_2D) + return false; + if (info->levels > 1) + return false; + + /* The Ivyrbridge PRM insists twice that signed integer formats cannot be + * multisampled. + * + * From the Ivybridge PRM, Volume 4 Part 1 p73, SURFACE_STATE, Number of + * Multisamples: + * + * - This field must be set to MULTISAMPLECOUNT_1 for SINT MSRTs when + * all RT channels are not written. + * + * And errata from the Ivybridge PRM, Volume 4 Part 1 p77, + * RENDER_SURFACE_STATE, MCS Enable: + * + * This field must be set to 0 [MULTISAMPLECOUNT_1] for all SINT MSRTs + * when all RT channels are not written. + * + * Note that the above SINT restrictions apply only to *MSRTs* (that is, + * *multisampled* render targets). The restrictions seem to permit an MCS + * if the render target is singlesampled. + */ + if (isl_format_has_sint_channel(info->format)) + return false; + + /* More obvious restrictions */ + if (isl_surf_usage_is_display(info->usage)) + return false; + if (tiling == ISL_TILING_LINEAR) + return false; + + /* From the Ivybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Multisampled + * Suface Storage Format: + * + * +---------------------+----------------------------------------------------------------+ + * | MSFMT_MSS | Multsampled surface was/is rendered as a render target | + * | MSFMT_DEPTH_STENCIL | Multisampled surface was rendered as a depth or stencil buffer | + * +---------------------+----------------------------------------------------------------+ + * + * In the table above, MSFMT_MSS refers to ISL_MSAA_LAYOUT_ARRAY, and + * MSFMT_DEPTH_STENCIL refers to ISL_MSAA_LAYOUT_INTERLEAVED. + */ + if (isl_surf_usage_is_depth_or_stencil(info->usage) || + (info->usage & ISL_SURF_USAGE_HIZ_BIT)) + require_interleaved = true; + + /* From the Ivybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Multisampled + * Suface Storage Format: + * + * If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8, Width + * is >= 8192 (meaning the actual surface width is >= 8193 pixels), this + * field must be set to MSFMT_MSS. + */ + if (info->samples == 8 && info->width == 8192) + require_array = true; + + /* From the Ivybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Multisampled + * Suface Storage Format: + * + * If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8, + * ((Depth+1) * (Height+1)) is > 4,194,304, OR if the surface’s Number + * of Multisamples is MULTISAMPLECOUNT_4, ((Depth+1) * (Height+1)) is + * > 8,388,608, this field must be set to MSFMT_DEPTH_STENCIL. + */ + if ((info->samples == 8 && info->height > 4194304u) || + (info->samples == 4 && info->height > 8388608u)) + require_interleaved = true; + + /* From the Ivybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Multisampled + * Suface Storage Format: + * + * This field must be set to MSFMT_DEPTH_STENCIL if Surface Format is + * one of the following: I24X8_UNORM, L24X8_UNORM, A24X8_UNORM, or + * R24_UNORM_X8_TYPELESS. + */ + if (info->format == ISL_FORMAT_I24X8_UNORM || + info->format == ISL_FORMAT_L24X8_UNORM || + info->format == ISL_FORMAT_A24X8_UNORM || + info->format == ISL_FORMAT_R24_UNORM_X8_TYPELESS) + require_interleaved = true; + + if (require_array && require_interleaved) + return false; + + if (require_interleaved) { + *msaa_layout = ISL_MSAA_LAYOUT_INTERLEAVED; + return true; + } + + /* Default to the array layout because it permits multisample + * compression. + */ + *msaa_layout = ISL_MSAA_LAYOUT_ARRAY; + return true; +} + +static bool +gen7_format_needs_valign2(const struct isl_device *dev, + enum isl_format format) +{ + assert(ISL_DEV_GEN(dev) == 7); + + /* From the Ivybridge PRM (2012-05-31), Volume 4, Part 1, Section 2.12.1, + * RENDER_SURFACE_STATE Surface Vertical Alignment: + * + * - Value of 1 [VALIGN_4] is not supported for format YCRCB_NORMAL + * (0x182), YCRCB_SWAPUVY (0x183), YCRCB_SWAPUV (0x18f), YCRCB_SWAPY + * (0x190) + * + * - VALIGN_4 is not supported for surface format R32G32B32_FLOAT. + */ + return isl_format_is_yuv(format) || + format == ISL_FORMAT_R32G32B32_FLOAT; +} + +/** + * @brief Filter out tiling flags that are incompatible with the surface. + * + * The resultant outgoing @a flags is a subset of the incoming @a flags. The + * outgoing flags may be empty (0x0) if the incoming flags were too + * restrictive. + * + * For example, if the surface will be used for a display + * (ISL_SURF_USAGE_DISPLAY_BIT), then this function filters out all tiling + * flags except ISL_TILING_X_BIT and ISL_TILING_LINEAR_BIT. + */ +void +isl_gen6_filter_tiling(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + isl_tiling_flags_t *flags) +{ + /* IVB+ requires separate stencil */ + assert(ISL_DEV_USE_SEPARATE_STENCIL(dev)); + + /* Clear flags unsupported on this hardware */ + if (ISL_DEV_GEN(dev) < 9) { + *flags &= ~ISL_TILING_Yf_BIT; + *flags &= ~ISL_TILING_Ys_BIT; + } + + /* And... clear the Yf and Ys bits anyway because Anvil doesn't support + * them yet. + */ + *flags &= ~ISL_TILING_Yf_BIT; /* FINISHME[SKL]: Support Yf */ + *flags &= ~ISL_TILING_Ys_BIT; /* FINISHME[SKL]: Support Ys */ + + if (isl_surf_usage_is_depth(info->usage)) { + /* Depth requires Y. */ + *flags &= ISL_TILING_ANY_Y_MASK; + } + + /* Separate stencil requires W tiling, and W tiling requires separate + * stencil. + */ + if (isl_surf_usage_is_stencil(info->usage)) { + *flags &= ISL_TILING_W_BIT; + } else { + *flags &= ~ISL_TILING_W_BIT; + } + + /* MCS buffers are always Y-tiled */ + if (isl_format_get_layout(info->format)->txc == ISL_TXC_MCS) + *flags &= ISL_TILING_Y0_BIT; + + if (info->usage & (ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT | + ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT | + ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT)) { + assert(*flags & ISL_SURF_USAGE_DISPLAY_BIT); + isl_finishme("%s:%s: handle rotated display surfaces", + __FILE__, __func__); + } + + if (info->usage & (ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT | + ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT)) { + assert(*flags & ISL_SURF_USAGE_DISPLAY_BIT); + isl_finishme("%s:%s: handle flipped display surfaces", + __FILE__, __func__); + } + + if (info->usage & ISL_SURF_USAGE_DISPLAY_BIT) { + /* Before Skylake, the display engine does not accept Y */ + /* FINISHME[SKL]: Y tiling for display surfaces */ + *flags &= (ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT); + } + + if (info->samples > 1) { + /* From the Sandybridge PRM, Volume 4 Part 1, SURFACE_STATE Tiled + * Surface: + * + * For multisample render targets, this field must be 1 (true). MSRTs + * can only be tiled. + * + * From the Broadwell PRM >> Volume2d: Command Structures >> + * RENDER_SURFACE_STATE Tile Mode: + * + * If Number of Multisamples is not MULTISAMPLECOUNT_1, this field + * must be YMAJOR. + * + * As usual, though, stencil is special and requires W-tiling. + */ + *flags &= (ISL_TILING_ANY_Y_MASK | ISL_TILING_W_BIT); + } + + /* workaround */ + if (ISL_DEV_GEN(dev) == 7 && + gen7_format_needs_valign2(dev, info->format) && + (info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) && + info->samples == 1) { + /* Y tiling is illegal. From the Ivybridge PRM, Vol4 Part1 2.12.2.1, + * SURFACE_STATE Surface Vertical Alignment: + * + * This field must be set to VALIGN_4 for all tiled Y Render Target + * surfaces. + */ + *flags &= ~ISL_TILING_Y0_BIT; + } + + /* From the Sandybridge PRM, Volume 1, Part 2, page 32: + * + * "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either + * TileX or Linear." + * + * This is necessary all the way back to 965, but is permitted on Gen7+. + */ + if (ISL_DEV_GEN(dev) < 7 && isl_format_get_layout(info->format)->bpb >= 128) + *flags &= ~ISL_TILING_Y0_BIT; +} + +/** + * Choose horizontal subimage alignment, in units of surface elements. + */ +static uint32_t +gen7_choose_halign_el(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info) +{ + if (isl_format_is_compressed(info->format)) + return 1; + + /* From the Ivybridge PRM (2012-05-31), Volume 4, Part 1, Section 2.12.1, + * RENDER_SURFACE_STATE Surface Hoizontal Alignment: + * + * - This field is intended to be set to HALIGN_8 only if the surface + * was rendered as a depth buffer with Z16 format or a stencil buffer, + * since these surfaces support only alignment of 8. Use of HALIGN_8 + * for other surfaces is supported, but uses more memory. + */ + if (isl_surf_info_is_z16(info) || + isl_surf_usage_is_stencil(info->usage)) + return 8; + + return 4; +} + +/** + * Choose vertical subimage alignment, in units of surface elements. + */ +static uint32_t +gen7_choose_valign_el(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + enum isl_tiling tiling) +{ + MAYBE_UNUSED bool require_valign2 = false; + bool require_valign4 = false; + + if (isl_format_is_compressed(info->format)) + return 1; + + if (gen7_format_needs_valign2(dev, info->format)) + require_valign2 = true; + + /* From the Ivybridge PRM, Volume 4, Part 1, Section 2.12.1: + * RENDER_SURFACE_STATE Surface Vertical Alignment: + * + * - This field is intended to be set to VALIGN_4 if the surface was + * rendered as a depth buffer, for a multisampled (4x) render target, + * or for a multisampled (8x) render target, since these surfaces + * support only alignment of 4. Use of VALIGN_4 for other surfaces is + * supported, but uses more memory. This field must be set to + * VALIGN_4 for all tiled Y Render Target surfaces. + * + */ + if (isl_surf_usage_is_depth(info->usage) || + info->samples > 1 || + ((info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) && + tiling == ISL_TILING_Y0)) { + require_valign4 = true; + } + + if (isl_surf_usage_is_stencil(info->usage)) { + /* The Ivybridge PRM states that the stencil buffer's vertical alignment + * is 8 [Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.4 Alignment + * Unit Size]. However, valign=8 is outside the set of valid values of + * RENDER_SURFACE_STATE.SurfaceVerticalAlignment, which is VALIGN_2 + * (0x0) and VALIGN_4 (0x1). + * + * The PRM is generally confused about the width, height, and alignment + * of the stencil buffer; and this confusion appears elsewhere. For + * example, the following PRM text effectively converts the stencil + * buffer's 8-pixel alignment to a 4-pixel alignment [Ivybridge PRM, + * Volume 1, Part 1, Section + * 6.18.4.2 Base Address and LOD Calculation]: + * + * For separate stencil buffer, the width must be mutiplied by 2 and + * height divided by 2 as follows: + * + * w_L = 2*i*ceil(W_L/i) + * h_L = 1/2*j*ceil(H_L/j) + * + * The root of the confusion is that, in W tiling, each pair of rows is + * interleaved into one. + * + * FINISHME(chadv): Decide to set valign=4 or valign=8 after isl's API + * is more polished. + */ + require_valign4 = true; + } + + assert(!require_valign2 || !require_valign4); + + if (require_valign4) + return 4; + + /* Prefer VALIGN_2 because it conserves memory. */ + return 2; +} + +void +isl_gen7_choose_image_alignment_el(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + enum isl_tiling tiling, + enum isl_dim_layout dim_layout, + enum isl_msaa_layout msaa_layout, + struct isl_extent3d *image_align_el) +{ + assert(ISL_DEV_GEN(dev) == 7); + + /* Handled by isl_choose_image_alignment_el */ + assert(info->format != ISL_FORMAT_HIZ); + + /* IVB+ does not support combined depthstencil. */ + assert(!isl_surf_usage_is_depth_and_stencil(info->usage)); + + *image_align_el = (struct isl_extent3d) { + .w = gen7_choose_halign_el(dev, info), + .h = gen7_choose_valign_el(dev, info, tiling), + .d = 1, + }; +} diff --git a/lib/mesa/src/intel/isl/isl_gen7.h b/lib/mesa/src/intel/isl/isl_gen7.h new file mode 100644 index 000000000..f1b7252ba --- /dev/null +++ b/lib/mesa/src/intel/isl/isl_gen7.h @@ -0,0 +1,56 @@ +/* + * Copyright 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#ifndef ISL_GEN7_H +#define ISL_GEN7_H + +#include "isl.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void +isl_gen6_filter_tiling(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + isl_tiling_flags_t *flags); + +bool +isl_gen7_choose_msaa_layout(const struct isl_device *dev, + const struct isl_surf_init_info *info, + enum isl_tiling tiling, + enum isl_msaa_layout *msaa_layout); + +void +isl_gen7_choose_image_alignment_el(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + enum isl_tiling tiling, + enum isl_dim_layout dim_layout, + enum isl_msaa_layout msaa_layout, + struct isl_extent3d *image_align_el); + +#ifdef __cplusplus +} +#endif + +#endif /* ISL_GEN7_H */ diff --git a/lib/mesa/src/intel/isl/isl_gen8.c b/lib/mesa/src/intel/isl/isl_gen8.c new file mode 100644 index 000000000..81c69dc13 --- /dev/null +++ b/lib/mesa/src/intel/isl/isl_gen8.c @@ -0,0 +1,234 @@ +/* + * Copyright 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#include "isl_gen8.h" +#include "isl_priv.h" + +bool +isl_gen8_choose_msaa_layout(const struct isl_device *dev, + const struct isl_surf_init_info *info, + enum isl_tiling tiling, + enum isl_msaa_layout *msaa_layout) +{ + bool require_array = false; + bool require_interleaved = false; + + assert(info->samples >= 1); + + if (info->samples == 1) { + *msaa_layout = ISL_MSAA_LAYOUT_NONE; + return true; + } + + /* From the Broadwell PRM >> Volume2d: Command Structures >> + * RENDER_SURFACE_STATE Multisampled Surface Storage Format: + * + * All multisampled render target surfaces must have this field set to + * MSFMT_MSS + */ + if (info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) + require_array = true; + + /* From the Broadwell PRM >> Volume2d: Command Structures >> + * RENDER_SURFACE_STATE Number of Multisamples: + * + * - If this field is any value other than MULTISAMPLECOUNT_1, the + * Surface Type must be SURFTYPE_2D This field must be set to + * MULTISAMPLECOUNT_1 unless the surface is a Sampling Engine surface + * or Render Target surface. + * + * - If this field is any value other than MULTISAMPLECOUNT_1, Surface + * Min LOD, Mip Count / LOD, and Resource Min LOD must be set to zero. + */ + if (info->dim != ISL_SURF_DIM_2D) + return false; + if (info->levels > 1) + return false; + + /* More obvious restrictions */ + if (isl_surf_usage_is_display(info->usage)) + return false; + if (!isl_format_supports_multisampling(dev->info, info->format)) + return false; + + if (isl_surf_usage_is_depth_or_stencil(info->usage) || + (info->usage & ISL_SURF_USAGE_HIZ_BIT)) + require_interleaved = true; + + if (require_array && require_interleaved) + return false; + + if (require_interleaved) { + *msaa_layout = ISL_MSAA_LAYOUT_INTERLEAVED; + return true; + } + + *msaa_layout = ISL_MSAA_LAYOUT_ARRAY; + return true; +} + +/** + * Choose horizontal subimage alignment, in units of surface elements. + */ +static uint32_t +gen8_choose_halign_el(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info) +{ + if (isl_format_is_compressed(info->format)) + return 1; + + /* From the Broadwell PRM, Volume 2d "Command Reference: Structures", + * RENDER_SURFACE_STATE Surface Horizontal Alignment, p326: + * + * - This field is intended to be set to HALIGN_8 only if the surface + * was rendered as a depth buffer with Z16 format or a stencil buffer. + * In this case it must be set to HALIGN_8 since these surfaces + * support only alignment of 8. [...] + */ + if (isl_surf_info_is_z16(info)) + return 8; + if (isl_surf_usage_is_stencil(info->usage)) + return 8; + + /* From the Broadwell PRM, Volume 2d "Command Reference: Structures", + * RENDER_SURFACE_STATE Surface Horizontal Alignment, p326: + * + * [...] For Z32 formats it must be set to HALIGN_4. + */ + if (isl_surf_usage_is_depth(info->usage)) + return 4; + + if (!(info->usage & ISL_SURF_USAGE_DISABLE_AUX_BIT)) { + /* From the Broadwell PRM, Volume 2d "Command Reference: Structures", + * RENDER_SURFACE_STATE Surface Horizontal Alignment, p326: + * + * - When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, + * HALIGN 16 must be used. + * + * This case handles color surfaces that may own an auxiliary MCS, CCS_D, + * or CCS_E. Depth buffers, including those that own an auxiliary HiZ + * surface, are handled above and do not require HALIGN_16. + */ + assert(!isl_surf_usage_is_depth(info->usage)); + return 16; + } + + /* XXX(chadv): I believe the hardware requires each image to be + * cache-aligned. If that's true, then defaulting to halign=4 is wrong for + * many formats. Depending on the format's block size, we may need to + * increase halign to 8. + */ + return 4; +} + +/** + * Choose vertical subimage alignment, in units of surface elements. + */ +static uint32_t +gen8_choose_valign_el(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info) +{ + /* From the Broadwell PRM > Volume 2d: Command Reference: Structures + * > RENDER_SURFACE_STATE Surface Vertical Alignment (p325): + * + * - For Sampling Engine and Render Target Surfaces: This field + * specifies the vertical alignment requirement in elements for the + * surface. [...] An element is defined as a pixel in uncompresed + * surface formats, and as a compression block in compressed surface + * formats. For MSFMT_DEPTH_STENCIL type multisampled surfaces, an + * element is a sample. + * + * - This field is intended to be set to VALIGN_4 if the surface was + * rendered as a depth buffer, for a multisampled (4x) render target, + * or for a multisampled (8x) render target, since these surfaces + * support only alignment of 4. Use of VALIGN_4 for other surfaces is + * supported, but increases memory usage. + * + * - This field is intended to be set to VALIGN_8 only if the surface + * was rendered as a stencil buffer, since stencil buffer surfaces + * support only alignment of 8. If set to VALIGN_8, Surface Format + * must be R8_UINT. + */ + + if (isl_format_is_compressed(info->format)) + return 1; + + if (isl_surf_usage_is_stencil(info->usage)) + return 8; + + return 4; +} + +void +isl_gen8_choose_image_alignment_el(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + enum isl_tiling tiling, + enum isl_dim_layout dim_layout, + enum isl_msaa_layout msaa_layout, + struct isl_extent3d *image_align_el) +{ + /* Handled by isl_choose_image_alignment_el */ + assert(info->format != ISL_FORMAT_HIZ); + + assert(!isl_tiling_is_std_y(tiling)); + + const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); + if (fmtl->txc == ISL_TXC_CCS) { + /* + * Broadwell PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 676): + * + * "Mip-mapped and arrayed surfaces are supported with MCS buffer + * layout with these alignments in the RT space: Horizontal + * Alignment = 256 and Vertical Alignment = 128. + */ + *image_align_el = isl_extent3d(256 / fmtl->bw, 128 / fmtl->bh, 1); + return; + } + + /* The below text from the Broadwell PRM provides some insight into the + * hardware's requirements for LOD alignment. From the Broadwell PRM >> + * Volume 5: Memory Views >> Surface Layout >> 2D Surfaces: + * + * These [2D surfaces] must adhere to the following memory organization + * rules: + * + * - For non-compressed texture formats, each mipmap must start on an + * even row within the monolithic rectangular area. For + * 1-texel-high mipmaps, this may require a row of padding below + * the previous mipmap. This restriction does not apply to any + * compressed texture formats; each subsequent (lower-res) + * compressed mipmap is positioned directly below the previous + * mipmap. + * + * - Vertical alignment restrictions vary with memory tiling type: + * 1 DWord for linear, 16-byte (DQWord) for tiled. (Note that tiled + * mipmaps are not required to start at the left edge of a tile + * row.) + */ + + *image_align_el = (struct isl_extent3d) { + .w = gen8_choose_halign_el(dev, info), + .h = gen8_choose_valign_el(dev, info), + .d = 1, + }; +} diff --git a/lib/mesa/src/intel/isl/isl_gen8.h b/lib/mesa/src/intel/isl/isl_gen8.h new file mode 100644 index 000000000..f5eb6a295 --- /dev/null +++ b/lib/mesa/src/intel/isl/isl_gen8.h @@ -0,0 +1,51 @@ +/* + * Copyright 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#ifndef ISL_GEN8_H +#define ISL_GEN8_H + +#include "isl.h" + +#ifdef __cplusplus +extern "C" { +#endif + +bool +isl_gen8_choose_msaa_layout(const struct isl_device *dev, + const struct isl_surf_init_info *info, + enum isl_tiling tiling, + enum isl_msaa_layout *msaa_layout); + +void +isl_gen8_choose_image_alignment_el(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + enum isl_tiling tiling, + enum isl_dim_layout dim_layout, + enum isl_msaa_layout msaa_layout, + struct isl_extent3d *image_align_el); + +#ifdef __cplusplus +} +#endif + +#endif /* ISL_GEN8_H */ diff --git a/lib/mesa/src/intel/isl/isl_gen9.c b/lib/mesa/src/intel/isl/isl_gen9.c new file mode 100644 index 000000000..e5d0f9540 --- /dev/null +++ b/lib/mesa/src/intel/isl/isl_gen9.c @@ -0,0 +1,201 @@ +/* + * Copyright 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#include "isl_gen8.h" +#include "isl_gen9.h" +#include "isl_priv.h" + +/** + * Calculate the surface's subimage alignment, in units of surface samples, + * for the standard tiling formats Yf and Ys. + */ +static void +gen9_calc_std_image_alignment_sa(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + enum isl_tiling tiling, + enum isl_msaa_layout msaa_layout, + struct isl_extent3d *align_sa) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); + + assert(isl_tiling_is_std_y(tiling)); + + const uint32_t bpb = fmtl->bpb; + const uint32_t is_Ys = tiling == ISL_TILING_Ys; + + switch (info->dim) { + case ISL_SURF_DIM_1D: + /* See the Skylake BSpec > Memory Views > Common Surface Formats > Surface + * Layout and Tiling > 1D Surfaces > 1D Alignment Requirements. + */ + *align_sa = (struct isl_extent3d) { + .w = 1 << (12 - (ffs(bpb) - 4) + (4 * is_Ys)), + .h = 1, + .d = 1, + }; + return; + case ISL_SURF_DIM_2D: + /* See the Skylake BSpec > Memory Views > Common Surface Formats > + * Surface Layout and Tiling > 2D Surfaces > 2D/CUBE Alignment + * Requirements. + */ + *align_sa = (struct isl_extent3d) { + .w = 1 << (6 - ((ffs(bpb) - 4) / 2) + (4 * is_Ys)), + .h = 1 << (6 - ((ffs(bpb) - 3) / 2) + (4 * is_Ys)), + .d = 1, + }; + + if (is_Ys) { + /* FINISHME(chadv): I don't trust this code. Untested. */ + isl_finishme("%s:%s: [SKL+] multisample TileYs", __FILE__, __func__); + + switch (msaa_layout) { + case ISL_MSAA_LAYOUT_NONE: + case ISL_MSAA_LAYOUT_INTERLEAVED: + break; + case ISL_MSAA_LAYOUT_ARRAY: + align_sa->w >>= (ffs(info->samples) - 0) / 2; + align_sa->h >>= (ffs(info->samples) - 1) / 2; + break; + } + } + return; + + case ISL_SURF_DIM_3D: + /* See the Skylake BSpec > Memory Views > Common Surface Formats > Surface + * Layout and Tiling > 1D Surfaces > 1D Alignment Requirements. + */ + *align_sa = (struct isl_extent3d) { + .w = 1 << (4 - ((ffs(bpb) - 2) / 3) + (4 * is_Ys)), + .h = 1 << (4 - ((ffs(bpb) - 4) / 3) + (2 * is_Ys)), + .d = 1 << (4 - ((ffs(bpb) - 3) / 3) + (2 * is_Ys)), + }; + return; + } + + unreachable("bad isl_surface_type"); +} + +void +isl_gen9_choose_image_alignment_el(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + enum isl_tiling tiling, + enum isl_dim_layout dim_layout, + enum isl_msaa_layout msaa_layout, + struct isl_extent3d *image_align_el) +{ + /* Handled by isl_choose_image_alignment_el */ + assert(info->format != ISL_FORMAT_HIZ); + + const struct isl_format_layout *fmtl = isl_format_get_layout(info->format); + if (fmtl->txc == ISL_TXC_CCS) { + /* Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)" (p. 632): + * + * "Mip-mapped and arrayed surfaces are supported with MCS buffer + * layout with these alignments in the RT space: Horizontal + * Alignment = 128 and Vertical Alignment = 64." + */ + *image_align_el = isl_extent3d(128 / fmtl->bw, 64 / fmtl->bh, 1); + return; + } + + /* This BSpec text provides some insight into the hardware's alignment + * requirements [Skylake BSpec > Memory Views > Common Surface Formats > + * Surface Layout and Tiling > 2D Surfaces]: + * + * An LOD must be aligned to a cache-line except for some special cases + * related to Planar YUV surfaces. In general, the cache-alignment + * restriction implies there is a minimum height for an LOD of 4 texels. + * So, LODs which are smaller than 4 high are padded. + * + * From the Skylake BSpec, RENDER_SURFACE_STATE Surface Vertical Alignment: + * + * - For Sampling Engine and Render Target Surfaces: This field + * specifies the vertical alignment requirement in elements for the + * surface. [...] An element is defined as a pixel in uncompresed + * surface formats, and as a compression block in compressed surface + * formats. For MSFMT_DEPTH_STENCIL type multisampled surfaces, an + * element is a sample. + * + * - This field is used for 2D, CUBE, and 3D surface alignment when Tiled + * Resource Mode is TRMODE_NONE (Tiled Resource Mode is disabled). + * This field is ignored for 1D surfaces and also when Tiled Resource + * Mode is not TRMODE_NONE (e.g. Tiled Resource Mode is enabled). + * + * See the appropriate Alignment table in the "Surface Layout and + * Tiling" section under Common Surface Formats for the table of + * alignment values for Tiled Resrouces. + * + * - For uncompressed surfaces, the units of "j" are rows of pixels on + * the physical surface. For compressed texture formats, the units of + * "j" are in compression blocks, thus each increment in "j" is equal + * to h pixels, where h is the height of the compression block in + * pixels. + * + * - Valid Values: VALIGN_4, VALIGN_8, VALIGN_16 + * + * From the Skylake BSpec, RENDER_SURFACE_STATE Surface Horizontal + * Alignment: + * + * - For uncompressed surfaces, the units of "i" are pixels on the + * physical surface. For compressed texture formats, the units of "i" + * are in compression blocks, thus each increment in "i" is equal to + * w pixels, where w is the width of the compression block in pixels. + * + * - Valid Values: HALIGN_4, HALIGN_8, HALIGN_16 + */ + + if (isl_tiling_is_std_y(tiling)) { + struct isl_extent3d image_align_sa; + gen9_calc_std_image_alignment_sa(dev, info, tiling, msaa_layout, + &image_align_sa); + + *image_align_el = isl_extent3d_sa_to_el(info->format, image_align_sa); + return; + } + + if (dim_layout == ISL_DIM_LAYOUT_GEN9_1D) { + /* See the Skylake BSpec > Memory Views > Common Surface Formats > Surface + * Layout and Tiling > 1D Surfaces > 1D Alignment Requirements. + */ + *image_align_el = isl_extent3d(64, 1, 1); + return; + } + + if (isl_format_is_compressed(info->format)) { + /* On Gen9, the meaning of RENDER_SURFACE_STATE's + * SurfaceHorizontalAlignment and SurfaceVerticalAlignment changed for + * compressed formats. They now indicate a multiple of the compression + * block. For example, if the compression mode is ETC2 then HALIGN_4 + * indicates a horizontal alignment of 16 pixels. + * + * To avoid wasting memory, choose the smallest alignment possible: + * HALIGN_4 and VALIGN_4. + */ + *image_align_el = isl_extent3d(4, 4, 1); + return; + } + + isl_gen8_choose_image_alignment_el(dev, info, tiling, dim_layout, + msaa_layout, image_align_el); +} diff --git a/lib/mesa/src/intel/isl/isl_gen9.h b/lib/mesa/src/intel/isl/isl_gen9.h new file mode 100644 index 000000000..26d716f8f --- /dev/null +++ b/lib/mesa/src/intel/isl/isl_gen9.h @@ -0,0 +1,45 @@ +/* + * Copyright 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#ifndef ISL_GEN9_H +#define ISL_GEN9_H + +#include "isl.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void +isl_gen9_choose_image_alignment_el(const struct isl_device *dev, + const struct isl_surf_init_info *restrict info, + enum isl_tiling tiling, + enum isl_dim_layout dim_layout, + enum isl_msaa_layout msaa_layout, + struct isl_extent3d *image_align_el); + +#ifdef __cplusplus +} +#endif + +#endif /* ISL_GEN9_H */ diff --git a/lib/mesa/src/intel/isl/isl_priv.h b/lib/mesa/src/intel/isl/isl_priv.h new file mode 100644 index 000000000..dc3975d3c --- /dev/null +++ b/lib/mesa/src/intel/isl/isl_priv.h @@ -0,0 +1,202 @@ +/* + * Copyright 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#ifndef ISL_PRIV_H +#define ISL_PRIV_H + +#include <assert.h> +#include <strings.h> + +#include "common/gen_device_info.h" +#include "util/macros.h" + +#include "isl.h" + +#define isl_finishme(format, ...) \ + __isl_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__) + +void PRINTFLIKE(3, 4) UNUSED +__isl_finishme(const char *file, int line, const char *fmt, ...); + +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#define MAX(a, b) ((a) > (b) ? (a) : (b)) + +static inline bool +isl_is_pow2(uintmax_t n) +{ + return !(n & (n - 1)); +} + +/** + * Alignment must be a power of 2. + */ +static inline bool +isl_is_aligned(uintmax_t n, uintmax_t a) +{ + assert(isl_is_pow2(a)); + return (n & (a - 1)) == 0; +} + +/** + * Alignment must be a power of 2. + */ +static inline uintmax_t +isl_align(uintmax_t n, uintmax_t a) +{ + assert(a != 0 && isl_is_pow2(a)); + return (n + a - 1) & ~(a - 1); +} + +static inline uintmax_t +isl_align_npot(uintmax_t n, uintmax_t a) +{ + assert(a > 0); + return ((n + a - 1) / a) * a; +} + +/** + * Alignment must be a power of 2. + */ +static inline uintmax_t +isl_align_div(uintmax_t n, uintmax_t a) +{ + return isl_align(n, a) / a; +} + +static inline uintmax_t +isl_align_div_npot(uintmax_t n, uintmax_t a) +{ + return isl_align_npot(n, a) / a; +} + +/** + * Log base 2, rounding towards zero. + */ +static inline uint32_t +isl_log2u(uint32_t n) +{ + assert(n != 0); + return 31 - __builtin_clz(n); +} + +static inline uint32_t +isl_round_up_to_power_of_two(uint32_t value) +{ + if (value <= 1) + return value; + + return 1 << (32 - __builtin_clz(value - 1)); +} + +static inline uint32_t +isl_minify(uint32_t n, uint32_t levels) +{ + if (unlikely(n == 0)) + return 0; + else + return MAX(n >> levels, 1); +} + +static inline struct isl_extent3d +isl_extent3d_sa_to_el(enum isl_format fmt, struct isl_extent3d extent_sa) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(fmt); + + assert(extent_sa.w % fmtl->bw == 0); + assert(extent_sa.h % fmtl->bh == 0); + assert(extent_sa.d % fmtl->bd == 0); + + return (struct isl_extent3d) { + .w = extent_sa.w / fmtl->bw, + .h = extent_sa.h / fmtl->bh, + .d = extent_sa.d / fmtl->bd, + }; +} + +static inline struct isl_extent3d +isl_extent3d_el_to_sa(enum isl_format fmt, struct isl_extent3d extent_el) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(fmt); + + return (struct isl_extent3d) { + .w = extent_el.w * fmtl->bw, + .h = extent_el.h * fmtl->bh, + .d = extent_el.d * fmtl->bd, + }; +} + +void +isl_gen4_surf_fill_state_s(const struct isl_device *dev, void *state, + const struct isl_surf_fill_state_info *restrict info); + +void +isl_gen5_surf_fill_state_s(const struct isl_device *dev, void *state, + const struct isl_surf_fill_state_info *restrict info); + +void +isl_gen6_surf_fill_state_s(const struct isl_device *dev, void *state, + const struct isl_surf_fill_state_info *restrict info); + +void +isl_gen7_surf_fill_state_s(const struct isl_device *dev, void *state, + const struct isl_surf_fill_state_info *restrict info); + +void +isl_gen75_surf_fill_state_s(const struct isl_device *dev, void *state, + const struct isl_surf_fill_state_info *restrict info); +void +isl_gen8_surf_fill_state_s(const struct isl_device *dev, void *state, + const struct isl_surf_fill_state_info *restrict info); +void +isl_gen9_surf_fill_state_s(const struct isl_device *dev, void *state, + const struct isl_surf_fill_state_info *restrict info); + +void +isl_gen4_buffer_fill_state_s(void *state, + const struct isl_buffer_fill_state_info *restrict info); + +void +isl_gen5_buffer_fill_state_s(void *state, + const struct isl_buffer_fill_state_info *restrict info); + +void +isl_gen6_buffer_fill_state_s(void *state, + const struct isl_buffer_fill_state_info *restrict info); + +void +isl_gen7_buffer_fill_state_s(void *state, + const struct isl_buffer_fill_state_info *restrict info); + +void +isl_gen75_buffer_fill_state_s(void *state, + const struct isl_buffer_fill_state_info *restrict info); + +void +isl_gen8_buffer_fill_state_s(void *state, + const struct isl_buffer_fill_state_info *restrict info); + +void +isl_gen9_buffer_fill_state_s(void *state, + const struct isl_buffer_fill_state_info *restrict info); + +#endif /* ISL_PRIV_H */ diff --git a/lib/mesa/src/intel/isl/isl_storage_image.c b/lib/mesa/src/intel/isl/isl_storage_image.c new file mode 100644 index 000000000..ffd03e4ad --- /dev/null +++ b/lib/mesa/src/intel/isl/isl_storage_image.c @@ -0,0 +1,306 @@ +/* + * Copyright 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#include "isl_priv.h" +#include "brw_compiler.h" + +bool +isl_is_storage_image_format(enum isl_format format) +{ + /* XXX: Maybe we should put this in the CSV? */ + + switch (format) { + case ISL_FORMAT_R32G32B32A32_UINT: + case ISL_FORMAT_R32G32B32A32_SINT: + case ISL_FORMAT_R32G32B32A32_FLOAT: + case ISL_FORMAT_R32_UINT: + case ISL_FORMAT_R32_SINT: + case ISL_FORMAT_R32_FLOAT: + case ISL_FORMAT_R16G16B16A16_UINT: + case ISL_FORMAT_R16G16B16A16_SINT: + case ISL_FORMAT_R16G16B16A16_FLOAT: + case ISL_FORMAT_R32G32_UINT: + case ISL_FORMAT_R32G32_SINT: + case ISL_FORMAT_R32G32_FLOAT: + case ISL_FORMAT_R8G8B8A8_UINT: + case ISL_FORMAT_R8G8B8A8_SINT: + case ISL_FORMAT_R16G16_UINT: + case ISL_FORMAT_R16G16_SINT: + case ISL_FORMAT_R16G16_FLOAT: + case ISL_FORMAT_R8G8_UINT: + case ISL_FORMAT_R8G8_SINT: + case ISL_FORMAT_R16_UINT: + case ISL_FORMAT_R16_FLOAT: + case ISL_FORMAT_R16_SINT: + case ISL_FORMAT_R8_UINT: + case ISL_FORMAT_R8_SINT: + case ISL_FORMAT_R10G10B10A2_UINT: + case ISL_FORMAT_R10G10B10A2_UNORM: + case ISL_FORMAT_R11G11B10_FLOAT: + case ISL_FORMAT_R16G16B16A16_UNORM: + case ISL_FORMAT_R16G16B16A16_SNORM: + case ISL_FORMAT_R8G8B8A8_UNORM: + case ISL_FORMAT_R8G8B8A8_SNORM: + case ISL_FORMAT_R16G16_UNORM: + case ISL_FORMAT_R16G16_SNORM: + case ISL_FORMAT_R8G8_UNORM: + case ISL_FORMAT_R8G8_SNORM: + case ISL_FORMAT_R16_UNORM: + case ISL_FORMAT_R16_SNORM: + case ISL_FORMAT_R8_UNORM: + case ISL_FORMAT_R8_SNORM: + return true; + default: + return false; + } +} + +enum isl_format +isl_lower_storage_image_format(const struct gen_device_info *devinfo, + enum isl_format format) +{ + switch (format) { + /* These are never lowered. Up to BDW we'll have to fall back to untyped + * surface access for 128bpp formats. + */ + case ISL_FORMAT_R32G32B32A32_UINT: + case ISL_FORMAT_R32G32B32A32_SINT: + case ISL_FORMAT_R32G32B32A32_FLOAT: + case ISL_FORMAT_R32_UINT: + case ISL_FORMAT_R32_SINT: + case ISL_FORMAT_R32_FLOAT: + return format; + + /* From HSW to BDW the only 64bpp format supported for typed access is + * RGBA_UINT16. IVB falls back to untyped. + */ + case ISL_FORMAT_R16G16B16A16_UINT: + case ISL_FORMAT_R16G16B16A16_SINT: + case ISL_FORMAT_R16G16B16A16_FLOAT: + case ISL_FORMAT_R32G32_UINT: + case ISL_FORMAT_R32G32_SINT: + case ISL_FORMAT_R32G32_FLOAT: + return (devinfo->gen >= 9 ? format : + devinfo->gen >= 8 || devinfo->is_haswell ? + ISL_FORMAT_R16G16B16A16_UINT : + ISL_FORMAT_R32G32_UINT); + + /* Up to BDW no SINT or FLOAT formats of less than 32 bits per component + * are supported. IVB doesn't support formats with more than one component + * for typed access. For 8 and 16 bpp formats IVB relies on the + * undocumented behavior that typed reads from R_UINT8 and R_UINT16 + * surfaces actually do a 32-bit misaligned read. The alternative would be + * to use two surface state entries with different formats for each image, + * one for reading (using R_UINT32) and another one for writing (using + * R_UINT8 or R_UINT16), but that would complicate the shaders we generate + * even more. + */ + case ISL_FORMAT_R8G8B8A8_UINT: + case ISL_FORMAT_R8G8B8A8_SINT: + return (devinfo->gen >= 9 ? format : + devinfo->gen >= 8 || devinfo->is_haswell ? + ISL_FORMAT_R8G8B8A8_UINT : ISL_FORMAT_R32_UINT); + + case ISL_FORMAT_R16G16_UINT: + case ISL_FORMAT_R16G16_SINT: + case ISL_FORMAT_R16G16_FLOAT: + return (devinfo->gen >= 9 ? format : + devinfo->gen >= 8 || devinfo->is_haswell ? + ISL_FORMAT_R16G16_UINT : ISL_FORMAT_R32_UINT); + + case ISL_FORMAT_R8G8_UINT: + case ISL_FORMAT_R8G8_SINT: + return (devinfo->gen >= 9 ? format : + devinfo->gen >= 8 || devinfo->is_haswell ? + ISL_FORMAT_R8G8_UINT : ISL_FORMAT_R16_UINT); + + case ISL_FORMAT_R16_UINT: + case ISL_FORMAT_R16_FLOAT: + case ISL_FORMAT_R16_SINT: + return (devinfo->gen >= 9 ? format : ISL_FORMAT_R16_UINT); + + case ISL_FORMAT_R8_UINT: + case ISL_FORMAT_R8_SINT: + return (devinfo->gen >= 9 ? format : ISL_FORMAT_R8_UINT); + + /* Neither the 2/10/10/10 nor the 11/11/10 packed formats are supported + * by the hardware. + */ + case ISL_FORMAT_R10G10B10A2_UINT: + case ISL_FORMAT_R10G10B10A2_UNORM: + case ISL_FORMAT_R11G11B10_FLOAT: + return ISL_FORMAT_R32_UINT; + + /* No normalized fixed-point formats are supported by the hardware. */ + case ISL_FORMAT_R16G16B16A16_UNORM: + case ISL_FORMAT_R16G16B16A16_SNORM: + return (devinfo->gen >= 8 || devinfo->is_haswell ? + ISL_FORMAT_R16G16B16A16_UINT : + ISL_FORMAT_R32G32_UINT); + + case ISL_FORMAT_R8G8B8A8_UNORM: + case ISL_FORMAT_R8G8B8A8_SNORM: + return (devinfo->gen >= 8 || devinfo->is_haswell ? + ISL_FORMAT_R8G8B8A8_UINT : ISL_FORMAT_R32_UINT); + + case ISL_FORMAT_R16G16_UNORM: + case ISL_FORMAT_R16G16_SNORM: + return (devinfo->gen >= 8 || devinfo->is_haswell ? + ISL_FORMAT_R16G16_UINT : ISL_FORMAT_R32_UINT); + + case ISL_FORMAT_R8G8_UNORM: + case ISL_FORMAT_R8G8_SNORM: + return (devinfo->gen >= 8 || devinfo->is_haswell ? + ISL_FORMAT_R8G8_UINT : ISL_FORMAT_R16_UINT); + + case ISL_FORMAT_R16_UNORM: + case ISL_FORMAT_R16_SNORM: + return ISL_FORMAT_R16_UINT; + + case ISL_FORMAT_R8_UNORM: + case ISL_FORMAT_R8_SNORM: + return ISL_FORMAT_R8_UINT; + + default: + assert(!"Unknown image format"); + return ISL_FORMAT_UNSUPPORTED; + } +} + +bool +isl_has_matching_typed_storage_image_format(const struct gen_device_info *devinfo, + enum isl_format fmt) +{ + if (devinfo->gen >= 9) { + return true; + } else if (devinfo->gen >= 8 || devinfo->is_haswell) { + return isl_format_get_layout(fmt)->bpb <= 64; + } else { + return isl_format_get_layout(fmt)->bpb <= 32; + } +} + +static const struct brw_image_param image_param_defaults = { + /* Set the swizzling shifts to all-ones to effectively disable + * swizzling -- See emit_address_calculation() in + * brw_fs_surface_builder.cpp for a more detailed explanation of + * these parameters. + */ + .swizzling = { 0xff, 0xff }, +}; + +void +isl_surf_fill_image_param(const struct isl_device *dev, + struct brw_image_param *param, + const struct isl_surf *surf, + const struct isl_view *view) +{ + *param = image_param_defaults; + + param->size[0] = isl_minify(surf->logical_level0_px.w, view->base_level); + param->size[1] = isl_minify(surf->logical_level0_px.h, view->base_level); + if (surf->dim == ISL_SURF_DIM_3D) { + param->size[2] = isl_minify(surf->logical_level0_px.d, view->base_level); + } else { + param->size[2] = surf->logical_level0_px.array_len - + view->base_array_layer; + } + + isl_surf_get_image_offset_el(surf, view->base_level, view->base_array_layer, + 0, ¶m->offset[0], ¶m->offset[1]); + + const int cpp = isl_format_get_layout(surf->format)->bpb / 8; + param->stride[0] = cpp; + param->stride[1] = surf->row_pitch / cpp; + + const struct isl_extent3d image_align_sa = + isl_surf_get_image_alignment_sa(surf); + if (ISL_DEV_GEN(dev) < 9 && surf->dim == ISL_SURF_DIM_3D) { + param->stride[2] = isl_align_npot(param->size[0], image_align_sa.w); + param->stride[3] = isl_align_npot(param->size[1], image_align_sa.h); + } else { + param->stride[2] = 0; + param->stride[3] = isl_surf_get_array_pitch_el_rows(surf); + } + + switch (surf->tiling) { + case ISL_TILING_LINEAR: + /* image_param_defaults is good enough */ + break; + + case ISL_TILING_X: + /* An X tile is a rectangular block of 512x8 bytes. */ + param->tiling[0] = isl_log2u(512 / cpp); + param->tiling[1] = isl_log2u(8); + + if (dev->has_bit6_swizzling) { + /* Right shifts required to swizzle bits 9 and 10 of the memory + * address with bit 6. + */ + param->swizzling[0] = 3; + param->swizzling[1] = 4; + } + break; + + case ISL_TILING_Y0: + /* The layout of a Y-tiled surface in memory isn't really fundamentally + * different to the layout of an X-tiled surface, we simply pretend that + * the surface is broken up in a number of smaller 16Bx32 tiles, each + * one arranged in X-major order just like is the case for X-tiling. + */ + param->tiling[0] = isl_log2u(16 / cpp); + param->tiling[1] = isl_log2u(32); + + if (dev->has_bit6_swizzling) { + /* Right shift required to swizzle bit 9 of the memory address with + * bit 6. + */ + param->swizzling[0] = 3; + param->swizzling[1] = 0xff; + } + break; + + default: + assert(!"Unhandled storage image tiling"); + } + + /* 3D textures are arranged in 2D in memory with 2^lod slices per row. The + * address calculation algorithm (emit_address_calculation() in + * brw_fs_surface_builder.cpp) handles this as a sort of tiling with + * modulus equal to the LOD. + */ + param->tiling[2] = (ISL_DEV_GEN(dev) < 9 && surf->dim == ISL_SURF_DIM_3D ? + view->base_level : 0); +} + +void +isl_buffer_fill_image_param(const struct isl_device *dev, + struct brw_image_param *param, + enum isl_format format, + uint64_t size) +{ + *param = image_param_defaults; + + param->stride[0] = isl_format_layouts[format].bpb / 8; + param->size[0] = size / param->stride[0]; +} diff --git a/lib/mesa/src/intel/isl/isl_surface_state.c b/lib/mesa/src/intel/isl/isl_surface_state.c new file mode 100644 index 000000000..3bb0abd5a --- /dev/null +++ b/lib/mesa/src/intel/isl/isl_surface_state.c @@ -0,0 +1,667 @@ +/* + * Copyright 2016 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#include <stdint.h> + +#define __gen_address_type uint64_t +#define __gen_user_data void + +static inline uint64_t +__gen_combine_address(void *data, void *loc, uint64_t addr, uint32_t delta) +{ + return addr + delta; +} + +#include "genxml/gen_macros.h" +#include "genxml/genX_pack.h" + +#include "isl_priv.h" + +#define __PASTE2(x, y) x ## y +#define __PASTE(x, y) __PASTE2(x, y) +#define isl_genX(x) __PASTE(isl_, genX(x)) + +#if GEN_GEN >= 8 +static const uint8_t isl_to_gen_halign[] = { + [4] = HALIGN4, + [8] = HALIGN8, + [16] = HALIGN16, +}; +#elif GEN_GEN >= 7 +static const uint8_t isl_to_gen_halign[] = { + [4] = HALIGN_4, + [8] = HALIGN_8, +}; +#endif + +#if GEN_GEN >= 8 +static const uint8_t isl_to_gen_valign[] = { + [4] = VALIGN4, + [8] = VALIGN8, + [16] = VALIGN16, +}; +#elif GEN_GEN >= 6 +static const uint8_t isl_to_gen_valign[] = { + [2] = VALIGN_2, + [4] = VALIGN_4, +}; +#endif + +#if GEN_GEN >= 8 +static const uint8_t isl_to_gen_tiling[] = { + [ISL_TILING_LINEAR] = LINEAR, + [ISL_TILING_X] = XMAJOR, + [ISL_TILING_Y0] = YMAJOR, + [ISL_TILING_Yf] = YMAJOR, + [ISL_TILING_Ys] = YMAJOR, + [ISL_TILING_W] = WMAJOR, +}; +#endif + +#if GEN_GEN >= 7 +static const uint32_t isl_to_gen_multisample_layout[] = { + [ISL_MSAA_LAYOUT_NONE] = MSFMT_MSS, + [ISL_MSAA_LAYOUT_INTERLEAVED] = MSFMT_DEPTH_STENCIL, + [ISL_MSAA_LAYOUT_ARRAY] = MSFMT_MSS, +}; +#endif + +#if GEN_GEN >= 9 +static const uint32_t isl_to_gen_aux_mode[] = { + [ISL_AUX_USAGE_NONE] = AUX_NONE, + [ISL_AUX_USAGE_HIZ] = AUX_HIZ, + [ISL_AUX_USAGE_MCS] = AUX_CCS_D, + [ISL_AUX_USAGE_CCS_D] = AUX_CCS_D, + [ISL_AUX_USAGE_CCS_E] = AUX_CCS_E, +}; +#elif GEN_GEN >= 8 +static const uint32_t isl_to_gen_aux_mode[] = { + [ISL_AUX_USAGE_NONE] = AUX_NONE, + [ISL_AUX_USAGE_HIZ] = AUX_HIZ, + [ISL_AUX_USAGE_MCS] = AUX_MCS, + [ISL_AUX_USAGE_CCS_D] = AUX_MCS, +}; +#endif + +static uint8_t +get_surftype(enum isl_surf_dim dim, isl_surf_usage_flags_t usage) +{ + switch (dim) { + default: + unreachable("bad isl_surf_dim"); + case ISL_SURF_DIM_1D: + assert(!(usage & ISL_SURF_USAGE_CUBE_BIT)); + return SURFTYPE_1D; + case ISL_SURF_DIM_2D: + if (usage & ISL_SURF_USAGE_STORAGE_BIT) { + /* Storage images are always plain 2-D, not cube */ + return SURFTYPE_2D; + } else if (usage & ISL_SURF_USAGE_CUBE_BIT) { + return SURFTYPE_CUBE; + } else { + return SURFTYPE_2D; + } + case ISL_SURF_DIM_3D: + assert(!(usage & ISL_SURF_USAGE_CUBE_BIT)); + return SURFTYPE_3D; + } +} + +/** + * Get the horizontal and vertical alignment in the units expected by the + * hardware. Note that this does NOT give you the actual hardware enum values + * but an index into the isl_to_gen_[hv]align arrays above. + */ +static inline struct isl_extent3d +get_image_alignment(const struct isl_surf *surf) +{ + if (GEN_GEN >= 9) { + if (isl_tiling_is_std_y(surf->tiling) || + surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) { + /* The hardware ignores the alignment values. Anyway, the surface's + * true alignment is likely outside the enum range of HALIGN* and + * VALIGN*. + */ + return isl_extent3d(4, 4, 1); + } else { + /* In Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in units + * of surface elements (not pixels nor samples). For compressed formats, + * a "surface element" is defined as a compression block. For example, + * if SurfaceVerticalAlignment is VALIGN_4 and SurfaceFormat is an ETC2 + * format (ETC2 has a block height of 4), then the vertical alignment is + * 4 compression blocks or, equivalently, 16 pixels. + */ + return isl_surf_get_image_alignment_el(surf); + } + } else { + /* Pre-Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in + * units of surface samples. For example, if SurfaceVerticalAlignment + * is VALIGN_4 and the surface is singlesampled, then for any surface + * format (compressed or not) the vertical alignment is + * 4 pixels. + */ + return isl_surf_get_image_alignment_sa(surf); + } +} + +#if GEN_GEN >= 8 +static uint32_t +get_qpitch(const struct isl_surf *surf) +{ + switch (surf->dim_layout) { + default: + unreachable("Bad isl_surf_dim"); + case ISL_DIM_LAYOUT_GEN4_2D: + if (GEN_GEN >= 9) { + if (surf->dim == ISL_SURF_DIM_3D && surf->tiling == ISL_TILING_W) { + /* This is rather annoying and completely undocumented. It + * appears that the hardware has a bug (or undocumented feature) + * regarding stencil buffers most likely related to the way + * W-tiling is handled as modified Y-tiling. If you bind a 3-D + * stencil buffer normally, and use texelFetch on it, the z or + * array index will get implicitly multiplied by 2 for no obvious + * reason. The fix appears to be to divide qpitch by 2 for + * W-tiled surfaces. + */ + return isl_surf_get_array_pitch_el_rows(surf) / 2; + } else { + return isl_surf_get_array_pitch_el_rows(surf); + } + } else { + /* From the Broadwell PRM for RENDER_SURFACE_STATE.QPitch + * + * "This field must be set to an integer multiple of the Surface + * Vertical Alignment. For compressed textures (BC*, FXT1, + * ETC*, and EAC* Surface Formats), this field is in units of + * rows in the uncompressed surface, and must be set to an + * integer multiple of the vertical alignment parameter "j" + * defined in the Common Surface Formats section." + */ + return isl_surf_get_array_pitch_sa_rows(surf); + } + case ISL_DIM_LAYOUT_GEN9_1D: + /* QPitch is usually expressed as rows of surface elements (where + * a surface element is an compression block or a single surface + * sample). Skylake 1D is an outlier. + * + * From the Skylake BSpec >> Memory Views >> Common Surface + * Formats >> Surface Layout and Tiling >> 1D Surfaces: + * + * Surface QPitch specifies the distance in pixels between array + * slices. + */ + return isl_surf_get_array_pitch_el(surf); + case ISL_DIM_LAYOUT_GEN4_3D: + /* QPitch doesn't make sense for ISL_DIM_LAYOUT_GEN4_3D since it uses a + * different pitch at each LOD. Also, the QPitch field is ignored for + * these surfaces. From the Broadwell PRM documentation for QPitch: + * + * This field specifies the distance in rows between array slices. It + * is used only in the following cases: + * - Surface Array is enabled OR + * - Number of Mulitsamples is not NUMSAMPLES_1 and Multisampled + * Surface Storage Format set to MSFMT_MSS OR + * - Surface Type is SURFTYPE_CUBE + * + * None of the three conditions above can possibly apply to a 3D surface + * so it is safe to just set QPitch to 0. + */ + return 0; + } +} +#endif /* GEN_GEN >= 8 */ + +void +isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, + const struct isl_surf_fill_state_info *restrict info) +{ + struct GENX(RENDER_SURFACE_STATE) s = { 0 }; + + s.SurfaceType = get_surftype(info->surf->dim, info->view->usage); + + if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) + assert(isl_format_supports_rendering(dev->info, info->view->format)); + else if (info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT) + assert(isl_format_supports_sampling(dev->info, info->view->format)); + + /* From the Sky Lake PRM Vol. 2d, RENDER_SURFACE_STATE::SurfaceFormat + * + * This field cannot be a compressed (BC*, DXT*, FXT*, ETC*, EAC*) + * format if the Surface Type is SURFTYPE_1D + */ + if (info->surf->dim == ISL_SURF_DIM_1D) + assert(!isl_format_is_compressed(info->view->format)); + + s.SurfaceFormat = info->view->format; + +#if GEN_IS_HASWELL + s.IntegerSurfaceFormat = isl_format_has_int_channel(s.SurfaceFormat); +#endif + + assert(info->surf->logical_level0_px.width > 0 && + info->surf->logical_level0_px.height > 0); + + s.Width = info->surf->logical_level0_px.width - 1; + s.Height = info->surf->logical_level0_px.height - 1; + + /* In the gen6 PRM Volume 1 Part 1: Graphics Core, Section 7.18.3.7.1 + * (Surface Arrays For all surfaces other than separate stencil buffer): + * + * "[DevSNB] Errata: Sampler MSAA Qpitch will be 4 greater than the value + * calculated in the equation above , for every other odd Surface Height + * starting from 1 i.e. 1,5,9,13" + * + * Since this Qpitch errata only impacts the sampler, we have to adjust the + * input for the rendering surface to achieve the same qpitch. For the + * affected heights, we increment the height by 1 for the rendering + * surface. + */ + if (GEN_GEN == 6 && (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) && + info->surf->samples > 1 && + (info->surf->logical_level0_px.height % 4) == 1) + s.Height++; + + switch (s.SurfaceType) { + case SURFTYPE_1D: + case SURFTYPE_2D: + /* From the Ivy Bridge PRM >> RENDER_SURFACE_STATE::MinimumArrayElement: + * + * "If Number of Multisamples is not MULTISAMPLECOUNT_1, this field + * must be set to zero if this surface is used with sampling engine + * messages." + * + * This restriction appears to exist only on Ivy Bridge. + */ + if (GEN_GEN == 7 && !GEN_IS_HASWELL && !ISL_DEV_IS_BAYTRAIL(dev) && + (info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT) && + info->surf->samples > 1) + assert(info->view->base_array_layer == 0); + + s.MinimumArrayElement = info->view->base_array_layer; + + /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth: + * + * For SURFTYPE_1D, 2D, and CUBE: The range of this field is reduced + * by one for each increase from zero of Minimum Array Element. For + * example, if Minimum Array Element is set to 1024 on a 2D surface, + * the range of this field is reduced to [0,1023]. + * + * In other words, 'Depth' is the number of array layers. + */ + s.Depth = info->view->array_len - 1; + + /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent: + * + * For Render Target and Typed Dataport 1D and 2D Surfaces: + * This field must be set to the same value as the Depth field. + */ + if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT | + ISL_SURF_USAGE_STORAGE_BIT)) + s.RenderTargetViewExtent = s.Depth; + break; + case SURFTYPE_CUBE: + s.MinimumArrayElement = info->view->base_array_layer; + /* Same as SURFTYPE_2D, but divided by 6 */ + s.Depth = info->view->array_len / 6 - 1; + if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT | + ISL_SURF_USAGE_STORAGE_BIT)) + s.RenderTargetViewExtent = s.Depth; + break; + case SURFTYPE_3D: + /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth: + * + * If the volume texture is MIP-mapped, this field specifies the + * depth of the base MIP level. + */ + s.Depth = info->surf->logical_level0_px.depth - 1; + + /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent: + * + * For Render Target and Typed Dataport 3D Surfaces: This field + * indicates the extent of the accessible 'R' coordinates minus 1 on + * the LOD currently being rendered to. + * + * The docs specify that this only matters for render targets and + * surfaces used with typed dataport messages. Prior to Ivy Bridge, the + * Depth field has more bits than RenderTargetViewExtent so we can have + * textures with more levels than we can render to. In order to prevent + * assert-failures in the packing function below, we only set the field + * when it's actually going to be used by the hardware. + * + * Similaraly, the MinimumArrayElement field is ignored by all hardware + * prior to Sky Lake when texturing and we want it set to 0 anyway. + * Since it's already initialized to 0, we can just leave it alone for + * texture surfaces. + */ + if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT | + ISL_SURF_USAGE_STORAGE_BIT)) { + s.MinimumArrayElement = info->view->base_array_layer; + s.RenderTargetViewExtent = info->view->array_len - 1; + } + break; + default: + unreachable("bad SurfaceType"); + } + +#if GEN_GEN >= 7 + s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D; +#endif + + if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) { + /* For render target surfaces, the hardware interprets field + * MIPCount/LOD as LOD. The Broadwell PRM says: + * + * MIPCountLOD defines the LOD that will be rendered into. + * SurfaceMinLOD is ignored. + */ + s.MIPCountLOD = info->view->base_level; + s.SurfaceMinLOD = 0; + } else { + /* For non render target surfaces, the hardware interprets field + * MIPCount/LOD as MIPCount. The range of levels accessible by the + * sampler engine is [SurfaceMinLOD, SurfaceMinLOD + MIPCountLOD]. + */ + s.SurfaceMinLOD = info->view->base_level; + s.MIPCountLOD = MAX(info->view->levels, 1) - 1; + } + +#if GEN_GEN >= 9 + /* We don't use miptails yet. The PRM recommends that you set "Mip Tail + * Start LOD" to 15 to prevent the hardware from trying to use them. + */ + s.TiledResourceMode = NONE; + s.MipTailStartLOD = 15; +#endif + +#if GEN_GEN >= 6 + const struct isl_extent3d image_align = get_image_alignment(info->surf); + s.SurfaceVerticalAlignment = isl_to_gen_valign[image_align.height]; +#if GEN_GEN >= 7 + s.SurfaceHorizontalAlignment = isl_to_gen_halign[image_align.width]; +#endif +#endif + + if (info->surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) { + /* For gen9 1-D textures, surface pitch is ignored */ + s.SurfacePitch = 0; + } else { + s.SurfacePitch = info->surf->row_pitch - 1; + } + +#if GEN_GEN >= 8 + s.SurfaceQPitch = get_qpitch(info->surf) >> 2; +#elif GEN_GEN == 7 + s.SurfaceArraySpacing = info->surf->array_pitch_span == + ISL_ARRAY_PITCH_SPAN_COMPACT; +#endif + +#if GEN_GEN >= 8 + s.TileMode = isl_to_gen_tiling[info->surf->tiling]; +#else + s.TiledSurface = info->surf->tiling != ISL_TILING_LINEAR, + s.TileWalk = info->surf->tiling == ISL_TILING_Y0 ? TILEWALK_YMAJOR : + TILEWALK_XMAJOR, +#endif + +#if GEN_GEN >= 8 + s.RenderCacheReadWriteMode = WriteOnlyCache; +#else + s.RenderCacheReadWriteMode = 0; +#endif + + if (info->view->usage & ISL_SURF_USAGE_CUBE_BIT) { +#if GEN_GEN >= 8 + s.CubeFaceEnablePositiveZ = 1; + s.CubeFaceEnableNegativeZ = 1; + s.CubeFaceEnablePositiveY = 1; + s.CubeFaceEnableNegativeY = 1; + s.CubeFaceEnablePositiveX = 1; + s.CubeFaceEnableNegativeX = 1; +#else + s.CubeFaceEnables = 0x3f; +#endif + } + +#if GEN_GEN >= 6 + s.NumberofMultisamples = ffs(info->surf->samples) - 1; +#if GEN_GEN >= 7 + s.MultisampledSurfaceStorageFormat = + isl_to_gen_multisample_layout[info->surf->msaa_layout]; +#endif +#endif + +#if (GEN_GEN >= 8 || GEN_IS_HASWELL) + s.ShaderChannelSelectRed = info->view->swizzle.r; + s.ShaderChannelSelectGreen = info->view->swizzle.g; + s.ShaderChannelSelectBlue = info->view->swizzle.b; + s.ShaderChannelSelectAlpha = info->view->swizzle.a; +#endif + + s.SurfaceBaseAddress = info->address; + +#if GEN_GEN >= 6 + s.MOCS = info->mocs; +#endif + +#if GEN_GEN > 4 || GEN_IS_G4X + if (info->x_offset_sa != 0 || info->y_offset_sa != 0) { + /* There are fairly strict rules about when the offsets can be used. + * These are mostly taken from the Sky Lake PRM documentation for + * RENDER_SURFACE_STATE. + */ + assert(info->surf->tiling != ISL_TILING_LINEAR); + assert(info->surf->dim == ISL_SURF_DIM_2D); + assert(isl_is_pow2(isl_format_get_layout(info->view->format)->bpb)); + assert(info->surf->levels == 1); + assert(info->surf->logical_level0_px.array_len == 1); + assert(info->aux_usage == ISL_AUX_USAGE_NONE); + + if (GEN_GEN >= 8) { + /* Broadwell added more rules. */ + assert(info->surf->samples == 1); + if (isl_format_get_layout(info->view->format)->bpb == 8) + assert(info->x_offset_sa % 16 == 0); + if (isl_format_get_layout(info->view->format)->bpb == 16) + assert(info->x_offset_sa % 8 == 0); + } + +#if GEN_GEN >= 7 + s.SurfaceArray = false; +#endif + } + + const unsigned x_div = 4; + const unsigned y_div = GEN_GEN >= 8 ? 4 : 2; + assert(info->x_offset_sa % x_div == 0); + assert(info->y_offset_sa % y_div == 0); + s.XOffset = info->x_offset_sa / x_div; + s.YOffset = info->y_offset_sa / y_div; +#else + assert(info->x_offset_sa == 0); + assert(info->y_offset_sa == 0); +#endif + +#if GEN_GEN >= 7 + if (info->aux_surf && info->aux_usage != ISL_AUX_USAGE_NONE) { + struct isl_tile_info tile_info; + isl_surf_get_tile_info(dev, info->aux_surf, &tile_info); + uint32_t pitch_in_tiles = + info->aux_surf->row_pitch / tile_info.phys_extent_B.width; + +#if GEN_GEN >= 8 + assert(GEN_GEN >= 9 || info->aux_usage != ISL_AUX_USAGE_CCS_E); + s.AuxiliarySurfacePitch = pitch_in_tiles - 1; + /* Auxiliary surfaces in ISL have compressed formats but the hardware + * doesn't expect our definition of the compression, it expects qpitch + * in units of samples on the main surface. + */ + s.AuxiliarySurfaceQPitch = + isl_surf_get_array_pitch_sa_rows(info->aux_surf) >> 2; + s.AuxiliarySurfaceBaseAddress = info->aux_address; + s.AuxiliarySurfaceMode = isl_to_gen_aux_mode[info->aux_usage]; +#else + assert(info->aux_usage == ISL_AUX_USAGE_MCS || + info->aux_usage == ISL_AUX_USAGE_CCS_D); + s.MCSBaseAddress = info->aux_address, + s.MCSSurfacePitch = pitch_in_tiles - 1; + s.MCSEnable = true; +#endif + } +#endif + +#if GEN_GEN >= 8 + /* From the CHV PRM, Volume 2d, page 321 (RENDER_SURFACE_STATE dword 0 + * bit 9 "Sampler L2 Bypass Mode Disable" Programming Notes): + * + * This bit must be set for the following surface types: BC2_UNORM + * BC3_UNORM BC5_UNORM BC5_SNORM BC7_UNORM + */ + if (GEN_GEN >= 9 || dev->info->is_cherryview) { + switch (info->view->format) { + case ISL_FORMAT_BC2_UNORM: + case ISL_FORMAT_BC3_UNORM: + case ISL_FORMAT_BC5_UNORM: + case ISL_FORMAT_BC5_SNORM: + case ISL_FORMAT_BC7_UNORM: + s.SamplerL2BypassModeDisable = true; + break; + default: + break; + } + } +#endif + + if (info->aux_usage != ISL_AUX_USAGE_NONE) { +#if GEN_GEN >= 9 + s.RedClearColor = info->clear_color.u32[0]; + s.GreenClearColor = info->clear_color.u32[1]; + s.BlueClearColor = info->clear_color.u32[2]; + s.AlphaClearColor = info->clear_color.u32[3]; +#elif GEN_GEN >= 7 + /* Prior to Sky Lake, we only have one bit for the clear color which + * gives us 0 or 1 in whatever the surface's format happens to be. + */ + if (isl_format_has_int_channel(info->view->format)) { + for (unsigned i = 0; i < 4; i++) { + assert(info->clear_color.u32[i] == 0 || + info->clear_color.u32[i] == 1); + } + s.RedClearColor = info->clear_color.u32[0] != 0; + s.GreenClearColor = info->clear_color.u32[1] != 0; + s.BlueClearColor = info->clear_color.u32[2] != 0; + s.AlphaClearColor = info->clear_color.u32[3] != 0; + } else { + for (unsigned i = 0; i < 4; i++) { + assert(info->clear_color.f32[i] == 0.0f || + info->clear_color.f32[i] == 1.0f); + } + s.RedClearColor = info->clear_color.f32[0] != 0.0f; + s.GreenClearColor = info->clear_color.f32[1] != 0.0f; + s.BlueClearColor = info->clear_color.f32[2] != 0.0f; + s.AlphaClearColor = info->clear_color.f32[3] != 0.0f; + } +#endif + } + + GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s); +} + +void +isl_genX(buffer_fill_state_s)(void *state, + const struct isl_buffer_fill_state_info *restrict info) +{ + uint32_t num_elements = info->size / info->stride; + + if (GEN_GEN >= 7) { + /* From the IVB PRM, SURFACE_STATE::Height, + * + * For typed buffer and structured buffer surfaces, the number + * of entries in the buffer ranges from 1 to 2^27. For raw buffer + * surfaces, the number of entries in the buffer is the number of bytes + * which can range from 1 to 2^30. + */ + if (info->format == ISL_FORMAT_RAW) { + assert(num_elements <= (1ull << 30)); + assert((num_elements & 3) == 0); + } else { + assert(num_elements <= (1ull << 27)); + } + } else { + assert(num_elements <= (1ull << 27)); + } + + struct GENX(RENDER_SURFACE_STATE) s = { 0, }; + + s.SurfaceType = SURFTYPE_BUFFER; + s.SurfaceFormat = info->format; + +#if GEN_GEN >= 6 + s.SurfaceVerticalAlignment = isl_to_gen_valign[4]; +#if GEN_GEN >= 7 + s.SurfaceHorizontalAlignment = isl_to_gen_halign[4]; + s.SurfaceArray = false; +#endif +#endif + +#if GEN_GEN >= 7 + s.Height = ((num_elements - 1) >> 7) & 0x3fff; + s.Width = (num_elements - 1) & 0x7f; + s.Depth = ((num_elements - 1) >> 21) & 0x3ff; +#else + s.Height = ((num_elements - 1) >> 7) & 0x1fff; + s.Width = (num_elements - 1) & 0x7f; + s.Depth = ((num_elements - 1) >> 20) & 0x7f; +#endif + + s.SurfacePitch = info->stride - 1; + +#if GEN_GEN >= 6 + s.NumberofMultisamples = MULTISAMPLECOUNT_1; +#endif + +#if (GEN_GEN >= 8) + s.TileMode = LINEAR; +#else + s.TiledSurface = false; +#endif + +#if (GEN_GEN >= 8) + s.RenderCacheReadWriteMode = WriteOnlyCache; +#else + s.RenderCacheReadWriteMode = 0; +#endif + + s.SurfaceBaseAddress = info->address; +#if GEN_GEN >= 6 + s.MOCS = info->mocs; +#endif + +#if (GEN_GEN >= 8 || GEN_IS_HASWELL) + s.ShaderChannelSelectRed = SCS_RED; + s.ShaderChannelSelectGreen = SCS_GREEN; + s.ShaderChannelSelectBlue = SCS_BLUE; + s.ShaderChannelSelectAlpha = SCS_ALPHA; +#endif + + GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s); +} diff --git a/lib/mesa/src/intel/isl/tests/isl_surf_get_image_offset_test.c b/lib/mesa/src/intel/isl/tests/isl_surf_get_image_offset_test.c new file mode 100644 index 000000000..1b3dc58b0 --- /dev/null +++ b/lib/mesa/src/intel/isl/tests/isl_surf_get_image_offset_test.c @@ -0,0 +1,284 @@ +/* + * Copyright 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include <assert.h> +#include <stdbool.h> +#include <stdio.h> +#include <stdlib.h> + +#include "common/gen_device_info.h" +#include "isl/isl.h" +#include "isl/isl_priv.h" + +#define BDW_GT2_DEVID 0x161a + +// An asssert that works regardless of NDEBUG. +#define t_assert(cond) \ + do { \ + if (!(cond)) { \ + fprintf(stderr, "%s:%d: assertion failed\n", __FILE__, __LINE__); \ + abort(); \ + } \ + } while (0) + +static void +t_assert_extent4d(const struct isl_extent4d *e, uint32_t width, + uint32_t height, uint32_t depth, uint32_t array_len) +{ + t_assert(e->width == width); + t_assert(e->height == height); + t_assert(e->depth == depth); + t_assert(e->array_len == array_len); +} + +static void +t_assert_image_alignment_el(const struct isl_surf *surf, + uint32_t w, uint32_t h, uint32_t d) +{ + struct isl_extent3d align_el; + + align_el = isl_surf_get_image_alignment_el(surf); + t_assert(align_el.w == w); + t_assert(align_el.h == h); + t_assert(align_el.d == d); + +} + +static void +t_assert_image_alignment_sa(const struct isl_surf *surf, + uint32_t w, uint32_t h, uint32_t d) +{ + struct isl_extent3d align_sa; + + align_sa = isl_surf_get_image_alignment_sa(surf); + t_assert(align_sa.w == w); + t_assert(align_sa.h == h); + t_assert(align_sa.d == d); + +} + +static void +t_assert_offset_el(const struct isl_surf *surf, + uint32_t level, + uint32_t logical_array_layer, + uint32_t logical_z_offset_px, + uint32_t expected_x_offset_el, + uint32_t expected_y_offset_el) +{ + uint32_t x, y; + isl_surf_get_image_offset_el(surf, level, logical_array_layer, + logical_z_offset_px, &x, &y); + + t_assert(x == expected_x_offset_el); + t_assert(y == expected_y_offset_el); +} + +static void +t_assert_phys_level0_sa(const struct isl_surf *surf, uint32_t width, + uint32_t height, uint32_t depth, uint32_t array_len) +{ + t_assert_extent4d(&surf->phys_level0_sa, width, height, depth, array_len); +} + +static void +t_assert_gen4_3d_layer(const struct isl_surf *surf, + uint32_t level, + uint32_t aligned_width, + uint32_t aligned_height, + uint32_t depth, + uint32_t horiz_layers, + uint32_t vert_layers, + uint32_t *base_y) +{ + for (uint32_t z = 0; z < depth; ++z) { + t_assert_offset_el(surf, level, 0, z, + aligned_width * (z % horiz_layers), + *base_y + aligned_height * (z / horiz_layers)); + } + + *base_y += aligned_height * vert_layers; +} + +static void +test_bdw_2d_r8g8b8a8_unorm_512x512_array01_samples01_noaux_tiley0(void) +{ + bool ok; + + struct gen_device_info devinfo; + t_assert(gen_get_device_info(BDW_GT2_DEVID, &devinfo)); + + struct isl_device dev; + isl_device_init(&dev, &devinfo, /*bit6_swizzle*/ false); + + struct isl_surf surf; + ok = isl_surf_init(&dev, &surf, + .dim = ISL_SURF_DIM_2D, + .format = ISL_FORMAT_R8G8B8A8_UNORM, + .width = 512, + .height = 512, + .depth = 1, + .levels = 10, + .array_len = 1, + .samples = 1, + .usage = ISL_SURF_USAGE_TEXTURE_BIT | + ISL_SURF_USAGE_DISABLE_AUX_BIT, + .tiling_flags = ISL_TILING_Y0_BIT); + t_assert(ok); + + t_assert_image_alignment_el(&surf, 4, 4, 1); + t_assert_image_alignment_sa(&surf, 4, 4, 1); + t_assert_phys_level0_sa(&surf, 512, 512, 1, 1); + t_assert(isl_surf_get_array_pitch_el_rows(&surf) >= 772); + t_assert(isl_surf_get_array_pitch_el_rows(&surf) == + isl_surf_get_array_pitch_sa_rows(&surf)); + + /* Row pitch should be minimal possible */ + t_assert(surf.row_pitch == 2048); + + t_assert_offset_el(&surf, 0, 0, 0, 0, 0); // +0, +0 + t_assert_offset_el(&surf, 1, 0, 0, 0, 512); // +0, +512 + t_assert_offset_el(&surf, 2, 0, 0, 256, 512); // +256, +0 + t_assert_offset_el(&surf, 3, 0, 0, 256, 640); // +0, +128 + t_assert_offset_el(&surf, 4, 0, 0, 256, 704); // +0, +64 + t_assert_offset_el(&surf, 5, 0, 0, 256, 736); // +0, +32 + t_assert_offset_el(&surf, 6, 0, 0, 256, 752); // +0, +16 + t_assert_offset_el(&surf, 7, 0, 0, 256, 760); // +0, +8 + t_assert_offset_el(&surf, 8, 0, 0, 256, 764); // +0, +4 + t_assert_offset_el(&surf, 9, 0, 0, 256, 768); // +0, +4 +} + +static void +test_bdw_2d_r8g8b8a8_unorm_1024x1024_array06_samples01_noaux_tiley0(void) +{ + bool ok; + + struct gen_device_info devinfo; + t_assert(gen_get_device_info(BDW_GT2_DEVID, &devinfo)); + + struct isl_device dev; + isl_device_init(&dev, &devinfo, /*bit6_swizzle*/ false); + + struct isl_surf surf; + ok = isl_surf_init(&dev, &surf, + .dim = ISL_SURF_DIM_2D, + .format = ISL_FORMAT_R8G8B8A8_UNORM, + .width = 1024, + .height = 1024, + .depth = 1, + .levels = 11, + .array_len = 6, + .samples = 1, + .usage = ISL_SURF_USAGE_TEXTURE_BIT | + ISL_SURF_USAGE_DISABLE_AUX_BIT, + .tiling_flags = ISL_TILING_Y0_BIT); + t_assert(ok); + + t_assert_image_alignment_el(&surf, 4, 4, 1); + t_assert_image_alignment_sa(&surf, 4, 4, 1); + + t_assert(isl_surf_get_array_pitch_el_rows(&surf) >= 1540); + t_assert(isl_surf_get_array_pitch_el_rows(&surf) == + isl_surf_get_array_pitch_sa_rows(&surf)); + + /* Row pitch should be minimal possible */ + t_assert(surf.row_pitch == 4096); + + for (uint32_t a = 0; a < 6; ++a) { + uint32_t b = a * isl_surf_get_array_pitch_sa_rows(&surf); + + t_assert_offset_el(&surf, 0, a, 0, 0, b + 0); // +0, +0 + t_assert_offset_el(&surf, 1, a, 0, 0, b + 1024); // +0, +1024 + t_assert_offset_el(&surf, 2, a, 0, 512, b + 1024); // +512, +0 + t_assert_offset_el(&surf, 3, a, 0, 512, b + 1280); // +0, +256 + t_assert_offset_el(&surf, 4, a, 0, 512, b + 1408); // +0, +128 + t_assert_offset_el(&surf, 5, a, 0, 512, b + 1472); // +0, +64 + t_assert_offset_el(&surf, 6, a, 0, 512, b + 1504); // +0, +32 + t_assert_offset_el(&surf, 7, a, 0, 512, b + 1520); // +0, +16 + t_assert_offset_el(&surf, 8, a, 0, 512, b + 1528); // +0, +8 + t_assert_offset_el(&surf, 9, a, 0, 512, b + 1532); // +0, +4 + t_assert_offset_el(&surf, 10, a, 0, 512, b + 1536); // +0, +4 + + } + + /* The layout below assumes a specific array pitch. It will need updating + * if isl's array pitch calculations ever change. + */ + t_assert(isl_surf_get_array_pitch_el_rows(&surf) == 1540); + + /* skip the remaining array layers */ +} + +static void +test_bdw_3d_r8g8b8a8_unorm_256x256x256_levels09_tiley0(void) +{ + bool ok; + + struct gen_device_info devinfo; + t_assert(gen_get_device_info(BDW_GT2_DEVID, &devinfo)); + + struct isl_device dev; + isl_device_init(&dev, &devinfo, /*bit6_swizzle*/ false); + + struct isl_surf surf; + ok = isl_surf_init(&dev, &surf, + .dim = ISL_SURF_DIM_3D, + .format = ISL_FORMAT_R8G8B8A8_UNORM, + .width = 256, + .height = 256, + .depth = 256, + .levels = 9, + .array_len = 1, + .samples = 1, + .usage = ISL_SURF_USAGE_TEXTURE_BIT | + ISL_SURF_USAGE_DISABLE_AUX_BIT, + .tiling_flags = ISL_TILING_Y0_BIT); + t_assert(ok); + + t_assert_image_alignment_el(&surf, 4, 4, 1); + t_assert_image_alignment_sa(&surf, 4, 4, 1); + t_assert(isl_surf_get_array_pitch_el_rows(&surf) == 74916); + t_assert(isl_surf_get_array_pitch_sa_rows(&surf) == + isl_surf_get_array_pitch_el_rows(&surf)); + + uint32_t base_y = 0; + + t_assert_gen4_3d_layer(&surf, 0, 256, 256, 256, 1, 256, &base_y); + t_assert_gen4_3d_layer(&surf, 1, 128, 128, 128, 2, 64, &base_y); + t_assert_gen4_3d_layer(&surf, 2, 64, 64, 64, 4, 16, &base_y); + t_assert_gen4_3d_layer(&surf, 3, 32, 32, 32, 8, 4, &base_y); + t_assert_gen4_3d_layer(&surf, 4, 16, 16, 16, 16, 1, &base_y); + t_assert_gen4_3d_layer(&surf, 5, 8, 8, 8, 32, 1, &base_y); + t_assert_gen4_3d_layer(&surf, 6, 4, 4, 4, 64, 1, &base_y); + t_assert_gen4_3d_layer(&surf, 7, 4, 4, 2, 128, 1, &base_y); + t_assert_gen4_3d_layer(&surf, 8, 4, 4, 1, 256, 1, &base_y); +} + +int main(void) +{ + /* FINISHME: Add tests for npot sizes */ + /* FINISHME: Add tests for 1D surfaces */ + + test_bdw_2d_r8g8b8a8_unorm_512x512_array01_samples01_noaux_tiley0(); + test_bdw_2d_r8g8b8a8_unorm_1024x1024_array06_samples01_noaux_tiley0(); + test_bdw_3d_r8g8b8a8_unorm_256x256x256_levels09_tiley0(); +} |