Import Mesa 20.0.8

6 files changed, 168 insertions, 122 deletions

diff --git a/lib/mesa/src/intel/vulkan/anv_android.c b/lib/mesa/src/intel/vulkan/anv_android.c
index 06623f4ba..b46a990b3 100644
--- a/lib/mesa/src/intel/vulkan/anv_android.c
+++ b/lib/mesa/src/intel/vulkan/anv_android.c
@@ -572,8 +572,8 @@ format_supported_with_usage(VkDevice device_h, VkFormat format,
 
 
 static VkResult
-setup_gralloc0_usage(struct anv_device *device, VkFormat format,
-                     VkImageUsageFlags imageUsage, int *grallocUsage)
+setup_gralloc0_usage(VkFormat format, VkImageUsageFlags imageUsage,
+                     int *grallocUsage)
 {
    /* WARNING: Android's libvulkan.so hardcodes the VkImageUsageFlags
     * returned to applications via VkSurfaceCapabilitiesKHR::supportedUsageFlags.
@@ -654,7 +654,7 @@ VkResult anv_GetSwapchainGrallocUsage2ANDROID(
       return result;
 
    int32_t grallocUsage = 0;
-   result = setup_gralloc0_usage(device, format, imageUsage, &grallocUsage);
+   result = setup_gralloc0_usage(format, imageUsage, &grallocUsage);
    if (result != VK_SUCCESS)
       return result;
 
@@ -686,7 +686,6 @@ VkResult anv_GetSwapchainGrallocUsageANDROID(
     VkImageUsageFlags   imageUsage,
     int*                grallocUsage)
 {
-   ANV_FROM_HANDLE(anv_device, device, device_h);
    VkResult result;
 
    *grallocUsage = 0;
@@ -696,7 +695,7 @@ VkResult anv_GetSwapchainGrallocUsageANDROID(
    if (result != VK_SUCCESS)
       return result;
 
-   return setup_gralloc0_usage(device, format, imageUsage, grallocUsage);
+   return setup_gralloc0_usage(format, imageUsage, grallocUsage);
 }
 
 VkResult
diff --git a/lib/mesa/src/intel/vulkan/anv_extensions.py b/lib/mesa/src/intel/vulkan/anv_extensions.py
index b88f01088..43e3038fe 100644
--- a/lib/mesa/src/intel/vulkan/anv_extensions.py
+++ b/lib/mesa/src/intel/vulkan/anv_extensions.py
@@ -113,7 +113,6 @@ EXTENSIONS = [
     Extension('VK_KHR_shader_draw_parameters',            1, True),
     Extension('VK_KHR_shader_float16_int8',               1, 'device->info.gen >= 8'),
     Extension('VK_KHR_shader_float_controls',             1, 'device->info.gen >= 8'),
-    Extension('VK_KHR_shader_non_semantic_info',          1, True),
     Extension('VK_KHR_shader_subgroup_extended_types',    1, 'device->info.gen >= 8'),
     Extension('VK_KHR_spirv_1_4',                         1, True),
     Extension('VK_KHR_storage_buffer_storage_class',      1, True),
@@ -155,7 +154,6 @@ EXTENSIONS = [
     Extension('VK_EXT_pipeline_creation_feedback',        1, True),
     Extension('VK_EXT_post_depth_coverage',               1, 'device->info.gen >= 9'),
     Extension('VK_EXT_queue_family_foreign',              1, 'ANDROID'),
-    Extension('VK_EXT_robustness2',                       1, True),
     Extension('VK_EXT_sampler_filter_minmax',             1, 'device->info.gen >= 9'),
     Extension('VK_EXT_scalar_block_layout',               1, True),
     Extension('VK_EXT_separate_stencil_usage',            1, True),
diff --git a/lib/mesa/src/intel/vulkan/anv_nir_compute_push_layout.c b/lib/mesa/src/intel/vulkan/anv_nir_compute_push_layout.c
index 9fcc2f74e..1dbfb08a1 100644
--- a/lib/mesa/src/intel/vulkan/anv_nir_compute_push_layout.c
+++ b/lib/mesa/src/intel/vulkan/anv_nir_compute_push_layout.c
@@ -22,22 +22,18 @@
  */
 
 #include "anv_nir.h"
-#include "nir_builder.h"
 #include "compiler/brw_nir.h"
 #include "util/mesa-sha1.h"
 
 void
 anv_nir_compute_push_layout(const struct anv_physical_device *pdevice,
-                            bool robust_buffer_access,
                             nir_shader *nir,
                             struct brw_stage_prog_data *prog_data,
                             struct anv_pipeline_bind_map *map,
                             void *mem_ctx)
 {
-   const struct brw_compiler *compiler = pdevice->compiler;
    memset(map->push_ranges, 0, sizeof(map->push_ranges));
 
-   bool has_const_ubo = false;
    unsigned push_start = UINT_MAX, push_end = 0;
    nir_foreach_function(function, nir) {
       if (!function->impl)
@@ -49,48 +45,19 @@ anv_nir_compute_push_layout(const struct anv_physical_device *pdevice,
                continue;
 
             nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
-            switch (intrin->intrinsic) {
-            case nir_intrinsic_load_ubo:
-               if (nir_src_is_const(intrin->src[0]) &&
-                   nir_src_is_const(intrin->src[1]))
-                  has_const_ubo = true;
-               break;
-
-            case nir_intrinsic_load_push_constant: {
-               unsigned base = nir_intrinsic_base(intrin);
-               unsigned range = nir_intrinsic_range(intrin);
-               push_start = MIN2(push_start, base);
-               push_end = MAX2(push_end, base + range);
-               break;
-            }
+            if (intrin->intrinsic != nir_intrinsic_load_push_constant)
+               continue;
 
-            default:
-               break;
-            }
+            unsigned base = nir_intrinsic_base(intrin);
+            unsigned range = nir_intrinsic_range(intrin);
+            push_start = MIN2(push_start, base);
+            push_end = MAX2(push_end, base + range);
          }
       }
    }
 
    const bool has_push_intrinsic = push_start <= push_end;
 
-   const bool push_ubo_ranges =
-      (pdevice->info.gen >= 8 || pdevice->info.is_haswell) &&
-      has_const_ubo && nir->info.stage != MESA_SHADER_COMPUTE;
-
-   if (push_ubo_ranges && robust_buffer_access) {
-      /* We can't on-the-fly adjust our push ranges because doing so would
-       * mess up the layout in the shader.  When robustBufferAccess is
-       * enabled, we push a mask into the shader indicating which pushed
-       * registers are valid and we zero out the invalid ones at the top of
-       * the shader.
-       */
-      const uint32_t push_reg_mask_start =
-         offsetof(struct anv_push_constants, push_reg_mask);
-      const uint32_t push_reg_mask_end = push_reg_mask_start + sizeof(uint64_t);
-      push_start = MIN2(push_start, push_reg_mask_start);
-      push_end = MAX2(push_end, push_reg_mask_end);
-   }
-
    if (nir->info.stage == MESA_SHADER_COMPUTE) {
       /* For compute shaders, we always have to have the subgroup ID.  The
        * back-end compiler will "helpfully" add it for us in the last push
@@ -107,21 +74,7 @@ anv_nir_compute_push_layout(const struct anv_physical_device *pdevice,
     * push_end (no push constants is indicated by push_start = UINT_MAX).
     */
    push_start = MIN2(push_start, push_end);
-   push_start = align_down_u32(push_start, 32);
-
-   /* For vec4 our push data size needs to be aligned to a vec4 and for
-    * scalar, it needs to be aligned to a DWORD.
-    */
-   const unsigned align = compiler->scalar_stage[nir->info.stage] ? 4 : 16;
-   nir->num_uniforms = ALIGN(push_end - push_start, align);
-   prog_data->nr_params = nir->num_uniforms / 4;
-   prog_data->param = rzalloc_array(mem_ctx, uint32_t, prog_data->nr_params);
-
-   struct anv_push_range push_constant_range = {
-      .set = ANV_DESCRIPTOR_SET_PUSH_CONSTANTS,
-      .start = push_start / 32,
-      .length = DIV_ROUND_UP(push_end - push_start, 32),
-   };
+   push_start &= ~31u;
 
    if (has_push_intrinsic) {
       nir_foreach_function(function, nir) {
@@ -129,29 +82,42 @@ anv_nir_compute_push_layout(const struct anv_physical_device *pdevice,
             continue;
 
          nir_foreach_block(block, function->impl) {
-            nir_foreach_instr_safe(instr, block) {
+            nir_foreach_instr(instr, block) {
                if (instr->type != nir_instr_type_intrinsic)
                   continue;
 
                nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
-               switch (intrin->intrinsic) {
-               case nir_intrinsic_load_push_constant:
-                  intrin->intrinsic = nir_intrinsic_load_uniform;
-                  nir_intrinsic_set_base(intrin,
-                                         nir_intrinsic_base(intrin) -
-                                         push_start);
-                  break;
-
-               default:
-                  break;
-               }
+               if (intrin->intrinsic != nir_intrinsic_load_push_constant)
+                  continue;
+
+               intrin->intrinsic = nir_intrinsic_load_uniform;
+               nir_intrinsic_set_base(intrin,
+                                      nir_intrinsic_base(intrin) -
+                                      push_start);
             }
          }
       }
    }
 
-   if (push_ubo_ranges) {
-      brw_nir_analyze_ubo_ranges(compiler, nir, NULL, prog_data->ubo_ranges);
+   /* For vec4 our push data size needs to be aligned to a vec4 and for
+    * scalar, it needs to be aligned to a DWORD.
+    */
+   const unsigned align =
+      pdevice->compiler->scalar_stage[nir->info.stage] ? 4 : 16;
+   nir->num_uniforms = ALIGN(push_end - push_start, align);
+   prog_data->nr_params = nir->num_uniforms / 4;
+   prog_data->param = rzalloc_array(mem_ctx, uint32_t, prog_data->nr_params);
+
+   struct anv_push_range push_constant_range = {
+      .set = ANV_DESCRIPTOR_SET_PUSH_CONSTANTS,
+      .start = push_start / 32,
+      .length = DIV_ROUND_UP(push_end - push_start, 32),
+   };
+
+   if ((pdevice->info.gen >= 8 || pdevice->info.is_haswell) &&
+       nir->info.stage != MESA_SHADER_COMPUTE) {
+      brw_nir_analyze_ubo_ranges(pdevice->compiler, nir, NULL,
+                                 prog_data->ubo_ranges);
 
       /* We can push at most 64 registers worth of data.  The back-end
        * compiler would do this fixup for us but we'd like to calculate
@@ -170,26 +136,11 @@ anv_nir_compute_push_layout(const struct anv_physical_device *pdevice,
       if (push_constant_range.length > 0)
          map->push_ranges[n++] = push_constant_range;
 
-      if (robust_buffer_access) {
-         const uint32_t push_reg_mask_offset =
-            offsetof(struct anv_push_constants, push_reg_mask);
-         assert(push_reg_mask_offset >= push_start);
-         prog_data->push_reg_mask_param =
-            (push_reg_mask_offset - push_start) / 4;
-      }
-
-      unsigned range_start_reg = push_constant_range.length;
-
       for (int i = 0; i < 4; i++) {
-         struct brw_ubo_range *ubo_range = &prog_data->ubo_ranges[i];
+         const struct brw_ubo_range *ubo_range = &prog_data->ubo_ranges[i];
          if (ubo_range->length == 0)
             continue;
 
-         if (n >= 4 || (n == 3 && compiler->constant_buffer_0_is_relative)) {
-            memset(ubo_range, 0, sizeof(*ubo_range));
-            continue;
-         }
-
          const struct anv_pipeline_binding *binding =
             &map->surface_to_descriptor[ubo_range->block];
 
@@ -200,14 +151,6 @@ anv_nir_compute_push_layout(const struct anv_physical_device *pdevice,
             .start = ubo_range->start,
             .length = ubo_range->length,
          };
-
-         /* We only bother to shader-zero pushed client UBOs */
-         if (binding->set < MAX_SETS && robust_buffer_access) {
-            prog_data->zero_push_reg |= BITFIELD64_RANGE(range_start_reg,
-                                                         ubo_range->length);
-         }
-
-         range_start_reg += ubo_range->length;
       }
    } else {
       /* For Ivy Bridge, the push constants packets have a different
diff --git a/lib/mesa/src/intel/vulkan/anv_nir_lower_ycbcr_textures.c b/lib/mesa/src/intel/vulkan/anv_nir_lower_ycbcr_textures.c
index e55e5317f..d18d8f6dd 100644
--- a/lib/mesa/src/intel/vulkan/anv_nir_lower_ycbcr_textures.c
+++ b/lib/mesa/src/intel/vulkan/anv_nir_lower_ycbcr_textures.c
@@ -25,7 +25,6 @@
 #include "anv_private.h"
 #include "nir/nir.h"
 #include "nir/nir_builder.h"
-#include "nir/nir_vulkan.h"
 
 struct ycbcr_state {
    nir_builder *builder;
@@ -35,6 +34,127 @@ struct ycbcr_state {
    struct anv_ycbcr_conversion *conversion;
 };
 
+static nir_ssa_def *
+y_range(nir_builder *b,
+        nir_ssa_def *y_channel,
+        int bpc,
+        VkSamplerYcbcrRange range)
+{
+   switch (range) {
+   case VK_SAMPLER_YCBCR_RANGE_ITU_FULL:
+      return y_channel;
+   case VK_SAMPLER_YCBCR_RANGE_ITU_NARROW:
+      return nir_fmul(b,
+                      nir_fadd(b,
+                               nir_fmul(b, y_channel,
+                                        nir_imm_float(b, pow(2, bpc) - 1)),
+                               nir_imm_float(b, -16.0f * pow(2, bpc - 8))),
+                      nir_frcp(b, nir_imm_float(b, 219.0f * pow(2, bpc - 8))));
+   default:
+      unreachable("missing Ycbcr range");
+      return NULL;
+   }
+}
+
+static nir_ssa_def *
+chroma_range(nir_builder *b,
+             nir_ssa_def *chroma_channel,
+             int bpc,
+             VkSamplerYcbcrRange range)
+{
+   switch (range) {
+   case VK_SAMPLER_YCBCR_RANGE_ITU_FULL:
+      return nir_fadd(b, chroma_channel,
+                      nir_imm_float(b, -pow(2, bpc - 1) / (pow(2, bpc) - 1.0f)));
+   case VK_SAMPLER_YCBCR_RANGE_ITU_NARROW:
+      return nir_fmul(b,
+                      nir_fadd(b,
+                               nir_fmul(b, chroma_channel,
+                                        nir_imm_float(b, pow(2, bpc) - 1)),
+                               nir_imm_float(b, -128.0f * pow(2, bpc - 8))),
+                      nir_frcp(b, nir_imm_float(b, 224.0f * pow(2, bpc - 8))));
+   default:
+      unreachable("missing Ycbcr range");
+      return NULL;
+   }
+}
+
+typedef struct nir_const_value_3_4 {
+   nir_const_value v[3][4];
+} nir_const_value_3_4;
+
+static const nir_const_value_3_4 *
+ycbcr_model_to_rgb_matrix(VkSamplerYcbcrModelConversion model)
+{
+   switch (model) {
+   case VK_SAMPLER_YCBCR_MODEL_CONVERSION_YCBCR_601: {
+      static const nir_const_value_3_4 bt601 = { {
+         { { .f32 =  1.402f             }, { .f32 = 1.0f }, { .f32 =  0.0f               }, { .f32 = 0.0f } },
+         { { .f32 = -0.714136286201022f }, { .f32 = 1.0f }, { .f32 = -0.344136286201022f }, { .f32 = 0.0f } },
+         { { .f32 =  0.0f               }, { .f32 = 1.0f }, { .f32 =  1.772f             }, { .f32 = 0.0f } },
+      } };
+
+      return &bt601;
+   }
+   case VK_SAMPLER_YCBCR_MODEL_CONVERSION_YCBCR_709: {
+      static const nir_const_value_3_4 bt709 = { {
+         { { .f32 =  1.5748031496063f   }, { .f32 = 1.0f }, { .f32 =  0.0f               }, { .f32 = 0.0f } },
+         { { .f32 = -0.468125209181067f }, { .f32 = 1.0f }, { .f32 = -0.187327487470334f }, { .f32 = 0.0f } },
+         { { .f32 =  0.0f               }, { .f32 = 1.0f }, { .f32 =  1.85563184264242f  }, { .f32 = 0.0f } },
+      } };
+
+      return &bt709;
+   }
+   case VK_SAMPLER_YCBCR_MODEL_CONVERSION_YCBCR_2020: {
+      static const nir_const_value_3_4 bt2020 = { {
+         { { .f32 =  1.4746f            }, { .f32 = 1.0f }, { .f32 =  0.0f               }, { .f32 = 0.0f } },
+         { { .f32 = -0.571353126843658f }, { .f32 = 1.0f }, { .f32 = -0.164553126843658f }, { .f32 = 0.0f } },
+         { { .f32 =  0.0f               }, { .f32 = 1.0f }, { .f32 =  1.8814f            }, { .f32 = 0.0f } },
+      } };
+
+      return &bt2020;
+   }
+   default:
+      unreachable("missing Ycbcr model");
+      return NULL;
+   }
+}
+
+static nir_ssa_def *
+convert_ycbcr(struct ycbcr_state *state,
+              nir_ssa_def *raw_channels,
+              uint32_t *bpcs)
+{
+   nir_builder *b = state->builder;
+   struct anv_ycbcr_conversion *conversion = state->conversion;
+
+   nir_ssa_def *expanded_channels =
+      nir_vec4(b,
+               chroma_range(b, nir_channel(b, raw_channels, 0),
+                            bpcs[0], conversion->ycbcr_range),
+               y_range(b, nir_channel(b, raw_channels, 1),
+                       bpcs[1], conversion->ycbcr_range),
+               chroma_range(b, nir_channel(b, raw_channels, 2),
+                            bpcs[2], conversion->ycbcr_range),
+               nir_imm_float(b, 1.0f));
+
+   if (conversion->ycbcr_model == VK_SAMPLER_YCBCR_MODEL_CONVERSION_YCBCR_IDENTITY)
+      return expanded_channels;
+
+   const nir_const_value_3_4 *conversion_matrix =
+      ycbcr_model_to_rgb_matrix(conversion->ycbcr_model);
+
+   nir_ssa_def *converted_channels[] = {
+      nir_fdot4(b, expanded_channels, nir_build_imm(b, 4, 32, conversion_matrix->v[0])),
+      nir_fdot4(b, expanded_channels, nir_build_imm(b, 4, 32, conversion_matrix->v[1])),
+      nir_fdot4(b, expanded_channels, nir_build_imm(b, 4, 32, conversion_matrix->v[2]))
+   };
+
+   return nir_vec4(b,
+                   converted_channels[0], converted_channels[1],
+                   converted_channels[2], nir_imm_float(b, 1.0f));
+}
+
 /* TODO: we should probably replace this with a push constant/uniform. */
 static nir_ssa_def *
 get_texture_size(struct ycbcr_state *state, nir_deref_instr *texture)
@@ -151,6 +271,7 @@ create_plane_tex_instr_implicit(struct ycbcr_state *state,
    tex->component = old_tex->component;
 
    tex->texture_index = old_tex->texture_index;
+   tex->texture_array_size = old_tex->texture_array_size;
    tex->sampler_index = old_tex->sampler_index;
    tex->is_array = old_tex->is_array;
 
@@ -316,13 +437,8 @@ try_lower_tex_ycbcr(const struct anv_pipeline_layout *layout,
    }
 
    nir_ssa_def *result = nir_vec(builder, swizzled_comp, 4);
-   if (state.conversion->ycbcr_model != VK_SAMPLER_YCBCR_MODEL_CONVERSION_RGB_IDENTITY) {
-      result = nir_convert_ycbcr_to_rgb(builder,
-                                        state.conversion->ycbcr_model,
-                                        state.conversion->ycbcr_range,
-                                        result,
-                                        swizzled_bpcs);
-   }
+   if (state.conversion->ycbcr_model != VK_SAMPLER_YCBCR_MODEL_CONVERSION_RGB_IDENTITY)
+      result = convert_ycbcr(&state, result, swizzled_bpcs);
 
    nir_ssa_def_rewrite_uses(&tex->dest.ssa, nir_src_for_ssa(result));
    nir_instr_remove(&tex->instr);
diff --git a/lib/mesa/src/intel/vulkan/anv_perf.c b/lib/mesa/src/intel/vulkan/anv_perf.c
index 9ee54a8c2..5c8fd5288 100644
--- a/lib/mesa/src/intel/vulkan/anv_perf.c
+++ b/lib/mesa/src/intel/vulkan/anv_perf.c
@@ -83,16 +83,6 @@ anv_device_perf_open(struct anv_device *device, uint64_t metric_id)
    properties[p++] = DRM_I915_PERF_PROP_HOLD_PREEMPTION;
    properties[p++] = true;
 
-   /* If global SSEU is available, pin it to the default. This will ensure on
-    * Gen11 for instance we use the full EU array. Initially when perf was
-    * enabled we would use only half on Gen11 because of functional
-    * requirements.
-    */
-   if (device->physical->perf->i915_perf_version >= 4) {
-      properties[p++] = DRM_I915_PERF_PROP_GLOBAL_SSEU;
-      properties[p++] = (uintptr_t) &device->physical->perf->sseu;
-   }
-
    memset(&param, 0, sizeof(param));
    param.flags = 0;
    param.flags |= I915_PERF_FLAG_FD_CLOEXEC | I915_PERF_FLAG_FD_NONBLOCK;
diff --git a/lib/mesa/src/intel/vulkan/meson.build b/lib/mesa/src/intel/vulkan/meson.build
index 5884ac056..b8d2f1e9e 100644
--- a/lib/mesa/src/intel/vulkan/meson.build
+++ b/lib/mesa/src/intel/vulkan/meson.build
@@ -86,7 +86,7 @@ foreach g : [['70', ['gen7_cmd_buffer.c']], ['75', ['gen7_cmd_buffer.c']],
     'anv_gen@0@'.format(_gen),
     [anv_gen_files, g[1], anv_entrypoints[0], anv_extensions_h],
     include_directories : [
-      inc_include, inc_src, inc_mapi, inc_mesa, inc_gallium, inc_compiler, inc_intel, inc_vulkan_wsi,
+      inc_common, inc_compiler, inc_include, inc_intel, inc_vulkan_wsi,
     ],
     c_args : [
       c_vis_args, no_override_init_args, c_sse2_args,
@@ -180,7 +180,7 @@ libanv_common = static_library(
     gen_xml_pack,
   ],
   include_directories : [
-    inc_include, inc_src, inc_mapi, inc_mesa, inc_gallium, inc_intel, inc_compiler,
+    inc_common, inc_intel, inc_compiler, inc_include,
     inc_vulkan_wsi, inc_util,
   ],
   c_args : anv_flags,
@@ -191,7 +191,7 @@ libvulkan_intel = shared_library(
   'vulkan_intel',
   [files('anv_gem.c'), anv_entrypoints[0], anv_extensions_h],
   include_directories : [
-    inc_include, inc_src, inc_mapi, inc_mesa, inc_gallium, inc_intel, inc_compiler, inc_vulkan_wsi,
+    inc_common, inc_intel, inc_compiler, inc_include, inc_vulkan_wsi,
   ],
   link_whole : [libanv_common, libanv_gen_libs],
   link_with : [
@@ -225,7 +225,7 @@ if with_tests
     'vulkan_intel_test',
     [files('anv_gem_stubs.c'), anv_entrypoints[0], anv_extensions_h],
     include_directories : [
-      inc_include, inc_src, inc_mapi, inc_mesa, inc_gallium, inc_intel, inc_compiler, inc_vulkan_wsi,
+      inc_common, inc_intel, inc_compiler, inc_include, inc_vulkan_wsi,
     ],
     link_whole : libanv_common,
     link_with : [
@@ -251,7 +251,7 @@ if with_tests
         link_with : libvulkan_intel_test,
         dependencies : [dep_libdrm, dep_thread, dep_m, dep_valgrind, idep_vulkan_util, ],
         include_directories : [
-          inc_include, inc_src, inc_mapi, inc_mesa, inc_gallium, inc_intel, inc_compiler, inc_vulkan_wsi,
+          inc_common, inc_intel, inc_compiler, inc_vulkan_wsi,
         ],
       ),
       suite : ['intel'],