diff options
| -rw-r--r-- | dist/Mesa/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp | 13 | ||||
| -rw-r--r-- | dist/Mesa/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp | 5 |
2 files changed, 11 insertions, 7 deletions
diff --git a/dist/Mesa/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp b/dist/Mesa/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp index af8304901..97f6404c0 100644 --- a/dist/Mesa/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp +++ b/dist/Mesa/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp @@ -113,8 +113,10 @@ gen8_fs_generator::generate_fb_write(fs_inst *ir) uint32_t msg_control = msg_type; - /* Set "Last Render Target Select" on the final FB write. */ - if (ir->eot) + /* "Last Render Target Select" must be set on all writes to the last of + * the render targets (if using MRT), or always for a single RT scenario. + */ + if ((ir->target == c->key.nr_color_regions - 1) || !c->key.nr_color_regions) msg_control |= (1 << 4); /* Last Render Target Select */ uint32_t surf_index = @@ -711,8 +713,13 @@ gen8_fs_generator::generate_set_omask(fs_inst *inst, mask.hstride == BRW_HORIZONTAL_STRIDE_0); } + unsigned save_exec_size = default_state.exec_size; + default_state.exec_size = BRW_EXECUTE_8; + gen8_instruction *mov = MOV(dst, retype(mask, dst.type)); gen8_set_mask_control(mov, BRW_MASK_DISABLE); + + default_state.exec_size = save_exec_size; } /** @@ -966,7 +973,7 @@ gen8_fs_generator::generate_code(exec_list *instructions) default_state.mask_control = ir->force_writemask_all; default_state.flag_subreg_nr = ir->flag_subreg; - if (dispatch_width == 16 && !ir->force_uncompressed && !ir->force_sechalf) + if (dispatch_width == 16 && !ir->force_uncompressed) default_state.exec_size = BRW_EXECUTE_16; else default_state.exec_size = BRW_EXECUTE_8; diff --git a/dist/Mesa/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp b/dist/Mesa/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp index 37bcc48e8..00cb17226 100644 --- a/dist/Mesa/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp +++ b/dist/Mesa/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp @@ -183,9 +183,7 @@ gen8_vec4_generator::generate_gs_set_vertex_count(struct brw_reg eot_mrf_header, /* Move the vertex count into the second MRF for the EOT write. */ assert(eot_mrf_header.file == BRW_MESSAGE_REGISTER_FILE); int dst_nr = GEN7_MRF_HACK_START + eot_mrf_header.nr + 1; - gen8_instruction *inst = - MOV(retype(brw_vec8_grf(dst_nr, 0), BRW_REGISTER_TYPE_UD), src); - gen8_set_mask_control(inst, BRW_MASK_DISABLE); + MOV(retype(brw_vec8_grf(dst_nr, 0), BRW_REGISTER_TYPE_UD), src); } void @@ -896,7 +894,6 @@ gen8_vec4_generator::generate_code(exec_list *instructions) default_state.predicate = ir->predicate; default_state.predicate_inverse = ir->predicate_inverse; default_state.saturate = ir->saturate; - default_state.mask_control = ir->force_writemask_all; const unsigned pre_emit_nr_inst = nr_inst; |