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path: root/driver/xf86-video-ati/src/radeon_tv.c
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-rw-r--r--driver/xf86-video-ati/src/radeon_tv.c321
1 files changed, 213 insertions, 108 deletions
diff --git a/driver/xf86-video-ati/src/radeon_tv.c b/driver/xf86-video-ati/src/radeon_tv.c
index 90020b315..eef45d9ed 100644
--- a/driver/xf86-video-ati/src/radeon_tv.c
+++ b/driver/xf86-video-ati/src/radeon_tv.c
@@ -23,6 +23,7 @@
#include "radeon_probe.h"
#include "radeon_version.h"
#include "radeon_tv.h"
+#include "radeon_atombios.h"
/**********************************************************************
*
@@ -140,7 +141,7 @@ static const uint16_t vert_timing_PAL[] =
**********************************************************************/
static const TVModeConstants availableTVModes[] =
{
- {
+ { /* NTSC timing for 27 Mhz ref clk */
800, /* horResolution */
600, /* verResolution */
TV_STD_NTSC, /* standard */
@@ -155,7 +156,7 @@ static const TVModeConstants availableTVModes[] =
4, /* crtcPLL_postDiv */
1022, /* pixToTV */
},
- {
+ { /* PAL timing for 27 Mhz ref clk */
800, /* horResolution */
600, /* verResolution */
TV_STD_PAL, /* standard */
@@ -169,7 +170,22 @@ static const TVModeConstants availableTVModes[] =
231, /* crtcPLL_M */
4, /* crtcPLL_postDiv */
759, /* pixToTV */
- }
+ },
+ { /* NTSC timing for 14 Mhz ref clk */
+ 800, /* horResolution */
+ 600, /* verResolution */
+ TV_STD_NTSC, /* standard */
+ 1018, /* horTotal */
+ 727, /* verTotal */
+ 813, /* horStart */
+ 840, /* horSyncStart */
+ 633, /* verSyncStart */
+ 630627, /* defRestart */
+ 347, /* crtcPLL_N */
+ 14, /* crtcPLL_M */
+ 8, /* crtcPLL_postDiv */
+ 1022, /* pixToTV */
+ },
};
#define N_AVAILABLE_MODES (sizeof(availableModes) / sizeof(availableModes[ 0 ]))
@@ -582,6 +598,9 @@ static Bool RADEONInitTVRestarts(xf86OutputPtr output, RADEONSavePtr save,
DisplayModePtr mode)
{
RADEONOutputPrivatePtr radeon_output = output->driver_private;
+ radeon_tvout_ptr tvout = &radeon_output->tvout;
+ RADEONInfoPtr info = RADEONPTR(output->scrn);
+ RADEONPLLPtr pll = &info->pll;
int restart;
unsigned hTotal;
unsigned vTotal;
@@ -595,30 +614,37 @@ static Bool RADEONInitTVRestarts(xf86OutputPtr output, RADEONSavePtr save,
const TVModeConstants *constPtr;
/* FIXME: need to revisit this when we add more modes */
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M)
- constPtr = &availableTVModes[0];
- else
- constPtr = &availableTVModes[1];
+ if (tvout->tvStd == TV_STD_NTSC ||
+ tvout->tvStd == TV_STD_NTSC_J ||
+ tvout->tvStd == TV_STD_PAL_M) {
+ if (pll->reference_freq == 2700)
+ constPtr = &availableTVModes[0];
+ else
+ constPtr = &availableTVModes[2];
+ } else {
+ if (pll->reference_freq == 2700)
+ constPtr = &availableTVModes[1];
+ else
+ constPtr = &availableTVModes[1]; /* FIXME */
+ }
hTotal = constPtr->horTotal;
vTotal = constPtr->verTotal;
-
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M ||
- radeon_output->tvStd == TV_STD_PAL_60)
+
+ if (tvout->tvStd == TV_STD_NTSC ||
+ tvout->tvStd == TV_STD_NTSC_J ||
+ tvout->tvStd == TV_STD_PAL_M ||
+ tvout->tvStd == TV_STD_PAL_60)
fTotal = NTSC_TV_VFTOTAL + 1;
else
fTotal = PAL_TV_VFTOTAL + 1;
/* Adjust positions 1&2 in hor. code timing table */
- hOffset = radeon_output->hPos * H_POS_UNIT;
+ hOffset = tvout->hPos * H_POS_UNIT;
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M) {
+ if (tvout->tvStd == TV_STD_NTSC ||
+ tvout->tvStd == TV_STD_NTSC_J ||
+ tvout->tvStd == TV_STD_PAL_M) {
/* improve image centering */
hOffset -= 50;
p1 = hor_timing_NTSC[ H_TABLE_POS1 ];
@@ -648,18 +674,18 @@ static Bool RADEONInitTVRestarts(xf86OutputPtr output, RADEONSavePtr save,
* Convert vPos TV lines to n. of CRTC pixels
* Be verrrrry careful when mixing signed & unsigned values in C..
*/
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M ||
- radeon_output->tvStd == TV_STD_PAL_60)
- vOffset = ((int)(vTotal * hTotal) * 2 * radeon_output->vPos) / (int)(NTSC_TV_LINES_PER_FRAME);
+ if (tvout->tvStd == TV_STD_NTSC ||
+ tvout->tvStd == TV_STD_NTSC_J ||
+ tvout->tvStd == TV_STD_PAL_M ||
+ tvout->tvStd == TV_STD_PAL_60)
+ vOffset = ((int)(vTotal * hTotal) * 2 * tvout->vPos) / (int)(NTSC_TV_LINES_PER_FRAME);
else
- vOffset = ((int)(vTotal * hTotal) * 2 * radeon_output->vPos) / (int)(PAL_TV_LINES_PER_FRAME);
+ vOffset = ((int)(vTotal * hTotal) * 2 * tvout->vPos) / (int)(PAL_TV_LINES_PER_FRAME);
restart -= vOffset + hOffset;
ErrorF("computeRestarts: def = %u, h = %d, v = %d, p1=%04x, p2=%04x, restart = %d\n",
- constPtr->defRestart , radeon_output->hPos , radeon_output->vPos , p1 , p2 , restart);
+ constPtr->defRestart , tvout->hPos , tvout->vPos , p1 , p2 , restart);
save->tv_hrestart = restart % hTotal;
restart /= hTotal;
@@ -672,19 +698,19 @@ static Bool RADEONInitTVRestarts(xf86OutputPtr output, RADEONSavePtr save,
(unsigned)save->tv_hrestart);
/* Compute H_INC from hSize */
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M)
+ if (tvout->tvStd == TV_STD_NTSC ||
+ tvout->tvStd == TV_STD_NTSC_J ||
+ tvout->tvStd == TV_STD_PAL_M)
hInc = (uint16_t)((int)(constPtr->horResolution * 4096 * NTSC_TV_CLOCK_T) /
- (radeon_output->hSize * (int)(NTSC_TV_H_SIZE_UNIT) + (int)(NTSC_TV_ZERO_H_SIZE)));
+ (tvout->hSize * (int)(NTSC_TV_H_SIZE_UNIT) + (int)(NTSC_TV_ZERO_H_SIZE)));
else
hInc = (uint16_t)((int)(constPtr->horResolution * 4096 * PAL_TV_CLOCK_T) /
- (radeon_output->hSize * (int)(PAL_TV_H_SIZE_UNIT) + (int)(PAL_TV_ZERO_H_SIZE)));
+ (tvout->hSize * (int)(PAL_TV_H_SIZE_UNIT) + (int)(PAL_TV_ZERO_H_SIZE)));
save->tv_timing_cntl = (save->tv_timing_cntl & ~RADEON_H_INC_MASK) |
((uint32_t)hInc << RADEON_H_INC_SHIFT);
- ErrorF("computeRestarts: hSize=%d,hInc=%u\n" , radeon_output->hSize , hInc);
+ ErrorF("computeRestarts: hSize=%d,hInc=%u\n" , tvout->hSize , hInc);
return hChanged;
}
@@ -695,22 +721,41 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
{
ScrnInfoPtr pScrn = output->scrn;
RADEONOutputPrivatePtr radeon_output = output->driver_private;
+ radeon_tvout_ptr tvout = &radeon_output->tvout;
RADEONInfoPtr info = RADEONPTR(pScrn);
+ RADEONPLLPtr pll = &info->pll;
+ unsigned m, n, p;
unsigned i;
unsigned long vert_space, flicker_removal;
uint32_t tmp;
const TVModeConstants *constPtr;
const uint16_t *hor_timing;
const uint16_t *vert_timing;
+ radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output);
+ radeon_tvdac_ptr tvdac = NULL;
+
+ if (radeon_encoder == NULL)
+ return;
+
+ tvdac = (radeon_tvdac_ptr)radeon_encoder->dev_priv;
+ if (tvdac == NULL)
+ return;
/* FIXME: need to revisit this when we add more modes */
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M)
- constPtr = &availableTVModes[0];
- else
- constPtr = &availableTVModes[1];
+ if (tvout->tvStd == TV_STD_NTSC ||
+ tvout->tvStd == TV_STD_NTSC_J ||
+ tvout->tvStd == TV_STD_PAL_M) {
+ if (pll->reference_freq == 2700)
+ constPtr = &availableTVModes[0];
+ else
+ constPtr = &availableTVModes[2];
+ } else {
+ if (pll->reference_freq == 2700)
+ constPtr = &availableTVModes[1];
+ else
+ constPtr = &availableTVModes[1]; /* FIXME */
+ }
save->tv_crc_cntl = 0;
@@ -732,8 +777,8 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
if (!IS_R300_VARIANT)
save->tv_master_cntl |= RADEON_TVCLK_ALWAYS_ONb;
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J)
+ if (tvout->tvStd == TV_STD_NTSC ||
+ tvout->tvStd == TV_STD_NTSC_J)
save->tv_master_cntl |= RADEON_RESTART_PHASE_FIX;
save->tv_modulator_cntl1 = RADEON_SLEW_RATE_LIMIT
@@ -742,13 +787,13 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
| RADEON_UVFLT_EN
| (6 << RADEON_CY_FILT_BLEND_SHIFT);
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J) {
+ if (tvout->tvStd == TV_STD_NTSC ||
+ tvout->tvStd == TV_STD_NTSC_J) {
save->tv_modulator_cntl1 |= (0x46 << RADEON_SET_UP_LEVEL_SHIFT)
| (0x3b << RADEON_BLANK_LEVEL_SHIFT);
save->tv_modulator_cntl2 = (-111 & RADEON_TV_U_BURST_LEVEL_MASK) |
((0 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT);
- } else if (radeon_output->tvStd == TV_STD_SCART_PAL) {
+ } else if (tvout->tvStd == TV_STD_SCART_PAL) {
save->tv_modulator_cntl1 |= RADEON_ALT_PHASE_EN;
save->tv_modulator_cntl2 = (0 & RADEON_TV_U_BURST_LEVEL_MASK) |
((0 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT);
@@ -770,7 +815,9 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
save->tv_rgb_cntl = (RADEON_RGB_DITHER_EN
| RADEON_TVOUT_SCALE_EN
| (0x0b << RADEON_UVRAM_READ_MARGIN_SHIFT)
- | (0x07 << RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT));
+ | (0x07 << RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT)
+ | RADEON_RGB_ATTEN_SEL(0x3)
+ | RADEON_RGB_ATTEN_VAL(0xc));
if (IsPrimary) {
if (radeon_output->Flags & RADEON_USE_RMX)
@@ -785,10 +832,10 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
save->tv_sync_size = constPtr->horResolution + 8;
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M ||
- radeon_output->tvStd == TV_STD_PAL_60)
+ if (tvout->tvStd == TV_STD_NTSC ||
+ tvout->tvStd == TV_STD_NTSC_J ||
+ tvout->tvStd == TV_STD_PAL_M ||
+ tvout->tvStd == TV_STD_PAL_60)
vert_space = constPtr->verTotal * 2 * 10000 / NTSC_TV_LINES_PER_FRAME;
else
vert_space = constPtr->verTotal * 2 * 10000 / PAL_TV_LINES_PER_FRAME;
@@ -796,16 +843,19 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
save->tv_vscaler_cntl1 = RADEON_Y_W_EN;
save->tv_vscaler_cntl1 =
(save->tv_vscaler_cntl1 & 0xe3ff0000) | (vert_space * (1 << FRAC_BITS) / 10000);
- save->tv_vscaler_cntl1 |= RADEON_RESTART_FIELD;
+
+ if (pll->reference_freq == 2700)
+ save->tv_vscaler_cntl1 |= RADEON_RESTART_FIELD;
+
if (constPtr->horResolution == 1024)
save->tv_vscaler_cntl1 |= (4 << RADEON_Y_DEL_W_SIG_SHIFT);
else
save->tv_vscaler_cntl1 |= (2 << RADEON_Y_DEL_W_SIG_SHIFT);
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M ||
- radeon_output->tvStd == TV_STD_PAL_60)
+ if (tvout->tvStd == TV_STD_NTSC ||
+ tvout->tvStd == TV_STD_NTSC_J ||
+ tvout->tvStd == TV_STD_PAL_M ||
+ tvout->tvStd == TV_STD_PAL_60)
flicker_removal =
(float) constPtr->verTotal * 2.0 / NTSC_TV_LINES_PER_FRAME + 0.5;
else
@@ -841,18 +891,18 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
tmp = (tmp << RADEON_UV_OUTPUT_POST_SCALE_SHIFT) | 0x000b0000;
save->tv_timing_cntl = tmp;
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M ||
- radeon_output->tvStd == TV_STD_PAL_60)
- save->tv_dac_cntl = radeon_output->ntsc_tvdac_adj;
+ if (tvout->tvStd == TV_STD_NTSC ||
+ tvout->tvStd == TV_STD_NTSC_J ||
+ tvout->tvStd == TV_STD_PAL_M ||
+ tvout->tvStd == TV_STD_PAL_60)
+ save->tv_dac_cntl = tvdac->ntsc_tvdac_adj;
else
- save->tv_dac_cntl = radeon_output->pal_tvdac_adj;
+ save->tv_dac_cntl = tvdac->pal_tvdac_adj;
save->tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD);
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J)
+ if (tvout->tvStd == TV_STD_NTSC ||
+ tvout->tvStd == TV_STD_NTSC_J)
save->tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC;
else
save->tv_dac_cntl |= RADEON_TV_DAC_STD_PAL;
@@ -872,19 +922,34 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
}
#endif
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J)
- save->tv_pll_cntl = (NTSC_TV_PLL_M & RADEON_TV_M0LO_MASK) |
- (((NTSC_TV_PLL_M >> 8) & RADEON_TV_M0HI_MASK) << RADEON_TV_M0HI_SHIFT) |
- ((NTSC_TV_PLL_N & RADEON_TV_N0LO_MASK) << RADEON_TV_N0LO_SHIFT) |
- (((NTSC_TV_PLL_N >> 9) & RADEON_TV_N0HI_MASK) << RADEON_TV_N0HI_SHIFT) |
- ((NTSC_TV_PLL_P & RADEON_TV_P_MASK) << RADEON_TV_P_SHIFT);
- else
- save->tv_pll_cntl = (PAL_TV_PLL_M & RADEON_TV_M0LO_MASK) |
- (((PAL_TV_PLL_M >> 8) & RADEON_TV_M0HI_MASK) << RADEON_TV_M0HI_SHIFT) |
- ((PAL_TV_PLL_N & RADEON_TV_N0LO_MASK) << RADEON_TV_N0LO_SHIFT) |
- (((PAL_TV_PLL_N >> 9) & RADEON_TV_N0HI_MASK) << RADEON_TV_N0HI_SHIFT) |
- ((PAL_TV_PLL_P & RADEON_TV_P_MASK) << RADEON_TV_P_SHIFT);
+ if (tvout->tvStd == TV_STD_NTSC ||
+ tvout->tvStd == TV_STD_NTSC_J) {
+ if (pll->reference_freq == 2700) {
+ m = NTSC_TV_PLL_M_27;
+ n = NTSC_TV_PLL_N_27;
+ p = NTSC_TV_PLL_P_27;
+ } else {
+ m = NTSC_TV_PLL_M_14;
+ n = NTSC_TV_PLL_N_14;
+ p = NTSC_TV_PLL_P_14;
+ }
+ } else {
+ if (pll->reference_freq == 2700) {
+ m = PAL_TV_PLL_M_27;
+ n = PAL_TV_PLL_N_27;
+ p = PAL_TV_PLL_P_27;
+ } else {
+ /* FIXME */
+ m = PAL_TV_PLL_M_27;
+ n = PAL_TV_PLL_N_27;
+ p = PAL_TV_PLL_P_27;
+ }
+ }
+ save->tv_pll_cntl = (m & RADEON_TV_M0LO_MASK) |
+ (((m >> 8) & RADEON_TV_M0HI_MASK) << RADEON_TV_M0HI_SHIFT) |
+ ((n & RADEON_TV_N0LO_MASK) << RADEON_TV_N0LO_SHIFT) |
+ (((n >> 9) & RADEON_TV_N0HI_MASK) << RADEON_TV_N0HI_SHIFT) |
+ ((p & RADEON_TV_P_MASK) << RADEON_TV_P_SHIFT);
save->tv_pll_cntl1 = (((4 & RADEON_TVPCP_MASK)<< RADEON_TVPCP_SHIFT) |
((4 & RADEON_TVPVG_MASK) << RADEON_TVPVG_SHIFT) |
@@ -898,28 +963,28 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
save->tv_vdisp = constPtr->verResolution - 1;
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M ||
- radeon_output->tvStd == TV_STD_PAL_60)
+ if (tvout->tvStd == TV_STD_NTSC ||
+ tvout->tvStd == TV_STD_NTSC_J ||
+ tvout->tvStd == TV_STD_PAL_M ||
+ tvout->tvStd == TV_STD_PAL_60)
save->tv_ftotal = NTSC_TV_VFTOTAL;
else
save->tv_ftotal = PAL_TV_VFTOTAL;
save->tv_vtotal = constPtr->verTotal - 1;
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M) {
+ if (tvout->tvStd == TV_STD_NTSC ||
+ tvout->tvStd == TV_STD_NTSC_J ||
+ tvout->tvStd == TV_STD_PAL_M) {
hor_timing = hor_timing_NTSC;
} else {
hor_timing = hor_timing_PAL;
}
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M ||
- radeon_output->tvStd == TV_STD_PAL_60) {
+ if (tvout->tvStd == TV_STD_NTSC ||
+ tvout->tvStd == TV_STD_NTSC_J ||
+ tvout->tvStd == TV_STD_PAL_M ||
+ tvout->tvStd == TV_STD_PAL_60) {
vert_timing = vert_timing_NTSC;
} else {
vert_timing = vert_timing_PAL;
@@ -999,14 +1064,24 @@ void RADEONAdjustCrtcRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
{
const TVModeConstants *constPtr;
RADEONOutputPrivatePtr radeon_output = output->driver_private;
+ radeon_tvout_ptr tvout = &radeon_output->tvout;
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ RADEONPLLPtr pll = &info->pll;
/* FIXME: need to revisit this when we add more modes */
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M)
- constPtr = &availableTVModes[0];
- else
- constPtr = &availableTVModes[1];
+ if (tvout->tvStd == TV_STD_NTSC ||
+ tvout->tvStd == TV_STD_NTSC_J ||
+ tvout->tvStd == TV_STD_PAL_M) {
+ if (pll->reference_freq == 2700)
+ constPtr = &availableTVModes[0];
+ else
+ constPtr = &availableTVModes[2];
+ } else {
+ if (pll->reference_freq == 2700)
+ constPtr = &availableTVModes[1];
+ else
+ constPtr = &availableTVModes[1]; /* FIXME */
+ }
save->crtc_h_total_disp = (((constPtr->horResolution / 8) - 1) << RADEON_CRTC_H_DISP_SHIFT) |
(((constPtr->horTotal / 8) - 1) << RADEON_CRTC_H_TOTAL_SHIFT);
@@ -1030,14 +1105,24 @@ void RADEONAdjustPLLRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
unsigned postDiv;
const TVModeConstants *constPtr;
RADEONOutputPrivatePtr radeon_output = output->driver_private;
+ radeon_tvout_ptr tvout = &radeon_output->tvout;
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ RADEONPLLPtr pll = &info->pll;
/* FIXME: need to revisit this when we add more modes */
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M)
- constPtr = &availableTVModes[0];
- else
- constPtr = &availableTVModes[1];
+ if (tvout->tvStd == TV_STD_NTSC ||
+ tvout->tvStd == TV_STD_NTSC_J ||
+ tvout->tvStd == TV_STD_PAL_M) {
+ if (pll->reference_freq == 2700)
+ constPtr = &availableTVModes[0];
+ else
+ constPtr = &availableTVModes[2];
+ } else {
+ if (pll->reference_freq == 2700)
+ constPtr = &availableTVModes[1];
+ else
+ constPtr = &availableTVModes[1]; /* FIXME */
+ }
save->htotal_cntl = (constPtr->horTotal & 0x7 /*0xf*/) | RADEON_HTOT_CNTL_VGA_EN;
@@ -1083,14 +1168,24 @@ void RADEONAdjustCrtc2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
{
const TVModeConstants *constPtr;
RADEONOutputPrivatePtr radeon_output = output->driver_private;
+ radeon_tvout_ptr tvout = &radeon_output->tvout;
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ RADEONPLLPtr pll = &info->pll;
/* FIXME: need to revisit this when we add more modes */
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M)
- constPtr = &availableTVModes[0];
- else
- constPtr = &availableTVModes[1];
+ if (tvout->tvStd == TV_STD_NTSC ||
+ tvout->tvStd == TV_STD_NTSC_J ||
+ tvout->tvStd == TV_STD_PAL_M) {
+ if (pll->reference_freq == 2700)
+ constPtr = &availableTVModes[0];
+ else
+ constPtr = &availableTVModes[2];
+ } else {
+ if (pll->reference_freq == 2700)
+ constPtr = &availableTVModes[1];
+ else
+ constPtr = &availableTVModes[1]; /* FIXME */
+ }
save->crtc2_h_total_disp = (((constPtr->horResolution / 8) - 1) << RADEON_CRTC_H_DISP_SHIFT) |
(((constPtr->horTotal / 8) - 1) << RADEON_CRTC_H_TOTAL_SHIFT);
@@ -1114,14 +1209,24 @@ void RADEONAdjustPLL2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
unsigned postDiv;
const TVModeConstants *constPtr;
RADEONOutputPrivatePtr radeon_output = output->driver_private;
+ radeon_tvout_ptr tvout = &radeon_output->tvout;
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ RADEONPLLPtr pll = &info->pll;
/* FIXME: need to revisit this when we add more modes */
- if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M)
- constPtr = &availableTVModes[0];
- else
- constPtr = &availableTVModes[1];
+ if (tvout->tvStd == TV_STD_NTSC ||
+ tvout->tvStd == TV_STD_NTSC_J ||
+ tvout->tvStd == TV_STD_PAL_M) {
+ if (pll->reference_freq == 2700)
+ constPtr = &availableTVModes[0];
+ else
+ constPtr = &availableTVModes[2];
+ } else {
+ if (pll->reference_freq == 2700)
+ constPtr = &availableTVModes[1];
+ else
+ constPtr = &availableTVModes[1]; /* FIXME */
+ }
save->htotal_cntl2 = (constPtr->horTotal & 0x7); /* 0xf */
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-12 17:50:49 +0000