diff options
Diffstat (limited to 'lib/libdrm/intel/intel_chipset.h')
| -rw-r--r-- | lib/libdrm/intel/intel_chipset.h | 254 |
1 files changed, 11 insertions, 243 deletions
diff --git a/lib/libdrm/intel/intel_chipset.h b/lib/libdrm/intel/intel_chipset.h index 4a34b7bed..5db207ccb 100644 --- a/lib/libdrm/intel/intel_chipset.h +++ b/lib/libdrm/intel/intel_chipset.h @@ -165,111 +165,8 @@ #define PCI_CHIP_CHERRYVIEW_2 0x22b2 #define PCI_CHIP_CHERRYVIEW_3 0x22b3 -#define PCI_CHIP_SKYLAKE_DT_GT1 0x1902 -#define PCI_CHIP_SKYLAKE_ULT_GT1 0x1906 -#define PCI_CHIP_SKYLAKE_SRV_GT1 0x190A /* Reserved */ -#define PCI_CHIP_SKYLAKE_H_GT1 0x190B -#define PCI_CHIP_SKYLAKE_ULX_GT1 0x190E /* Reserved */ #define PCI_CHIP_SKYLAKE_DT_GT2 0x1912 -#define PCI_CHIP_SKYLAKE_FUSED0_GT2 0x1913 /* Reserved */ -#define PCI_CHIP_SKYLAKE_FUSED1_GT2 0x1915 /* Reserved */ -#define PCI_CHIP_SKYLAKE_ULT_GT2 0x1916 -#define PCI_CHIP_SKYLAKE_FUSED2_GT2 0x1917 /* Reserved */ -#define PCI_CHIP_SKYLAKE_SRV_GT2 0x191A /* Reserved */ -#define PCI_CHIP_SKYLAKE_HALO_GT2 0x191B -#define PCI_CHIP_SKYLAKE_WKS_GT2 0x191D -#define PCI_CHIP_SKYLAKE_ULX_GT2 0x191E -#define PCI_CHIP_SKYLAKE_MOBILE_GT2 0x1921 /* Reserved */ -#define PCI_CHIP_SKYLAKE_ULT_GT3_0 0x1923 -#define PCI_CHIP_SKYLAKE_ULT_GT3_1 0x1926 -#define PCI_CHIP_SKYLAKE_ULT_GT3_2 0x1927 -#define PCI_CHIP_SKYLAKE_SRV_GT4 0x192A -#define PCI_CHIP_SKYLAKE_HALO_GT3 0x192B /* Reserved */ -#define PCI_CHIP_SKYLAKE_SRV_GT3 0x192D -#define PCI_CHIP_SKYLAKE_DT_GT4 0x1932 -#define PCI_CHIP_SKYLAKE_SRV_GT4X 0x193A -#define PCI_CHIP_SKYLAKE_H_GT4 0x193B -#define PCI_CHIP_SKYLAKE_WKS_GT4 0x193D - -#define PCI_CHIP_KABYLAKE_ULT_GT2 0x5916 -#define PCI_CHIP_KABYLAKE_ULT_GT1_5 0x5913 -#define PCI_CHIP_KABYLAKE_ULT_GT1 0x5906 -#define PCI_CHIP_KABYLAKE_ULT_GT3_0 0x5923 -#define PCI_CHIP_KABYLAKE_ULT_GT3_1 0x5926 -#define PCI_CHIP_KABYLAKE_ULT_GT3_2 0x5927 -#define PCI_CHIP_KABYLAKE_ULT_GT2F 0x5921 -#define PCI_CHIP_KABYLAKE_ULX_GT1_5 0x5915 -#define PCI_CHIP_KABYLAKE_ULX_GT1 0x590E -#define PCI_CHIP_KABYLAKE_ULX_GT2_0 0x591E #define PCI_CHIP_KABYLAKE_DT_GT2 0x5912 -#define PCI_CHIP_KABYLAKE_M_GT2 0x5917 -#define PCI_CHIP_KABYLAKE_DT_GT1 0x5902 -#define PCI_CHIP_KABYLAKE_HALO_GT2 0x591B -#define PCI_CHIP_KABYLAKE_HALO_GT4 0x593B -#define PCI_CHIP_KABYLAKE_HALO_GT1_0 0x5908 -#define PCI_CHIP_KABYLAKE_HALO_GT1_1 0x590B -#define PCI_CHIP_KABYLAKE_SRV_GT2 0x591A -#define PCI_CHIP_KABYLAKE_SRV_GT1 0x590A -#define PCI_CHIP_KABYLAKE_WKS_GT2 0x591D - -#define PCI_CHIP_AMBERLAKE_ULX_GT2_1 0x591C -#define PCI_CHIP_AMBERLAKE_ULX_GT2_2 0x87C0 - -#define PCI_CHIP_BROXTON_0 0x0A84 -#define PCI_CHIP_BROXTON_1 0x1A84 -#define PCI_CHIP_BROXTON_2 0x5A84 -#define PCI_CHIP_BROXTON_3 0x1A85 -#define PCI_CHIP_BROXTON_4 0x5A85 - -#define PCI_CHIP_GLK 0x3184 -#define PCI_CHIP_GLK_2X6 0x3185 - -#define PCI_CHIP_COFFEELAKE_S_GT1_1 0x3E90 -#define PCI_CHIP_COFFEELAKE_S_GT1_2 0x3E93 -#define PCI_CHIP_COFFEELAKE_S_GT1_3 0x3E99 -#define PCI_CHIP_COFFEELAKE_S_GT2_1 0x3E91 -#define PCI_CHIP_COFFEELAKE_S_GT2_2 0x3E92 -#define PCI_CHIP_COFFEELAKE_S_GT2_3 0x3E96 -#define PCI_CHIP_COFFEELAKE_S_GT2_4 0x3E98 -#define PCI_CHIP_COFFEELAKE_S_GT2_5 0x3E9A -#define PCI_CHIP_COFFEELAKE_H_GT2_1 0x3E9B -#define PCI_CHIP_COFFEELAKE_H_GT2_2 0x3E94 -#define PCI_CHIP_COFFEELAKE_U_GT2_1 0x3EA9 -#define PCI_CHIP_COFFEELAKE_U_GT3_1 0x3EA5 -#define PCI_CHIP_COFFEELAKE_U_GT3_2 0x3EA6 -#define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA7 -#define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA8 - -#define PCI_CHIP_WHISKEYLAKE_U_GT1_1 0x3EA1 -#define PCI_CHIP_WHISKEYLAKE_U_GT2_1 0x3EA0 -#define PCI_CHIP_WHISKEYLAKE_U_GT3_1 0x3EA2 -#define PCI_CHIP_WHISKEYLAKE_U_GT3_2 0x3EA3 -#define PCI_CHIP_WHISKEYLAKE_U_GT3_3 0x3EA4 - -#define PCI_CHIP_CANNONLAKE_0 0x5A51 -#define PCI_CHIP_CANNONLAKE_1 0x5A59 -#define PCI_CHIP_CANNONLAKE_2 0x5A41 -#define PCI_CHIP_CANNONLAKE_3 0x5A49 -#define PCI_CHIP_CANNONLAKE_4 0x5A52 -#define PCI_CHIP_CANNONLAKE_5 0x5A5A -#define PCI_CHIP_CANNONLAKE_6 0x5A42 -#define PCI_CHIP_CANNONLAKE_7 0x5A4A -#define PCI_CHIP_CANNONLAKE_8 0x5A50 -#define PCI_CHIP_CANNONLAKE_9 0x5A40 -#define PCI_CHIP_CANNONLAKE_10 0x5A54 -#define PCI_CHIP_CANNONLAKE_11 0x5A5C -#define PCI_CHIP_CANNONLAKE_12 0x5A44 -#define PCI_CHIP_CANNONLAKE_13 0x5A4C - -#define PCI_CHIP_ICELAKE_11_0 0x8A50 -#define PCI_CHIP_ICELAKE_11_1 0x8A51 -#define PCI_CHIP_ICELAKE_11_2 0x8A5C -#define PCI_CHIP_ICELAKE_11_3 0x8A5D -#define PCI_CHIP_ICELAKE_11_4 0x8A52 -#define PCI_CHIP_ICELAKE_11_5 0x8A5A -#define PCI_CHIP_ICELAKE_11_6 0x8A5B -#define PCI_CHIP_ICELAKE_11_7 0x8A71 -#define PCI_CHIP_ICELAKE_11_8 0x8A70 #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \ (devid) == PCI_CHIP_I915_GM || \ @@ -430,143 +327,16 @@ #define IS_GEN8(devid) (IS_BROADWELL(devid) || \ IS_CHERRYVIEW(devid)) -#define IS_SKL_GT1(devid) ((devid) == PCI_CHIP_SKYLAKE_DT_GT1 || \ - (devid) == PCI_CHIP_SKYLAKE_ULT_GT1 || \ - (devid) == PCI_CHIP_SKYLAKE_SRV_GT1 || \ - (devid) == PCI_CHIP_SKYLAKE_H_GT1 || \ - (devid) == PCI_CHIP_SKYLAKE_ULX_GT1) - -#define IS_SKL_GT2(devid) ((devid) == PCI_CHIP_SKYLAKE_DT_GT2 || \ - (devid) == PCI_CHIP_SKYLAKE_FUSED0_GT2 || \ - (devid) == PCI_CHIP_SKYLAKE_FUSED1_GT2 || \ - (devid) == PCI_CHIP_SKYLAKE_ULT_GT2 || \ - (devid) == PCI_CHIP_SKYLAKE_FUSED2_GT2 || \ - (devid) == PCI_CHIP_SKYLAKE_SRV_GT2 || \ - (devid) == PCI_CHIP_SKYLAKE_HALO_GT2 || \ - (devid) == PCI_CHIP_SKYLAKE_WKS_GT2 || \ - (devid) == PCI_CHIP_SKYLAKE_ULX_GT2 || \ - (devid) == PCI_CHIP_SKYLAKE_MOBILE_GT2) - -#define IS_SKL_GT3(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT3_0 || \ - (devid) == PCI_CHIP_SKYLAKE_ULT_GT3_1 || \ - (devid) == PCI_CHIP_SKYLAKE_ULT_GT3_2 || \ - (devid) == PCI_CHIP_SKYLAKE_HALO_GT3 || \ - (devid) == PCI_CHIP_SKYLAKE_SRV_GT3) - -#define IS_SKL_GT4(devid) ((devid) == PCI_CHIP_SKYLAKE_SRV_GT4 || \ - (devid) == PCI_CHIP_SKYLAKE_DT_GT4 || \ - (devid) == PCI_CHIP_SKYLAKE_SRV_GT4X || \ - (devid) == PCI_CHIP_SKYLAKE_H_GT4 || \ - (devid) == PCI_CHIP_SKYLAKE_WKS_GT4) - -#define IS_KBL_GT1(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT1_5 || \ - (devid) == PCI_CHIP_KABYLAKE_ULX_GT1_5 || \ - (devid) == PCI_CHIP_KABYLAKE_ULT_GT1 || \ - (devid) == PCI_CHIP_KABYLAKE_ULX_GT1 || \ - (devid) == PCI_CHIP_KABYLAKE_DT_GT1 || \ - (devid) == PCI_CHIP_KABYLAKE_HALO_GT1_0 || \ - (devid) == PCI_CHIP_KABYLAKE_HALO_GT1_1 || \ - (devid) == PCI_CHIP_KABYLAKE_SRV_GT1) - -#define IS_KBL_GT2(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT2 || \ - (devid) == PCI_CHIP_KABYLAKE_ULT_GT2F || \ - (devid) == PCI_CHIP_KABYLAKE_ULX_GT2_0 || \ - (devid) == PCI_CHIP_KABYLAKE_DT_GT2 || \ - (devid) == PCI_CHIP_KABYLAKE_M_GT2 || \ - (devid) == PCI_CHIP_KABYLAKE_HALO_GT2 || \ - (devid) == PCI_CHIP_KABYLAKE_SRV_GT2 || \ - (devid) == PCI_CHIP_KABYLAKE_WKS_GT2 || \ - (devid) == PCI_CHIP_AMBERLAKE_ULX_GT2_1 || \ - (devid) == PCI_CHIP_AMBERLAKE_ULX_GT2_2) - -#define IS_KBL_GT3(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT3_0 || \ - (devid) == PCI_CHIP_KABYLAKE_ULT_GT3_1 || \ - (devid) == PCI_CHIP_KABYLAKE_ULT_GT3_2) - -#define IS_KBL_GT4(devid) ((devid) == PCI_CHIP_KABYLAKE_HALO_GT4) - -#define IS_KABYLAKE(devid) (IS_KBL_GT1(devid) || \ - IS_KBL_GT2(devid) || \ - IS_KBL_GT3(devid) || \ - IS_KBL_GT4(devid)) - -#define IS_SKYLAKE(devid) (IS_SKL_GT1(devid) || \ - IS_SKL_GT2(devid) || \ - IS_SKL_GT3(devid) || \ - IS_SKL_GT4(devid)) - -#define IS_BROXTON(devid) ((devid) == PCI_CHIP_BROXTON_0 || \ - (devid) == PCI_CHIP_BROXTON_1 || \ - (devid) == PCI_CHIP_BROXTON_2 || \ - (devid) == PCI_CHIP_BROXTON_3 || \ - (devid) == PCI_CHIP_BROXTON_4) - -#define IS_GEMINILAKE(devid) ((devid) == PCI_CHIP_GLK || \ - (devid) == PCI_CHIP_GLK_2X6) - -#define IS_CFL_S(devid) ((devid) == PCI_CHIP_COFFEELAKE_S_GT1_1 || \ - (devid) == PCI_CHIP_COFFEELAKE_S_GT1_2 || \ - (devid) == PCI_CHIP_COFFEELAKE_S_GT1_3 || \ - (devid) == PCI_CHIP_COFFEELAKE_S_GT2_1 || \ - (devid) == PCI_CHIP_COFFEELAKE_S_GT2_2 || \ - (devid) == PCI_CHIP_COFFEELAKE_S_GT2_3 || \ - (devid) == PCI_CHIP_COFFEELAKE_S_GT2_4 || \ - (devid) == PCI_CHIP_COFFEELAKE_S_GT2_5) - -#define IS_CFL_H(devid) ((devid) == PCI_CHIP_COFFEELAKE_H_GT2_1 || \ - (devid) == PCI_CHIP_COFFEELAKE_H_GT2_2) - -#define IS_CFL_U(devid) ((devid) == PCI_CHIP_COFFEELAKE_U_GT2_1 || \ - (devid) == PCI_CHIP_COFFEELAKE_U_GT3_1 || \ - (devid) == PCI_CHIP_COFFEELAKE_U_GT3_2 || \ - (devid) == PCI_CHIP_COFFEELAKE_U_GT3_3 || \ - (devid) == PCI_CHIP_COFFEELAKE_U_GT3_4 || \ - (devid) == PCI_CHIP_WHISKEYLAKE_U_GT1_1 || \ - (devid) == PCI_CHIP_WHISKEYLAKE_U_GT2_1 || \ - (devid) == PCI_CHIP_WHISKEYLAKE_U_GT3_1 || \ - (devid) == PCI_CHIP_WHISKEYLAKE_U_GT3_2 || \ - (devid) == PCI_CHIP_WHISKEYLAKE_U_GT3_3) - -#define IS_COFFEELAKE(devid) (IS_CFL_S(devid) || \ - IS_CFL_H(devid) || \ - IS_CFL_U(devid)) - -#define IS_GEN9(devid) (IS_SKYLAKE(devid) || \ - IS_BROXTON(devid) || \ - IS_KABYLAKE(devid) || \ - IS_GEMINILAKE(devid) || \ - IS_COFFEELAKE(devid)) - -#define IS_CANNONLAKE(devid) ((devid) == PCI_CHIP_CANNONLAKE_0 || \ - (devid) == PCI_CHIP_CANNONLAKE_1 || \ - (devid) == PCI_CHIP_CANNONLAKE_2 || \ - (devid) == PCI_CHIP_CANNONLAKE_3 || \ - (devid) == PCI_CHIP_CANNONLAKE_4 || \ - (devid) == PCI_CHIP_CANNONLAKE_5 || \ - (devid) == PCI_CHIP_CANNONLAKE_6 || \ - (devid) == PCI_CHIP_CANNONLAKE_7 || \ - (devid) == PCI_CHIP_CANNONLAKE_8 || \ - (devid) == PCI_CHIP_CANNONLAKE_9 || \ - (devid) == PCI_CHIP_CANNONLAKE_10 || \ - (devid) == PCI_CHIP_CANNONLAKE_11 || \ - (devid) == PCI_CHIP_CANNONLAKE_12 || \ - (devid) == PCI_CHIP_CANNONLAKE_13) - -#define IS_GEN10(devid) (IS_CANNONLAKE(devid)) - -#define IS_ICELAKE_11(devid) ((devid) == PCI_CHIP_ICELAKE_11_0 || \ - (devid) == PCI_CHIP_ICELAKE_11_1 || \ - (devid) == PCI_CHIP_ICELAKE_11_2 || \ - (devid) == PCI_CHIP_ICELAKE_11_3 || \ - (devid) == PCI_CHIP_ICELAKE_11_4 || \ - (devid) == PCI_CHIP_ICELAKE_11_5 || \ - (devid) == PCI_CHIP_ICELAKE_11_6 || \ - (devid) == PCI_CHIP_ICELAKE_11_7 || \ - (devid) == PCI_CHIP_ICELAKE_11_8) - -#define IS_ICELAKE(devid) (IS_ICELAKE_11(devid)) - -#define IS_GEN11(devid) (IS_ICELAKE_11(devid)) +/* New platforms use kernel pci ids */ +#include <stdbool.h> +#include <libdrm_macros.h> + +drm_private bool intel_is_genx(unsigned int devid, int gen); +drm_private bool intel_get_genx(unsigned int devid, int *gen); + +#define IS_GEN9(devid) intel_is_genx(devid, 9) +#define IS_GEN10(devid) intel_is_genx(devid, 10) +#define IS_GEN11(devid) intel_is_genx(devid, 11) #define IS_9XX(dev) (IS_GEN3(dev) || \ IS_GEN4(dev) || \ @@ -574,8 +344,6 @@ IS_GEN6(dev) || \ IS_GEN7(dev) || \ IS_GEN8(dev) || \ - IS_GEN9(dev) || \ - IS_GEN10(dev) || \ - IS_GEN11(dev)) + intel_get_genx(dev, NULL)) #endif /* _INTEL_CHIPSET_H */ |