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Diffstat (limited to 'lib/mesa/src/gallium/drivers/iris/iris_screen.c')
-rw-r--r--lib/mesa/src/gallium/drivers/iris/iris_screen.c493
1 files changed, 128 insertions, 365 deletions
diff --git a/lib/mesa/src/gallium/drivers/iris/iris_screen.c b/lib/mesa/src/gallium/drivers/iris/iris_screen.c
index 6834b083e..10b1b5969 100644
--- a/lib/mesa/src/gallium/drivers/iris/iris_screen.c
+++ b/lib/mesa/src/gallium/drivers/iris/iris_screen.c
@@ -38,10 +38,8 @@
#include "pipe/p_context.h"
#include "pipe/p_screen.h"
#include "util/debug.h"
-#include "util/os_file.h"
-#include "util/u_cpu_detect.h"
#include "util/u_inlines.h"
-#include "util/format/u_format.h"
+#include "util/u_format.h"
#include "util/u_transfer_helper.h"
#include "util/u_upload_mgr.h"
#include "util/ralloc.h"
@@ -53,33 +51,17 @@
#include "iris_pipe.h"
#include "iris_resource.h"
#include "iris_screen.h"
-#include "compiler/glsl_types.h"
#include "intel/compiler/brw_compiler.h"
-#include "intel/common/intel_gem.h"
-#include "intel/common/intel_l3_config.h"
-#include "intel/common/intel_uuid.h"
+#include "intel/common/gen_gem.h"
#include "iris_monitor.h"
-#define genX_call(devinfo, func, ...) \
- switch ((devinfo)->verx10) { \
- case 125: \
- gfx125_##func(__VA_ARGS__); \
- break; \
- case 120: \
- gfx12_##func(__VA_ARGS__); \
- break; \
- case 110: \
- gfx11_##func(__VA_ARGS__); \
- break; \
- case 90: \
- gfx9_##func(__VA_ARGS__); \
- break; \
- case 80: \
- gfx8_##func(__VA_ARGS__); \
- break; \
- default: \
- unreachable("Unknown hardware generation"); \
- }
+static void
+iris_flush_frontbuffer(struct pipe_screen *_screen,
+ struct pipe_resource *resource,
+ unsigned level, unsigned layer,
+ void *context_private, struct pipe_box *box)
+{
+}
static const char *
iris_get_vendor(struct pipe_screen *pscreen)
@@ -93,104 +75,39 @@ iris_get_device_vendor(struct pipe_screen *pscreen)
return "Intel";
}
-static void
-iris_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
-{
- struct iris_screen *screen = (struct iris_screen *)pscreen;
-
- intel_uuid_compute_device_id((uint8_t *)uuid, &screen->devinfo, PIPE_UUID_SIZE);
-}
-
-static void
-iris_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
-{
- struct iris_screen *screen = (struct iris_screen *)pscreen;
- const struct intel_device_info *devinfo = &screen->devinfo;
-
- intel_uuid_compute_driver_id((uint8_t *)uuid, devinfo, PIPE_UUID_SIZE);
-}
-
-static bool
-iris_enable_clover()
-{
- static int enable = -1;
- if (enable < 0)
- enable = env_var_as_boolean("IRIS_ENABLE_CLOVER", false);
- return enable;
-}
-
-static void
-iris_warn_clover()
-{
- static bool warned = false;
- if (warned)
- return;
-
- warned = true;
- fprintf(stderr, "WARNING: OpenCL support via iris+clover is incomplete.\n"
- "For a complete and conformant OpenCL implementation, use\n"
- "https://github.com/intel/compute-runtime instead\n");
-}
-
static const char *
iris_get_name(struct pipe_screen *pscreen)
{
struct iris_screen *screen = (struct iris_screen *)pscreen;
- const struct intel_device_info *devinfo = &screen->devinfo;
static char buf[128];
+ const char *chipset;
+
+ switch (screen->pci_id) {
+#undef CHIPSET
+#define CHIPSET(id, symbol, str) case id: chipset = str; break;
+#include "pci_ids/i965_pci_ids.h"
+ default:
+ chipset = "Unknown Intel Chipset";
+ break;
+ }
- snprintf(buf, sizeof(buf), "Mesa %s", devinfo->name);
+ snprintf(buf, sizeof(buf), "Mesa %s", chipset);
return buf;
}
-static int
-iris_get_video_memory(struct iris_screen *screen)
+static uint64_t
+get_aperture_size(int fd)
{
- uint64_t vram = iris_bufmgr_vram_size(screen->bufmgr);
- uint64_t sram = iris_bufmgr_sram_size(screen->bufmgr);
- uint64_t osmem;
- if (vram) {
- return vram / (1024 * 1024);
- } else if (sram) {
- return sram / (1024 * 1024);
- } else if (os_get_available_system_memory(&osmem)) {
- return osmem / (1024 * 1024);
- } else {
- /* This is the old code path, it get the GGTT size from the kernel
- * (which should always be 4Gb on Gfx8+).
- *
- * We should probably never end up here. This is just a fallback to get
- * some kind of value in case os_get_available_system_memory fails.
- */
- const struct intel_device_info *devinfo = &screen->devinfo;
- /* Once a batch uses more than 75% of the maximum mappable size, we
- * assume that there's some fragmentation, and we start doing extra
- * flushing, etc. That's the big cliff apps will care about.
- */
- const unsigned gpu_mappable_megabytes =
- (devinfo->aperture_bytes * 3 / 4) / (1024 * 1024);
-
- const long system_memory_pages = sysconf(_SC_PHYS_PAGES);
- const long system_page_size = sysconf(_SC_PAGE_SIZE);
-
- if (system_memory_pages <= 0 || system_page_size <= 0)
- return -1;
-
- const uint64_t system_memory_bytes =
- (uint64_t) system_memory_pages * (uint64_t) system_page_size;
-
- const unsigned system_memory_megabytes =
- (unsigned) (system_memory_bytes / (1024 * 1024));
-
- return MIN2(system_memory_megabytes, gpu_mappable_megabytes);
- }
+ struct drm_i915_gem_get_aperture aperture = {};
+ gen_ioctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
+ return aperture.aper_size;
}
static int
iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
{
struct iris_screen *screen = (struct iris_screen *)pscreen;
- const struct intel_device_info *devinfo = &screen->devinfo;
+ const struct gen_device_info *devinfo = &screen->devinfo;
switch (param) {
case PIPE_CAP_NPOT_TEXTURES:
@@ -205,14 +122,13 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
case PIPE_CAP_VERTEX_SHADER_SATURATE:
case PIPE_CAP_PRIMITIVE_RESTART:
- case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
case PIPE_CAP_INDEP_BLEND_ENABLE:
case PIPE_CAP_INDEP_BLEND_FUNC:
case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
- case PIPE_CAP_FS_COORD_ORIGIN_UPPER_LEFT:
- case PIPE_CAP_FS_COORD_PIXEL_CENTER_INTEGER:
+ case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
+ case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
case PIPE_CAP_DEPTH_CLIP_DISABLE:
- case PIPE_CAP_VS_INSTANCEID:
+ case PIPE_CAP_TGSI_INSTANCEID:
case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
case PIPE_CAP_SEAMLESS_CUBE_MAP:
@@ -236,10 +152,10 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_MULTI_DRAW_INDIRECT:
case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
- case PIPE_CAP_VS_LAYER_VIEWPORT:
- case PIPE_CAP_TES_LAYER_VIEWPORT:
- case PIPE_CAP_FS_FINE_DERIVATIVE:
- case PIPE_CAP_SHADER_PACK_HALF_FLOAT:
+ case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
+ case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
+ case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
+ case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
case PIPE_CAP_ACCELERATED:
case PIPE_CAP_UMA:
case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
@@ -263,39 +179,28 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_QUERY_SO_OVERFLOW:
case PIPE_CAP_QUERY_BUFFER_OBJECT:
case PIPE_CAP_TGSI_TEX_TXF_LZ:
- case PIPE_CAP_TEXTURE_QUERY_SAMPLES:
- case PIPE_CAP_SHADER_CLOCK:
- case PIPE_CAP_SHADER_BALLOT:
+ case PIPE_CAP_TGSI_TXQS:
+ case PIPE_CAP_TGSI_CLOCK:
+ case PIPE_CAP_TGSI_BALLOT:
case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
case PIPE_CAP_CLEAR_TEXTURE:
- case PIPE_CAP_CLEAR_SCISSORED:
- case PIPE_CAP_SHADER_GROUP_VOTE:
- case PIPE_CAP_VS_WINDOW_SPACE_POSITION:
+ case PIPE_CAP_TGSI_VOTE:
+ case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
case PIPE_CAP_TEXTURE_GATHER_SM5:
- case PIPE_CAP_SHADER_ARRAY_COMPONENTS:
+ case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
case PIPE_CAP_LOAD_CONSTBUF:
case PIPE_CAP_NIR_COMPACT_ARRAYS:
case PIPE_CAP_DRAW_PARAMETERS:
- case PIPE_CAP_FS_POSITION_IS_SYSVAL:
- case PIPE_CAP_FS_FACE_IS_INTEGER_SYSVAL:
+ case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
+ case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES:
case PIPE_CAP_INVALIDATE_BUFFER:
case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
case PIPE_CAP_CS_DERIVED_SYSTEM_VALUES_SUPPORTED:
case PIPE_CAP_TEXTURE_SHADOW_LOD:
case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
- case PIPE_CAP_GL_SPIRV:
- case PIPE_CAP_GL_SPIRV_VARIABLE_POINTERS:
- case PIPE_CAP_DEMOTE_TO_HELPER_INVOCATION:
- case PIPE_CAP_NATIVE_FENCE_FD:
- case PIPE_CAP_MEMOBJ:
- case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
- case PIPE_CAP_FENCE_SIGNAL:
- case PIPE_CAP_IMAGE_STORE_FORMATTED:
return true;
- case PIPE_CAP_PREFER_BACK_BUFFER_REUSE:
- return false;
case PIPE_CAP_FBFETCH:
return BRW_MAX_DRAW_BUFFERS;
case PIPE_CAP_FBFETCH_COHERENT:
@@ -305,9 +210,7 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
case PIPE_CAP_FRAGMENT_SHADER_INTERLOCK:
case PIPE_CAP_ATOMIC_FLOAT_MINMAX:
- return devinfo->ver >= 9;
- case PIPE_CAP_DEPTH_BOUNDS_TEST:
- return devinfo->ver >= 12;
+ return devinfo->gen >= 9;
case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
return 1;
case PIPE_CAP_MAX_RENDER_TARGETS:
@@ -335,13 +238,20 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
return IRIS_MAP_BUFFER_ALIGNMENT;
case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
- return 4;
+ /* Choose a cacheline (64 bytes) so that we can safely have the CPU and
+ * GPU writing the same SSBO on non-coherent systems (Atom CPUs). With
+ * UBOs, the GPU never writes, so there's no problem. For an SSBO, the
+ * GPU and the CPU can be updating disjoint regions of the buffer
+ * simultaneously and that will break if the regions overlap the same
+ * cacheline.
+ */
+ return 64;
case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
return 1 << 27;
case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
return 16; // XXX: u_screen says 256 is the minimum value...
- case PIPE_CAP_TEXTURE_TRANSFER_MODES:
- return PIPE_TEXTURE_TRANSFER_BLIT;
+ case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
+ return true;
case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
return IRIS_MAX_TEXTURE_BUFFER_SIZE;
case PIPE_CAP_MAX_VIEWPORTS:
@@ -364,8 +274,28 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
return 0x8086;
case PIPE_CAP_DEVICE_ID:
return screen->pci_id;
- case PIPE_CAP_VIDEO_MEMORY:
- return iris_get_video_memory(screen);
+ case PIPE_CAP_VIDEO_MEMORY: {
+ /* Once a batch uses more than 75% of the maximum mappable size, we
+ * assume that there's some fragmentation, and we start doing extra
+ * flushing, etc. That's the big cliff apps will care about.
+ */
+ const unsigned gpu_mappable_megabytes =
+ (screen->aperture_bytes * 3 / 4) / (1024 * 1024);
+
+ const long system_memory_pages = sysconf(_SC_PHYS_PAGES);
+ const long system_page_size = sysconf(_SC_PAGE_SIZE);
+
+ if (system_memory_pages <= 0 || system_page_size <= 0)
+ return -1;
+
+ const uint64_t system_memory_bytes =
+ (uint64_t) system_memory_pages * (uint64_t) system_page_size;
+
+ const unsigned system_memory_megabytes =
+ (unsigned) (system_memory_bytes / (1024 * 1024));
+
+ return MIN2(system_memory_megabytes, gpu_mappable_megabytes);
+ }
case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
case PIPE_CAP_MAX_VARYINGS:
return 32;
@@ -378,17 +308,12 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
* illegal snoop <-> snoop transfers.
*/
return devinfo->has_llc;
- case PIPE_CAP_THROTTLE:
- return screen->driconf.disable_throttling ? 0 : 1;
case PIPE_CAP_CONTEXT_PRIORITY_MASK:
return PIPE_CONTEXT_PRIORITY_LOW |
PIPE_CONTEXT_PRIORITY_MEDIUM |
PIPE_CONTEXT_PRIORITY_HIGH;
- case PIPE_CAP_FRONTEND_NOOP:
- return true;
-
// XXX: don't hardcode 00:00:02.0 PCI here
case PIPE_CAP_PCI_GROUP:
return 0;
@@ -399,17 +324,6 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_PCI_FUNCTION:
return 0;
- case PIPE_CAP_OPENCL_INTEGER_FUNCTIONS:
- case PIPE_CAP_INTEGER_MULTIPLY_32X16:
- return true;
-
- case PIPE_CAP_ALLOW_DYNAMIC_VAO_FASTPATH:
- /* Internal details of VF cache make this optimization harmful on GFX
- * version 8 and 9, because generated VERTEX_BUFFER_STATEs are cached
- * separately.
- */
- return devinfo->ver >= 11;
-
default:
return u_pipe_screen_get_param_defaults(pscreen, param);
}
@@ -420,22 +334,12 @@ static float
iris_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
{
switch (param) {
- case PIPE_CAPF_MIN_LINE_WIDTH:
- case PIPE_CAPF_MIN_LINE_WIDTH_AA:
- case PIPE_CAPF_MIN_POINT_SIZE:
- case PIPE_CAPF_MIN_POINT_SIZE_AA:
- return 1;
-
- case PIPE_CAPF_POINT_SIZE_GRANULARITY:
- case PIPE_CAPF_LINE_WIDTH_GRANULARITY:
- return 0.1;
-
case PIPE_CAPF_MAX_LINE_WIDTH:
case PIPE_CAPF_MAX_LINE_WIDTH_AA:
return 7.375f;
- case PIPE_CAPF_MAX_POINT_SIZE:
- case PIPE_CAPF_MAX_POINT_SIZE_AA:
+ case PIPE_CAPF_MAX_POINT_WIDTH:
+ case PIPE_CAPF_MAX_POINT_WIDTH_AA:
return 255.0f;
case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
@@ -494,13 +398,10 @@ iris_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_SUBROUTINES:
return 0;
case PIPE_SHADER_CAP_INTEGERS:
+ case PIPE_SHADER_CAP_SCALAR_ISA:
return 1;
case PIPE_SHADER_CAP_INT64_ATOMICS:
case PIPE_SHADER_CAP_FP16:
- case PIPE_SHADER_CAP_FP16_DERIVATIVES:
- case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
- case PIPE_SHADER_CAP_INT16:
- case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
return 0;
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
@@ -513,12 +414,8 @@ iris_get_shader_param(struct pipe_screen *pscreen,
return 0;
case PIPE_SHADER_CAP_PREFERRED_IR:
return PIPE_SHADER_IR_NIR;
- case PIPE_SHADER_CAP_SUPPORTED_IRS: {
- int irs = 1 << PIPE_SHADER_IR_NIR;
- if (iris_enable_clover())
- irs |= 1 << PIPE_SHADER_IR_NIR_SERIALIZED;
- return irs;
- }
+ case PIPE_SHADER_CAP_SUPPORTED_IRS:
+ return 1 << PIPE_SHADER_IR_NIR;
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
return 1;
@@ -542,10 +439,10 @@ iris_get_compute_param(struct pipe_screen *pscreen,
void *ret)
{
struct iris_screen *screen = (struct iris_screen *)pscreen;
- const struct intel_device_info *devinfo = &screen->devinfo;
+ const struct gen_device_info *devinfo = &screen->devinfo;
- const uint32_t max_invocations =
- MIN2(1024, 32 * devinfo->max_cs_workgroup_threads);
+ const unsigned max_threads = MIN2(64, devinfo->max_cs_threads);
+ const uint32_t max_invocations = 32 * max_threads;
#define RET(x) do { \
if (ret) \
@@ -555,11 +452,7 @@ iris_get_compute_param(struct pipe_screen *pscreen,
switch (param) {
case PIPE_COMPUTE_CAP_ADDRESS_BITS:
- /* This gets queried on clover device init and is never queried by the
- * OpenGL state tracker.
- */
- iris_warn_clover();
- RET((uint32_t []){ 64 });
+ RET((uint32_t []){ 32 });
case PIPE_COMPUTE_CAP_IR_TARGET:
if (ret)
@@ -578,8 +471,6 @@ iris_get_compute_param(struct pipe_screen *pscreen,
case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
/* MaxComputeWorkGroupInvocations */
- case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
- /* MaxComputeVariableGroupInvocations */
RET((uint64_t []) { max_invocations });
case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
@@ -593,23 +484,14 @@ iris_get_compute_param(struct pipe_screen *pscreen,
RET((uint32_t []) { BRW_SUBGROUP_SIZE });
case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
- case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
- RET((uint64_t []) { 1 << 30 }); /* TODO */
-
case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
- RET((uint32_t []) { 400 }); /* TODO */
-
- case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS: {
- RET((uint32_t []) { intel_device_info_subslice_total(devinfo) });
- }
-
+ case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
+ case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
- /* MaxComputeSharedMemorySize */
- RET((uint64_t []) { 64 * 1024 });
-
case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
- /* We could probably allow more; this is the OpenCL minimum */
- RET((uint64_t []) { 1024 });
+ case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
+ // XXX: I think these are for Clover...
+ return 0;
default:
unreachable("unknown compute param");
@@ -625,33 +507,25 @@ iris_get_timestamp(struct pipe_screen *pscreen)
iris_reg_read(screen->bufmgr, TIMESTAMP | 1, &result);
- result = intel_device_info_timebase_scale(&screen->devinfo, result);
+ result = gen_device_info_timebase_scale(&screen->devinfo, result);
result &= (1ull << TIMESTAMP_BITS) - 1;
return result;
}
-void
-iris_screen_destroy(struct iris_screen *screen)
+static void
+iris_destroy_screen(struct pipe_screen *pscreen)
{
- iris_destroy_screen_measure(screen);
- util_queue_destroy(&screen->shader_compiler_queue);
- glsl_type_singleton_decref();
+ struct iris_screen *screen = (struct iris_screen *) pscreen;
iris_bo_unreference(screen->workaround_bo);
- u_transfer_helper_destroy(screen->base.transfer_helper);
- iris_bufmgr_unref(screen->bufmgr);
+ u_transfer_helper_destroy(pscreen->transfer_helper);
+ iris_bufmgr_destroy(screen->bufmgr);
disk_cache_destroy(screen->disk_cache);
- close(screen->winsys_fd);
+ close(screen->fd);
ralloc_free(screen);
}
static void
-iris_screen_unref(struct pipe_screen *pscreen)
-{
- iris_pscreen_unref(pscreen);
-}
-
-static void
iris_query_memory_info(struct pipe_screen *pscreen,
struct pipe_memory_info *info)
{
@@ -666,7 +540,7 @@ iris_get_compiler_options(struct pipe_screen *pscreen,
gl_shader_stage stage = stage_from_pipe(pstage);
assert(ir == PIPE_SHADER_IR_NIR);
- return screen->compiler->nir_options[stage];
+ return screen->compiler->glsl_compiler_options[stage].NirOptions;
}
static struct disk_cache *
@@ -677,60 +551,51 @@ iris_get_disk_shader_cache(struct pipe_screen *pscreen)
}
static int
-iris_getparam(int fd, int param, int *value)
+iris_getparam(struct iris_screen *screen, int param, int *value)
{
struct drm_i915_getparam gp = { .param = param, .value = value };
- if (ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1)
+ if (ioctl(screen->fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1)
return -errno;
return 0;
}
static int
-iris_getparam_integer(int fd, int param)
+iris_getparam_integer(struct iris_screen *screen, int param)
{
int value = -1;
- if (iris_getparam(fd, param, &value) == 0)
+ if (iris_getparam(screen, param, &value) == 0)
return value;
return -1;
}
-static const struct intel_l3_config *
-iris_get_default_l3_config(const struct intel_device_info *devinfo,
- bool compute)
-{
- bool wants_dc_cache = true;
- bool has_slm = compute;
- const struct intel_l3_weights w =
- intel_get_default_l3_weights(devinfo, wants_dc_cache, has_slm);
- return intel_get_l3_config(devinfo, w);
-}
-
static void
-iris_shader_debug_log(void *data, unsigned *id, const char *fmt, ...)
+iris_shader_debug_log(void *data, const char *fmt, ...)
{
- struct util_debug_callback *dbg = data;
+ struct pipe_debug_callback *dbg = data;
+ unsigned id = 0;
va_list args;
if (!dbg->debug_message)
return;
va_start(args, fmt);
- dbg->debug_message(dbg->data, id, UTIL_DEBUG_TYPE_SHADER_INFO, fmt, args);
+ dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_SHADER_INFO, fmt, args);
va_end(args);
}
static void
-iris_shader_perf_log(void *data, unsigned *id, const char *fmt, ...)
+iris_shader_perf_log(void *data, const char *fmt, ...)
{
- struct util_debug_callback *dbg = data;
+ struct pipe_debug_callback *dbg = data;
+ unsigned id = 0;
va_list args;
va_start(args, fmt);
- if (INTEL_DEBUG(DEBUG_PERF)) {
+ if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
va_list args_copy;
va_copy(args_copy, args);
vfprintf(stderr, fmt, args_copy);
@@ -738,143 +603,73 @@ iris_shader_perf_log(void *data, unsigned *id, const char *fmt, ...)
}
if (dbg->debug_message) {
- dbg->debug_message(dbg->data, id, UTIL_DEBUG_TYPE_PERF_INFO, fmt, args);
+ dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_PERF_INFO, fmt, args);
}
va_end(args);
}
-static void
-iris_detect_kernel_features(struct iris_screen *screen)
-{
- /* Kernel 5.2+ */
- if (intel_gem_supports_syncobj_wait(screen->fd))
- screen->kernel_features |= KERNEL_HAS_WAIT_FOR_SUBMIT;
-}
-
-static bool
-iris_init_identifier_bo(struct iris_screen *screen)
-{
- void *bo_map;
-
- bo_map = iris_bo_map(NULL, screen->workaround_bo, MAP_READ | MAP_WRITE);
- if (!bo_map)
- return false;
-
- assert(iris_bo_is_real(screen->workaround_bo));
-
- screen->workaround_bo->real.kflags |=
- EXEC_OBJECT_CAPTURE | EXEC_OBJECT_ASYNC;
- screen->workaround_address = (struct iris_address) {
- .bo = screen->workaround_bo,
- .offset = ALIGN(
- intel_debug_write_identifiers(bo_map, 4096, "Iris") + 8, 8),
- };
-
- iris_bo_unmap(screen->workaround_bo);
-
- return true;
-}
-
struct pipe_screen *
iris_screen_create(int fd, const struct pipe_screen_config *config)
{
- /* Here are the i915 features we need for Iris (in chronological order) :
- * - I915_PARAM_HAS_EXEC_NO_RELOC (3.10)
- * - I915_PARAM_HAS_EXEC_HANDLE_LUT (3.10)
- * - I915_PARAM_HAS_EXEC_BATCH_FIRST (4.13)
- * - I915_PARAM_HAS_EXEC_FENCE_ARRAY (4.14)
- * - I915_PARAM_HAS_CONTEXT_ISOLATION (4.16)
- *
- * Checking the last feature availability will include all previous ones.
- */
- if (iris_getparam_integer(fd, I915_PARAM_HAS_CONTEXT_ISOLATION) <= 0) {
- debug_error("Kernel is too old for Iris. Consider upgrading to kernel v4.16.\n");
- return NULL;
- }
-
struct iris_screen *screen = rzalloc(NULL, struct iris_screen);
if (!screen)
return NULL;
- if (!intel_get_device_info_from_fd(fd, &screen->devinfo))
- return NULL;
- screen->pci_id = screen->devinfo.pci_device_id;
+ screen->fd = fd;
- p_atomic_set(&screen->refcount, 1);
+ if (!gen_get_device_info_from_fd(fd, &screen->devinfo))
+ return NULL;
+ screen->pci_id = screen->devinfo.chipset_id;
+ screen->no_hw = screen->devinfo.no_hw;
- if (screen->devinfo.ver < 8 || screen->devinfo.platform == INTEL_PLATFORM_CHV)
+ if (screen->devinfo.gen < 8 || screen->devinfo.is_cherryview)
return NULL;
- driParseConfigFiles(config->options, config->options_info, 0, "iris",
- NULL, NULL, NULL, 0, NULL, 0);
+ screen->aperture_bytes = get_aperture_size(fd);
- bool bo_reuse = false;
- int bo_reuse_mode = driQueryOptioni(config->options, "bo_reuse");
- switch (bo_reuse_mode) {
- case DRI_CONF_BO_REUSE_DISABLED:
- break;
- case DRI_CONF_BO_REUSE_ALL:
- bo_reuse = true;
- break;
- }
-
- brw_process_intel_debug_variable();
+ if (getenv("INTEL_NO_HW") != NULL)
+ screen->no_hw = true;
- screen->bufmgr = iris_bufmgr_get_for_fd(&screen->devinfo, fd, bo_reuse);
+ screen->bufmgr = iris_bufmgr_init(&screen->devinfo, fd);
if (!screen->bufmgr)
return NULL;
- screen->fd = iris_bufmgr_get_fd(screen->bufmgr);
- screen->winsys_fd = os_dupfd_cloexec(fd);
-
- screen->id = iris_bufmgr_create_screen_id(screen->bufmgr);
-
screen->workaround_bo =
- iris_bo_alloc(screen->bufmgr, "workaround", 4096, 1,
- IRIS_MEMZONE_OTHER, BO_ALLOC_NO_SUBALLOC);
+ iris_bo_alloc(screen->bufmgr, "workaround", 4096, IRIS_MEMZONE_OTHER);
if (!screen->workaround_bo)
return NULL;
- if (!iris_init_identifier_bo(screen))
- return NULL;
+ brw_process_intel_debug_variable();
screen->driconf.dual_color_blend_by_location =
driQueryOptionb(config->options, "dual_color_blend_by_location");
- screen->driconf.disable_throttling =
- driQueryOptionb(config->options, "disable_throttling");
- screen->driconf.always_flush_cache =
- driQueryOptionb(config->options, "always_flush_cache");
- screen->driconf.sync_compile =
- driQueryOptionb(config->options, "sync_compile");
screen->precompile = env_var_as_boolean("shader_precompile", true);
- isl_device_init(&screen->isl_dev, &screen->devinfo);
+ isl_device_init(&screen->isl_dev, &screen->devinfo, false);
screen->compiler = brw_compiler_create(screen, &screen->devinfo);
screen->compiler->shader_debug_log = iris_shader_debug_log;
screen->compiler->shader_perf_log = iris_shader_perf_log;
+ screen->compiler->supports_pull_constants = false;
screen->compiler->supports_shader_constants = true;
- screen->compiler->indirect_ubos_use_sampler = screen->devinfo.ver < 12;
-
- screen->l3_config_3d = iris_get_default_l3_config(&screen->devinfo, false);
- screen->l3_config_cs = iris_get_default_l3_config(&screen->devinfo, true);
iris_disk_cache_init(screen);
slab_create_parent(&screen->transfer_pool,
sizeof(struct iris_transfer), 64);
- iris_detect_kernel_features(screen);
+ screen->subslice_total =
+ iris_getparam_integer(screen, I915_PARAM_SUBSLICE_TOTAL);
+ assert(screen->subslice_total >= 1);
struct pipe_screen *pscreen = &screen->base;
iris_init_screen_fence_functions(pscreen);
iris_init_screen_resource_functions(pscreen);
- iris_init_screen_measure(screen);
- pscreen->destroy = iris_screen_unref;
+ pscreen->destroy = iris_destroy_screen;
pscreen->get_name = iris_get_name;
pscreen->get_vendor = iris_get_vendor;
pscreen->get_device_vendor = iris_get_device_vendor;
@@ -883,46 +678,14 @@ iris_screen_create(int fd, const struct pipe_screen_config *config)
pscreen->get_compute_param = iris_get_compute_param;
pscreen->get_paramf = iris_get_paramf;
pscreen->get_compiler_options = iris_get_compiler_options;
- pscreen->get_device_uuid = iris_get_device_uuid;
- pscreen->get_driver_uuid = iris_get_driver_uuid;
pscreen->get_disk_shader_cache = iris_get_disk_shader_cache;
pscreen->is_format_supported = iris_is_format_supported;
pscreen->context_create = iris_create_context;
+ pscreen->flush_frontbuffer = iris_flush_frontbuffer;
pscreen->get_timestamp = iris_get_timestamp;
pscreen->query_memory_info = iris_query_memory_info;
pscreen->get_driver_query_group_info = iris_get_monitor_group_info;
pscreen->get_driver_query_info = iris_get_monitor_info;
- iris_init_screen_program_functions(pscreen);
-
- genX_call(&screen->devinfo, init_screen_state, screen);
-
- glsl_type_singleton_init_or_ref();
-
- intel_driver_ds_init();
-
- /* FINISHME: Big core vs little core (for CPUs that have both kinds of
- * cores) and, possibly, thread vs core should be considered here too.
- */
- unsigned compiler_threads = 1;
- const struct util_cpu_caps_t *caps = util_get_cpu_caps();
- unsigned hw_threads = caps->nr_cpus;
-
- if (hw_threads >= 12) {
- compiler_threads = hw_threads * 3 / 4;
- } else if (hw_threads >= 6) {
- compiler_threads = hw_threads - 2;
- } else if (hw_threads >= 2) {
- compiler_threads = hw_threads - 1;
- }
-
- if (!util_queue_init(&screen->shader_compiler_queue,
- "sh", 64, compiler_threads,
- UTIL_QUEUE_INIT_RESIZE_IF_FULL |
- UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY,
- NULL)) {
- iris_screen_destroy(screen);
- return NULL;
- }
return pscreen;
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-26 19:48:11 +0000