diff options
Diffstat (limited to 'lib/mesa/src/gallium/drivers')
33 files changed, 445 insertions, 15373 deletions
diff --git a/lib/mesa/src/gallium/drivers/ddebug/Makefile.in b/lib/mesa/src/gallium/drivers/ddebug/Makefile.in index c9f5bd4f6..a93d08778 100644 --- a/lib/mesa/src/gallium/drivers/ddebug/Makefile.in +++ b/lib/mesa/src/gallium/drivers/ddebug/Makefile.in @@ -199,6 +199,8 @@ GLESv2_LIB_DEPS = @GLESv2_LIB_DEPS@ GLESv2_PC_LIB_PRIV = @GLESv2_PC_LIB_PRIV@ GLPROTO_CFLAGS = @GLPROTO_CFLAGS@ GLPROTO_LIBS = @GLPROTO_LIBS@ +GLVND_CFLAGS = @GLVND_CFLAGS@ +GLVND_LIBS = @GLVND_LIBS@ GLX_TLS = @GLX_TLS@ GL_LIB = @GL_LIB@ GL_LIB_DEPS = @GL_LIB_DEPS@ @@ -230,11 +232,10 @@ LIBELF_CFLAGS = @LIBELF_CFLAGS@ LIBELF_LIBS = @LIBELF_LIBS@ LIBOBJS = @LIBOBJS@ LIBS = @LIBS@ +LIBSENSORS_LDFLAGS = @LIBSENSORS_LDFLAGS@ LIBSHA1_CFLAGS = @LIBSHA1_CFLAGS@ LIBSHA1_LIBS = @LIBSHA1_LIBS@ LIBTOOL = @LIBTOOL@ -LIBUDEV_CFLAGS = @LIBUDEV_CFLAGS@ -LIBUDEV_LIBS = @LIBUDEV_LIBS@ LIB_DIR = @LIB_DIR@ LIB_EXT = @LIB_EXT@ LIPO = @LIPO@ @@ -297,6 +298,8 @@ PKG_CONFIG_PATH = @PKG_CONFIG_PATH@ POSIX_SHELL = @POSIX_SHELL@ PRESENTPROTO_CFLAGS = @PRESENTPROTO_CFLAGS@ PRESENTPROTO_LIBS = @PRESENTPROTO_LIBS@ +PTHREADSTUBS_CFLAGS = @PTHREADSTUBS_CFLAGS@ +PTHREADSTUBS_LIBS = @PTHREADSTUBS_LIBS@ PTHREAD_CC = @PTHREAD_CC@ PTHREAD_CFLAGS = @PTHREAD_CFLAGS@ PTHREAD_LIBS = @PTHREAD_LIBS@ @@ -317,11 +320,19 @@ SIMPENROSE_CFLAGS = @SIMPENROSE_CFLAGS@ SIMPENROSE_LIBS = @SIMPENROSE_LIBS@ SSE41_CFLAGS = @SSE41_CFLAGS@ STRIP = @STRIP@ +SWR_AVX2_CXXFLAGS = @SWR_AVX2_CXXFLAGS@ +SWR_AVX_CXXFLAGS = @SWR_AVX_CXXFLAGS@ +SWR_CXX11_CXXFLAGS = @SWR_CXX11_CXXFLAGS@ +TIMESTAMP_CMD = @TIMESTAMP_CMD@ +VALGRIND_CFLAGS = @VALGRIND_CFLAGS@ +VALGRIND_LIBS = @VALGRIND_LIBS@ VA_CFLAGS = @VA_CFLAGS@ VA_LIBS = @VA_LIBS@ VA_LIB_INSTALL_DIR = @VA_LIB_INSTALL_DIR@ VA_MAJOR = @VA_MAJOR@ VA_MINOR = @VA_MINOR@ +VC4_CFLAGS = @VC4_CFLAGS@ +VC4_LIBS = @VC4_LIBS@ VDPAU_CFLAGS = @VDPAU_CFLAGS@ VDPAU_LIBS = @VDPAU_LIBS@ VDPAU_LIB_INSTALL_DIR = @VDPAU_LIB_INSTALL_DIR@ @@ -333,6 +344,7 @@ VISIBILITY_CFLAGS = @VISIBILITY_CFLAGS@ VISIBILITY_CXXFLAGS = @VISIBILITY_CXXFLAGS@ VL_CFLAGS = @VL_CFLAGS@ VL_LIBS = @VL_LIBS@ +VULKAN_ICD_INSTALL_DIR = @VULKAN_ICD_INSTALL_DIR@ WAYLAND_CFLAGS = @WAYLAND_CFLAGS@ WAYLAND_LIBS = @WAYLAND_LIBS@ WAYLAND_SCANNER = @WAYLAND_SCANNER@ @@ -356,6 +368,7 @@ XVMC_LIBS = @XVMC_LIBS@ XVMC_LIB_INSTALL_DIR = @XVMC_LIB_INSTALL_DIR@ XVMC_MAJOR = @XVMC_MAJOR@ XVMC_MINOR = @XVMC_MINOR@ +XXD = @XXD@ YACC = @YACC@ YFLAGS = @YFLAGS@ abs_builddir = @abs_builddir@ diff --git a/lib/mesa/src/gallium/drivers/freedreno/Makefile.in b/lib/mesa/src/gallium/drivers/freedreno/Makefile.in index 334276b3a..a7d025c7b 100644 --- a/lib/mesa/src/gallium/drivers/freedreno/Makefile.in +++ b/lib/mesa/src/gallium/drivers/freedreno/Makefile.in @@ -82,9 +82,10 @@ CONFIG_CLEAN_FILES = CONFIG_CLEAN_VPATH_FILES = LTLIBRARIES = $(noinst_LTLIBRARIES) libfreedreno_la_LIBADD = -am__objects_1 = freedreno_context.lo freedreno_draw.lo \ - freedreno_fence.lo freedreno_gmem.lo freedreno_program.lo \ - freedreno_query.lo freedreno_query_hw.lo freedreno_query_sw.lo \ +am__objects_1 = freedreno_batch.lo freedreno_batch_cache.lo \ + freedreno_context.lo freedreno_draw.lo freedreno_fence.lo \ + freedreno_gmem.lo freedreno_program.lo freedreno_query.lo \ + freedreno_query_hw.lo freedreno_query_sw.lo \ freedreno_resource.lo freedreno_screen.lo freedreno_state.lo \ freedreno_surface.lo freedreno_texture.lo freedreno_util.lo am__dirstamp = $(am__leading_dot)dirstamp @@ -106,8 +107,10 @@ am__objects_5 = ir3/disasm-a3xx.lo ir3/ir3.lo ir3/ir3_compiler_nir.lo \ ir3/ir3_group.lo ir3/ir3_legalize.lo ir3/ir3_nir.lo \ ir3/ir3_nir_lower_if_else.lo ir3/ir3_print.lo ir3/ir3_ra.lo \ ir3/ir3_sched.lo ir3/ir3_shader.lo +am__objects_6 = ir3/ir3_nir_trig.lo am_libfreedreno_la_OBJECTS = $(am__objects_1) $(am__objects_2) \ - $(am__objects_3) $(am__objects_4) $(am__objects_5) + $(am__objects_3) $(am__objects_4) $(am__objects_5) \ + $(am__objects_6) libfreedreno_la_OBJECTS = $(am_libfreedreno_la_OBJECTS) AM_V_lt = $(am__v_lt_@AM_V@) am__v_lt_ = $(am__v_lt_@AM_DEFAULT_V@) @@ -122,8 +125,10 @@ am__DEPENDENCIES_2 = $(am__DEPENDENCIES_1) $(am__DEPENDENCIES_1) \ ir3_compiler_DEPENDENCIES = libfreedreno.la \ $(top_builddir)/src/gallium/auxiliary/libgallium.la \ $(top_builddir)/src/compiler/nir/libnir.la \ - $(top_builddir)/src/util/libmesautil.la $(am__DEPENDENCIES_2) \ - $(am__DEPENDENCIES_1) + $(top_builddir)/src/compiler/glsl/libstandalone.la \ + $(top_builddir)/src/util/libmesautil.la \ + $(top_builddir)/src/mesa/libmesagallium.la \ + $(am__DEPENDENCIES_2) $(am__DEPENDENCIES_1) AM_V_P = $(am__v_P_@AM_V@) am__v_P_ = $(am__v_P_@AM_DEFAULT_V@) am__v_P_0 = false @@ -255,6 +260,8 @@ GLESv2_LIB_DEPS = @GLESv2_LIB_DEPS@ GLESv2_PC_LIB_PRIV = @GLESv2_PC_LIB_PRIV@ GLPROTO_CFLAGS = @GLPROTO_CFLAGS@ GLPROTO_LIBS = @GLPROTO_LIBS@ +GLVND_CFLAGS = @GLVND_CFLAGS@ +GLVND_LIBS = @GLVND_LIBS@ GLX_TLS = @GLX_TLS@ GL_LIB = @GL_LIB@ GL_LIB_DEPS = @GL_LIB_DEPS@ @@ -286,11 +293,10 @@ LIBELF_CFLAGS = @LIBELF_CFLAGS@ LIBELF_LIBS = @LIBELF_LIBS@ LIBOBJS = @LIBOBJS@ LIBS = @LIBS@ +LIBSENSORS_LDFLAGS = @LIBSENSORS_LDFLAGS@ LIBSHA1_CFLAGS = @LIBSHA1_CFLAGS@ LIBSHA1_LIBS = @LIBSHA1_LIBS@ LIBTOOL = @LIBTOOL@ -LIBUDEV_CFLAGS = @LIBUDEV_CFLAGS@ -LIBUDEV_LIBS = @LIBUDEV_LIBS@ LIB_DIR = @LIB_DIR@ LIB_EXT = @LIB_EXT@ LIPO = @LIPO@ @@ -353,6 +359,8 @@ PKG_CONFIG_PATH = @PKG_CONFIG_PATH@ POSIX_SHELL = @POSIX_SHELL@ PRESENTPROTO_CFLAGS = @PRESENTPROTO_CFLAGS@ PRESENTPROTO_LIBS = @PRESENTPROTO_LIBS@ +PTHREADSTUBS_CFLAGS = @PTHREADSTUBS_CFLAGS@ +PTHREADSTUBS_LIBS = @PTHREADSTUBS_LIBS@ PTHREAD_CC = @PTHREAD_CC@ PTHREAD_CFLAGS = @PTHREAD_CFLAGS@ PTHREAD_LIBS = @PTHREAD_LIBS@ @@ -373,11 +381,19 @@ SIMPENROSE_CFLAGS = @SIMPENROSE_CFLAGS@ SIMPENROSE_LIBS = @SIMPENROSE_LIBS@ SSE41_CFLAGS = @SSE41_CFLAGS@ STRIP = @STRIP@ +SWR_AVX2_CXXFLAGS = @SWR_AVX2_CXXFLAGS@ +SWR_AVX_CXXFLAGS = @SWR_AVX_CXXFLAGS@ +SWR_CXX11_CXXFLAGS = @SWR_CXX11_CXXFLAGS@ +TIMESTAMP_CMD = @TIMESTAMP_CMD@ +VALGRIND_CFLAGS = @VALGRIND_CFLAGS@ +VALGRIND_LIBS = @VALGRIND_LIBS@ VA_CFLAGS = @VA_CFLAGS@ VA_LIBS = @VA_LIBS@ VA_LIB_INSTALL_DIR = @VA_LIB_INSTALL_DIR@ VA_MAJOR = @VA_MAJOR@ VA_MINOR = @VA_MINOR@ +VC4_CFLAGS = @VC4_CFLAGS@ +VC4_LIBS = @VC4_LIBS@ VDPAU_CFLAGS = @VDPAU_CFLAGS@ VDPAU_LIBS = @VDPAU_LIBS@ VDPAU_LIB_INSTALL_DIR = @VDPAU_LIB_INSTALL_DIR@ @@ -389,6 +405,7 @@ VISIBILITY_CFLAGS = @VISIBILITY_CFLAGS@ VISIBILITY_CXXFLAGS = @VISIBILITY_CXXFLAGS@ VL_CFLAGS = @VL_CFLAGS@ VL_LIBS = @VL_LIBS@ +VULKAN_ICD_INSTALL_DIR = @VULKAN_ICD_INSTALL_DIR@ WAYLAND_CFLAGS = @WAYLAND_CFLAGS@ WAYLAND_LIBS = @WAYLAND_LIBS@ WAYLAND_SCANNER = @WAYLAND_SCANNER@ @@ -412,6 +429,7 @@ XVMC_LIBS = @XVMC_LIBS@ XVMC_LIB_INSTALL_DIR = @XVMC_LIB_INSTALL_DIR@ XVMC_MAJOR = @XVMC_MAJOR@ XVMC_MINOR = @XVMC_MINOR@ +XXD = @XXD@ YACC = @YACC@ YFLAGS = @YFLAGS@ abs_builddir = @abs_builddir@ @@ -478,6 +496,10 @@ C_SOURCES := \ adreno_common.xml.h \ adreno_pm4.xml.h \ disasm.h \ + freedreno_batch.c \ + freedreno_batch.h \ + freedreno_batch_cache.c \ + freedreno_batch_cache.h \ freedreno_context.c \ freedreno_context.h \ freedreno_draw.c \ @@ -613,6 +635,9 @@ ir3_SOURCES := \ ir3/ir3_shader.c \ ir3/ir3_shader.h +ir3_GENERATED_FILES := \ + ir3/ir3_nir_trig.c + GALLIUM_CFLAGS = \ -I$(top_srcdir)/include \ -I$(top_srcdir)/src \ @@ -682,6 +707,7 @@ AM_CFLAGS = \ -Wno-packed-bitfield-compat \ -I$(top_srcdir)/src/gallium/drivers/freedreno/ir3 \ -I$(top_builddir)/src/compiler/nir \ + -I$(top_srcdir)/src/compiler/nir \ $(GALLIUM_DRIVER_CFLAGS) \ $(FREEDRENO_CFLAGS) @@ -691,8 +717,12 @@ libfreedreno_la_SOURCES = \ $(a2xx_SOURCES) \ $(a3xx_SOURCES) \ $(a4xx_SOURCES) \ - $(ir3_SOURCES) + $(ir3_SOURCES) \ + $(ir3_GENERATED_FILES) +BUILT_SOURCES := $(ir3_GENERATED_FILES) +CLEANFILES := $(BUILT_SOURCES) +EXTRA_DIST = ir3/ir3_nir_trig.py # XXX: Required due to the C++ sources in libnir nodist_EXTRA_ir3_compiler_SOURCES = dummy.cpp @@ -703,11 +733,14 @@ ir3_compiler_LDADD = \ libfreedreno.la \ $(top_builddir)/src/gallium/auxiliary/libgallium.la \ $(top_builddir)/src/compiler/nir/libnir.la \ + $(top_builddir)/src/compiler/glsl/libstandalone.la \ $(top_builddir)/src/util/libmesautil.la \ + $(top_builddir)/src/mesa/libmesagallium.la \ $(GALLIUM_COMMON_LIB_DEPS) \ $(FREEDRENO_LIBS) -all: all-am +all: $(BUILT_SOURCES) + $(MAKE) $(AM_MAKEFLAGS) all-am .SUFFIXES: .SUFFIXES: .c .cpp .lo .o .obj @@ -850,6 +883,7 @@ ir3/ir3_print.lo: ir3/$(am__dirstamp) ir3/$(DEPDIR)/$(am__dirstamp) ir3/ir3_ra.lo: ir3/$(am__dirstamp) ir3/$(DEPDIR)/$(am__dirstamp) ir3/ir3_sched.lo: ir3/$(am__dirstamp) ir3/$(DEPDIR)/$(am__dirstamp) ir3/ir3_shader.lo: ir3/$(am__dirstamp) ir3/$(DEPDIR)/$(am__dirstamp) +ir3/ir3_nir_trig.lo: ir3/$(am__dirstamp) ir3/$(DEPDIR)/$(am__dirstamp) libfreedreno.la: $(libfreedreno_la_OBJECTS) $(libfreedreno_la_DEPENDENCIES) $(EXTRA_libfreedreno_la_DEPENDENCIES) $(AM_V_CCLD)$(LINK) $(libfreedreno_la_OBJECTS) $(libfreedreno_la_LIBADD) $(LIBS) @@ -882,6 +916,8 @@ distclean-compile: -rm -f *.tab.c @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/dummy.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/freedreno_batch.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/freedreno_batch_cache.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/freedreno_context.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/freedreno_draw.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/freedreno_fence.Plo@am__quote@ @@ -945,6 +981,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@ir3/$(DEPDIR)/ir3_legalize.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@ir3/$(DEPDIR)/ir3_nir.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@ir3/$(DEPDIR)/ir3_nir_lower_if_else.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@ir3/$(DEPDIR)/ir3_nir_trig.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@ir3/$(DEPDIR)/ir3_print.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@ir3/$(DEPDIR)/ir3_ra.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@ir3/$(DEPDIR)/ir3_sched.Plo@am__quote@ @@ -1105,10 +1142,12 @@ distdir: $(DISTFILES) fi; \ done check-am: all-am -check: check-am +check: $(BUILT_SOURCES) + $(MAKE) $(AM_MAKEFLAGS) check-am all-am: Makefile $(LTLIBRARIES) $(PROGRAMS) installdirs: -install: install-am +install: $(BUILT_SOURCES) + $(MAKE) $(AM_MAKEFLAGS) install-am install-exec: install-exec-am install-data: install-data-am uninstall: uninstall-am @@ -1130,6 +1169,7 @@ install-strip: mostlyclean-generic: clean-generic: + -test -z "$(CLEANFILES)" || rm -f $(CLEANFILES) distclean-generic: -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES) @@ -1146,6 +1186,7 @@ distclean-generic: maintainer-clean-generic: @echo "This command is intended for maintainers to use" @echo "it deletes files that may require special tools to rebuild." + -test -z "$(BUILT_SOURCES)" || rm -f $(BUILT_SOURCES) clean: clean-am clean-am: clean-generic clean-libtool clean-noinstLTLIBRARIES \ @@ -1217,7 +1258,7 @@ ps-am: uninstall-am: -.MAKE: install-am install-strip +.MAKE: all check install install-am install-strip .PHONY: CTAGS GTAGS all all-am check check-am clean clean-generic \ clean-libtool clean-noinstLTLIBRARIES clean-noinstPROGRAMS \ @@ -1234,6 +1275,10 @@ uninstall-am: tags uninstall uninstall-am +ir3/ir3_nir_trig.c: ir3/ir3_nir_trig.py $(top_srcdir)/src/compiler/nir/nir_algebraic.py + $(MKDIR_GEN) + $(AM_V_GEN) PYTHONPATH=$(top_srcdir)/src/compiler/nir $(PYTHON2) $(PYTHON_FLAGS) $(srcdir)/ir3/ir3_nir_trig.py > $@ || ($(RM) $@; false) + # Tell versions [3.59,3.63) of GNU make to not export all variables. # Otherwise a system limit (for SysV at least) may be exceeded. .NOEXPORT: diff --git a/lib/mesa/src/gallium/drivers/i915/Makefile.in b/lib/mesa/src/gallium/drivers/i915/Makefile.in index 10c22c504..f8f316bb3 100644 --- a/lib/mesa/src/gallium/drivers/i915/Makefile.in +++ b/lib/mesa/src/gallium/drivers/i915/Makefile.in @@ -228,6 +228,8 @@ GLESv2_LIB_DEPS = @GLESv2_LIB_DEPS@ GLESv2_PC_LIB_PRIV = @GLESv2_PC_LIB_PRIV@ GLPROTO_CFLAGS = @GLPROTO_CFLAGS@ GLPROTO_LIBS = @GLPROTO_LIBS@ +GLVND_CFLAGS = @GLVND_CFLAGS@ +GLVND_LIBS = @GLVND_LIBS@ GLX_TLS = @GLX_TLS@ GL_LIB = @GL_LIB@ GL_LIB_DEPS = @GL_LIB_DEPS@ @@ -259,11 +261,10 @@ LIBELF_CFLAGS = @LIBELF_CFLAGS@ LIBELF_LIBS = @LIBELF_LIBS@ LIBOBJS = @LIBOBJS@ LIBS = @LIBS@ +LIBSENSORS_LDFLAGS = @LIBSENSORS_LDFLAGS@ LIBSHA1_CFLAGS = @LIBSHA1_CFLAGS@ LIBSHA1_LIBS = @LIBSHA1_LIBS@ LIBTOOL = @LIBTOOL@ -LIBUDEV_CFLAGS = @LIBUDEV_CFLAGS@ -LIBUDEV_LIBS = @LIBUDEV_LIBS@ LIB_DIR = @LIB_DIR@ LIB_EXT = @LIB_EXT@ LIPO = @LIPO@ @@ -326,6 +327,8 @@ PKG_CONFIG_PATH = @PKG_CONFIG_PATH@ POSIX_SHELL = @POSIX_SHELL@ PRESENTPROTO_CFLAGS = @PRESENTPROTO_CFLAGS@ PRESENTPROTO_LIBS = @PRESENTPROTO_LIBS@ +PTHREADSTUBS_CFLAGS = @PTHREADSTUBS_CFLAGS@ +PTHREADSTUBS_LIBS = @PTHREADSTUBS_LIBS@ PTHREAD_CC = @PTHREAD_CC@ PTHREAD_CFLAGS = @PTHREAD_CFLAGS@ PTHREAD_LIBS = @PTHREAD_LIBS@ @@ -346,11 +349,19 @@ SIMPENROSE_CFLAGS = @SIMPENROSE_CFLAGS@ SIMPENROSE_LIBS = @SIMPENROSE_LIBS@ SSE41_CFLAGS = @SSE41_CFLAGS@ STRIP = @STRIP@ +SWR_AVX2_CXXFLAGS = @SWR_AVX2_CXXFLAGS@ +SWR_AVX_CXXFLAGS = @SWR_AVX_CXXFLAGS@ +SWR_CXX11_CXXFLAGS = @SWR_CXX11_CXXFLAGS@ +TIMESTAMP_CMD = @TIMESTAMP_CMD@ +VALGRIND_CFLAGS = @VALGRIND_CFLAGS@ +VALGRIND_LIBS = @VALGRIND_LIBS@ VA_CFLAGS = @VA_CFLAGS@ VA_LIBS = @VA_LIBS@ VA_LIB_INSTALL_DIR = @VA_LIB_INSTALL_DIR@ VA_MAJOR = @VA_MAJOR@ VA_MINOR = @VA_MINOR@ +VC4_CFLAGS = @VC4_CFLAGS@ +VC4_LIBS = @VC4_LIBS@ VDPAU_CFLAGS = @VDPAU_CFLAGS@ VDPAU_LIBS = @VDPAU_LIBS@ VDPAU_LIB_INSTALL_DIR = @VDPAU_LIB_INSTALL_DIR@ @@ -362,6 +373,7 @@ VISIBILITY_CFLAGS = @VISIBILITY_CFLAGS@ VISIBILITY_CXXFLAGS = @VISIBILITY_CXXFLAGS@ VL_CFLAGS = @VL_CFLAGS@ VL_LIBS = @VL_LIBS@ +VULKAN_ICD_INSTALL_DIR = @VULKAN_ICD_INSTALL_DIR@ WAYLAND_CFLAGS = @WAYLAND_CFLAGS@ WAYLAND_LIBS = @WAYLAND_LIBS@ WAYLAND_SCANNER = @WAYLAND_SCANNER@ @@ -385,6 +397,7 @@ XVMC_LIBS = @XVMC_LIBS@ XVMC_LIB_INSTALL_DIR = @XVMC_LIB_INSTALL_DIR@ XVMC_MAJOR = @XVMC_MAJOR@ XVMC_MINOR = @XVMC_MINOR@ +XXD = @XXD@ YACC = @YACC@ YFLAGS = @YFLAGS@ abs_builddir = @abs_builddir@ diff --git a/lib/mesa/src/gallium/drivers/ilo/Makefile.in b/lib/mesa/src/gallium/drivers/ilo/Makefile.in index 5c6d3f19d..fd61f3ea2 100644 --- a/lib/mesa/src/gallium/drivers/ilo/Makefile.in +++ b/lib/mesa/src/gallium/drivers/ilo/Makefile.in @@ -246,6 +246,8 @@ GLESv2_LIB_DEPS = @GLESv2_LIB_DEPS@ GLESv2_PC_LIB_PRIV = @GLESv2_PC_LIB_PRIV@ GLPROTO_CFLAGS = @GLPROTO_CFLAGS@ GLPROTO_LIBS = @GLPROTO_LIBS@ +GLVND_CFLAGS = @GLVND_CFLAGS@ +GLVND_LIBS = @GLVND_LIBS@ GLX_TLS = @GLX_TLS@ GL_LIB = @GL_LIB@ GL_LIB_DEPS = @GL_LIB_DEPS@ @@ -277,11 +279,10 @@ LIBELF_CFLAGS = @LIBELF_CFLAGS@ LIBELF_LIBS = @LIBELF_LIBS@ LIBOBJS = @LIBOBJS@ LIBS = @LIBS@ +LIBSENSORS_LDFLAGS = @LIBSENSORS_LDFLAGS@ LIBSHA1_CFLAGS = @LIBSHA1_CFLAGS@ LIBSHA1_LIBS = @LIBSHA1_LIBS@ LIBTOOL = @LIBTOOL@ -LIBUDEV_CFLAGS = @LIBUDEV_CFLAGS@ -LIBUDEV_LIBS = @LIBUDEV_LIBS@ LIB_DIR = @LIB_DIR@ LIB_EXT = @LIB_EXT@ LIPO = @LIPO@ @@ -344,6 +345,8 @@ PKG_CONFIG_PATH = @PKG_CONFIG_PATH@ POSIX_SHELL = @POSIX_SHELL@ PRESENTPROTO_CFLAGS = @PRESENTPROTO_CFLAGS@ PRESENTPROTO_LIBS = @PRESENTPROTO_LIBS@ +PTHREADSTUBS_CFLAGS = @PTHREADSTUBS_CFLAGS@ +PTHREADSTUBS_LIBS = @PTHREADSTUBS_LIBS@ PTHREAD_CC = @PTHREAD_CC@ PTHREAD_CFLAGS = @PTHREAD_CFLAGS@ PTHREAD_LIBS = @PTHREAD_LIBS@ @@ -364,11 +367,19 @@ SIMPENROSE_CFLAGS = @SIMPENROSE_CFLAGS@ SIMPENROSE_LIBS = @SIMPENROSE_LIBS@ SSE41_CFLAGS = @SSE41_CFLAGS@ STRIP = @STRIP@ +SWR_AVX2_CXXFLAGS = @SWR_AVX2_CXXFLAGS@ +SWR_AVX_CXXFLAGS = @SWR_AVX_CXXFLAGS@ +SWR_CXX11_CXXFLAGS = @SWR_CXX11_CXXFLAGS@ +TIMESTAMP_CMD = @TIMESTAMP_CMD@ +VALGRIND_CFLAGS = @VALGRIND_CFLAGS@ +VALGRIND_LIBS = @VALGRIND_LIBS@ VA_CFLAGS = @VA_CFLAGS@ VA_LIBS = @VA_LIBS@ VA_LIB_INSTALL_DIR = @VA_LIB_INSTALL_DIR@ VA_MAJOR = @VA_MAJOR@ VA_MINOR = @VA_MINOR@ +VC4_CFLAGS = @VC4_CFLAGS@ +VC4_LIBS = @VC4_LIBS@ VDPAU_CFLAGS = @VDPAU_CFLAGS@ VDPAU_LIBS = @VDPAU_LIBS@ VDPAU_LIB_INSTALL_DIR = @VDPAU_LIB_INSTALL_DIR@ @@ -380,6 +391,7 @@ VISIBILITY_CFLAGS = @VISIBILITY_CFLAGS@ VISIBILITY_CXXFLAGS = @VISIBILITY_CXXFLAGS@ VL_CFLAGS = @VL_CFLAGS@ VL_LIBS = @VL_LIBS@ +VULKAN_ICD_INSTALL_DIR = @VULKAN_ICD_INSTALL_DIR@ WAYLAND_CFLAGS = @WAYLAND_CFLAGS@ WAYLAND_LIBS = @WAYLAND_LIBS@ WAYLAND_SCANNER = @WAYLAND_SCANNER@ @@ -403,6 +415,7 @@ XVMC_LIBS = @XVMC_LIBS@ XVMC_LIB_INSTALL_DIR = @XVMC_LIB_INSTALL_DIR@ XVMC_MAJOR = @XVMC_MAJOR@ XVMC_MINOR = @XVMC_MINOR@ +XXD = @XXD@ YACC = @YACC@ YFLAGS = @YFLAGS@ abs_builddir = @abs_builddir@ diff --git a/lib/mesa/src/gallium/drivers/llvmpipe/Makefile.in b/lib/mesa/src/gallium/drivers/llvmpipe/Makefile.in index f54fb4d02..3a26a7c13 100644 --- a/lib/mesa/src/gallium/drivers/llvmpipe/Makefile.in +++ b/lib/mesa/src/gallium/drivers/llvmpipe/Makefile.in @@ -297,6 +297,8 @@ GLESv2_LIB_DEPS = @GLESv2_LIB_DEPS@ GLESv2_PC_LIB_PRIV = @GLESv2_PC_LIB_PRIV@ GLPROTO_CFLAGS = @GLPROTO_CFLAGS@ GLPROTO_LIBS = @GLPROTO_LIBS@ +GLVND_CFLAGS = @GLVND_CFLAGS@ +GLVND_LIBS = @GLVND_LIBS@ GLX_TLS = @GLX_TLS@ GL_LIB = @GL_LIB@ GL_LIB_DEPS = @GL_LIB_DEPS@ @@ -328,11 +330,10 @@ LIBELF_CFLAGS = @LIBELF_CFLAGS@ LIBELF_LIBS = @LIBELF_LIBS@ LIBOBJS = @LIBOBJS@ LIBS = @LIBS@ +LIBSENSORS_LDFLAGS = @LIBSENSORS_LDFLAGS@ LIBSHA1_CFLAGS = @LIBSHA1_CFLAGS@ LIBSHA1_LIBS = @LIBSHA1_LIBS@ LIBTOOL = @LIBTOOL@ -LIBUDEV_CFLAGS = @LIBUDEV_CFLAGS@ -LIBUDEV_LIBS = @LIBUDEV_LIBS@ LIB_DIR = @LIB_DIR@ LIB_EXT = @LIB_EXT@ LIPO = @LIPO@ @@ -395,6 +396,8 @@ PKG_CONFIG_PATH = @PKG_CONFIG_PATH@ POSIX_SHELL = @POSIX_SHELL@ PRESENTPROTO_CFLAGS = @PRESENTPROTO_CFLAGS@ PRESENTPROTO_LIBS = @PRESENTPROTO_LIBS@ +PTHREADSTUBS_CFLAGS = @PTHREADSTUBS_CFLAGS@ +PTHREADSTUBS_LIBS = @PTHREADSTUBS_LIBS@ PTHREAD_CC = @PTHREAD_CC@ PTHREAD_CFLAGS = @PTHREAD_CFLAGS@ PTHREAD_LIBS = @PTHREAD_LIBS@ @@ -415,11 +418,19 @@ SIMPENROSE_CFLAGS = @SIMPENROSE_CFLAGS@ SIMPENROSE_LIBS = @SIMPENROSE_LIBS@ SSE41_CFLAGS = @SSE41_CFLAGS@ STRIP = @STRIP@ +SWR_AVX2_CXXFLAGS = @SWR_AVX2_CXXFLAGS@ +SWR_AVX_CXXFLAGS = @SWR_AVX_CXXFLAGS@ +SWR_CXX11_CXXFLAGS = @SWR_CXX11_CXXFLAGS@ +TIMESTAMP_CMD = @TIMESTAMP_CMD@ +VALGRIND_CFLAGS = @VALGRIND_CFLAGS@ +VALGRIND_LIBS = @VALGRIND_LIBS@ VA_CFLAGS = @VA_CFLAGS@ VA_LIBS = @VA_LIBS@ VA_LIB_INSTALL_DIR = @VA_LIB_INSTALL_DIR@ VA_MAJOR = @VA_MAJOR@ VA_MINOR = @VA_MINOR@ +VC4_CFLAGS = @VC4_CFLAGS@ +VC4_LIBS = @VC4_LIBS@ VDPAU_CFLAGS = @VDPAU_CFLAGS@ VDPAU_LIBS = @VDPAU_LIBS@ VDPAU_LIB_INSTALL_DIR = @VDPAU_LIB_INSTALL_DIR@ @@ -431,6 +442,7 @@ VISIBILITY_CFLAGS = @VISIBILITY_CFLAGS@ VISIBILITY_CXXFLAGS = @VISIBILITY_CXXFLAGS@ VL_CFLAGS = @VL_CFLAGS@ VL_LIBS = @VL_LIBS@ +VULKAN_ICD_INSTALL_DIR = @VULKAN_ICD_INSTALL_DIR@ WAYLAND_CFLAGS = @WAYLAND_CFLAGS@ WAYLAND_LIBS = @WAYLAND_LIBS@ WAYLAND_SCANNER = @WAYLAND_SCANNER@ @@ -454,6 +466,7 @@ XVMC_LIBS = @XVMC_LIBS@ XVMC_LIB_INSTALL_DIR = @XVMC_LIB_INSTALL_DIR@ XVMC_MAJOR = @XVMC_MAJOR@ XVMC_MINOR = @XVMC_MINOR@ +XXD = @XXD@ YACC = @YACC@ YFLAGS = @YFLAGS@ abs_builddir = @abs_builddir@ diff --git a/lib/mesa/src/gallium/drivers/noop/Makefile.in b/lib/mesa/src/gallium/drivers/noop/Makefile.in index fc1e39dfc..709bea70c 100644 --- a/lib/mesa/src/gallium/drivers/noop/Makefile.in +++ b/lib/mesa/src/gallium/drivers/noop/Makefile.in @@ -204,6 +204,8 @@ GLESv2_LIB_DEPS = @GLESv2_LIB_DEPS@ GLESv2_PC_LIB_PRIV = @GLESv2_PC_LIB_PRIV@ GLPROTO_CFLAGS = @GLPROTO_CFLAGS@ GLPROTO_LIBS = @GLPROTO_LIBS@ +GLVND_CFLAGS = @GLVND_CFLAGS@ +GLVND_LIBS = @GLVND_LIBS@ GLX_TLS = @GLX_TLS@ GL_LIB = @GL_LIB@ GL_LIB_DEPS = @GL_LIB_DEPS@ @@ -235,11 +237,10 @@ LIBELF_CFLAGS = @LIBELF_CFLAGS@ LIBELF_LIBS = @LIBELF_LIBS@ LIBOBJS = @LIBOBJS@ LIBS = @LIBS@ +LIBSENSORS_LDFLAGS = @LIBSENSORS_LDFLAGS@ LIBSHA1_CFLAGS = @LIBSHA1_CFLAGS@ LIBSHA1_LIBS = @LIBSHA1_LIBS@ LIBTOOL = @LIBTOOL@ -LIBUDEV_CFLAGS = @LIBUDEV_CFLAGS@ -LIBUDEV_LIBS = @LIBUDEV_LIBS@ LIB_DIR = @LIB_DIR@ LIB_EXT = @LIB_EXT@ LIPO = @LIPO@ @@ -302,6 +303,8 @@ PKG_CONFIG_PATH = @PKG_CONFIG_PATH@ POSIX_SHELL = @POSIX_SHELL@ PRESENTPROTO_CFLAGS = @PRESENTPROTO_CFLAGS@ PRESENTPROTO_LIBS = @PRESENTPROTO_LIBS@ +PTHREADSTUBS_CFLAGS = @PTHREADSTUBS_CFLAGS@ +PTHREADSTUBS_LIBS = @PTHREADSTUBS_LIBS@ PTHREAD_CC = @PTHREAD_CC@ PTHREAD_CFLAGS = @PTHREAD_CFLAGS@ PTHREAD_LIBS = @PTHREAD_LIBS@ @@ -322,11 +325,19 @@ SIMPENROSE_CFLAGS = @SIMPENROSE_CFLAGS@ SIMPENROSE_LIBS = @SIMPENROSE_LIBS@ SSE41_CFLAGS = @SSE41_CFLAGS@ STRIP = @STRIP@ +SWR_AVX2_CXXFLAGS = @SWR_AVX2_CXXFLAGS@ +SWR_AVX_CXXFLAGS = @SWR_AVX_CXXFLAGS@ +SWR_CXX11_CXXFLAGS = @SWR_CXX11_CXXFLAGS@ +TIMESTAMP_CMD = @TIMESTAMP_CMD@ +VALGRIND_CFLAGS = @VALGRIND_CFLAGS@ +VALGRIND_LIBS = @VALGRIND_LIBS@ VA_CFLAGS = @VA_CFLAGS@ VA_LIBS = @VA_LIBS@ VA_LIB_INSTALL_DIR = @VA_LIB_INSTALL_DIR@ VA_MAJOR = @VA_MAJOR@ VA_MINOR = @VA_MINOR@ +VC4_CFLAGS = @VC4_CFLAGS@ +VC4_LIBS = @VC4_LIBS@ VDPAU_CFLAGS = @VDPAU_CFLAGS@ VDPAU_LIBS = @VDPAU_LIBS@ VDPAU_LIB_INSTALL_DIR = @VDPAU_LIB_INSTALL_DIR@ @@ -338,6 +349,7 @@ VISIBILITY_CFLAGS = @VISIBILITY_CFLAGS@ VISIBILITY_CXXFLAGS = @VISIBILITY_CXXFLAGS@ VL_CFLAGS = @VL_CFLAGS@ VL_LIBS = @VL_LIBS@ +VULKAN_ICD_INSTALL_DIR = @VULKAN_ICD_INSTALL_DIR@ WAYLAND_CFLAGS = @WAYLAND_CFLAGS@ WAYLAND_LIBS = @WAYLAND_LIBS@ WAYLAND_SCANNER = @WAYLAND_SCANNER@ @@ -361,6 +373,7 @@ XVMC_LIBS = @XVMC_LIBS@ XVMC_LIB_INSTALL_DIR = @XVMC_LIB_INSTALL_DIR@ XVMC_MAJOR = @XVMC_MAJOR@ XVMC_MINOR = @XVMC_MINOR@ +XXD = @XXD@ YACC = @YACC@ YFLAGS = @YFLAGS@ abs_builddir = @abs_builddir@ diff --git a/lib/mesa/src/gallium/drivers/nouveau/Makefile.in b/lib/mesa/src/gallium/drivers/nouveau/Makefile.in index cb7afdc2b..01160d958 100644 --- a/lib/mesa/src/gallium/drivers/nouveau/Makefile.in +++ b/lib/mesa/src/gallium/drivers/nouveau/Makefile.in @@ -301,6 +301,8 @@ GLESv2_LIB_DEPS = @GLESv2_LIB_DEPS@ GLESv2_PC_LIB_PRIV = @GLESv2_PC_LIB_PRIV@ GLPROTO_CFLAGS = @GLPROTO_CFLAGS@ GLPROTO_LIBS = @GLPROTO_LIBS@ +GLVND_CFLAGS = @GLVND_CFLAGS@ +GLVND_LIBS = @GLVND_LIBS@ GLX_TLS = @GLX_TLS@ GL_LIB = @GL_LIB@ GL_LIB_DEPS = @GL_LIB_DEPS@ @@ -332,11 +334,10 @@ LIBELF_CFLAGS = @LIBELF_CFLAGS@ LIBELF_LIBS = @LIBELF_LIBS@ LIBOBJS = @LIBOBJS@ LIBS = @LIBS@ +LIBSENSORS_LDFLAGS = @LIBSENSORS_LDFLAGS@ LIBSHA1_CFLAGS = @LIBSHA1_CFLAGS@ LIBSHA1_LIBS = @LIBSHA1_LIBS@ LIBTOOL = @LIBTOOL@ -LIBUDEV_CFLAGS = @LIBUDEV_CFLAGS@ -LIBUDEV_LIBS = @LIBUDEV_LIBS@ LIB_DIR = @LIB_DIR@ LIB_EXT = @LIB_EXT@ LIPO = @LIPO@ @@ -399,6 +400,8 @@ PKG_CONFIG_PATH = @PKG_CONFIG_PATH@ POSIX_SHELL = @POSIX_SHELL@ PRESENTPROTO_CFLAGS = @PRESENTPROTO_CFLAGS@ PRESENTPROTO_LIBS = @PRESENTPROTO_LIBS@ +PTHREADSTUBS_CFLAGS = @PTHREADSTUBS_CFLAGS@ +PTHREADSTUBS_LIBS = @PTHREADSTUBS_LIBS@ PTHREAD_CC = @PTHREAD_CC@ PTHREAD_CFLAGS = @PTHREAD_CFLAGS@ PTHREAD_LIBS = @PTHREAD_LIBS@ @@ -419,11 +422,19 @@ SIMPENROSE_CFLAGS = @SIMPENROSE_CFLAGS@ SIMPENROSE_LIBS = @SIMPENROSE_LIBS@ SSE41_CFLAGS = @SSE41_CFLAGS@ STRIP = @STRIP@ +SWR_AVX2_CXXFLAGS = @SWR_AVX2_CXXFLAGS@ +SWR_AVX_CXXFLAGS = @SWR_AVX_CXXFLAGS@ +SWR_CXX11_CXXFLAGS = @SWR_CXX11_CXXFLAGS@ +TIMESTAMP_CMD = @TIMESTAMP_CMD@ +VALGRIND_CFLAGS = @VALGRIND_CFLAGS@ +VALGRIND_LIBS = @VALGRIND_LIBS@ VA_CFLAGS = @VA_CFLAGS@ VA_LIBS = @VA_LIBS@ VA_LIB_INSTALL_DIR = @VA_LIB_INSTALL_DIR@ VA_MAJOR = @VA_MAJOR@ VA_MINOR = @VA_MINOR@ +VC4_CFLAGS = @VC4_CFLAGS@ +VC4_LIBS = @VC4_LIBS@ VDPAU_CFLAGS = @VDPAU_CFLAGS@ VDPAU_LIBS = @VDPAU_LIBS@ VDPAU_LIB_INSTALL_DIR = @VDPAU_LIB_INSTALL_DIR@ @@ -435,6 +446,7 @@ VISIBILITY_CFLAGS = @VISIBILITY_CFLAGS@ VISIBILITY_CXXFLAGS = @VISIBILITY_CXXFLAGS@ VL_CFLAGS = @VL_CFLAGS@ VL_LIBS = @VL_LIBS@ +VULKAN_ICD_INSTALL_DIR = @VULKAN_ICD_INSTALL_DIR@ WAYLAND_CFLAGS = @WAYLAND_CFLAGS@ WAYLAND_LIBS = @WAYLAND_LIBS@ WAYLAND_SCANNER = @WAYLAND_SCANNER@ @@ -458,6 +470,7 @@ XVMC_LIBS = @XVMC_LIBS@ XVMC_LIB_INSTALL_DIR = @XVMC_LIB_INSTALL_DIR@ XVMC_MAJOR = @XVMC_MAJOR@ XVMC_MINOR = @XVMC_MINOR@ +XXD = @XXD@ YACC = @YACC@ YFLAGS = @YFLAGS@ abs_builddir = @abs_builddir@ @@ -672,7 +685,6 @@ NVC0_C_SOURCES := \ nvc0/gm107_texture.xml.h \ nvc0/nvc0_3d.xml.h \ nvc0/nvc0_compute.c \ - nvc0/nvc0_compute.h \ nvc0/nvc0_compute.xml.h \ nvc0/nvc0_context.c \ nvc0/nvc0_context.h \ diff --git a/lib/mesa/src/gallium/drivers/nouveau/nvc0/nvc0_compute.h b/lib/mesa/src/gallium/drivers/nouveau/nvc0/nvc0_compute.h deleted file mode 100644 index 168a6d1be..000000000 --- a/lib/mesa/src/gallium/drivers/nouveau/nvc0/nvc0_compute.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef NVC0_COMPUTE_H -#define NVC0_COMPUTE_H - -#include "nv50/nv50_defs.xml.h" -#include "nvc0/nvc0_compute.xml.h" - -bool -nvc0_compute_validate_program(struct nvc0_context *nvc0); - -#endif /* NVC0_COMPUTE_H */ diff --git a/lib/mesa/src/gallium/drivers/r300/Makefile.in b/lib/mesa/src/gallium/drivers/r300/Makefile.in index 14a623da4..40a2a4546 100644 --- a/lib/mesa/src/gallium/drivers/r300/Makefile.in +++ b/lib/mesa/src/gallium/drivers/r300/Makefile.in @@ -250,6 +250,8 @@ GLESv2_LIB_DEPS = @GLESv2_LIB_DEPS@ GLESv2_PC_LIB_PRIV = @GLESv2_PC_LIB_PRIV@ GLPROTO_CFLAGS = @GLPROTO_CFLAGS@ GLPROTO_LIBS = @GLPROTO_LIBS@ +GLVND_CFLAGS = @GLVND_CFLAGS@ +GLVND_LIBS = @GLVND_LIBS@ GLX_TLS = @GLX_TLS@ GL_LIB = @GL_LIB@ GL_LIB_DEPS = @GL_LIB_DEPS@ @@ -281,11 +283,10 @@ LIBELF_CFLAGS = @LIBELF_CFLAGS@ LIBELF_LIBS = @LIBELF_LIBS@ LIBOBJS = @LIBOBJS@ LIBS = @LIBS@ +LIBSENSORS_LDFLAGS = @LIBSENSORS_LDFLAGS@ LIBSHA1_CFLAGS = @LIBSHA1_CFLAGS@ LIBSHA1_LIBS = @LIBSHA1_LIBS@ LIBTOOL = @LIBTOOL@ -LIBUDEV_CFLAGS = @LIBUDEV_CFLAGS@ -LIBUDEV_LIBS = @LIBUDEV_LIBS@ LIB_DIR = @LIB_DIR@ LIB_EXT = @LIB_EXT@ LIPO = @LIPO@ @@ -348,6 +349,8 @@ PKG_CONFIG_PATH = @PKG_CONFIG_PATH@ POSIX_SHELL = @POSIX_SHELL@ PRESENTPROTO_CFLAGS = @PRESENTPROTO_CFLAGS@ PRESENTPROTO_LIBS = @PRESENTPROTO_LIBS@ +PTHREADSTUBS_CFLAGS = @PTHREADSTUBS_CFLAGS@ +PTHREADSTUBS_LIBS = @PTHREADSTUBS_LIBS@ PTHREAD_CC = @PTHREAD_CC@ PTHREAD_CFLAGS = @PTHREAD_CFLAGS@ PTHREAD_LIBS = @PTHREAD_LIBS@ @@ -368,11 +371,19 @@ SIMPENROSE_CFLAGS = @SIMPENROSE_CFLAGS@ SIMPENROSE_LIBS = @SIMPENROSE_LIBS@ SSE41_CFLAGS = @SSE41_CFLAGS@ STRIP = @STRIP@ +SWR_AVX2_CXXFLAGS = @SWR_AVX2_CXXFLAGS@ +SWR_AVX_CXXFLAGS = @SWR_AVX_CXXFLAGS@ +SWR_CXX11_CXXFLAGS = @SWR_CXX11_CXXFLAGS@ +TIMESTAMP_CMD = @TIMESTAMP_CMD@ +VALGRIND_CFLAGS = @VALGRIND_CFLAGS@ +VALGRIND_LIBS = @VALGRIND_LIBS@ VA_CFLAGS = @VA_CFLAGS@ VA_LIBS = @VA_LIBS@ VA_LIB_INSTALL_DIR = @VA_LIB_INSTALL_DIR@ VA_MAJOR = @VA_MAJOR@ VA_MINOR = @VA_MINOR@ +VC4_CFLAGS = @VC4_CFLAGS@ +VC4_LIBS = @VC4_LIBS@ VDPAU_CFLAGS = @VDPAU_CFLAGS@ VDPAU_LIBS = @VDPAU_LIBS@ VDPAU_LIB_INSTALL_DIR = @VDPAU_LIB_INSTALL_DIR@ @@ -384,6 +395,7 @@ VISIBILITY_CFLAGS = @VISIBILITY_CFLAGS@ VISIBILITY_CXXFLAGS = @VISIBILITY_CXXFLAGS@ VL_CFLAGS = @VL_CFLAGS@ VL_LIBS = @VL_LIBS@ +VULKAN_ICD_INSTALL_DIR = @VULKAN_ICD_INSTALL_DIR@ WAYLAND_CFLAGS = @WAYLAND_CFLAGS@ WAYLAND_LIBS = @WAYLAND_LIBS@ WAYLAND_SCANNER = @WAYLAND_SCANNER@ @@ -407,6 +419,7 @@ XVMC_LIBS = @XVMC_LIBS@ XVMC_LIB_INSTALL_DIR = @XVMC_LIB_INSTALL_DIR@ XVMC_MAJOR = @XVMC_MAJOR@ XVMC_MINOR = @XVMC_MINOR@ +XXD = @XXD@ YACC = @YACC@ YFLAGS = @YFLAGS@ abs_builddir = @abs_builddir@ diff --git a/lib/mesa/src/gallium/drivers/r600/Makefile.in b/lib/mesa/src/gallium/drivers/r600/Makefile.in index 1da4fd29f..92152df6d 100644 --- a/lib/mesa/src/gallium/drivers/r600/Makefile.in +++ b/lib/mesa/src/gallium/drivers/r600/Makefile.in @@ -65,13 +65,7 @@ DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in \ @NEED_RADEON_LLVM_TRUE@ $(LLVM_CFLAGS) \ @NEED_RADEON_LLVM_TRUE@ -I$(top_srcdir)/src/gallium/drivers/radeon/ -@NEED_RADEON_LLVM_TRUE@am__append_4 = \ -@NEED_RADEON_LLVM_TRUE@ $(LLVM_C_SOURCES) - -@USE_R600_LLVM_COMPILER_TRUE@am__append_5 = \ -@USE_R600_LLVM_COMPILER_TRUE@ -DR600_USE_LLVM - -@HAVE_GALLIUM_COMPUTE_TRUE@am__append_6 = \ +@HAVE_GALLIUM_COMPUTE_TRUE@am__append_4 = \ @HAVE_GALLIUM_COMPUTE_TRUE@ -DHAVE_OPENCL subdir = src/gallium/drivers/r600 @@ -93,26 +87,6 @@ CONFIG_CLEAN_FILES = CONFIG_CLEAN_VPATH_FILES = LTLIBRARIES = $(noinst_LTLIBRARIES) libr600_la_LIBADD = -am__libr600_la_SOURCES_DIST = compute_memory_pool.c \ - compute_memory_pool.h eg_asm.c eg_sq.h evergreen_compute.c \ - evergreen_compute.h evergreen_compute_internal.h evergreend.h \ - evergreen_hw_context.c evergreen_state.c r600_asm.c r600_asm.h \ - r600_blit.c r600d.h r600_formats.h r600_hw_context.c \ - r600_isa.c r600_isa.h r600_opcodes.h r600_pipe.c r600_pipe.h \ - r600_public.h r600_shader.c r600_shader.h r600_sq.h \ - r600_state.c r600_state_common.c r600_uvd.c r700_asm.c \ - r700_sq.h sb/sb_bc_builder.cpp sb/sb_bc_decoder.cpp \ - sb/sb_bc_dump.cpp sb/sb_bc_finalize.cpp sb/sb_bc.h \ - sb/sb_bc_parser.cpp sb/sb_context.cpp sb/sb_core.cpp \ - sb/sb_dce_cleanup.cpp sb/sb_def_use.cpp sb/sb_dump.cpp \ - sb/sb_expr.cpp sb/sb_expr.h sb/sb_gcm.cpp sb/sb_gvn.cpp \ - sb/sb_if_conversion.cpp sb/sb_ir.cpp sb/sb_ir.h \ - sb/sb_liveness.cpp sb/sb_pass.cpp sb/sb_pass.h \ - sb/sb_peephole.cpp sb/sb_psi_ops.cpp sb/sb_public.h \ - sb/sb_ra_checker.cpp sb/sb_ra_coalesce.cpp sb/sb_ra_init.cpp \ - sb/sb_sched.cpp sb/sb_sched.h sb/sb_shader.cpp sb/sb_shader.h \ - sb/sb_ssa_builder.cpp sb/sb_valtable.cpp r600_llvm.c \ - r600_llvm.h am__objects_1 = compute_memory_pool.lo eg_asm.lo evergreen_compute.lo \ evergreen_hw_context.lo evergreen_state.lo r600_asm.lo \ r600_blit.lo r600_hw_context.lo r600_isa.lo r600_pipe.lo \ @@ -128,10 +102,7 @@ am__objects_2 = sb/sb_bc_builder.lo sb/sb_bc_decoder.lo \ sb/sb_psi_ops.lo sb/sb_ra_checker.lo sb/sb_ra_coalesce.lo \ sb/sb_ra_init.lo sb/sb_sched.lo sb/sb_shader.lo \ sb/sb_ssa_builder.lo sb/sb_valtable.lo -am__objects_3 = r600_llvm.lo -@NEED_RADEON_LLVM_TRUE@am__objects_4 = $(am__objects_3) -am_libr600_la_OBJECTS = $(am__objects_1) $(am__objects_2) \ - $(am__objects_4) +am_libr600_la_OBJECTS = $(am__objects_1) $(am__objects_2) libr600_la_OBJECTS = $(am_libr600_la_OBJECTS) AM_V_lt = $(am__v_lt_@AM_V@) am__v_lt_ = $(am__v_lt_@AM_DEFAULT_V@) @@ -190,7 +161,7 @@ am__v_CXXLD_ = $(am__v_CXXLD_@AM_DEFAULT_V@) am__v_CXXLD_0 = @echo " CXXLD " $@; am__v_CXXLD_1 = SOURCES = $(libr600_la_SOURCES) -DIST_SOURCES = $(am__libr600_la_SOURCES_DIST) +DIST_SOURCES = $(libr600_la_SOURCES) am__can_run_installinfo = \ case $$AM_UPDATE_INFO_DIR in \ n|no|NO) false;; \ @@ -267,6 +238,8 @@ GLESv2_LIB_DEPS = @GLESv2_LIB_DEPS@ GLESv2_PC_LIB_PRIV = @GLESv2_PC_LIB_PRIV@ GLPROTO_CFLAGS = @GLPROTO_CFLAGS@ GLPROTO_LIBS = @GLPROTO_LIBS@ +GLVND_CFLAGS = @GLVND_CFLAGS@ +GLVND_LIBS = @GLVND_LIBS@ GLX_TLS = @GLX_TLS@ GL_LIB = @GL_LIB@ GL_LIB_DEPS = @GL_LIB_DEPS@ @@ -298,11 +271,10 @@ LIBELF_CFLAGS = @LIBELF_CFLAGS@ LIBELF_LIBS = @LIBELF_LIBS@ LIBOBJS = @LIBOBJS@ LIBS = @LIBS@ +LIBSENSORS_LDFLAGS = @LIBSENSORS_LDFLAGS@ LIBSHA1_CFLAGS = @LIBSHA1_CFLAGS@ LIBSHA1_LIBS = @LIBSHA1_LIBS@ LIBTOOL = @LIBTOOL@ -LIBUDEV_CFLAGS = @LIBUDEV_CFLAGS@ -LIBUDEV_LIBS = @LIBUDEV_LIBS@ LIB_DIR = @LIB_DIR@ LIB_EXT = @LIB_EXT@ LIPO = @LIPO@ @@ -365,6 +337,8 @@ PKG_CONFIG_PATH = @PKG_CONFIG_PATH@ POSIX_SHELL = @POSIX_SHELL@ PRESENTPROTO_CFLAGS = @PRESENTPROTO_CFLAGS@ PRESENTPROTO_LIBS = @PRESENTPROTO_LIBS@ +PTHREADSTUBS_CFLAGS = @PTHREADSTUBS_CFLAGS@ +PTHREADSTUBS_LIBS = @PTHREADSTUBS_LIBS@ PTHREAD_CC = @PTHREAD_CC@ PTHREAD_CFLAGS = @PTHREAD_CFLAGS@ PTHREAD_LIBS = @PTHREAD_LIBS@ @@ -385,11 +359,19 @@ SIMPENROSE_CFLAGS = @SIMPENROSE_CFLAGS@ SIMPENROSE_LIBS = @SIMPENROSE_LIBS@ SSE41_CFLAGS = @SSE41_CFLAGS@ STRIP = @STRIP@ +SWR_AVX2_CXXFLAGS = @SWR_AVX2_CXXFLAGS@ +SWR_AVX_CXXFLAGS = @SWR_AVX_CXXFLAGS@ +SWR_CXX11_CXXFLAGS = @SWR_CXX11_CXXFLAGS@ +TIMESTAMP_CMD = @TIMESTAMP_CMD@ +VALGRIND_CFLAGS = @VALGRIND_CFLAGS@ +VALGRIND_LIBS = @VALGRIND_LIBS@ VA_CFLAGS = @VA_CFLAGS@ VA_LIBS = @VA_LIBS@ VA_LIB_INSTALL_DIR = @VA_LIB_INSTALL_DIR@ VA_MAJOR = @VA_MAJOR@ VA_MINOR = @VA_MINOR@ +VC4_CFLAGS = @VC4_CFLAGS@ +VC4_LIBS = @VC4_LIBS@ VDPAU_CFLAGS = @VDPAU_CFLAGS@ VDPAU_LIBS = @VDPAU_LIBS@ VDPAU_LIB_INSTALL_DIR = @VDPAU_LIB_INSTALL_DIR@ @@ -401,6 +383,7 @@ VISIBILITY_CFLAGS = @VISIBILITY_CFLAGS@ VISIBILITY_CXXFLAGS = @VISIBILITY_CXXFLAGS@ VL_CFLAGS = @VL_CFLAGS@ VL_LIBS = @VL_LIBS@ +VULKAN_ICD_INSTALL_DIR = @VULKAN_ICD_INSTALL_DIR@ WAYLAND_CFLAGS = @WAYLAND_CFLAGS@ WAYLAND_LIBS = @WAYLAND_LIBS@ WAYLAND_SCANNER = @WAYLAND_SCANNER@ @@ -424,6 +407,7 @@ XVMC_LIBS = @XVMC_LIBS@ XVMC_LIB_INSTALL_DIR = @XVMC_LIB_INSTALL_DIR@ XVMC_MAJOR = @XVMC_MAJOR@ XVMC_MINOR = @XVMC_MINOR@ +XXD = @XXD@ YACC = @YACC@ YFLAGS = @YFLAGS@ abs_builddir = @abs_builddir@ @@ -553,10 +537,6 @@ CXX_SOURCES = \ sb/sb_ssa_builder.cpp \ sb/sb_valtable.cpp -LLVM_C_SOURCES = \ - r600_llvm.c \ - r600_llvm.h - GALLIUM_CFLAGS = \ -I$(top_srcdir)/include \ -I$(top_srcdir)/src \ @@ -622,14 +602,18 @@ GALLIUM_PIPE_LOADER_WINSYS_LIBS = \ $(top_builddir)/src/gallium/winsys/sw/null/libws_null.la \ $(top_builddir)/src/gallium/winsys/sw/wrapper/libwsw.la \ $(am__append_1) $(am__append_2) -AM_CFLAGS = $(GALLIUM_DRIVER_CFLAGS) $(RADEON_CFLAGS) $(am__append_3) \ - $(am__append_5) $(am__append_6) +AM_CFLAGS = $(GALLIUM_DRIVER_CFLAGS) $(RADEON_CFLAGS) \ + -I$(top_srcdir)/src/amd/common $(am__append_3) $(am__append_4) AM_CXXFLAGS = \ $(GALLIUM_DRIVER_CXXFLAGS) \ - $(RADEON_CFLAGS) + $(RADEON_CFLAGS) \ + -I$(top_srcdir)/src/amd/common noinst_LTLIBRARIES = libr600.la -libr600_la_SOURCES = $(C_SOURCES) $(CXX_SOURCES) $(am__append_4) +libr600_la_SOURCES = \ + $(C_SOURCES) \ + $(CXX_SOURCES) + EXTRA_DIST = \ sb/notes.markdown \ sb/sb_bc_fmt_def.inc @@ -733,7 +717,6 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/r600_blit.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/r600_hw_context.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/r600_isa.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/r600_llvm.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/r600_pipe.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/r600_shader.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/r600_state.Plo@am__quote@ diff --git a/lib/mesa/src/gallium/drivers/r600/r600_llvm.c b/lib/mesa/src/gallium/drivers/r600/r600_llvm.c deleted file mode 100644 index faf538ccb..000000000 --- a/lib/mesa/src/gallium/drivers/r600/r600_llvm.c +++ /dev/null @@ -1,1043 +0,0 @@ -#include "r600_llvm.h" - -#include "gallivm/lp_bld_const.h" -#include "gallivm/lp_bld_intr.h" -#include "gallivm/lp_bld_gather.h" -#include "tgsi/tgsi_parse.h" -#include "util/list.h" -#include "util/u_memory.h" - -#include "evergreend.h" -#include "r600_asm.h" -#include "r600_sq.h" -#include "r600_opcodes.h" -#include "r600_shader.h" -#include "r600_pipe.h" -#include "radeon_llvm.h" -#include "radeon_llvm_emit.h" -#include "radeon_elf_util.h" - -#include <stdio.h> - -#if defined R600_USE_LLVM || defined HAVE_OPENCL - -#define CONSTANT_BUFFER_0_ADDR_SPACE 8 -#define CONSTANT_BUFFER_1_ADDR_SPACE (CONSTANT_BUFFER_0_ADDR_SPACE + R600_UCP_CONST_BUFFER) -#define LLVM_R600_BUFFER_INFO_CONST_BUFFER \ - (CONSTANT_BUFFER_0_ADDR_SPACE + R600_BUFFER_INFO_CONST_BUFFER) - -static LLVMValueRef llvm_load_const_buffer( - struct lp_build_tgsi_context * bld_base, - LLVMValueRef OffsetValue, - unsigned ConstantAddressSpace) -{ - LLVMValueRef offset[2] = { - LLVMConstInt(LLVMInt64TypeInContext(bld_base->base.gallivm->context), 0, false), - OffsetValue - }; - - LLVMTypeRef const_ptr_type = LLVMPointerType(LLVMArrayType(LLVMVectorType(bld_base->base.elem_type, 4), 1024), - ConstantAddressSpace); - LLVMValueRef const_ptr = LLVMBuildIntToPtr(bld_base->base.gallivm->builder, lp_build_const_int32(bld_base->base.gallivm, 0), const_ptr_type, ""); - LLVMValueRef ptr = LLVMBuildGEP(bld_base->base.gallivm->builder, const_ptr, offset, 2, ""); - return LLVMBuildLoad(bld_base->base.gallivm->builder, ptr, ""); -} - -static LLVMValueRef llvm_fetch_const( - struct lp_build_tgsi_context * bld_base, - const struct tgsi_full_src_register *reg, - enum tgsi_opcode_type type, - unsigned swizzle) -{ - LLVMValueRef offset = lp_build_const_int32(bld_base->base.gallivm, reg->Register.Index); - if (reg->Register.Indirect) { - struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base); - LLVMValueRef index = LLVMBuildLoad(bld_base->base.gallivm->builder, bld->addr[reg->Indirect.Index][reg->Indirect.Swizzle], ""); - offset = LLVMBuildAdd(bld_base->base.gallivm->builder, offset, index, ""); - } - unsigned ConstantAddressSpace = CONSTANT_BUFFER_0_ADDR_SPACE ; - if (reg->Register.Dimension) { - ConstantAddressSpace += reg->Dimension.Index; - } - LLVMValueRef cvecval = llvm_load_const_buffer(bld_base, offset, ConstantAddressSpace); - LLVMValueRef cval = LLVMBuildExtractElement(bld_base->base.gallivm->builder, cvecval, lp_build_const_int32(bld_base->base.gallivm, swizzle), ""); - return bitcast(bld_base, type, cval); -} - -static void llvm_load_system_value( - struct radeon_llvm_context * ctx, - unsigned index, - const struct tgsi_full_declaration *decl) -{ - unsigned chan; - - switch (decl->Semantic.Name) { - case TGSI_SEMANTIC_INSTANCEID: chan = 3; break; - case TGSI_SEMANTIC_VERTEXID: chan = 0; break; - default: assert(!"unknown system value"); - } - -#if HAVE_LLVM >= 0x0304 - ctx->system_values[index] = LLVMBuildExtractElement(ctx->gallivm.builder, - LLVMGetParam(ctx->main_fn, 0), lp_build_const_int32(&(ctx->gallivm), chan), - ""); -#else - LLVMValueRef reg = lp_build_const_int32( - ctx->soa.bld_base.base.gallivm, chan); - ctx->system_values[index] = lp_build_intrinsic( - ctx->soa.bld_base.base.gallivm->builder, - "llvm.R600.load.input", - ctx->soa.bld_base.base.elem_type, ®, 1, - LLVMReadNoneAttribute); -#endif -} - -#if HAVE_LLVM >= 0x0304 -static LLVMValueRef -llvm_load_input_vector( - struct radeon_llvm_context * ctx, unsigned location, unsigned ijregs, - boolean interp) -{ - LLVMTypeRef VecType; - LLVMValueRef Args[3] = { - lp_build_const_int32(&(ctx->gallivm), location) - }; - unsigned ArgCount = 1; - if (interp) { - VecType = LLVMVectorType(ctx->soa.bld_base.base.elem_type, 2); - LLVMValueRef IJIndex = LLVMGetParam(ctx->main_fn, ijregs / 2); - Args[ArgCount++] = LLVMBuildExtractElement(ctx->gallivm.builder, IJIndex, - lp_build_const_int32(&(ctx->gallivm), 2 * (ijregs % 2)), ""); - Args[ArgCount++] = LLVMBuildExtractElement(ctx->gallivm.builder, IJIndex, - lp_build_const_int32(&(ctx->gallivm), 2 * (ijregs % 2) + 1), ""); - LLVMValueRef HalfVec[2] = { - lp_build_intrinsic(ctx->gallivm.builder, "llvm.R600.interp.xy", - VecType, Args, ArgCount, LLVMReadNoneAttribute), - lp_build_intrinsic(ctx->gallivm.builder, "llvm.R600.interp.zw", - VecType, Args, ArgCount, LLVMReadNoneAttribute) - }; - LLVMValueRef MaskInputs[4] = { - lp_build_const_int32(&(ctx->gallivm), 0), - lp_build_const_int32(&(ctx->gallivm), 1), - lp_build_const_int32(&(ctx->gallivm), 2), - lp_build_const_int32(&(ctx->gallivm), 3) - }; - LLVMValueRef Mask = LLVMConstVector(MaskInputs, 4); - return LLVMBuildShuffleVector(ctx->gallivm.builder, HalfVec[0], HalfVec[1], - Mask, ""); - } else { - VecType = LLVMVectorType(ctx->soa.bld_base.base.elem_type, 4); - return lp_build_intrinsic(ctx->gallivm.builder, "llvm.R600.interp.const", - VecType, Args, ArgCount, LLVMReadNoneAttribute); - } -} -#else -static LLVMValueRef -llvm_load_input_helper( - struct radeon_llvm_context * ctx, - unsigned idx, int interp, int ij_index) -{ - const struct lp_build_context * bb = &ctx->soa.bld_base.base; - LLVMValueRef arg[2]; - int arg_count; - const char * intrinsic; - - arg[0] = lp_build_const_int32(bb->gallivm, idx); - - if (interp) { - intrinsic = "llvm.R600.interp.input"; - arg[1] = lp_build_const_int32(bb->gallivm, ij_index); - arg_count = 2; - } else { - intrinsic = "llvm.R600.load.input"; - arg_count = 1; - } - - return lp_build_intrinsic(bb->gallivm->builder, intrinsic, - bb->elem_type, &arg[0], arg_count, LLVMReadNoneAttribute); -} -#endif - -#if HAVE_LLVM >= 0x0304 -static LLVMValueRef -llvm_face_select_helper( - struct radeon_llvm_context * ctx, - LLVMValueRef face, LLVMValueRef front_color, LLVMValueRef back_color) -{ - const struct lp_build_context * bb = &ctx->soa.bld_base.base; - LLVMValueRef is_front = LLVMBuildFCmp( - bb->gallivm->builder, LLVMRealUGT, face, - lp_build_const_float(bb->gallivm, 0.0f), ""); - return LLVMBuildSelect(bb->gallivm->builder, is_front, - front_color, back_color, ""); -} -#else -static LLVMValueRef -llvm_face_select_helper( - struct radeon_llvm_context * ctx, - unsigned face_loc, LLVMValueRef front_color, LLVMValueRef back_color) -{ - const struct lp_build_context * bb = &ctx->soa.bld_base.base; - LLVMValueRef face = llvm_load_input_helper(ctx, face_loc, 0, 0); - LLVMValueRef is_front = LLVMBuildFCmp( - bb->gallivm->builder, LLVMRealUGT, face, - lp_build_const_float(bb->gallivm, 0.0f), ""); - return LLVMBuildSelect(bb->gallivm->builder, is_front, - front_color, back_color, ""); -} -#endif - -static void llvm_load_input( - struct radeon_llvm_context * ctx, - unsigned input_index, - const struct tgsi_full_declaration *decl) -{ - const struct r600_shader_io * input = &ctx->r600_inputs[input_index]; - unsigned chan; -#if HAVE_LLVM < 0x0304 - unsigned interp = 0; - int ij_index; -#endif - int two_side = (ctx->two_side && input->name == TGSI_SEMANTIC_COLOR); - LLVMValueRef v; -#if HAVE_LLVM >= 0x0304 - boolean require_interp_intrinsic = ctx->chip_class >= EVERGREEN && - ctx->type == TGSI_PROCESSOR_FRAGMENT; -#endif - -#if HAVE_LLVM >= 0x0304 - if (require_interp_intrinsic && input->spi_sid) { - v = llvm_load_input_vector(ctx, input->lds_pos, input->ij_index, - (input->interpolate > 0)); - } else - v = LLVMGetParam(ctx->main_fn, input->gpr); - - if (two_side) { - struct r600_shader_io * back_input = - &ctx->r600_inputs[input->back_color_input]; - LLVMValueRef v2; - LLVMValueRef face = LLVMGetParam(ctx->main_fn, ctx->face_gpr); - face = LLVMBuildExtractElement(ctx->gallivm.builder, face, - lp_build_const_int32(&(ctx->gallivm), 0), ""); - - if (require_interp_intrinsic && back_input->spi_sid) - v2 = llvm_load_input_vector(ctx, back_input->lds_pos, - back_input->ij_index, (back_input->interpolate > 0)); - else - v2 = LLVMGetParam(ctx->main_fn, back_input->gpr); - v = llvm_face_select_helper(ctx, face, v, v2); - } - - for (chan = 0; chan < 4; chan++) { - unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan); - - ctx->inputs[soa_index] = LLVMBuildExtractElement(ctx->gallivm.builder, v, - lp_build_const_int32(&(ctx->gallivm), chan), ""); - - if (input->name == TGSI_SEMANTIC_POSITION && - ctx->type == TGSI_PROCESSOR_FRAGMENT && chan == 3) { - /* RCP for fragcoord.w */ - ctx->inputs[soa_index] = LLVMBuildFDiv(ctx->gallivm.builder, - lp_build_const_float(&(ctx->gallivm), 1.0f), - ctx->inputs[soa_index], ""); - } -} -#else - if (ctx->chip_class >= EVERGREEN && ctx->type == TGSI_PROCESSOR_FRAGMENT && - input->spi_sid) { - interp = 1; - ij_index = (input->interpolate > 0) ? input->ij_index : -1; - } - - for (chan = 0; chan < 4; chan++) { - unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan); - int loc; - - if (interp) { - loc = 4 * input->lds_pos + chan; - } else { - if (input->name == TGSI_SEMANTIC_FACE) - loc = 4 * ctx->face_gpr; - else - loc = 4 * input->gpr + chan; - } - - v = llvm_load_input_helper(ctx, loc, interp, ij_index); - - if (two_side) { - struct r600_shader_io * back_input = - &ctx->r600_inputs[input->back_color_input]; - int back_loc = interp ? back_input->lds_pos : back_input->gpr; - LLVMValueRef v2; - - back_loc = 4 * back_loc + chan; - v2 = llvm_load_input_helper(ctx, back_loc, interp, ij_index); - v = llvm_face_select_helper(ctx, 4 * ctx->face_gpr, v, v2); - } else if (input->name == TGSI_SEMANTIC_POSITION && - ctx->type == TGSI_PROCESSOR_FRAGMENT && chan == 3) { - /* RCP for fragcoord.w */ - v = LLVMBuildFDiv(ctx->gallivm.builder, - lp_build_const_float(&(ctx->gallivm), 1.0f), - v, ""); - } - - ctx->inputs[soa_index] = v; - } -#endif -} - -static void llvm_emit_prologue(struct lp_build_tgsi_context * bld_base) -{ - struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base); - radeon_llvm_shader_type(ctx->main_fn, ctx->type); - -} - -static void llvm_emit_epilogue(struct lp_build_tgsi_context * bld_base) -{ - struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base); - struct lp_build_context * base = &bld_base->base; - struct pipe_stream_output_info * so = ctx->stream_outputs; - unsigned i; - unsigned next_pos = 60; - unsigned next_param = 0; - - unsigned color_count = 0; - boolean has_color = false; - - if (ctx->type == TGSI_PROCESSOR_VERTEX && so->num_outputs) { - for (i = 0; i < so->num_outputs; i++) { - unsigned register_index = so->output[i].register_index; - unsigned start_component = so->output[i].start_component; - unsigned num_components = so->output[i].num_components; - unsigned dst_offset = so->output[i].dst_offset; - unsigned chan; - LLVMValueRef elements[4]; - if (dst_offset < start_component) { - for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) { - elements[chan] = LLVMBuildLoad(base->gallivm->builder, - ctx->soa.outputs[register_index][(chan + start_component) % TGSI_NUM_CHANNELS], ""); - } - start_component = 0; - } else { - for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) { - elements[chan] = LLVMBuildLoad(base->gallivm->builder, - ctx->soa.outputs[register_index][chan], ""); - } - } - LLVMValueRef output = lp_build_gather_values(base->gallivm, elements, 4); - LLVMValueRef args[4]; - args[0] = output; - args[1] = lp_build_const_int32(base->gallivm, dst_offset - start_component); - args[2] = lp_build_const_int32(base->gallivm, so->output[i].output_buffer); - args[3] = lp_build_const_int32(base->gallivm, ((1 << num_components) - 1) << start_component); - lp_build_intrinsic(base->gallivm->builder, "llvm.R600.store.stream.output", - LLVMVoidTypeInContext(base->gallivm->context), args, 4, 0); - } - } - - /* Add the necessary export instructions */ - for (i = 0; i < ctx->output_reg_count; i++) { - unsigned chan; - LLVMValueRef elements[4]; - for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) { - elements[chan] = LLVMBuildLoad(base->gallivm->builder, - ctx->soa.outputs[i][chan], ""); - } - if (ctx->alpha_to_one && ctx->type == TGSI_PROCESSOR_FRAGMENT && ctx->r600_outputs[i].name == TGSI_SEMANTIC_COLOR) - elements[3] = lp_build_const_float(base->gallivm, 1.0f); - LLVMValueRef output = lp_build_gather_values(base->gallivm, elements, 4); - - if (ctx->type == TGSI_PROCESSOR_VERTEX) { - switch (ctx->r600_outputs[i].name) { - case TGSI_SEMANTIC_POSITION: - case TGSI_SEMANTIC_PSIZE: { - LLVMValueRef args[3]; - args[0] = output; - args[1] = lp_build_const_int32(base->gallivm, next_pos++); - args[2] = lp_build_const_int32(base->gallivm, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS); - lp_build_intrinsic( - base->gallivm->builder, - "llvm.R600.store.swizzle", - LLVMVoidTypeInContext(base->gallivm->context), - args, 3, 0); - break; - } - case TGSI_SEMANTIC_CLIPVERTEX: { - LLVMValueRef args[3]; - unsigned reg_index; - LLVMValueRef adjusted_elements[4]; - for (reg_index = 0; reg_index < 2; reg_index ++) { - for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) { - LLVMValueRef offset = lp_build_const_int32(bld_base->base.gallivm, reg_index * 4 + chan); - LLVMValueRef base_vector = llvm_load_const_buffer(bld_base, offset, CONSTANT_BUFFER_1_ADDR_SPACE); - args[0] = output; - args[1] = base_vector; - adjusted_elements[chan] = lp_build_intrinsic(base->gallivm->builder, - "llvm.AMDGPU.dp4", bld_base->base.elem_type, - args, 2, LLVMReadNoneAttribute); - } - args[0] = lp_build_gather_values(base->gallivm, - adjusted_elements, 4); - args[1] = lp_build_const_int32(base->gallivm, next_pos++); - args[2] = lp_build_const_int32(base->gallivm, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS); - lp_build_intrinsic( - base->gallivm->builder, - "llvm.R600.store.swizzle", - LLVMVoidTypeInContext(base->gallivm->context), - args, 3, 0); - } - break; - } - case TGSI_SEMANTIC_CLIPDIST : { - LLVMValueRef args[3]; - args[0] = output; - args[1] = lp_build_const_int32(base->gallivm, next_pos++); - args[2] = lp_build_const_int32(base->gallivm, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS); - lp_build_intrinsic( - base->gallivm->builder, - "llvm.R600.store.swizzle", - LLVMVoidTypeInContext(base->gallivm->context), - args, 3, 0); - args[1] = lp_build_const_int32(base->gallivm, next_param++); - args[2] = lp_build_const_int32(base->gallivm, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM); - lp_build_intrinsic( - base->gallivm->builder, - "llvm.R600.store.swizzle", - LLVMVoidTypeInContext(base->gallivm->context), - args, 3, 0); - break; - } - case TGSI_SEMANTIC_FOG: { - elements[0] = LLVMBuildLoad(base->gallivm->builder, - ctx->soa.outputs[i][0], ""); - elements[1] = elements[2] = lp_build_const_float(base->gallivm, 0.0f); - elements[3] = lp_build_const_float(base->gallivm, 1.0f); - - LLVMValueRef args[3]; - args[0] = lp_build_gather_values(base->gallivm, elements, 4); - args[1] = lp_build_const_int32(base->gallivm, next_param++); - args[2] = lp_build_const_int32(base->gallivm, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM); - lp_build_intrinsic( - base->gallivm->builder, - "llvm.R600.store.swizzle", - LLVMVoidTypeInContext(base->gallivm->context), - args, 3, 0); - break; - } - default: { - LLVMValueRef args[3]; - args[0] = output; - args[1] = lp_build_const_int32(base->gallivm, next_param++); - args[2] = lp_build_const_int32(base->gallivm, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM); - lp_build_intrinsic( - base->gallivm->builder, - "llvm.R600.store.swizzle", - LLVMVoidTypeInContext(base->gallivm->context), - args, 3, 0); - break; - } - } - } else if (ctx->type == TGSI_PROCESSOR_FRAGMENT) { - switch (ctx->r600_outputs[i].name) { - case TGSI_SEMANTIC_COLOR: - has_color = true; - if ( color_count < ctx->color_buffer_count) { - LLVMValueRef args[3]; - args[0] = output; - if (ctx->fs_color_all) { - for (unsigned j = 0; j < ctx->color_buffer_count; j++) { - args[1] = lp_build_const_int32(base->gallivm, j); - args[2] = lp_build_const_int32(base->gallivm, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL); - lp_build_intrinsic( - base->gallivm->builder, - "llvm.R600.store.swizzle", - LLVMVoidTypeInContext(base->gallivm->context), - args, 3, 0); - } - } else { - args[1] = lp_build_const_int32(base->gallivm, color_count++); - args[2] = lp_build_const_int32(base->gallivm, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL); - lp_build_intrinsic( - base->gallivm->builder, - "llvm.R600.store.swizzle", - LLVMVoidTypeInContext(base->gallivm->context), - args, 3, 0); - } - } - break; - case TGSI_SEMANTIC_POSITION: - lp_build_intrinsic_unary( - base->gallivm->builder, - "llvm.R600.store.pixel.depth", - LLVMVoidTypeInContext(base->gallivm->context), - LLVMBuildLoad(base->gallivm->builder, ctx->soa.outputs[i][2], "")); - break; - case TGSI_SEMANTIC_STENCIL: - lp_build_intrinsic_unary( - base->gallivm->builder, - "llvm.R600.store.pixel.stencil", - LLVMVoidTypeInContext(base->gallivm->context), - LLVMBuildLoad(base->gallivm->builder, ctx->soa.outputs[i][1], "")); - break; - } - } - } - // Add dummy exports - if (ctx->type == TGSI_PROCESSOR_VERTEX) { - if (!next_param) { - lp_build_intrinsic_unary(base->gallivm->builder, "llvm.R600.store.dummy", - LLVMVoidTypeInContext(base->gallivm->context), - lp_build_const_int32(base->gallivm, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM)); - } - if (!(next_pos-60)) { - lp_build_intrinsic_unary(base->gallivm->builder, "llvm.R600.store.dummy", - LLVMVoidTypeInContext(base->gallivm->context), - lp_build_const_int32(base->gallivm, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS)); - } - } - if (ctx->type == TGSI_PROCESSOR_FRAGMENT) { - if (!has_color) { - lp_build_intrinsic_unary(base->gallivm->builder, "llvm.R600.store.dummy", - LLVMVoidTypeInContext(base->gallivm->context), - lp_build_const_int32(base->gallivm, V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL)); - } - } - -} - -static void llvm_emit_tex( - const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - struct gallivm_state * gallivm = bld_base->base.gallivm; - LLVMValueRef args[7]; - unsigned c, sampler_src; - struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base); - - if (emit_data->inst->Texture.Texture == TGSI_TEXTURE_BUFFER) { - switch (emit_data->inst->Instruction.Opcode) { - case TGSI_OPCODE_TXQ: { - struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base); - ctx->uses_tex_buffers = true; - bool isEgPlus = (ctx->chip_class >= EVERGREEN); - LLVMValueRef offset = lp_build_const_int32(bld_base->base.gallivm, - isEgPlus ? 0 : 1); - LLVMValueRef cvecval = llvm_load_const_buffer(bld_base, offset, - LLVM_R600_BUFFER_INFO_CONST_BUFFER); - if (!isEgPlus) { - LLVMValueRef maskval[4] = { - lp_build_const_int32(gallivm, 1), - lp_build_const_int32(gallivm, 2), - lp_build_const_int32(gallivm, 3), - lp_build_const_int32(gallivm, 0), - }; - LLVMValueRef mask = LLVMConstVector(maskval, 4); - cvecval = LLVMBuildShuffleVector(gallivm->builder, cvecval, cvecval, - mask, ""); - } - emit_data->output[0] = cvecval; - return; - } - case TGSI_OPCODE_TXF: { - args[0] = LLVMBuildExtractElement(gallivm->builder, emit_data->args[0], lp_build_const_int32(gallivm, 0), ""); - args[1] = lp_build_const_int32(gallivm, R600_MAX_CONST_BUFFERS); - emit_data->output[0] = lp_build_intrinsic(gallivm->builder, - "llvm.R600.load.texbuf", - emit_data->dst_type, args, 2, LLVMReadNoneAttribute); - if (ctx->chip_class >= EVERGREEN) - return; - ctx->uses_tex_buffers = true; - LLVMDumpValue(emit_data->output[0]); - emit_data->output[0] = LLVMBuildBitCast(gallivm->builder, - emit_data->output[0], LLVMVectorType(bld_base->base.int_elem_type, 4), - ""); - LLVMValueRef Mask = llvm_load_const_buffer(bld_base, - lp_build_const_int32(gallivm, 0), - LLVM_R600_BUFFER_INFO_CONST_BUFFER); - Mask = LLVMBuildBitCast(gallivm->builder, Mask, - LLVMVectorType(bld_base->base.int_elem_type, 4), ""); - emit_data->output[0] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_AND, - emit_data->output[0], - Mask); - LLVMValueRef WComponent = LLVMBuildExtractElement(gallivm->builder, - emit_data->output[0], lp_build_const_int32(gallivm, 3), ""); - Mask = llvm_load_const_buffer(bld_base, lp_build_const_int32(gallivm, 1), - LLVM_R600_BUFFER_INFO_CONST_BUFFER); - Mask = LLVMBuildExtractElement(gallivm->builder, Mask, - lp_build_const_int32(gallivm, 0), ""); - Mask = LLVMBuildBitCast(gallivm->builder, Mask, - bld_base->base.int_elem_type, ""); - WComponent = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_OR, - WComponent, Mask); - emit_data->output[0] = LLVMBuildInsertElement(gallivm->builder, - emit_data->output[0], WComponent, lp_build_const_int32(gallivm, 3), ""); - emit_data->output[0] = LLVMBuildBitCast(gallivm->builder, - emit_data->output[0], LLVMVectorType(bld_base->base.elem_type, 4), ""); - } - return; - default: - break; - } - } - - if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_TEX || - emit_data->inst->Instruction.Opcode == TGSI_OPCODE_TXP) { - LLVMValueRef Vector[4] = { - LLVMBuildExtractElement(gallivm->builder, emit_data->args[0], - lp_build_const_int32(gallivm, 0), ""), - LLVMBuildExtractElement(gallivm->builder, emit_data->args[0], - lp_build_const_int32(gallivm, 1), ""), - LLVMBuildExtractElement(gallivm->builder, emit_data->args[0], - lp_build_const_int32(gallivm, 2), ""), - LLVMBuildExtractElement(gallivm->builder, emit_data->args[0], - lp_build_const_int32(gallivm, 3), ""), - }; - switch (emit_data->inst->Texture.Texture) { - case TGSI_TEXTURE_2D: - case TGSI_TEXTURE_RECT: - Vector[2] = Vector[3] = LLVMGetUndef(bld_base->base.elem_type); - break; - case TGSI_TEXTURE_1D: - Vector[1] = Vector[2] = Vector[3] = LLVMGetUndef(bld_base->base.elem_type); - break; - default: - break; - } - args[0] = lp_build_gather_values(gallivm, Vector, 4); - } else { - args[0] = emit_data->args[0]; - } - - assert(emit_data->arg_count + 2 <= Elements(args)); - - for (c = 1; c < emit_data->arg_count; ++c) - args[c] = emit_data->args[c]; - - if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_TXF) { - args[1] = LLVMBuildShl(gallivm->builder, args[1], lp_build_const_int32(gallivm, 1), ""); - args[2] = LLVMBuildShl(gallivm->builder, args[2], lp_build_const_int32(gallivm, 1), ""); - args[3] = LLVMBuildShl(gallivm->builder, args[3], lp_build_const_int32(gallivm, 1), ""); - } - - sampler_src = emit_data->inst->Instruction.NumSrcRegs-1; - - args[c++] = lp_build_const_int32(gallivm, - emit_data->inst->Src[sampler_src].Register.Index + R600_MAX_CONST_BUFFERS); - args[c++] = lp_build_const_int32(gallivm, - emit_data->inst->Src[sampler_src].Register.Index); - args[c++] = lp_build_const_int32(gallivm, - emit_data->inst->Texture.Texture); - - if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_TXF && - (emit_data->inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA || - emit_data->inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA)) { - - switch (emit_data->inst->Texture.Texture) { - case TGSI_TEXTURE_2D_MSAA: - args[6] = lp_build_const_int32(gallivm, TGSI_TEXTURE_2D); - break; - case TGSI_TEXTURE_2D_ARRAY_MSAA: - args[6] = lp_build_const_int32(gallivm, TGSI_TEXTURE_2D_ARRAY); - break; - default: - break; - } - - if (ctx->has_compressed_msaa_texturing) { - LLVMValueRef ldptr_args[10] = { - args[0], // Coord - args[1], // Offset X - args[2], // Offset Y - args[3], // Offset Z - args[4], - args[5], - lp_build_const_int32(gallivm, 1), - lp_build_const_int32(gallivm, 1), - lp_build_const_int32(gallivm, 1), - lp_build_const_int32(gallivm, 1) - }; - LLVMValueRef ptr = lp_build_intrinsic(gallivm->builder, - "llvm.R600.ldptr", - emit_data->dst_type, ldptr_args, 10, LLVMReadNoneAttribute); - LLVMValueRef Tmp = LLVMBuildExtractElement(gallivm->builder, args[0], - lp_build_const_int32(gallivm, 3), ""); - Tmp = LLVMBuildMul(gallivm->builder, Tmp, - lp_build_const_int32(gallivm, 4), ""); - LLVMValueRef ResX = LLVMBuildExtractElement(gallivm->builder, ptr, - lp_build_const_int32(gallivm, 0), ""); - ResX = LLVMBuildBitCast(gallivm->builder, ResX, - bld_base->base.int_elem_type, ""); - Tmp = LLVMBuildLShr(gallivm->builder, ResX, Tmp, ""); - Tmp = LLVMBuildAnd(gallivm->builder, Tmp, - lp_build_const_int32(gallivm, 0xF), ""); - args[0] = LLVMBuildInsertElement(gallivm->builder, args[0], Tmp, - lp_build_const_int32(gallivm, 3), ""); - args[c++] = lp_build_const_int32(gallivm, - emit_data->inst->Texture.Texture); - } - } - - emit_data->output[0] = lp_build_intrinsic(gallivm->builder, - action->intr_name, - emit_data->dst_type, args, c, LLVMReadNoneAttribute); - - if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_TXQ && - ((emit_data->inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY || - emit_data->inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY))) - if (emit_data->inst->Dst[0].Register.WriteMask & 4) { - LLVMValueRef offset = lp_build_const_int32(bld_base->base.gallivm, 0); - LLVMValueRef ZLayer = LLVMBuildExtractElement(gallivm->builder, - llvm_load_const_buffer(bld_base, offset, LLVM_R600_BUFFER_INFO_CONST_BUFFER), - lp_build_const_int32(gallivm, 0), ""); - - emit_data->output[0] = LLVMBuildInsertElement(gallivm->builder, emit_data->output[0], ZLayer, lp_build_const_int32(gallivm, 2), ""); - struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base); - ctx->has_txq_cube_array_z_comp = true; - } -} - -static void emit_cndlt( - const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - LLVMBuilderRef builder = bld_base->base.gallivm->builder; - LLVMValueRef float_zero = lp_build_const_float( - bld_base->base.gallivm, 0.0f); - LLVMValueRef cmp = LLVMBuildFCmp( - builder, LLVMRealULT, emit_data->args[0], float_zero, ""); - emit_data->output[emit_data->chan] = LLVMBuildSelect(builder, - cmp, emit_data->args[1], emit_data->args[2], ""); -} - -static void dp_fetch_args( - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - struct lp_build_context * base = &bld_base->base; - unsigned chan; - LLVMValueRef elements[2][4]; - unsigned opcode = emit_data->inst->Instruction.Opcode; - unsigned dp_components = (opcode == TGSI_OPCODE_DP2 ? 2 : - (opcode == TGSI_OPCODE_DP3 ? 3 : 4)); - for (chan = 0 ; chan < dp_components; chan++) { - elements[0][chan] = lp_build_emit_fetch(bld_base, - emit_data->inst, 0, chan); - elements[1][chan] = lp_build_emit_fetch(bld_base, - emit_data->inst, 1, chan); - } - - for ( ; chan < 4; chan++) { - elements[0][chan] = base->zero; - elements[1][chan] = base->zero; - } - - /* Fix up for DPH */ - if (opcode == TGSI_OPCODE_DPH) { - elements[0][TGSI_CHAN_W] = base->one; - } - - emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm, - elements[0], 4); - emit_data->args[1] = lp_build_gather_values(bld_base->base.gallivm, - elements[1], 4); - emit_data->arg_count = 2; - - emit_data->dst_type = base->elem_type; -} - -static struct lp_build_tgsi_action dot_action = { - .fetch_args = dp_fetch_args, - .emit = build_tgsi_intrinsic_nomem, - .intr_name = "llvm.AMDGPU.dp4" -}; - -static void txd_fetch_args( - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - const struct tgsi_full_instruction * inst = emit_data->inst; - - LLVMValueRef coords[4]; - unsigned chan, src; - for (src = 0; src < 3; src++) { - for (chan = 0; chan < 4; chan++) - coords[chan] = lp_build_emit_fetch(bld_base, inst, src, chan); - - emit_data->args[src] = lp_build_gather_values(bld_base->base.gallivm, - coords, 4); - } - emit_data->arg_count = 3; - emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4); -} - - -static void txp_fetch_args( - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - const struct tgsi_full_instruction * inst = emit_data->inst; - LLVMValueRef src_w; - unsigned chan; - LLVMValueRef coords[5]; - - emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4); - src_w = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W); - - for (chan = 0; chan < 3; chan++ ) { - LLVMValueRef arg = lp_build_emit_fetch(bld_base, - emit_data->inst, 0, chan); - coords[chan] = lp_build_emit_llvm_binary(bld_base, - TGSI_OPCODE_DIV, arg, src_w); - } - coords[3] = bld_base->base.one; - - if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE || - inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY || - inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE || - inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) && - inst->Instruction.Opcode != TGSI_OPCODE_TXQ && - inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) { - radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords, NULL); - } - - emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm, - coords, 4); - emit_data->arg_count = 1; -} - -static void tex_fetch_args( - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - const struct tgsi_full_instruction * inst = emit_data->inst; - - LLVMValueRef coords[5]; - unsigned chan; - for (chan = 0; chan < 4; chan++) { - coords[chan] = lp_build_emit_fetch(bld_base, inst, 0, chan); - } - - if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 || - inst->Instruction.Opcode == TGSI_OPCODE_TXB2 || - inst->Instruction.Opcode == TGSI_OPCODE_TXL2) { - /* These instructions have additional operand that should be packed - * into the cube coord vector by radeon_llvm_emit_prepare_cube_coords. - * That operand should be passed as a float value in the args array - * right after the coord vector. After packing it's not used anymore, - * that's why arg_count is not increased */ - coords[4] = lp_build_emit_fetch(bld_base, inst, 1, 0); - } - - if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE || - inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY || - inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE || - inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) && - inst->Instruction.Opcode != TGSI_OPCODE_TXQ && - inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) { - radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords, NULL); - } - - emit_data->arg_count = 1; - emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm, - coords, 4); - emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4); -} - -static void txf_fetch_args( - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - const struct tgsi_full_instruction * inst = emit_data->inst; - struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base); - const struct tgsi_texture_offset * off = inst->TexOffsets; - LLVMTypeRef offset_type = bld_base->int_bld.elem_type; - - /* fetch tex coords */ - tex_fetch_args(bld_base, emit_data); - - /* fetch tex offsets */ - if (inst->Texture.NumOffsets) { - assert(inst->Texture.NumOffsets == 1); - - emit_data->args[1] = LLVMConstBitCast( - bld->immediates[off->Index][off->SwizzleX], - offset_type); - emit_data->args[2] = LLVMConstBitCast( - bld->immediates[off->Index][off->SwizzleY], - offset_type); - emit_data->args[3] = LLVMConstBitCast( - bld->immediates[off->Index][off->SwizzleZ], - offset_type); - } else { - emit_data->args[1] = bld_base->int_bld.zero; - emit_data->args[2] = bld_base->int_bld.zero; - emit_data->args[3] = bld_base->int_bld.zero; - } - - emit_data->arg_count = 4; -} - -LLVMModuleRef r600_tgsi_llvm( - struct radeon_llvm_context * ctx, - const struct tgsi_token * tokens) -{ - struct tgsi_shader_info shader_info; - struct lp_build_tgsi_context * bld_base = &ctx->soa.bld_base; - radeon_llvm_context_init(ctx); -#if HAVE_LLVM >= 0x0304 - LLVMTypeRef Arguments[32]; - unsigned ArgumentsCount = 0; - for (unsigned i = 0; i < ctx->inputs_count; i++) - Arguments[ArgumentsCount++] = LLVMVectorType(bld_base->base.elem_type, 4); - radeon_llvm_create_func(ctx, Arguments, ArgumentsCount); - for (unsigned i = 0; i < ctx->inputs_count; i++) { - LLVMValueRef P = LLVMGetParam(ctx->main_fn, i); - LLVMAddAttribute(P, LLVMInRegAttribute); - } -#else - radeon_llvm_create_func(ctx, NULL, 0); -#endif - tgsi_scan_shader(tokens, &shader_info); - - bld_base->info = &shader_info; - bld_base->userdata = ctx; - bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = llvm_fetch_const; - bld_base->emit_prologue = llvm_emit_prologue; - bld_base->emit_epilogue = llvm_emit_epilogue; - ctx->load_input = llvm_load_input; - ctx->load_system_value = llvm_load_system_value; - - bld_base->op_actions[TGSI_OPCODE_DP2] = dot_action; - bld_base->op_actions[TGSI_OPCODE_DP3] = dot_action; - bld_base->op_actions[TGSI_OPCODE_DP4] = dot_action; - bld_base->op_actions[TGSI_OPCODE_DPH] = dot_action; - bld_base->op_actions[TGSI_OPCODE_DDX].intr_name = "llvm.AMDGPU.ddx"; - bld_base->op_actions[TGSI_OPCODE_DDX].fetch_args = tex_fetch_args; - bld_base->op_actions[TGSI_OPCODE_DDX].emit = llvm_emit_tex; - bld_base->op_actions[TGSI_OPCODE_DDY].intr_name = "llvm.AMDGPU.ddy"; - bld_base->op_actions[TGSI_OPCODE_DDY].fetch_args = tex_fetch_args; - bld_base->op_actions[TGSI_OPCODE_DDY].emit = llvm_emit_tex; - bld_base->op_actions[TGSI_OPCODE_TEX].fetch_args = tex_fetch_args; - bld_base->op_actions[TGSI_OPCODE_TEX].intr_name = "llvm.AMDGPU.tex"; - bld_base->op_actions[TGSI_OPCODE_TEX].emit = llvm_emit_tex; - bld_base->op_actions[TGSI_OPCODE_TEX2].fetch_args = tex_fetch_args; - bld_base->op_actions[TGSI_OPCODE_TEX2].intr_name = "llvm.AMDGPU.tex"; - bld_base->op_actions[TGSI_OPCODE_TEX2].emit = llvm_emit_tex; - bld_base->op_actions[TGSI_OPCODE_TXB].fetch_args = tex_fetch_args; - bld_base->op_actions[TGSI_OPCODE_TXB].intr_name = "llvm.AMDGPU.txb"; - bld_base->op_actions[TGSI_OPCODE_TXB].emit = llvm_emit_tex; - bld_base->op_actions[TGSI_OPCODE_TXB2].fetch_args = tex_fetch_args; - bld_base->op_actions[TGSI_OPCODE_TXB2].intr_name = "llvm.AMDGPU.txb"; - bld_base->op_actions[TGSI_OPCODE_TXB2].emit = llvm_emit_tex; - bld_base->op_actions[TGSI_OPCODE_TXD].fetch_args = txd_fetch_args; - bld_base->op_actions[TGSI_OPCODE_TXD].intr_name = "llvm.AMDGPU.txd"; - bld_base->op_actions[TGSI_OPCODE_TXD].emit = llvm_emit_tex; - bld_base->op_actions[TGSI_OPCODE_TXF].fetch_args = txf_fetch_args; - bld_base->op_actions[TGSI_OPCODE_TXF].intr_name = "llvm.AMDGPU.txf"; - bld_base->op_actions[TGSI_OPCODE_TXF].emit = llvm_emit_tex; - bld_base->op_actions[TGSI_OPCODE_TXL].fetch_args = tex_fetch_args; - bld_base->op_actions[TGSI_OPCODE_TXL].intr_name = "llvm.AMDGPU.txl"; - bld_base->op_actions[TGSI_OPCODE_TXL].emit = llvm_emit_tex; - bld_base->op_actions[TGSI_OPCODE_TXL2].fetch_args = tex_fetch_args; - bld_base->op_actions[TGSI_OPCODE_TXL2].intr_name = "llvm.AMDGPU.txl"; - bld_base->op_actions[TGSI_OPCODE_TXL2].emit = llvm_emit_tex; - bld_base->op_actions[TGSI_OPCODE_TXP].fetch_args = txp_fetch_args; - bld_base->op_actions[TGSI_OPCODE_TXP].intr_name = "llvm.AMDGPU.tex"; - bld_base->op_actions[TGSI_OPCODE_TXP].emit = llvm_emit_tex; - bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = tex_fetch_args; - bld_base->op_actions[TGSI_OPCODE_TXQ].intr_name = "llvm.AMDGPU.txq"; - bld_base->op_actions[TGSI_OPCODE_TXQ].emit = llvm_emit_tex; - bld_base->op_actions[TGSI_OPCODE_CMP].emit = emit_cndlt; - - lp_build_tgsi_llvm(bld_base, tokens); - - radeon_llvm_finalize_module(ctx); - - return ctx->gallivm.module; -} - -/* We need to define these R600 registers here, because we can't include - * evergreend.h and r600d.h. - */ -#define R_028868_SQ_PGM_RESOURCES_VS 0x028868 -#define R_028850_SQ_PGM_RESOURCES_PS 0x028850 - -void r600_shader_binary_read_config(const struct radeon_shader_binary *binary, - struct r600_bytecode *bc, - uint64_t symbol_offset, - boolean *use_kill) -{ - unsigned i; - const unsigned char *config = - radeon_shader_binary_config_start(binary, symbol_offset); - - for (i = 0; i < binary->config_size_per_symbol; i+= 8) { - unsigned reg = - util_le32_to_cpu(*(uint32_t*)(config + i)); - unsigned value = - util_le32_to_cpu(*(uint32_t*)(config + i + 4)); - switch (reg) { - /* R600 / R700 */ - case R_028850_SQ_PGM_RESOURCES_PS: - case R_028868_SQ_PGM_RESOURCES_VS: - /* Evergreen / Northern Islands */ - case R_028844_SQ_PGM_RESOURCES_PS: - case R_028860_SQ_PGM_RESOURCES_VS: - case R_0288D4_SQ_PGM_RESOURCES_LS: - bc->ngpr = MAX2(bc->ngpr, G_028844_NUM_GPRS(value)); - bc->nstack = MAX2(bc->nstack, G_028844_STACK_SIZE(value)); - break; - case R_02880C_DB_SHADER_CONTROL: - *use_kill = G_02880C_KILL_ENABLE(value); - break; - case CM_R_0288E8_SQ_LDS_ALLOC: - bc->nlds_dw = value; - break; - } - } - -} - -unsigned r600_create_shader(struct r600_bytecode *bc, - const struct radeon_shader_binary *binary, - boolean *use_kill) - -{ - assert(binary->code_size % 4 == 0); - bc->bytecode = CALLOC(1, binary->code_size); - memcpy(bc->bytecode, binary->code, binary->code_size); - bc->ndw = binary->code_size / 4; - - r600_shader_binary_read_config(binary, bc, 0, use_kill); - - return 0; -} - -unsigned r600_llvm_compile( - LLVMModuleRef mod, - enum radeon_family family, - struct r600_bytecode *bc, - boolean *use_kill, - unsigned dump) -{ - unsigned r; - struct radeon_shader_binary binary; - const char * gpu_family = r600_get_llvm_processor_name(family); - - memset(&binary, 0, sizeof(struct radeon_shader_binary)); - r = radeon_llvm_compile(mod, &binary, gpu_family, dump, dump, NULL); - - r = r600_create_shader(bc, &binary, use_kill); - - FREE(binary.code); - FREE(binary.config); - FREE(binary.rodata); - FREE(binary.global_symbol_offsets); - - return r; -} - -#endif diff --git a/lib/mesa/src/gallium/drivers/r600/r600_llvm.h b/lib/mesa/src/gallium/drivers/r600/r600_llvm.h deleted file mode 100644 index 9b5304d9f..000000000 --- a/lib/mesa/src/gallium/drivers/r600/r600_llvm.h +++ /dev/null @@ -1,38 +0,0 @@ - -#ifndef R600_LLVM_H -#define R600_LLVM_H - -#if defined R600_USE_LLVM || defined HAVE_OPENCL - -#include "radeon/radeon_llvm.h" -#include <llvm-c/Core.h> - -struct r600_bytecode; -struct r600_shader_ctx; -struct radeon_llvm_context; -struct radeon_shader_binary; -enum radeon_family; - -LLVMModuleRef r600_tgsi_llvm( - struct radeon_llvm_context * ctx, - const struct tgsi_token * tokens); - -unsigned r600_llvm_compile( - LLVMModuleRef mod, - enum radeon_family family, - struct r600_bytecode *bc, - boolean *use_kill, - unsigned dump); - -unsigned r600_create_shader(struct r600_bytecode *bc, - const struct radeon_shader_binary *binary, - boolean *use_kill); - -void r600_shader_binary_read_config(const struct radeon_shader_binary *binary, - struct r600_bytecode *bc, - uint64_t symbol_offset, - boolean *use_kill); - -#endif /* defined R600_USE_LLVM || defined HAVE_OPENCL */ - -#endif /* R600_LLVM_H */ diff --git a/lib/mesa/src/gallium/drivers/radeon/Makefile.in b/lib/mesa/src/gallium/drivers/radeon/Makefile.in index e14afd089..8e5f0fc19 100644 --- a/lib/mesa/src/gallium/drivers/radeon/Makefile.in +++ b/lib/mesa/src/gallium/drivers/radeon/Makefile.in @@ -92,22 +92,20 @@ am__DEPENDENCIES_1 = @NEED_RADEON_LLVM_TRUE@ $(am__DEPENDENCIES_1) \ @NEED_RADEON_LLVM_TRUE@ $(am__DEPENDENCIES_1) am__libradeon_la_SOURCES_DIST = cayman_msaa.c r600_buffer_common.c \ - r600_cs.h r600d_common.h r600_gpu_load.c r600_perfcounter.c \ + r600_cs.h r600_gpu_load.c r600_perfcounter.c \ r600_pipe_common.c r600_pipe_common.h r600_query.c \ - r600_query.h r600_streamout.c r600_texture.c radeon_uvd.c \ - radeon_uvd.h radeon_vce_40_2_2.c radeon_vce_50.c \ - radeon_vce_52.c radeon_vce.c radeon_vce.h radeon_video.c \ - radeon_video.h radeon_winsys.h radeon_elf_util.c \ - radeon_elf_util.h radeon_llvm_emit.c radeon_llvm_emit.h \ - radeon_llvm.h radeon_llvm_util.c radeon_llvm_util.h \ - radeon_setup_tgsi_llvm.c + r600_query.h r600_streamout.c r600_test_dma.c r600_texture.c \ + r600_viewport.c radeon_uvd.c radeon_uvd.h radeon_vce_40_2_2.c \ + radeon_vce_50.c radeon_vce_52.c radeon_vce.c radeon_vce.h \ + radeon_video.c radeon_video.h radeon_winsys.h \ + radeon_elf_util.c radeon_elf_util.h am__objects_1 = cayman_msaa.lo r600_buffer_common.lo r600_gpu_load.lo \ r600_perfcounter.lo r600_pipe_common.lo r600_query.lo \ - r600_streamout.lo r600_texture.lo radeon_uvd.lo \ - radeon_vce_40_2_2.lo radeon_vce_50.lo radeon_vce_52.lo \ - radeon_vce.lo radeon_video.lo -am__objects_2 = radeon_elf_util.lo radeon_llvm_emit.lo \ - radeon_llvm_util.lo radeon_setup_tgsi_llvm.lo + r600_streamout.lo r600_test_dma.lo r600_texture.lo \ + r600_viewport.lo radeon_uvd.lo radeon_vce_40_2_2.lo \ + radeon_vce_50.lo radeon_vce_52.lo radeon_vce.lo \ + radeon_video.lo +am__objects_2 = radeon_elf_util.lo @NEED_RADEON_LLVM_TRUE@am__objects_3 = $(am__objects_2) am_libradeon_la_OBJECTS = $(am__objects_1) $(am__objects_3) libradeon_la_OBJECTS = $(am_libradeon_la_OBJECTS) @@ -230,6 +228,8 @@ GLESv2_LIB_DEPS = @GLESv2_LIB_DEPS@ GLESv2_PC_LIB_PRIV = @GLESv2_PC_LIB_PRIV@ GLPROTO_CFLAGS = @GLPROTO_CFLAGS@ GLPROTO_LIBS = @GLPROTO_LIBS@ +GLVND_CFLAGS = @GLVND_CFLAGS@ +GLVND_LIBS = @GLVND_LIBS@ GLX_TLS = @GLX_TLS@ GL_LIB = @GL_LIB@ GL_LIB_DEPS = @GL_LIB_DEPS@ @@ -261,11 +261,10 @@ LIBELF_CFLAGS = @LIBELF_CFLAGS@ LIBELF_LIBS = @LIBELF_LIBS@ LIBOBJS = @LIBOBJS@ LIBS = @LIBS@ +LIBSENSORS_LDFLAGS = @LIBSENSORS_LDFLAGS@ LIBSHA1_CFLAGS = @LIBSHA1_CFLAGS@ LIBSHA1_LIBS = @LIBSHA1_LIBS@ LIBTOOL = @LIBTOOL@ -LIBUDEV_CFLAGS = @LIBUDEV_CFLAGS@ -LIBUDEV_LIBS = @LIBUDEV_LIBS@ LIB_DIR = @LIB_DIR@ LIB_EXT = @LIB_EXT@ LIPO = @LIPO@ @@ -328,6 +327,8 @@ PKG_CONFIG_PATH = @PKG_CONFIG_PATH@ POSIX_SHELL = @POSIX_SHELL@ PRESENTPROTO_CFLAGS = @PRESENTPROTO_CFLAGS@ PRESENTPROTO_LIBS = @PRESENTPROTO_LIBS@ +PTHREADSTUBS_CFLAGS = @PTHREADSTUBS_CFLAGS@ +PTHREADSTUBS_LIBS = @PTHREADSTUBS_LIBS@ PTHREAD_CC = @PTHREAD_CC@ PTHREAD_CFLAGS = @PTHREAD_CFLAGS@ PTHREAD_LIBS = @PTHREAD_LIBS@ @@ -348,11 +349,19 @@ SIMPENROSE_CFLAGS = @SIMPENROSE_CFLAGS@ SIMPENROSE_LIBS = @SIMPENROSE_LIBS@ SSE41_CFLAGS = @SSE41_CFLAGS@ STRIP = @STRIP@ +SWR_AVX2_CXXFLAGS = @SWR_AVX2_CXXFLAGS@ +SWR_AVX_CXXFLAGS = @SWR_AVX_CXXFLAGS@ +SWR_CXX11_CXXFLAGS = @SWR_CXX11_CXXFLAGS@ +TIMESTAMP_CMD = @TIMESTAMP_CMD@ +VALGRIND_CFLAGS = @VALGRIND_CFLAGS@ +VALGRIND_LIBS = @VALGRIND_LIBS@ VA_CFLAGS = @VA_CFLAGS@ VA_LIBS = @VA_LIBS@ VA_LIB_INSTALL_DIR = @VA_LIB_INSTALL_DIR@ VA_MAJOR = @VA_MAJOR@ VA_MINOR = @VA_MINOR@ +VC4_CFLAGS = @VC4_CFLAGS@ +VC4_LIBS = @VC4_LIBS@ VDPAU_CFLAGS = @VDPAU_CFLAGS@ VDPAU_LIBS = @VDPAU_LIBS@ VDPAU_LIB_INSTALL_DIR = @VDPAU_LIB_INSTALL_DIR@ @@ -364,6 +373,7 @@ VISIBILITY_CFLAGS = @VISIBILITY_CFLAGS@ VISIBILITY_CXXFLAGS = @VISIBILITY_CXXFLAGS@ VL_CFLAGS = @VL_CFLAGS@ VL_LIBS = @VL_LIBS@ +VULKAN_ICD_INSTALL_DIR = @VULKAN_ICD_INSTALL_DIR@ WAYLAND_CFLAGS = @WAYLAND_CFLAGS@ WAYLAND_LIBS = @WAYLAND_LIBS@ WAYLAND_SCANNER = @WAYLAND_SCANNER@ @@ -387,6 +397,7 @@ XVMC_LIBS = @XVMC_LIBS@ XVMC_LIB_INSTALL_DIR = @XVMC_LIB_INSTALL_DIR@ XVMC_MAJOR = @XVMC_MAJOR@ XVMC_MINOR = @XVMC_MINOR@ +XXD = @XXD@ YACC = @YACC@ YFLAGS = @YFLAGS@ abs_builddir = @abs_builddir@ @@ -453,7 +464,6 @@ C_SOURCES := \ cayman_msaa.c \ r600_buffer_common.c \ r600_cs.h \ - r600d_common.h \ r600_gpu_load.c \ r600_perfcounter.c \ r600_pipe_common.c \ @@ -461,7 +471,9 @@ C_SOURCES := \ r600_query.c \ r600_query.h \ r600_streamout.c \ + r600_test_dma.c \ r600_texture.c \ + r600_viewport.c \ radeon_uvd.c \ radeon_uvd.h \ radeon_vce_40_2_2.c \ @@ -475,13 +487,7 @@ C_SOURCES := \ LLVM_C_FILES := \ radeon_elf_util.c \ - radeon_elf_util.h \ - radeon_llvm_emit.c \ - radeon_llvm_emit.h \ - radeon_llvm.h \ - radeon_llvm_util.c \ - radeon_llvm_util.h \ - radeon_setup_tgsi_llvm.c + radeon_elf_util.h GALLIUM_CFLAGS = \ -I$(top_srcdir)/include \ @@ -626,11 +632,10 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/r600_pipe_common.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/r600_query.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/r600_streamout.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/r600_test_dma.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/r600_texture.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/r600_viewport.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/radeon_elf_util.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/radeon_llvm_emit.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/radeon_llvm_util.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/radeon_setup_tgsi_llvm.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/radeon_uvd.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/radeon_vce.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/radeon_vce_40_2_2.Plo@am__quote@ diff --git a/lib/mesa/src/gallium/drivers/radeon/r600d_common.h b/lib/mesa/src/gallium/drivers/radeon/r600d_common.h deleted file mode 100644 index 115042d15..000000000 --- a/lib/mesa/src/gallium/drivers/radeon/r600d_common.h +++ /dev/null @@ -1,209 +0,0 @@ -/* - * Copyright 2013 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * on the rights to use, copy, modify, merge, publish, distribute, sub - * license, and/or sell copies of the Software, and to permit persons to whom - * the Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE - * USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Marek Olšák <maraeo@gmail.com> - */ - -#ifndef R600D_COMMON_H -#define R600D_COMMON_H - -#define R600_CONFIG_REG_OFFSET 0x08000 -#define R600_CONTEXT_REG_OFFSET 0x28000 -#define SI_SH_REG_OFFSET 0x0000B000 -#define SI_SH_REG_END 0x0000C000 -#define CIK_UCONFIG_REG_OFFSET 0x00030000 -#define CIK_UCONFIG_REG_END 0x00031000 - -#define PKT_TYPE_S(x) (((x) & 0x3) << 30) -#define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16) -#define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8) -#define PKT3_PREDICATE(x) (((x) >> 0) & 0x1) -#define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate)) - -#define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002 - -#define PKT3_NOP 0x10 -#define PKT3_SET_PREDICATION 0x20 -#define PKT3_STRMOUT_BUFFER_UPDATE 0x34 -#define STRMOUT_STORE_BUFFER_FILLED_SIZE 1 -#define STRMOUT_OFFSET_SOURCE(x) (((x) & 0x3) << 1) -#define STRMOUT_OFFSET_FROM_PACKET 0 -#define STRMOUT_OFFSET_FROM_VGT_FILLED_SIZE 1 -#define STRMOUT_OFFSET_FROM_MEM 2 -#define STRMOUT_OFFSET_NONE 3 -#define STRMOUT_SELECT_BUFFER(x) (((x) & 0x3) << 8) -#define PKT3_WAIT_REG_MEM 0x3C -#define WAIT_REG_MEM_EQUAL 3 -#define PKT3_EVENT_WRITE 0x46 -#define PKT3_EVENT_WRITE_EOP 0x47 -#define PKT3_SET_CONFIG_REG 0x68 -#define PKT3_SET_CONTEXT_REG 0x69 -#define PKT3_STRMOUT_BASE_UPDATE 0x72 /* r700 only */ -#define PKT3_SURFACE_BASE_UPDATE 0x73 /* r600 only */ -#define SURFACE_BASE_UPDATE_DEPTH (1 << 0) -#define SURFACE_BASE_UPDATE_COLOR(x) (2 << (x)) -#define SURFACE_BASE_UPDATE_COLOR_NUM(x) (((1 << x) - 1) << 1) -#define SURFACE_BASE_UPDATE_STRMOUT(x) (0x200 << (x)) -#define PKT3_SET_SH_REG 0x76 /* SI and later */ -#define PKT3_SET_UCONFIG_REG 0x79 /* CIK and later */ - -#define EVENT_TYPE_SAMPLE_STREAMOUTSTATS1 0x1 /* EG and later */ -#define EVENT_TYPE_SAMPLE_STREAMOUTSTATS2 0x2 /* EG and later */ -#define EVENT_TYPE_SAMPLE_STREAMOUTSTATS3 0x3 /* EG and later */ -#define EVENT_TYPE_PS_PARTIAL_FLUSH 0x10 -#define EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT 0x14 -#define EVENT_TYPE_ZPASS_DONE 0x15 -#define EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT 0x16 -#define EVENT_TYPE_PIPELINESTAT_START 25 -#define EVENT_TYPE_PIPELINESTAT_STOP 26 -#define EVENT_TYPE_SAMPLE_PIPELINESTAT 30 -#define EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH 0x1f -#define EVENT_TYPE_SAMPLE_STREAMOUTSTATS 0x20 -#define EVENT_TYPE_FLUSH_AND_INV_DB_META 0x2c /* supported on r700+ */ -#define EVENT_TYPE_FLUSH_AND_INV_CB_META 46 /* supported on r700+ */ -#define EVENT_TYPE(x) ((x) << 0) -#define EVENT_INDEX(x) ((x) << 8) - /* 0 - any non-TS event - * 1 - ZPASS_DONE - * 2 - SAMPLE_PIPELINESTAT - * 3 - SAMPLE_STREAMOUTSTAT* - * 4 - *S_PARTIAL_FLUSH - * 5 - TS events - */ - -#define PREDICATION_OP_CLEAR 0x0 -#define PREDICATION_OP_ZPASS 0x1 -#define PREDICATION_OP_PRIMCOUNT 0x2 -#define PRED_OP(x) ((x) << 16) -#define PREDICATION_CONTINUE (1 << 31) -#define PREDICATION_HINT_WAIT (0 << 12) -#define PREDICATION_HINT_NOWAIT_DRAW (1 << 12) -#define PREDICATION_DRAW_NOT_VISIBLE (0 << 8) -#define PREDICATION_DRAW_VISIBLE (1 << 8) - -/* R600-R700*/ -#define R_008490_CP_STRMOUT_CNTL 0x008490 -#define S_008490_OFFSET_UPDATE_DONE(x) (((x) & 0x1) << 0) -#define R_028AB0_VGT_STRMOUT_EN 0x028AB0 -#define S_028AB0_STREAMOUT(x) (((x) & 0x1) << 0) -#define G_028AB0_STREAMOUT(x) (((x) >> 0) & 0x1) -#define C_028AB0_STREAMOUT 0xFFFFFFFE -#define R_028B20_VGT_STRMOUT_BUFFER_EN 0x028B20 -#define S_028B20_BUFFER_0_EN(x) (((x) & 0x1) << 0) -#define G_028B20_BUFFER_0_EN(x) (((x) >> 0) & 0x1) -#define C_028B20_BUFFER_0_EN 0xFFFFFFFE -#define S_028B20_BUFFER_1_EN(x) (((x) & 0x1) << 1) -#define G_028B20_BUFFER_1_EN(x) (((x) >> 1) & 0x1) -#define C_028B20_BUFFER_1_EN 0xFFFFFFFD -#define S_028B20_BUFFER_2_EN(x) (((x) & 0x1) << 2) -#define G_028B20_BUFFER_2_EN(x) (((x) >> 2) & 0x1) -#define C_028B20_BUFFER_2_EN 0xFFFFFFFB -#define S_028B20_BUFFER_3_EN(x) (((x) & 0x1) << 3) -#define G_028B20_BUFFER_3_EN(x) (((x) >> 3) & 0x1) -#define C_028B20_BUFFER_3_EN 0xFFFFFFF7 -#define R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 0x028AD0 - -#define V_0280A0_SWAP_STD 0x00000000 -#define V_0280A0_SWAP_ALT 0x00000001 -#define V_0280A0_SWAP_STD_REV 0x00000002 -#define V_0280A0_SWAP_ALT_REV 0x00000003 - -/* EG+ */ -#define R_0084FC_CP_STRMOUT_CNTL 0x0084FC -#define S_0084FC_OFFSET_UPDATE_DONE(x) (((x) & 0x1) << 0) -#define R_028B94_VGT_STRMOUT_CONFIG 0x028B94 -#define S_028B94_STREAMOUT_0_EN(x) (((x) & 0x1) << 0) -#define G_028B94_STREAMOUT_0_EN(x) (((x) >> 0) & 0x1) -#define C_028B94_STREAMOUT_0_EN 0xFFFFFFFE -#define S_028B94_STREAMOUT_1_EN(x) (((x) & 0x1) << 1) -#define G_028B94_STREAMOUT_1_EN(x) (((x) >> 1) & 0x1) -#define C_028B94_STREAMOUT_1_EN 0xFFFFFFFD -#define S_028B94_STREAMOUT_2_EN(x) (((x) & 0x1) << 2) -#define G_028B94_STREAMOUT_2_EN(x) (((x) >> 2) & 0x1) -#define C_028B94_STREAMOUT_2_EN 0xFFFFFFFB -#define S_028B94_STREAMOUT_3_EN(x) (((x) & 0x1) << 3) -#define G_028B94_STREAMOUT_3_EN(x) (((x) >> 3) & 0x1) -#define C_028B94_STREAMOUT_3_EN 0xFFFFFFF7 -#define S_028B94_RAST_STREAM(x) (((x) & 0x07) << 4) -#define G_028B94_RAST_STREAM(x) (((x) >> 4) & 0x07) -#define C_028B94_RAST_STREAM 0xFFFFFF8F -#define S_028B94_RAST_STREAM_MASK(x) (((x) & 0x0F) << 8) /* SI+ */ -#define G_028B94_RAST_STREAM_MASK(x) (((x) >> 8) & 0x0F) -#define C_028B94_RAST_STREAM_MASK 0xFFFFF0FF -#define S_028B94_USE_RAST_STREAM_MASK(x) (((x) & 0x1) << 31) /* SI+ */ -#define G_028B94_USE_RAST_STREAM_MASK(x) (((x) >> 31) & 0x1) -#define C_028B94_USE_RAST_STREAM_MASK 0x7FFFFFFF -#define R_028B98_VGT_STRMOUT_BUFFER_CONFIG 0x028B98 -#define S_028B98_STREAM_0_BUFFER_EN(x) (((x) & 0x0F) << 0) -#define G_028B98_STREAM_0_BUFFER_EN(x) (((x) >> 0) & 0x0F) -#define C_028B98_STREAM_0_BUFFER_EN 0xFFFFFFF0 -#define S_028B98_STREAM_1_BUFFER_EN(x) (((x) & 0x0F) << 4) -#define G_028B98_STREAM_1_BUFFER_EN(x) (((x) >> 4) & 0x0F) -#define C_028B98_STREAM_1_BUFFER_EN 0xFFFFFF0F -#define S_028B98_STREAM_2_BUFFER_EN(x) (((x) & 0x0F) << 8) -#define G_028B98_STREAM_2_BUFFER_EN(x) (((x) >> 8) & 0x0F) -#define C_028B98_STREAM_2_BUFFER_EN 0xFFFFF0FF -#define S_028B98_STREAM_3_BUFFER_EN(x) (((x) & 0x0F) << 12) -#define G_028B98_STREAM_3_BUFFER_EN(x) (((x) >> 12) & 0x0F) -#define C_028B98_STREAM_3_BUFFER_EN 0xFFFF0FFF - -#define EG_R_028A4C_PA_SC_MODE_CNTL_1 0x028A4C -#define EG_S_028A4C_PS_ITER_SAMPLE(x) (((x) & 0x1) << 16) - -#define CM_R_028804_DB_EQAA 0x00028804 -#define S_028804_MAX_ANCHOR_SAMPLES(x) (((x) & 0x7) << 0) -#define S_028804_PS_ITER_SAMPLES(x) (((x) & 0x7) << 4) -#define S_028804_MASK_EXPORT_NUM_SAMPLES(x) (((x) & 0x7) << 8) -#define S_028804_ALPHA_TO_MASK_NUM_SAMPLES(x) (((x) & 0x7) << 12) -#define S_028804_HIGH_QUALITY_INTERSECTIONS(x) (((x) & 0x1) << 16) -#define S_028804_INCOHERENT_EQAA_READS(x) (((x) & 0x1) << 17) -#define S_028804_INTERPOLATE_COMP_Z(x) (((x) & 0x1) << 18) -#define S_028804_INTERPOLATE_SRC_Z(x) (((x) & 0x1) << 19) -#define S_028804_STATIC_ANCHOR_ASSOCIATIONS(x) (((x) & 0x1) << 20) -#define S_028804_ALPHA_TO_MASK_EQAA_DISABLE(x) (((x) & 0x1) << 21) -#define S_028804_OVERRASTERIZATION_AMOUNT(x) (((x) & 0x07) << 24) -#define S_028804_ENABLE_POSTZ_OVERRASTERIZATION(x) (((x) & 0x1) << 27) -#define CM_R_028BDC_PA_SC_LINE_CNTL 0x28bdc -#define S_028BDC_EXPAND_LINE_WIDTH(x) (((x) & 0x1) << 9) -#define G_028BDC_EXPAND_LINE_WIDTH(x) (((x) >> 9) & 0x1) -#define C_028BDC_EXPAND_LINE_WIDTH 0xFFFFFDFF -#define S_028BDC_LAST_PIXEL(x) (((x) & 0x1) << 10) -#define G_028BDC_LAST_PIXEL(x) (((x) >> 10) & 0x1) -#define C_028BDC_LAST_PIXEL 0xFFFFFBFF -#define CM_R_028BE0_PA_SC_AA_CONFIG 0x28be0 -#define S_028BE0_MSAA_NUM_SAMPLES(x) (((x) & 0x7) << 0) -#define S_028BE0_AA_MASK_CENTROID_DTMN(x) (((x) & 0x1) << 4) -#define S_028BE0_MAX_SAMPLE_DIST(x) (((x) & 0xf) << 13) -#define S_028BE0_MSAA_EXPOSED_SAMPLES(x) (((x) & 0x7) << 20) -#define S_028BE0_DETAIL_TO_EXPOSED_MODE(x) (((x) & 0x3) << 24) -#define CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0x28bf8 -#define CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0x28c08 -#define CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0x28c18 -#define CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0x28c28 - -#define EG_S_028C70_FAST_CLEAR(x) (((x) & 0x1) << 17) -#define SI_S_028C70_FAST_CLEAR(x) (((x) & 0x1) << 13) - -/*CIK+*/ -#define R_0300FC_CP_STRMOUT_CNTL 0x0300FC - -#endif diff --git a/lib/mesa/src/gallium/drivers/radeon/radeon_llvm.h b/lib/mesa/src/gallium/drivers/radeon/radeon_llvm.h deleted file mode 100644 index e967ad221..000000000 --- a/lib/mesa/src/gallium/drivers/radeon/radeon_llvm.h +++ /dev/null @@ -1,203 +0,0 @@ -/* - * Copyright 2011 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - * - * Authors: Tom Stellard <thomas.stellard@amd.com> - * - */ - -#ifndef RADEON_LLVM_H -#define RADEON_LLVM_H - -#include <llvm-c/Core.h> -#include "gallivm/lp_bld_init.h" -#include "gallivm/lp_bld_tgsi.h" - -#define RADEON_LLVM_MAX_INPUTS 32 * 4 -#define RADEON_LLVM_MAX_OUTPUTS 32 * 4 - -#define RADEON_LLVM_INITIAL_CF_DEPTH 4 - -#define RADEON_LLVM_MAX_SYSTEM_VALUES 4 - -struct radeon_llvm_branch { - LLVMBasicBlockRef endif_block; - LLVMBasicBlockRef if_block; - LLVMBasicBlockRef else_block; - unsigned has_else; -}; - -struct radeon_llvm_loop { - LLVMBasicBlockRef loop_block; - LLVMBasicBlockRef endloop_block; -}; - -struct radeon_llvm_context { - - struct lp_build_tgsi_soa_context soa; - - unsigned chip_class; - unsigned type; - unsigned face_gpr; - unsigned two_side; - unsigned inputs_count; - struct r600_shader_io * r600_inputs; - struct r600_shader_io * r600_outputs; - struct pipe_stream_output_info *stream_outputs; - unsigned color_buffer_count; - unsigned fs_color_all; - unsigned alpha_to_one; - unsigned has_txq_cube_array_z_comp; - unsigned uses_tex_buffers; - unsigned has_compressed_msaa_texturing; - - /*=== Front end configuration ===*/ - - /* Instructions that are not described by any of the TGSI opcodes. */ - - /** This function is responsible for initilizing the inputs array and will be - * called once for each input declared in the TGSI shader. - */ - void (*load_input)(struct radeon_llvm_context *, - unsigned input_index, - const struct tgsi_full_declaration *decl); - - void (*load_system_value)(struct radeon_llvm_context *, - unsigned index, - const struct tgsi_full_declaration *decl); - - /** This array contains the input values for the shader. Typically these - * values will be in the form of a target intrinsic that will inform the - * backend how to load the actual inputs to the shader. - */ - LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS]; - LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS][TGSI_NUM_CHANNELS]; - unsigned output_reg_count; - - /** This pointer is used to contain the temporary values. - * The amount of temporary used in tgsi can't be bound to a max value and - * thus we must allocate this array at runtime. - */ - LLVMValueRef *temps; - unsigned temps_count; - LLVMValueRef system_values[RADEON_LLVM_MAX_SYSTEM_VALUES]; - - /*=== Private Members ===*/ - - struct radeon_llvm_branch *branch; - struct radeon_llvm_loop *loop; - - unsigned branch_depth; - unsigned branch_depth_max; - unsigned loop_depth; - unsigned loop_depth_max; - - struct tgsi_declaration_range *arrays; - - LLVMValueRef main_fn; - - struct gallivm_state gallivm; -}; - -static inline LLVMTypeRef tgsi2llvmtype( - struct lp_build_tgsi_context * bld_base, - enum tgsi_opcode_type type) -{ - LLVMContextRef ctx = bld_base->base.gallivm->context; - - switch (type) { - case TGSI_TYPE_UNSIGNED: - case TGSI_TYPE_SIGNED: - return LLVMInt32TypeInContext(ctx); - case TGSI_TYPE_DOUBLE: - return LLVMDoubleTypeInContext(ctx); - case TGSI_TYPE_UNTYPED: - case TGSI_TYPE_FLOAT: - return LLVMFloatTypeInContext(ctx); - default: break; - } - return 0; -} - -static inline LLVMValueRef bitcast( - struct lp_build_tgsi_context * bld_base, - enum tgsi_opcode_type type, - LLVMValueRef value -) -{ - LLVMBuilderRef builder = bld_base->base.gallivm->builder; - LLVMTypeRef dst_type = tgsi2llvmtype(bld_base, type); - - if (dst_type) - return LLVMBuildBitCast(builder, value, dst_type, ""); - else - return value; -} - - -void radeon_llvm_emit_prepare_cube_coords(struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data, - LLVMValueRef *coords_arg, - LLVMValueRef *derivs_arg); - -void radeon_llvm_context_init(struct radeon_llvm_context * ctx); - -void radeon_llvm_create_func(struct radeon_llvm_context * ctx, - LLVMTypeRef *ParamTypes, unsigned ParamCount); - -void radeon_llvm_dispose(struct radeon_llvm_context * ctx); - -inline static struct radeon_llvm_context * radeon_llvm_context( - struct lp_build_tgsi_context * bld_base) -{ - return (struct radeon_llvm_context*)bld_base; -} - -unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan); - -void radeon_llvm_finalize_module(struct radeon_llvm_context * ctx); - -void -build_tgsi_intrinsic_nomem( - const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data); - -LLVMValueRef -radeon_llvm_emit_fetch_double(struct lp_build_tgsi_context *bld_base, - LLVMValueRef ptr, - LLVMValueRef ptr2); - -LLVMValueRef radeon_llvm_saturate(struct lp_build_tgsi_context *bld_base, - LLVMValueRef value); - -LLVMValueRef radeon_llvm_emit_fetch(struct lp_build_tgsi_context *bld_base, - const struct tgsi_full_src_register *reg, - enum tgsi_opcode_type type, - unsigned swizzle); - -void radeon_llvm_emit_store( - struct lp_build_tgsi_context * bld_base, - const struct tgsi_full_instruction * inst, - const struct tgsi_opcode_info * info, - LLVMValueRef dst[4]); - -#endif /* RADEON_LLVM_H */ diff --git a/lib/mesa/src/gallium/drivers/radeon/radeon_llvm_emit.c b/lib/mesa/src/gallium/drivers/radeon/radeon_llvm_emit.c deleted file mode 100644 index 1a66a55ee..000000000 --- a/lib/mesa/src/gallium/drivers/radeon/radeon_llvm_emit.c +++ /dev/null @@ -1,218 +0,0 @@ -/* - * Copyright 2011 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - * - * Authors: Tom Stellard <thomas.stellard@amd.com> - * - */ -#include "radeon_llvm_emit.h" -#include "radeon_elf_util.h" -#include "c11/threads.h" -#include "gallivm/lp_bld_misc.h" -#include "util/u_memory.h" -#include "pipe/p_shader_tokens.h" - -#include <llvm-c/Target.h> -#include <llvm-c/TargetMachine.h> -#include <llvm-c/Core.h> - -#include <stdlib.h> -#include <stdio.h> -#include <string.h> - -#define CPU_STRING_LEN 30 -#define FS_STRING_LEN 30 -#define TRIPLE_STRING_LEN 7 - -/** - * Shader types for the LLVM backend. - */ -enum radeon_llvm_shader_type { - RADEON_LLVM_SHADER_PS = 0, - RADEON_LLVM_SHADER_VS = 1, - RADEON_LLVM_SHADER_GS = 2, - RADEON_LLVM_SHADER_CS = 3, -}; - -/** - * Set the shader type we want to compile - * - * @param type shader type to set - */ -void radeon_llvm_shader_type(LLVMValueRef F, unsigned type) -{ - char Str[2]; - enum radeon_llvm_shader_type llvm_type; - - switch (type) { - case TGSI_PROCESSOR_VERTEX: - case TGSI_PROCESSOR_TESS_CTRL: - case TGSI_PROCESSOR_TESS_EVAL: - llvm_type = RADEON_LLVM_SHADER_VS; - break; - case TGSI_PROCESSOR_GEOMETRY: - llvm_type = RADEON_LLVM_SHADER_GS; - break; - case TGSI_PROCESSOR_FRAGMENT: - llvm_type = RADEON_LLVM_SHADER_PS; - break; - case TGSI_PROCESSOR_COMPUTE: - llvm_type = RADEON_LLVM_SHADER_CS; - break; - default: - assert(0); - } - - sprintf(Str, "%1d", llvm_type); - - LLVMAddTargetDependentFunctionAttr(F, "ShaderType", Str); -} - -static void init_r600_target() -{ - gallivm_init_llvm_targets(); -#if HAVE_LLVM < 0x0307 - LLVMInitializeR600TargetInfo(); - LLVMInitializeR600Target(); - LLVMInitializeR600TargetMC(); - LLVMInitializeR600AsmPrinter(); -#else - LLVMInitializeAMDGPUTargetInfo(); - LLVMInitializeAMDGPUTarget(); - LLVMInitializeAMDGPUTargetMC(); - LLVMInitializeAMDGPUAsmPrinter(); - -#endif -} - -static once_flag init_r600_target_once_flag = ONCE_FLAG_INIT; - -LLVMTargetRef radeon_llvm_get_r600_target(const char *triple) -{ - LLVMTargetRef target = NULL; - char *err_message = NULL; - - call_once(&init_r600_target_once_flag, init_r600_target); - - if (LLVMGetTargetFromTriple(triple, &target, &err_message)) { - fprintf(stderr, "Cannot find target for triple %s ", triple); - if (err_message) { - fprintf(stderr, "%s\n", err_message); - } - LLVMDisposeMessage(err_message); - return NULL; - } - return target; -} - -#if HAVE_LLVM >= 0x0305 - -static void radeonDiagnosticHandler(LLVMDiagnosticInfoRef di, void *context) -{ - if (LLVMGetDiagInfoSeverity(di) == LLVMDSError) { - unsigned int *diagnosticflag = (unsigned int *)context; - char *diaginfo_message = LLVMGetDiagInfoDescription(di); - - *diagnosticflag = 1; - fprintf(stderr,"LLVM triggered Diagnostic Handler: %s\n", diaginfo_message); - LLVMDisposeMessage(diaginfo_message); - } -} - -#endif - -/** - * Compile an LLVM module to machine code. - * - * @returns 0 for success, 1 for failure - */ -unsigned radeon_llvm_compile(LLVMModuleRef M, struct radeon_shader_binary *binary, - const char *gpu_family, bool dump_ir, bool dump_asm, - LLVMTargetMachineRef tm) -{ - - char cpu[CPU_STRING_LEN]; - char fs[FS_STRING_LEN]; - char *err; - bool dispose_tm = false; - LLVMContextRef llvm_ctx; - unsigned rval = 0; - LLVMMemoryBufferRef out_buffer; - unsigned buffer_size; - const char *buffer_data; - char triple[TRIPLE_STRING_LEN]; - LLVMBool mem_err; - - if (!tm) { - strncpy(triple, "r600--", TRIPLE_STRING_LEN); - LLVMTargetRef target = radeon_llvm_get_r600_target(triple); - if (!target) { - return 1; - } - strncpy(cpu, gpu_family, CPU_STRING_LEN); - memset(fs, 0, sizeof(fs)); - if (dump_asm) - strncpy(fs, "+DumpCode", FS_STRING_LEN); - tm = LLVMCreateTargetMachine(target, triple, cpu, fs, - LLVMCodeGenLevelDefault, LLVMRelocDefault, - LLVMCodeModelDefault); - dispose_tm = true; - } - if (dump_ir) - LLVMDumpModule(M); - /* Setup Diagnostic Handler*/ - llvm_ctx = LLVMGetModuleContext(M); - -#if HAVE_LLVM >= 0x0305 - LLVMContextSetDiagnosticHandler(llvm_ctx, radeonDiagnosticHandler, &rval); -#endif - rval = 0; - - /* Compile IR*/ - mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile, &err, - &out_buffer); - - /* Process Errors/Warnings */ - if (mem_err) { - fprintf(stderr, "%s: %s", __FUNCTION__, err); - FREE(err); - LLVMDisposeTargetMachine(tm); - return 1; - } - - if (0 != rval) { - fprintf(stderr, "%s: Processing Diag Flag\n", __FUNCTION__); - } - - /* Extract Shader Code*/ - buffer_size = LLVMGetBufferSize(out_buffer); - buffer_data = LLVMGetBufferStart(out_buffer); - - radeon_elf_read(buffer_data, buffer_size, binary); - - /* Clean up */ - LLVMDisposeMemoryBuffer(out_buffer); - - if (dispose_tm) { - LLVMDisposeTargetMachine(tm); - } - return rval; -} diff --git a/lib/mesa/src/gallium/drivers/radeon/radeon_llvm_emit.h b/lib/mesa/src/gallium/drivers/radeon/radeon_llvm_emit.h deleted file mode 100644 index e20aed94c..000000000 --- a/lib/mesa/src/gallium/drivers/radeon/radeon_llvm_emit.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright 2012 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - * - * Authors: Tom Stellard <thomas.stellard@amd.com> - * - */ - -#ifndef RADEON_LLVM_EMIT_H -#define RADEON_LLVM_EMIT_H - -#include <llvm-c/Core.h> -#include <llvm-c/TargetMachine.h> -#include <stdbool.h> - -struct radeon_shader_binary; - -void radeon_llvm_shader_type(LLVMValueRef F, unsigned type); - -LLVMTargetRef radeon_llvm_get_r600_target(const char *triple); - -unsigned radeon_llvm_compile(LLVMModuleRef M, struct radeon_shader_binary *binary, - const char *gpu_family, bool dump_ir, bool dump_asm, - LLVMTargetMachineRef tm); - -#endif /* RADEON_LLVM_EMIT_H */ diff --git a/lib/mesa/src/gallium/drivers/radeon/radeon_llvm_util.c b/lib/mesa/src/gallium/drivers/radeon/radeon_llvm_util.c deleted file mode 100644 index 0dfd9ad48..000000000 --- a/lib/mesa/src/gallium/drivers/radeon/radeon_llvm_util.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright 2012, 2013 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - * - * Authors: Tom Stellard <thomas.stellard@amd.com> - * - */ - -#include "radeon_llvm_util.h" -#include "util/u_memory.h" - -#include <llvm-c/BitReader.h> -#include <llvm-c/Core.h> -#include <llvm-c/Target.h> -#include <llvm-c/Transforms/IPO.h> -#include <llvm-c/Transforms/PassManagerBuilder.h> - -LLVMModuleRef radeon_llvm_parse_bitcode(LLVMContextRef ctx, - const char * bitcode, unsigned bitcode_len) -{ - LLVMMemoryBufferRef buf; - LLVMModuleRef module; - - buf = LLVMCreateMemoryBufferWithMemoryRangeCopy((const char*)bitcode, - bitcode_len, "radeon"); - LLVMParseBitcodeInContext(ctx, buf, &module, NULL); - LLVMDisposeMemoryBuffer(buf); - return module; -} - -unsigned radeon_llvm_get_num_kernels(LLVMContextRef ctx, - const char *bitcode, unsigned bitcode_len) -{ - LLVMModuleRef mod = radeon_llvm_parse_bitcode(ctx, bitcode, bitcode_len); - return LLVMGetNamedMetadataNumOperands(mod, "opencl.kernels"); -} - -static void radeon_llvm_optimize(LLVMModuleRef mod) -{ - const char *data_layout = LLVMGetDataLayout(mod); - LLVMTargetDataRef TD = LLVMCreateTargetData(data_layout); - LLVMPassManagerBuilderRef builder = LLVMPassManagerBuilderCreate(); - LLVMPassManagerRef pass_manager = LLVMCreatePassManager(); - - /* Functions calls are not supported yet, so we need to inline - * everything. The most efficient way to do this is to add - * the always_inline attribute to all non-kernel functions - * and then run the Always Inline pass. The Always Inline - * pass will automaically inline functions with this attribute - * and does not perform the expensive cost analysis that the normal - * inliner does. - */ - - LLVMValueRef fn; - for (fn = LLVMGetFirstFunction(mod); fn; fn = LLVMGetNextFunction(fn)) { - /* All the non-kernel functions have internal linkage */ - if (LLVMGetLinkage(fn) == LLVMInternalLinkage) { - LLVMAddFunctionAttr(fn, LLVMAlwaysInlineAttribute); - } - } - - LLVMAddTargetData(TD, pass_manager); - LLVMAddAlwaysInlinerPass(pass_manager); - LLVMPassManagerBuilderPopulateModulePassManager(builder, pass_manager); - - LLVMRunPassManager(pass_manager, mod); - LLVMPassManagerBuilderDispose(builder); - LLVMDisposePassManager(pass_manager); - LLVMDisposeTargetData(TD); -} - -LLVMModuleRef radeon_llvm_get_kernel_module(LLVMContextRef ctx, unsigned index, - const char *bitcode, unsigned bitcode_len) -{ - LLVMModuleRef mod; - unsigned num_kernels; - LLVMValueRef *kernel_metadata; - unsigned i; - - mod = radeon_llvm_parse_bitcode(ctx, bitcode, bitcode_len); - num_kernels = LLVMGetNamedMetadataNumOperands(mod, "opencl.kernels"); - kernel_metadata = MALLOC(num_kernels * sizeof(LLVMValueRef)); - LLVMGetNamedMetadataOperands(mod, "opencl.kernels", kernel_metadata); - for (i = 0; i < num_kernels; i++) { - LLVMValueRef kernel_signature, *kernel_function; - unsigned num_kernel_md_operands; - if (i == index) { - continue; - } - kernel_signature = kernel_metadata[i]; - num_kernel_md_operands = LLVMGetMDNodeNumOperands(kernel_signature); - kernel_function = MALLOC(num_kernel_md_operands * sizeof (LLVMValueRef)); - LLVMGetMDNodeOperands(kernel_signature, kernel_function); - LLVMDeleteFunction(*kernel_function); - FREE(kernel_function); - } - FREE(kernel_metadata); - radeon_llvm_optimize(mod); - return mod; -} diff --git a/lib/mesa/src/gallium/drivers/radeon/radeon_llvm_util.h b/lib/mesa/src/gallium/drivers/radeon/radeon_llvm_util.h deleted file mode 100644 index cc1932aef..000000000 --- a/lib/mesa/src/gallium/drivers/radeon/radeon_llvm_util.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright 2012, 2013 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - * - * Authors: Tom Stellard <thomas.stellard@amd.com> - * - */ - -#ifndef RADEON_LLVM_UTIL_H -#define RADEON_LLVM_UTIL_H - -#include <llvm-c/Core.h> - -LLVMModuleRef radeon_llvm_parse_bitcode(LLVMContextRef ctx, - const char * bitcode, unsigned bitcode_len); -unsigned radeon_llvm_get_num_kernels(LLVMContextRef ctx, - const char *bitcode, unsigned bitcode_len); -LLVMModuleRef radeon_llvm_get_kernel_module(LLVMContextRef ctx, unsigned index, - const char *bitcode, unsigned bitcode_len); - -#endif diff --git a/lib/mesa/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c b/lib/mesa/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c deleted file mode 100644 index 56694700a..000000000 --- a/lib/mesa/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c +++ /dev/null @@ -1,1617 +0,0 @@ -/* - * Copyright 2011 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - * - * Authors: Tom Stellard <thomas.stellard@amd.com> - * - */ -#include "radeon_llvm.h" - -#include "gallivm/lp_bld_const.h" -#include "gallivm/lp_bld_gather.h" -#include "gallivm/lp_bld_flow.h" -#include "gallivm/lp_bld_init.h" -#include "gallivm/lp_bld_intr.h" -#include "gallivm/lp_bld_swizzle.h" -#include "tgsi/tgsi_info.h" -#include "tgsi/tgsi_parse.h" -#include "util/u_math.h" -#include "util/u_memory.h" -#include "util/u_debug.h" - -#include <llvm-c/Core.h> -#include <llvm-c/Transforms/Scalar.h> - -static struct radeon_llvm_loop * get_current_loop(struct radeon_llvm_context * ctx) -{ - return ctx->loop_depth > 0 ? ctx->loop + (ctx->loop_depth - 1) : NULL; -} - -static struct radeon_llvm_branch * get_current_branch( - struct radeon_llvm_context * ctx) -{ - return ctx->branch_depth > 0 ? - ctx->branch + (ctx->branch_depth - 1) : NULL; -} - -unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan) -{ - return (index * 4) + chan; -} - -static LLVMValueRef emit_swizzle( - struct lp_build_tgsi_context * bld_base, - LLVMValueRef value, - unsigned swizzle_x, - unsigned swizzle_y, - unsigned swizzle_z, - unsigned swizzle_w) -{ - LLVMValueRef swizzles[4]; - LLVMTypeRef i32t = - LLVMInt32TypeInContext(bld_base->base.gallivm->context); - - swizzles[0] = LLVMConstInt(i32t, swizzle_x, 0); - swizzles[1] = LLVMConstInt(i32t, swizzle_y, 0); - swizzles[2] = LLVMConstInt(i32t, swizzle_z, 0); - swizzles[3] = LLVMConstInt(i32t, swizzle_w, 0); - - return LLVMBuildShuffleVector(bld_base->base.gallivm->builder, - value, - LLVMGetUndef(LLVMTypeOf(value)), - LLVMConstVector(swizzles, 4), ""); -} - -static struct tgsi_declaration_range -get_array_range(struct lp_build_tgsi_context *bld_base, - unsigned File, const struct tgsi_ind_register *reg) -{ - struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base); - - if (File != TGSI_FILE_TEMPORARY || reg->ArrayID == 0 || - reg->ArrayID > bld_base->info->array_max[TGSI_FILE_TEMPORARY]) { - struct tgsi_declaration_range range; - range.First = 0; - range.Last = bld_base->info->file_max[File]; - return range; - } - - return ctx->arrays[reg->ArrayID - 1]; -} - -static LLVMValueRef -emit_array_index( - struct lp_build_tgsi_soa_context *bld, - const struct tgsi_ind_register *reg, - unsigned offset) -{ - struct gallivm_state * gallivm = bld->bld_base.base.gallivm; - - LLVMValueRef addr = LLVMBuildLoad(gallivm->builder, bld->addr[reg->Index][reg->Swizzle], ""); - return LLVMBuildAdd(gallivm->builder, addr, lp_build_const_int32(gallivm, offset), ""); -} - -LLVMValueRef -radeon_llvm_emit_fetch_double( - struct lp_build_tgsi_context *bld_base, - LLVMValueRef ptr, - LLVMValueRef ptr2) -{ - LLVMBuilderRef builder = bld_base->base.gallivm->builder; - LLVMValueRef result; - - result = LLVMGetUndef(LLVMVectorType(LLVMIntTypeInContext(bld_base->base.gallivm->context, 32), bld_base->base.type.length * 2)); - - result = LLVMBuildInsertElement(builder, - result, - bitcast(bld_base, TGSI_TYPE_UNSIGNED, ptr), - bld_base->int_bld.zero, ""); - result = LLVMBuildInsertElement(builder, - result, - bitcast(bld_base, TGSI_TYPE_UNSIGNED, ptr2), - bld_base->int_bld.one, ""); - return bitcast(bld_base, TGSI_TYPE_DOUBLE, result); -} - -static LLVMValueRef -emit_array_fetch( - struct lp_build_tgsi_context *bld_base, - unsigned File, enum tgsi_opcode_type type, - struct tgsi_declaration_range range, - unsigned swizzle) -{ - struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base); - struct gallivm_state * gallivm = bld->bld_base.base.gallivm; - LLVMBuilderRef builder = bld_base->base.gallivm->builder; - - unsigned i, size = range.Last - range.First + 1; - LLVMTypeRef vec = LLVMVectorType(tgsi2llvmtype(bld_base, type), size); - LLVMValueRef result = LLVMGetUndef(vec); - - struct tgsi_full_src_register tmp_reg = {}; - tmp_reg.Register.File = File; - - for (i = 0; i < size; ++i) { - tmp_reg.Register.Index = i + range.First; - LLVMValueRef temp = radeon_llvm_emit_fetch(bld_base, &tmp_reg, type, swizzle); - result = LLVMBuildInsertElement(builder, result, temp, - lp_build_const_int32(gallivm, i), ""); - } - return result; -} - -static bool uses_temp_indirect_addressing( - struct lp_build_tgsi_context *bld_base) -{ - struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base); - return (bld->indirect_files & (1 << TGSI_FILE_TEMPORARY)); -} - -LLVMValueRef radeon_llvm_emit_fetch(struct lp_build_tgsi_context *bld_base, - const struct tgsi_full_src_register *reg, - enum tgsi_opcode_type type, - unsigned swizzle) -{ - struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base); - struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base); - LLVMBuilderRef builder = bld_base->base.gallivm->builder; - LLVMValueRef result = NULL, ptr, ptr2; - - if (swizzle == ~0) { - LLVMValueRef values[TGSI_NUM_CHANNELS]; - unsigned chan; - for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) { - values[chan] = radeon_llvm_emit_fetch(bld_base, reg, type, chan); - } - return lp_build_gather_values(bld_base->base.gallivm, values, - TGSI_NUM_CHANNELS); - } - - if (reg->Register.Indirect) { - struct tgsi_declaration_range range = get_array_range(bld_base, - reg->Register.File, ®->Indirect); - return LLVMBuildExtractElement(builder, - emit_array_fetch(bld_base, reg->Register.File, type, range, swizzle), - emit_array_index(bld, ®->Indirect, reg->Register.Index - range.First), - ""); - } - - switch(reg->Register.File) { - case TGSI_FILE_IMMEDIATE: { - LLVMTypeRef ctype = tgsi2llvmtype(bld_base, type); - if (type == TGSI_TYPE_DOUBLE) { - result = LLVMGetUndef(LLVMVectorType(LLVMIntTypeInContext(bld_base->base.gallivm->context, 32), bld_base->base.type.length * 2)); - result = LLVMConstInsertElement(result, - bld->immediates[reg->Register.Index][swizzle], - bld_base->int_bld.zero); - result = LLVMConstInsertElement(result, - bld->immediates[reg->Register.Index][swizzle + 1], - bld_base->int_bld.one); - return LLVMConstBitCast(result, ctype); - } else { - return LLVMConstBitCast(bld->immediates[reg->Register.Index][swizzle], ctype); - } - } - - case TGSI_FILE_INPUT: - result = ctx->inputs[radeon_llvm_reg_index_soa(reg->Register.Index, swizzle)]; - if (type == TGSI_TYPE_DOUBLE) { - ptr = result; - ptr2 = ctx->inputs[radeon_llvm_reg_index_soa(reg->Register.Index, swizzle + 1)]; - return radeon_llvm_emit_fetch_double(bld_base, ptr, ptr2); - } - break; - - case TGSI_FILE_TEMPORARY: - if (reg->Register.Index >= ctx->temps_count) - return LLVMGetUndef(tgsi2llvmtype(bld_base, type)); - if (uses_temp_indirect_addressing(bld_base)) { - ptr = lp_get_temp_ptr_soa(bld, reg->Register.Index, swizzle); - break; - } - ptr = ctx->temps[reg->Register.Index * TGSI_NUM_CHANNELS + swizzle]; - if (type == TGSI_TYPE_DOUBLE) { - ptr2 = ctx->temps[reg->Register.Index * TGSI_NUM_CHANNELS + swizzle + 1]; - return radeon_llvm_emit_fetch_double(bld_base, - LLVMBuildLoad(builder, ptr, ""), - LLVMBuildLoad(builder, ptr2, "")); - } - result = LLVMBuildLoad(builder, ptr, ""); - break; - - case TGSI_FILE_OUTPUT: - ptr = lp_get_output_ptr(bld, reg->Register.Index, swizzle); - if (type == TGSI_TYPE_DOUBLE) { - ptr2 = lp_get_output_ptr(bld, reg->Register.Index, swizzle + 1); - return radeon_llvm_emit_fetch_double(bld_base, - LLVMBuildLoad(builder, ptr, ""), - LLVMBuildLoad(builder, ptr2, "")); - } - result = LLVMBuildLoad(builder, ptr, ""); - break; - - default: - return LLVMGetUndef(tgsi2llvmtype(bld_base, type)); - } - - return bitcast(bld_base, type, result); -} - -static LLVMValueRef fetch_system_value( - struct lp_build_tgsi_context * bld_base, - const struct tgsi_full_src_register *reg, - enum tgsi_opcode_type type, - unsigned swizzle) -{ - struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base); - struct gallivm_state *gallivm = bld_base->base.gallivm; - - LLVMValueRef cval = ctx->system_values[reg->Register.Index]; - if (LLVMGetTypeKind(LLVMTypeOf(cval)) == LLVMVectorTypeKind) { - cval = LLVMBuildExtractElement(gallivm->builder, cval, - lp_build_const_int32(gallivm, swizzle), ""); - } - return bitcast(bld_base, type, cval); -} - -static void emit_declaration( - struct lp_build_tgsi_context * bld_base, - const struct tgsi_full_declaration *decl) -{ - struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base); - unsigned first, last, i, idx; - switch(decl->Declaration.File) { - case TGSI_FILE_ADDRESS: - { - unsigned idx; - for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) { - unsigned chan; - for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) { - ctx->soa.addr[idx][chan] = lp_build_alloca( - &ctx->gallivm, - ctx->soa.bld_base.uint_bld.elem_type, ""); - } - } - break; - } - - case TGSI_FILE_TEMPORARY: - if (decl->Declaration.Array) { - if (!ctx->arrays) { - int size = bld_base->info->array_max[TGSI_FILE_TEMPORARY]; - ctx->arrays = MALLOC(sizeof(ctx->arrays[0]) * size); - } - - ctx->arrays[decl->Array.ArrayID - 1] = decl->Range; - } - if (uses_temp_indirect_addressing(bld_base)) { - lp_emit_declaration_soa(bld_base, decl); - break; - } - first = decl->Range.First; - last = decl->Range.Last; - if (!ctx->temps_count) { - ctx->temps_count = bld_base->info->file_max[TGSI_FILE_TEMPORARY] + 1; - ctx->temps = MALLOC(TGSI_NUM_CHANNELS * ctx->temps_count * sizeof(LLVMValueRef)); - } - for (idx = first; idx <= last; idx++) { - for (i = 0; i < TGSI_NUM_CHANNELS; i++) { - ctx->temps[idx * TGSI_NUM_CHANNELS + i] = - lp_build_alloca(bld_base->base.gallivm, bld_base->base.vec_type, - "temp"); - } - } - break; - - case TGSI_FILE_INPUT: - { - unsigned idx; - for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) { - if (ctx->load_input) - ctx->load_input(ctx, idx, decl); - } - } - break; - - case TGSI_FILE_SYSTEM_VALUE: - { - unsigned idx; - for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) { - ctx->load_system_value(ctx, idx, decl); - } - } - break; - - case TGSI_FILE_OUTPUT: - { - unsigned idx; - for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) { - unsigned chan; - assert(idx < RADEON_LLVM_MAX_OUTPUTS); - for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) { - ctx->soa.outputs[idx][chan] = lp_build_alloca(&ctx->gallivm, - ctx->soa.bld_base.base.elem_type, ""); - } - } - - ctx->output_reg_count = MAX2(ctx->output_reg_count, - decl->Range.Last + 1); - break; - } - - default: - break; - } -} - -LLVMValueRef radeon_llvm_saturate(struct lp_build_tgsi_context *bld_base, - LLVMValueRef value) -{ - struct lp_build_emit_data clamp_emit_data; - - memset(&clamp_emit_data, 0, sizeof(clamp_emit_data)); - clamp_emit_data.arg_count = 3; - clamp_emit_data.args[0] = value; - clamp_emit_data.args[2] = bld_base->base.one; - clamp_emit_data.args[1] = bld_base->base.zero; - - return lp_build_emit_llvm(bld_base, TGSI_OPCODE_CLAMP, - &clamp_emit_data); -} - -void radeon_llvm_emit_store( - struct lp_build_tgsi_context * bld_base, - const struct tgsi_full_instruction * inst, - const struct tgsi_opcode_info * info, - LLVMValueRef dst[4]) -{ - struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base); - struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base); - struct gallivm_state *gallivm = bld->bld_base.base.gallivm; - const struct tgsi_full_dst_register *reg = &inst->Dst[0]; - LLVMBuilderRef builder = bld->bld_base.base.gallivm->builder; - LLVMValueRef temp_ptr, temp_ptr2 = NULL; - unsigned chan, chan_index; - boolean is_vec_store = FALSE; - enum tgsi_opcode_type dtype = tgsi_opcode_infer_dst_type(inst->Instruction.Opcode); - - if (dst[0]) { - LLVMTypeKind k = LLVMGetTypeKind(LLVMTypeOf(dst[0])); - is_vec_store = (k == LLVMVectorTypeKind); - } - - if (is_vec_store) { - LLVMValueRef values[4] = {}; - TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan) { - LLVMValueRef index = lp_build_const_int32(gallivm, chan); - values[chan] = LLVMBuildExtractElement(gallivm->builder, - dst[0], index, ""); - } - bld_base->emit_store(bld_base, inst, info, values); - return; - } - - TGSI_FOR_EACH_DST0_ENABLED_CHANNEL( inst, chan_index ) { - LLVMValueRef value = dst[chan_index]; - - if (dtype == TGSI_TYPE_DOUBLE && (chan_index == 1 || chan_index == 3)) - continue; - if (inst->Instruction.Saturate) - value = radeon_llvm_saturate(bld_base, value); - - if (reg->Register.File == TGSI_FILE_ADDRESS) { - temp_ptr = bld->addr[reg->Register.Index][chan_index]; - LLVMBuildStore(builder, value, temp_ptr); - continue; - } - - if (dtype != TGSI_TYPE_DOUBLE) - value = bitcast(bld_base, TGSI_TYPE_FLOAT, value); - - if (reg->Register.Indirect) { - struct tgsi_declaration_range range = get_array_range(bld_base, - reg->Register.File, ®->Indirect); - - unsigned i, size = range.Last - range.First + 1; - LLVMValueRef array = LLVMBuildInsertElement(builder, - emit_array_fetch(bld_base, reg->Register.File, TGSI_TYPE_FLOAT, range, chan_index), - value, emit_array_index(bld, ®->Indirect, reg->Register.Index - range.First), ""); - - for (i = 0; i < size; ++i) { - switch(reg->Register.File) { - case TGSI_FILE_OUTPUT: - temp_ptr = bld->outputs[i + range.First][chan_index]; - break; - - case TGSI_FILE_TEMPORARY: - if (range.First + i >= ctx->temps_count) - continue; - if (uses_temp_indirect_addressing(bld_base)) - temp_ptr = lp_get_temp_ptr_soa(bld, i + range.First, chan_index); - else - temp_ptr = ctx->temps[(i + range.First) * TGSI_NUM_CHANNELS + chan_index]; - break; - - default: - return; - } - value = LLVMBuildExtractElement(builder, array, - lp_build_const_int32(gallivm, i), ""); - LLVMBuildStore(builder, value, temp_ptr); - } - - } else { - switch(reg->Register.File) { - case TGSI_FILE_OUTPUT: - temp_ptr = bld->outputs[reg->Register.Index][chan_index]; - if (dtype == TGSI_TYPE_DOUBLE) - temp_ptr2 = bld->outputs[reg->Register.Index][chan_index + 1]; - break; - - case TGSI_FILE_TEMPORARY: - if (reg->Register.Index >= ctx->temps_count) - continue; - if (uses_temp_indirect_addressing(bld_base)) { - temp_ptr = NULL; - break; - } - temp_ptr = ctx->temps[ TGSI_NUM_CHANNELS * reg->Register.Index + chan_index]; - if (dtype == TGSI_TYPE_DOUBLE) - temp_ptr2 = ctx->temps[ TGSI_NUM_CHANNELS * reg->Register.Index + chan_index + 1]; - - break; - - default: - return; - } - if (dtype != TGSI_TYPE_DOUBLE) - LLVMBuildStore(builder, value, temp_ptr); - else { - LLVMValueRef ptr = LLVMBuildBitCast(builder, value, - LLVMVectorType(LLVMIntTypeInContext(bld_base->base.gallivm->context, 32), 2), ""); - LLVMValueRef val2; - value = LLVMBuildExtractElement(builder, ptr, - bld_base->uint_bld.zero, ""); - val2 = LLVMBuildExtractElement(builder, ptr, - bld_base->uint_bld.one, ""); - - LLVMBuildStore(builder, bitcast(bld_base, TGSI_TYPE_FLOAT, value), temp_ptr); - LLVMBuildStore(builder, bitcast(bld_base, TGSI_TYPE_FLOAT, val2), temp_ptr2); - } - } - } -} - -static void bgnloop_emit( - const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base); - struct gallivm_state * gallivm = bld_base->base.gallivm; - LLVMBasicBlockRef loop_block; - LLVMBasicBlockRef endloop_block; - endloop_block = LLVMAppendBasicBlockInContext(gallivm->context, - ctx->main_fn, "ENDLOOP"); - loop_block = LLVMInsertBasicBlockInContext(gallivm->context, - endloop_block, "LOOP"); - LLVMBuildBr(gallivm->builder, loop_block); - LLVMPositionBuilderAtEnd(gallivm->builder, loop_block); - - if (++ctx->loop_depth > ctx->loop_depth_max) { - unsigned new_max = ctx->loop_depth_max << 1; - - if (!new_max) - new_max = RADEON_LLVM_INITIAL_CF_DEPTH; - - ctx->loop = REALLOC(ctx->loop, ctx->loop_depth_max * - sizeof(ctx->loop[0]), - new_max * sizeof(ctx->loop[0])); - ctx->loop_depth_max = new_max; - } - - ctx->loop[ctx->loop_depth - 1].loop_block = loop_block; - ctx->loop[ctx->loop_depth - 1].endloop_block = endloop_block; -} - -static void brk_emit( - const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base); - struct gallivm_state * gallivm = bld_base->base.gallivm; - struct radeon_llvm_loop * current_loop = get_current_loop(ctx); - - LLVMBuildBr(gallivm->builder, current_loop->endloop_block); -} - -static void cont_emit( - const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base); - struct gallivm_state * gallivm = bld_base->base.gallivm; - struct radeon_llvm_loop * current_loop = get_current_loop(ctx); - - LLVMBuildBr(gallivm->builder, current_loop->loop_block); -} - -static void else_emit( - const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base); - struct gallivm_state * gallivm = bld_base->base.gallivm; - struct radeon_llvm_branch * current_branch = get_current_branch(ctx); - LLVMBasicBlockRef current_block = LLVMGetInsertBlock(gallivm->builder); - - /* We need to add a terminator to the current block if the previous - * instruction was an ENDIF.Example: - * IF - * [code] - * IF - * [code] - * ELSE - * [code] - * ENDIF <-- - * ELSE<-- - * [code] - * ENDIF - */ - - if (current_block != current_branch->if_block) { - LLVMBuildBr(gallivm->builder, current_branch->endif_block); - } - if (!LLVMGetBasicBlockTerminator(current_branch->if_block)) { - LLVMBuildBr(gallivm->builder, current_branch->endif_block); - } - current_branch->has_else = 1; - LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->else_block); -} - -static void endif_emit( - const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base); - struct gallivm_state * gallivm = bld_base->base.gallivm; - struct radeon_llvm_branch * current_branch = get_current_branch(ctx); - LLVMBasicBlockRef current_block = LLVMGetInsertBlock(gallivm->builder); - - /* If we have consecutive ENDIF instructions, then the first ENDIF - * will not have a terminator, so we need to add one. */ - if (current_block != current_branch->if_block - && current_block != current_branch->else_block - && !LLVMGetBasicBlockTerminator(current_block)) { - - LLVMBuildBr(gallivm->builder, current_branch->endif_block); - } - if (!LLVMGetBasicBlockTerminator(current_branch->else_block)) { - LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->else_block); - LLVMBuildBr(gallivm->builder, current_branch->endif_block); - } - - if (!LLVMGetBasicBlockTerminator(current_branch->if_block)) { - LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->if_block); - LLVMBuildBr(gallivm->builder, current_branch->endif_block); - } - - LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->endif_block); - ctx->branch_depth--; -} - -static void endloop_emit( - const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base); - struct gallivm_state * gallivm = bld_base->base.gallivm; - struct radeon_llvm_loop * current_loop = get_current_loop(ctx); - - if (!LLVMGetBasicBlockTerminator(LLVMGetInsertBlock(gallivm->builder))) { - LLVMBuildBr(gallivm->builder, current_loop->loop_block); - } - - LLVMPositionBuilderAtEnd(gallivm->builder, current_loop->endloop_block); - ctx->loop_depth--; -} - -static void if_cond_emit( - const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data, - LLVMValueRef cond) -{ - struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base); - struct gallivm_state * gallivm = bld_base->base.gallivm; - LLVMBasicBlockRef if_block, else_block, endif_block; - - endif_block = LLVMAppendBasicBlockInContext(gallivm->context, - ctx->main_fn, "ENDIF"); - if_block = LLVMInsertBasicBlockInContext(gallivm->context, - endif_block, "IF"); - else_block = LLVMInsertBasicBlockInContext(gallivm->context, - endif_block, "ELSE"); - LLVMBuildCondBr(gallivm->builder, cond, if_block, else_block); - LLVMPositionBuilderAtEnd(gallivm->builder, if_block); - - if (++ctx->branch_depth > ctx->branch_depth_max) { - unsigned new_max = ctx->branch_depth_max << 1; - - if (!new_max) - new_max = RADEON_LLVM_INITIAL_CF_DEPTH; - - ctx->branch = REALLOC(ctx->branch, ctx->branch_depth_max * - sizeof(ctx->branch[0]), - new_max * sizeof(ctx->branch[0])); - ctx->branch_depth_max = new_max; - } - - ctx->branch[ctx->branch_depth - 1].endif_block = endif_block; - ctx->branch[ctx->branch_depth - 1].if_block = if_block; - ctx->branch[ctx->branch_depth - 1].else_block = else_block; - ctx->branch[ctx->branch_depth - 1].has_else = 0; -} - -static void if_emit( - const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - struct gallivm_state * gallivm = bld_base->base.gallivm; - LLVMValueRef cond; - - cond = LLVMBuildFCmp(gallivm->builder, LLVMRealUNE, - emit_data->args[0], - bld_base->base.zero, ""); - - if_cond_emit(action, bld_base, emit_data, cond); -} - -static void uif_emit( - const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - struct gallivm_state * gallivm = bld_base->base.gallivm; - LLVMValueRef cond; - - cond = LLVMBuildICmp(gallivm->builder, LLVMIntNE, - bitcast(bld_base, TGSI_TYPE_UNSIGNED, emit_data->args[0]), - bld_base->int_bld.zero, ""); - - if_cond_emit(action, bld_base, emit_data, cond); -} - -static void kill_if_fetch_args( - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - const struct tgsi_full_instruction * inst = emit_data->inst; - struct gallivm_state *gallivm = bld_base->base.gallivm; - LLVMBuilderRef builder = gallivm->builder; - unsigned i; - LLVMValueRef conds[TGSI_NUM_CHANNELS]; - - for (i = 0; i < TGSI_NUM_CHANNELS; i++) { - LLVMValueRef value = lp_build_emit_fetch(bld_base, inst, 0, i); - conds[i] = LLVMBuildFCmp(builder, LLVMRealOLT, value, - bld_base->base.zero, ""); - } - - /* Or the conditions together */ - for (i = TGSI_NUM_CHANNELS - 1; i > 0; i--) { - conds[i - 1] = LLVMBuildOr(builder, conds[i], conds[i - 1], ""); - } - - emit_data->dst_type = LLVMVoidTypeInContext(gallivm->context); - emit_data->arg_count = 1; - emit_data->args[0] = LLVMBuildSelect(builder, conds[0], - lp_build_const_float(gallivm, -1.0f), - bld_base->base.zero, ""); -} - -static void kil_emit( - const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - unsigned i; - for (i = 0; i < emit_data->arg_count; i++) { - emit_data->output[i] = lp_build_intrinsic_unary( - bld_base->base.gallivm->builder, - action->intr_name, - emit_data->dst_type, emit_data->args[i]); - } -} - -static void radeon_llvm_cube_to_2d_coords(struct lp_build_tgsi_context *bld_base, - LLVMValueRef *in, LLVMValueRef *out) -{ - struct gallivm_state * gallivm = bld_base->base.gallivm; - LLVMBuilderRef builder = gallivm->builder; - LLVMTypeRef type = bld_base->base.elem_type; - LLVMValueRef coords[4]; - LLVMValueRef mad_args[3]; - LLVMValueRef v, cube_vec; - unsigned i; - - cube_vec = lp_build_gather_values(bld_base->base.gallivm, in, 4); - v = lp_build_intrinsic(builder, "llvm.AMDGPU.cube", LLVMVectorType(type, 4), - &cube_vec, 1, LLVMReadNoneAttribute); - - for (i = 0; i < 4; ++i) - coords[i] = LLVMBuildExtractElement(builder, v, - lp_build_const_int32(gallivm, i), ""); - - coords[2] = lp_build_intrinsic(builder, "llvm.fabs.f32", - type, &coords[2], 1, LLVMReadNoneAttribute); - coords[2] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_RCP, coords[2]); - - mad_args[1] = coords[2]; - mad_args[2] = LLVMConstReal(type, 1.5); - - mad_args[0] = coords[0]; - coords[0] = lp_build_emit_llvm_ternary(bld_base, TGSI_OPCODE_MAD, - mad_args[0], mad_args[1], mad_args[2]); - - mad_args[0] = coords[1]; - coords[1] = lp_build_emit_llvm_ternary(bld_base, TGSI_OPCODE_MAD, - mad_args[0], mad_args[1], mad_args[2]); - - /* apply xyz = yxw swizzle to cooords */ - out[0] = coords[1]; - out[1] = coords[0]; - out[2] = coords[3]; -} - -void radeon_llvm_emit_prepare_cube_coords( - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data, - LLVMValueRef *coords_arg, - LLVMValueRef *derivs_arg) -{ - - unsigned target = emit_data->inst->Texture.Texture; - unsigned opcode = emit_data->inst->Instruction.Opcode; - struct gallivm_state * gallivm = bld_base->base.gallivm; - LLVMBuilderRef builder = gallivm->builder; - LLVMValueRef coords[4]; - unsigned i; - - radeon_llvm_cube_to_2d_coords(bld_base, coords_arg, coords); - - if (opcode == TGSI_OPCODE_TXD && derivs_arg) { - LLVMValueRef derivs[4]; - int axis; - - /* Convert cube derivatives to 2D derivatives. */ - for (axis = 0; axis < 2; axis++) { - LLVMValueRef shifted_cube_coords[4], shifted_coords[4]; - - /* Shift the cube coordinates by the derivatives to get - * the cube coordinates of the "neighboring pixel". - */ - for (i = 0; i < 3; i++) - shifted_cube_coords[i] = - LLVMBuildFAdd(builder, coords_arg[i], - derivs_arg[axis*3+i], ""); - shifted_cube_coords[3] = LLVMGetUndef(bld_base->base.elem_type); - - /* Project the shifted cube coordinates onto the face. */ - radeon_llvm_cube_to_2d_coords(bld_base, shifted_cube_coords, - shifted_coords); - - /* Subtract both sets of 2D coordinates to get 2D derivatives. - * This won't work if the shifted coordinates ended up - * in a different face. - */ - for (i = 0; i < 2; i++) - derivs[axis * 2 + i] = - LLVMBuildFSub(builder, shifted_coords[i], - coords[i], ""); - } - - memcpy(derivs_arg, derivs, sizeof(derivs)); - } - - if (target == TGSI_TEXTURE_CUBE_ARRAY || - target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) { - /* for cube arrays coord.z = coord.w(array_index) * 8 + face */ - /* coords_arg.w component - array_index for cube arrays */ - coords[2] = lp_build_emit_llvm_ternary(bld_base, TGSI_OPCODE_MAD, - coords_arg[3], lp_build_const_float(gallivm, 8.0), coords[2]); - } - - /* Preserve compare/lod/bias. Put it in coords.w. */ - if (opcode == TGSI_OPCODE_TEX2 || - opcode == TGSI_OPCODE_TXB2 || - opcode == TGSI_OPCODE_TXL2) { - coords[3] = coords_arg[4]; - } else if (opcode == TGSI_OPCODE_TXB || - opcode == TGSI_OPCODE_TXL || - target == TGSI_TEXTURE_SHADOWCUBE) { - coords[3] = coords_arg[3]; - } - - memcpy(coords_arg, coords, sizeof(coords)); -} - -static void emit_icmp( - const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - unsigned pred; - LLVMBuilderRef builder = bld_base->base.gallivm->builder; - LLVMContextRef context = bld_base->base.gallivm->context; - - switch (emit_data->inst->Instruction.Opcode) { - case TGSI_OPCODE_USEQ: pred = LLVMIntEQ; break; - case TGSI_OPCODE_USNE: pred = LLVMIntNE; break; - case TGSI_OPCODE_USGE: pred = LLVMIntUGE; break; - case TGSI_OPCODE_USLT: pred = LLVMIntULT; break; - case TGSI_OPCODE_ISGE: pred = LLVMIntSGE; break; - case TGSI_OPCODE_ISLT: pred = LLVMIntSLT; break; - default: - assert(!"unknown instruction"); - pred = 0; - break; - } - - LLVMValueRef v = LLVMBuildICmp(builder, pred, - emit_data->args[0], emit_data->args[1],""); - - v = LLVMBuildSExtOrBitCast(builder, v, - LLVMInt32TypeInContext(context), ""); - - emit_data->output[emit_data->chan] = v; -} - -static void emit_ucmp( - const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - LLVMBuilderRef builder = bld_base->base.gallivm->builder; - - LLVMValueRef arg0 = LLVMBuildBitCast(builder, emit_data->args[0], - bld_base->uint_bld.elem_type, ""); - - LLVMValueRef v = LLVMBuildICmp(builder, LLVMIntNE, arg0, - bld_base->uint_bld.zero, ""); - - emit_data->output[emit_data->chan] = - LLVMBuildSelect(builder, v, emit_data->args[1], emit_data->args[2], ""); -} - -static void emit_cmp( - const struct lp_build_tgsi_action *action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - LLVMBuilderRef builder = bld_base->base.gallivm->builder; - LLVMRealPredicate pred; - LLVMValueRef cond; - - /* Use ordered for everything but NE (which is usual for - * float comparisons) - */ - switch (emit_data->inst->Instruction.Opcode) { - case TGSI_OPCODE_SGE: pred = LLVMRealOGE; break; - case TGSI_OPCODE_SEQ: pred = LLVMRealOEQ; break; - case TGSI_OPCODE_SLE: pred = LLVMRealOLE; break; - case TGSI_OPCODE_SLT: pred = LLVMRealOLT; break; - case TGSI_OPCODE_SNE: pred = LLVMRealUNE; break; - case TGSI_OPCODE_SGT: pred = LLVMRealOGT; break; - default: assert(!"unknown instruction"); pred = 0; break; - } - - cond = LLVMBuildFCmp(builder, - pred, emit_data->args[0], emit_data->args[1], ""); - - emit_data->output[emit_data->chan] = LLVMBuildSelect(builder, - cond, bld_base->base.one, bld_base->base.zero, ""); -} - -static void emit_fcmp( - const struct lp_build_tgsi_action *action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - LLVMBuilderRef builder = bld_base->base.gallivm->builder; - LLVMContextRef context = bld_base->base.gallivm->context; - LLVMRealPredicate pred; - - /* Use ordered for everything but NE (which is usual for - * float comparisons) - */ - switch (emit_data->inst->Instruction.Opcode) { - case TGSI_OPCODE_FSEQ: pred = LLVMRealOEQ; break; - case TGSI_OPCODE_FSGE: pred = LLVMRealOGE; break; - case TGSI_OPCODE_FSLT: pred = LLVMRealOLT; break; - case TGSI_OPCODE_FSNE: pred = LLVMRealUNE; break; - default: assert(!"unknown instruction"); pred = 0; break; - } - - LLVMValueRef v = LLVMBuildFCmp(builder, pred, - emit_data->args[0], emit_data->args[1],""); - - v = LLVMBuildSExtOrBitCast(builder, v, - LLVMInt32TypeInContext(context), ""); - - emit_data->output[emit_data->chan] = v; -} - -static void emit_dcmp( - const struct lp_build_tgsi_action *action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - LLVMBuilderRef builder = bld_base->base.gallivm->builder; - LLVMContextRef context = bld_base->base.gallivm->context; - LLVMRealPredicate pred; - - /* Use ordered for everything but NE (which is usual for - * float comparisons) - */ - switch (emit_data->inst->Instruction.Opcode) { - case TGSI_OPCODE_DSEQ: pred = LLVMRealOEQ; break; - case TGSI_OPCODE_DSGE: pred = LLVMRealOGE; break; - case TGSI_OPCODE_DSLT: pred = LLVMRealOLT; break; - case TGSI_OPCODE_DSNE: pred = LLVMRealUNE; break; - default: assert(!"unknown instruction"); pred = 0; break; - } - - LLVMValueRef v = LLVMBuildFCmp(builder, pred, - emit_data->args[0], emit_data->args[1],""); - - v = LLVMBuildSExtOrBitCast(builder, v, - LLVMInt32TypeInContext(context), ""); - - emit_data->output[emit_data->chan] = v; -} - -static void emit_not( - const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - LLVMBuilderRef builder = bld_base->base.gallivm->builder; - LLVMValueRef v = bitcast(bld_base, TGSI_TYPE_UNSIGNED, - emit_data->args[0]); - emit_data->output[emit_data->chan] = LLVMBuildNot(builder, v, ""); -} - -static void emit_arl( - const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - LLVMBuilderRef builder = bld_base->base.gallivm->builder; - LLVMValueRef floor_index = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_FLR, emit_data->args[0]); - emit_data->output[emit_data->chan] = LLVMBuildFPToSI(builder, - floor_index, bld_base->base.int_elem_type , ""); -} - -static void emit_and( - const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - LLVMBuilderRef builder = bld_base->base.gallivm->builder; - emit_data->output[emit_data->chan] = LLVMBuildAnd(builder, - emit_data->args[0], emit_data->args[1], ""); -} - -static void emit_or( - const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - LLVMBuilderRef builder = bld_base->base.gallivm->builder; - emit_data->output[emit_data->chan] = LLVMBuildOr(builder, - emit_data->args[0], emit_data->args[1], ""); -} - -static void emit_uadd( - const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - LLVMBuilderRef builder = bld_base->base.gallivm->builder; - emit_data->output[emit_data->chan] = LLVMBuildAdd(builder, - emit_data->args[0], emit_data->args[1], ""); -} - -static void emit_udiv( - const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - LLVMBuilderRef builder = bld_base->base.gallivm->builder; - emit_data->output[emit_data->chan] = LLVMBuildUDiv(builder, - emit_data->args[0], emit_data->args[1], ""); -} - -static void emit_idiv( - const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - LLVMBuilderRef builder = bld_base->base.gallivm->builder; - emit_data->output[emit_data->chan] = LLVMBuildSDiv(builder, - emit_data->args[0], emit_data->args[1], ""); -} - -static void emit_mod( - const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - LLVMBuilderRef builder = bld_base->base.gallivm->builder; - emit_data->output[emit_data->chan] = LLVMBuildSRem(builder, - emit_data->args[0], emit_data->args[1], ""); -} - -static void emit_umod( - const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - LLVMBuilderRef builder = bld_base->base.gallivm->builder; - emit_data->output[emit_data->chan] = LLVMBuildURem(builder, - emit_data->args[0], emit_data->args[1], ""); -} - -static void emit_shl( - const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - LLVMBuilderRef builder = bld_base->base.gallivm->builder; - emit_data->output[emit_data->chan] = LLVMBuildShl(builder, - emit_data->args[0], emit_data->args[1], ""); -} - -static void emit_ushr( - const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - LLVMBuilderRef builder = bld_base->base.gallivm->builder; - emit_data->output[emit_data->chan] = LLVMBuildLShr(builder, - emit_data->args[0], emit_data->args[1], ""); -} -static void emit_ishr( - const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - LLVMBuilderRef builder = bld_base->base.gallivm->builder; - emit_data->output[emit_data->chan] = LLVMBuildAShr(builder, - emit_data->args[0], emit_data->args[1], ""); -} - -static void emit_xor( - const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - LLVMBuilderRef builder = bld_base->base.gallivm->builder; - emit_data->output[emit_data->chan] = LLVMBuildXor(builder, - emit_data->args[0], emit_data->args[1], ""); -} - -static void emit_ssg( - const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - LLVMBuilderRef builder = bld_base->base.gallivm->builder; - - LLVMValueRef cmp, val; - - if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_ISSG) { - cmp = LLVMBuildICmp(builder, LLVMIntSGT, emit_data->args[0], bld_base->int_bld.zero, ""); - val = LLVMBuildSelect(builder, cmp, bld_base->int_bld.one, emit_data->args[0], ""); - cmp = LLVMBuildICmp(builder, LLVMIntSGE, val, bld_base->int_bld.zero, ""); - val = LLVMBuildSelect(builder, cmp, val, LLVMConstInt(bld_base->int_bld.elem_type, -1, true), ""); - } else { // float SSG - cmp = LLVMBuildFCmp(builder, LLVMRealOGT, emit_data->args[0], bld_base->base.zero, ""); - val = LLVMBuildSelect(builder, cmp, bld_base->base.one, emit_data->args[0], ""); - cmp = LLVMBuildFCmp(builder, LLVMRealOGE, val, bld_base->base.zero, ""); - val = LLVMBuildSelect(builder, cmp, val, LLVMConstReal(bld_base->base.elem_type, -1), ""); - } - - emit_data->output[emit_data->chan] = val; -} - -static void emit_ineg( - const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - LLVMBuilderRef builder = bld_base->base.gallivm->builder; - emit_data->output[emit_data->chan] = LLVMBuildNeg(builder, - emit_data->args[0], ""); -} - -static void emit_dneg( - const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - LLVMBuilderRef builder = bld_base->base.gallivm->builder; - emit_data->output[emit_data->chan] = LLVMBuildFNeg(builder, - emit_data->args[0], ""); -} - -static void emit_frac( - const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - LLVMBuilderRef builder = bld_base->base.gallivm->builder; - char *intr; - - if (emit_data->info->opcode == TGSI_OPCODE_FRC) - intr = "llvm.floor.f32"; - else if (emit_data->info->opcode == TGSI_OPCODE_DFRAC) - intr = "llvm.floor.f64"; - else { - assert(0); - return; - } - - LLVMValueRef floor = lp_build_intrinsic(builder, intr, emit_data->dst_type, - &emit_data->args[0], 1, - LLVMReadNoneAttribute); - emit_data->output[emit_data->chan] = LLVMBuildFSub(builder, - emit_data->args[0], floor, ""); -} - -static void emit_f2i( - const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - LLVMBuilderRef builder = bld_base->base.gallivm->builder; - emit_data->output[emit_data->chan] = LLVMBuildFPToSI(builder, - emit_data->args[0], bld_base->int_bld.elem_type, ""); -} - -static void emit_f2u( - const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - LLVMBuilderRef builder = bld_base->base.gallivm->builder; - emit_data->output[emit_data->chan] = LLVMBuildFPToUI(builder, - emit_data->args[0], bld_base->uint_bld.elem_type, ""); -} - -static void emit_i2f( - const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - LLVMBuilderRef builder = bld_base->base.gallivm->builder; - emit_data->output[emit_data->chan] = LLVMBuildSIToFP(builder, - emit_data->args[0], bld_base->base.elem_type, ""); -} - -static void emit_u2f( - const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - LLVMBuilderRef builder = bld_base->base.gallivm->builder; - emit_data->output[emit_data->chan] = LLVMBuildUIToFP(builder, - emit_data->args[0], bld_base->base.elem_type, ""); -} - -static void emit_immediate(struct lp_build_tgsi_context * bld_base, - const struct tgsi_full_immediate *imm) -{ - unsigned i; - struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base); - - for (i = 0; i < 4; ++i) { - ctx->soa.immediates[ctx->soa.num_immediates][i] = - LLVMConstInt(bld_base->uint_bld.elem_type, imm->u[i].Uint, false ); - } - - ctx->soa.num_immediates++; -} - -void -build_tgsi_intrinsic_nomem(const struct lp_build_tgsi_action *action, - struct lp_build_tgsi_context *bld_base, - struct lp_build_emit_data *emit_data) -{ - struct lp_build_context * base = &bld_base->base; - emit_data->output[emit_data->chan] = - lp_build_intrinsic(base->gallivm->builder, action->intr_name, - emit_data->dst_type, emit_data->args, - emit_data->arg_count, LLVMReadNoneAttribute); -} - -static void emit_bfi(const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - struct gallivm_state *gallivm = bld_base->base.gallivm; - LLVMBuilderRef builder = gallivm->builder; - LLVMValueRef bfi_args[3]; - - // Calculate the bitmask: (((1 << src3) - 1) << src2 - bfi_args[0] = LLVMBuildShl(builder, - LLVMBuildSub(builder, - LLVMBuildShl(builder, - bld_base->int_bld.one, - emit_data->args[3], ""), - bld_base->int_bld.one, ""), - emit_data->args[2], ""); - - bfi_args[1] = LLVMBuildShl(builder, emit_data->args[1], - emit_data->args[2], ""); - - bfi_args[2] = emit_data->args[0]; - - /* Calculate: - * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2) - * Use the right-hand side, which the LLVM backend can convert to V_BFI. - */ - emit_data->output[emit_data->chan] = - LLVMBuildXor(builder, bfi_args[2], - LLVMBuildAnd(builder, bfi_args[0], - LLVMBuildXor(builder, bfi_args[1], bfi_args[2], - ""), ""), ""); -} - -/* this is ffs in C */ -static void emit_lsb(const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - struct gallivm_state *gallivm = bld_base->base.gallivm; - LLVMValueRef args[2] = { - emit_data->args[0], - - /* The value of 1 means that ffs(x=0) = undef, so LLVM won't - * add special code to check for x=0. The reason is that - * the LLVM behavior for x=0 is different from what we - * need here. - * - * The hardware already implements the correct behavior. - */ - lp_build_const_int32(gallivm, 1) - }; - - emit_data->output[emit_data->chan] = - lp_build_intrinsic(gallivm->builder, "llvm.cttz.i32", - emit_data->dst_type, args, Elements(args), - LLVMReadNoneAttribute); -} - -/* Find the last bit set. */ -static void emit_umsb(const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - struct gallivm_state *gallivm = bld_base->base.gallivm; - LLVMBuilderRef builder = gallivm->builder; - LLVMValueRef args[2] = { - emit_data->args[0], - /* Don't generate code for handling zero: */ - lp_build_const_int32(gallivm, 1) - }; - - LLVMValueRef msb = - lp_build_intrinsic(builder, "llvm.ctlz.i32", - emit_data->dst_type, args, Elements(args), - LLVMReadNoneAttribute); - - /* The HW returns the last bit index from MSB, but TGSI wants - * the index from LSB. Invert it by doing "31 - msb". */ - msb = LLVMBuildSub(builder, lp_build_const_int32(gallivm, 31), - msb, ""); - - /* Check for zero: */ - emit_data->output[emit_data->chan] = - LLVMBuildSelect(builder, - LLVMBuildICmp(builder, LLVMIntEQ, args[0], - bld_base->uint_bld.zero, ""), - lp_build_const_int32(gallivm, -1), msb, ""); -} - -/* Find the last bit opposite of the sign bit. */ -static void emit_imsb(const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) -{ - struct gallivm_state *gallivm = bld_base->base.gallivm; - LLVMBuilderRef builder = gallivm->builder; - LLVMValueRef arg = emit_data->args[0]; - - LLVMValueRef msb = - lp_build_intrinsic(builder, "llvm.AMDGPU.flbit.i32", - emit_data->dst_type, &arg, 1, - LLVMReadNoneAttribute); - - /* The HW returns the last bit index from MSB, but TGSI wants - * the index from LSB. Invert it by doing "31 - msb". */ - msb = LLVMBuildSub(builder, lp_build_const_int32(gallivm, 31), - msb, ""); - - /* If arg == 0 || arg == -1 (0xffffffff), return -1. */ - LLVMValueRef all_ones = lp_build_const_int32(gallivm, -1); - - LLVMValueRef cond = - LLVMBuildOr(builder, - LLVMBuildICmp(builder, LLVMIntEQ, arg, - bld_base->uint_bld.zero, ""), - LLVMBuildICmp(builder, LLVMIntEQ, arg, - all_ones, ""), ""); - - emit_data->output[emit_data->chan] = - LLVMBuildSelect(builder, cond, all_ones, msb, ""); -} - -void radeon_llvm_context_init(struct radeon_llvm_context * ctx) -{ - struct lp_type type; - - /* Initialize the gallivm object: - * We are only using the module, context, and builder fields of this struct. - * This should be enough for us to be able to pass our gallivm struct to the - * helper functions in the gallivm module. - */ - memset(&ctx->gallivm, 0, sizeof (ctx->gallivm)); - memset(&ctx->soa, 0, sizeof(ctx->soa)); - ctx->gallivm.context = LLVMContextCreate(); - ctx->gallivm.module = LLVMModuleCreateWithNameInContext("tgsi", - ctx->gallivm.context); - ctx->gallivm.builder = LLVMCreateBuilderInContext(ctx->gallivm.context); - - struct lp_build_tgsi_context * bld_base = &ctx->soa.bld_base; - - type.floating = TRUE; - type.fixed = FALSE; - type.sign = TRUE; - type.norm = FALSE; - type.width = 32; - type.length = 1; - - lp_build_context_init(&bld_base->base, &ctx->gallivm, type); - lp_build_context_init(&ctx->soa.bld_base.uint_bld, &ctx->gallivm, lp_uint_type(type)); - lp_build_context_init(&ctx->soa.bld_base.int_bld, &ctx->gallivm, lp_int_type(type)); - { - struct lp_type dbl_type; - dbl_type = type; - dbl_type.width *= 2; - lp_build_context_init(&ctx->soa.bld_base.dbl_bld, &ctx->gallivm, dbl_type); - } - - bld_base->soa = 1; - bld_base->emit_store = radeon_llvm_emit_store; - bld_base->emit_swizzle = emit_swizzle; - bld_base->emit_declaration = emit_declaration; - bld_base->emit_immediate = emit_immediate; - - bld_base->emit_fetch_funcs[TGSI_FILE_IMMEDIATE] = radeon_llvm_emit_fetch; - bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = radeon_llvm_emit_fetch; - bld_base->emit_fetch_funcs[TGSI_FILE_TEMPORARY] = radeon_llvm_emit_fetch; - bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = radeon_llvm_emit_fetch; - bld_base->emit_fetch_funcs[TGSI_FILE_SYSTEM_VALUE] = fetch_system_value; - - /* Allocate outputs */ - ctx->soa.outputs = ctx->outputs; - - lp_set_default_actions(bld_base); - - bld_base->op_actions[TGSI_OPCODE_ABS].emit = build_tgsi_intrinsic_nomem; - bld_base->op_actions[TGSI_OPCODE_ABS].intr_name = "llvm.fabs.f32"; - bld_base->op_actions[TGSI_OPCODE_AND].emit = emit_and; - bld_base->op_actions[TGSI_OPCODE_ARL].emit = emit_arl; - bld_base->op_actions[TGSI_OPCODE_BFI].emit = emit_bfi; - bld_base->op_actions[TGSI_OPCODE_BGNLOOP].emit = bgnloop_emit; - bld_base->op_actions[TGSI_OPCODE_BREV].emit = build_tgsi_intrinsic_nomem; - bld_base->op_actions[TGSI_OPCODE_BREV].intr_name = "llvm.AMDGPU.brev"; - bld_base->op_actions[TGSI_OPCODE_BRK].emit = brk_emit; - bld_base->op_actions[TGSI_OPCODE_CEIL].emit = build_tgsi_intrinsic_nomem; - bld_base->op_actions[TGSI_OPCODE_CEIL].intr_name = "llvm.ceil.f32"; - bld_base->op_actions[TGSI_OPCODE_CLAMP].emit = build_tgsi_intrinsic_nomem; - bld_base->op_actions[TGSI_OPCODE_CLAMP].intr_name = "llvm.AMDIL.clamp."; - bld_base->op_actions[TGSI_OPCODE_CMP].emit = build_tgsi_intrinsic_nomem; - bld_base->op_actions[TGSI_OPCODE_CMP].intr_name = "llvm.AMDGPU.cndlt"; - bld_base->op_actions[TGSI_OPCODE_CONT].emit = cont_emit; - bld_base->op_actions[TGSI_OPCODE_COS].emit = build_tgsi_intrinsic_nomem; - bld_base->op_actions[TGSI_OPCODE_COS].intr_name = "llvm.cos.f32"; - bld_base->op_actions[TGSI_OPCODE_DABS].emit = build_tgsi_intrinsic_nomem; - bld_base->op_actions[TGSI_OPCODE_DABS].intr_name = "llvm.fabs.f64"; - bld_base->op_actions[TGSI_OPCODE_DFMA].emit = build_tgsi_intrinsic_nomem; - bld_base->op_actions[TGSI_OPCODE_DFMA].intr_name = "llvm.fma.f64"; - bld_base->op_actions[TGSI_OPCODE_DFRAC].emit = emit_frac; - bld_base->op_actions[TGSI_OPCODE_DNEG].emit = emit_dneg; - bld_base->op_actions[TGSI_OPCODE_DSEQ].emit = emit_dcmp; - bld_base->op_actions[TGSI_OPCODE_DSGE].emit = emit_dcmp; - bld_base->op_actions[TGSI_OPCODE_DSLT].emit = emit_dcmp; - bld_base->op_actions[TGSI_OPCODE_DSNE].emit = emit_dcmp; - bld_base->op_actions[TGSI_OPCODE_DRSQ].emit = build_tgsi_intrinsic_nomem; - bld_base->op_actions[TGSI_OPCODE_DRSQ].intr_name = "llvm.AMDGPU.rsq.f64"; - bld_base->op_actions[TGSI_OPCODE_DSQRT].emit = build_tgsi_intrinsic_nomem; - bld_base->op_actions[TGSI_OPCODE_DSQRT].intr_name = "llvm.sqrt.f64"; - bld_base->op_actions[TGSI_OPCODE_ELSE].emit = else_emit; - bld_base->op_actions[TGSI_OPCODE_ENDIF].emit = endif_emit; - bld_base->op_actions[TGSI_OPCODE_ENDLOOP].emit = endloop_emit; - bld_base->op_actions[TGSI_OPCODE_EX2].emit = build_tgsi_intrinsic_nomem; - bld_base->op_actions[TGSI_OPCODE_EX2].intr_name = "llvm.AMDIL.exp."; - bld_base->op_actions[TGSI_OPCODE_FLR].emit = build_tgsi_intrinsic_nomem; - bld_base->op_actions[TGSI_OPCODE_FLR].intr_name = "llvm.floor.f32"; - bld_base->op_actions[TGSI_OPCODE_FMA].emit = build_tgsi_intrinsic_nomem; - bld_base->op_actions[TGSI_OPCODE_FMA].intr_name = "llvm.fma.f32"; - bld_base->op_actions[TGSI_OPCODE_FRC].emit = emit_frac; - bld_base->op_actions[TGSI_OPCODE_F2I].emit = emit_f2i; - bld_base->op_actions[TGSI_OPCODE_F2U].emit = emit_f2u; - bld_base->op_actions[TGSI_OPCODE_FSEQ].emit = emit_fcmp; - bld_base->op_actions[TGSI_OPCODE_FSGE].emit = emit_fcmp; - bld_base->op_actions[TGSI_OPCODE_FSLT].emit = emit_fcmp; - bld_base->op_actions[TGSI_OPCODE_FSNE].emit = emit_fcmp; - bld_base->op_actions[TGSI_OPCODE_IABS].emit = build_tgsi_intrinsic_nomem; - bld_base->op_actions[TGSI_OPCODE_IABS].intr_name = "llvm.AMDIL.abs."; - bld_base->op_actions[TGSI_OPCODE_IBFE].emit = build_tgsi_intrinsic_nomem; - bld_base->op_actions[TGSI_OPCODE_IBFE].intr_name = "llvm.AMDGPU.bfe.i32"; - bld_base->op_actions[TGSI_OPCODE_IDIV].emit = emit_idiv; - bld_base->op_actions[TGSI_OPCODE_IF].emit = if_emit; - bld_base->op_actions[TGSI_OPCODE_UIF].emit = uif_emit; - bld_base->op_actions[TGSI_OPCODE_IMAX].emit = build_tgsi_intrinsic_nomem; - bld_base->op_actions[TGSI_OPCODE_IMAX].intr_name = "llvm.AMDGPU.imax"; - bld_base->op_actions[TGSI_OPCODE_IMIN].emit = build_tgsi_intrinsic_nomem; - bld_base->op_actions[TGSI_OPCODE_IMIN].intr_name = "llvm.AMDGPU.imin"; - bld_base->op_actions[TGSI_OPCODE_IMSB].emit = emit_imsb; - bld_base->op_actions[TGSI_OPCODE_INEG].emit = emit_ineg; - bld_base->op_actions[TGSI_OPCODE_ISHR].emit = emit_ishr; - bld_base->op_actions[TGSI_OPCODE_ISGE].emit = emit_icmp; - bld_base->op_actions[TGSI_OPCODE_ISLT].emit = emit_icmp; - bld_base->op_actions[TGSI_OPCODE_ISSG].emit = emit_ssg; - bld_base->op_actions[TGSI_OPCODE_I2F].emit = emit_i2f; - bld_base->op_actions[TGSI_OPCODE_KILL_IF].fetch_args = kill_if_fetch_args; - bld_base->op_actions[TGSI_OPCODE_KILL_IF].emit = kil_emit; - bld_base->op_actions[TGSI_OPCODE_KILL_IF].intr_name = "llvm.AMDGPU.kill"; - bld_base->op_actions[TGSI_OPCODE_KILL].emit = lp_build_tgsi_intrinsic; - bld_base->op_actions[TGSI_OPCODE_KILL].intr_name = "llvm.AMDGPU.kilp"; - bld_base->op_actions[TGSI_OPCODE_LSB].emit = emit_lsb; - bld_base->op_actions[TGSI_OPCODE_LG2].emit = build_tgsi_intrinsic_nomem; - bld_base->op_actions[TGSI_OPCODE_LG2].intr_name = "llvm.log2.f32"; - bld_base->op_actions[TGSI_OPCODE_LRP].emit = build_tgsi_intrinsic_nomem; - bld_base->op_actions[TGSI_OPCODE_LRP].intr_name = "llvm.AMDGPU.lrp"; - bld_base->op_actions[TGSI_OPCODE_MOD].emit = emit_mod; - bld_base->op_actions[TGSI_OPCODE_UMSB].emit = emit_umsb; - bld_base->op_actions[TGSI_OPCODE_NOT].emit = emit_not; - bld_base->op_actions[TGSI_OPCODE_OR].emit = emit_or; - bld_base->op_actions[TGSI_OPCODE_POPC].emit = build_tgsi_intrinsic_nomem; - bld_base->op_actions[TGSI_OPCODE_POPC].intr_name = "llvm.ctpop.i32"; - bld_base->op_actions[TGSI_OPCODE_POW].emit = build_tgsi_intrinsic_nomem; - bld_base->op_actions[TGSI_OPCODE_POW].intr_name = "llvm.pow.f32"; - bld_base->op_actions[TGSI_OPCODE_ROUND].emit = build_tgsi_intrinsic_nomem; - bld_base->op_actions[TGSI_OPCODE_ROUND].intr_name = "llvm.AMDIL.round.nearest."; - bld_base->op_actions[TGSI_OPCODE_RSQ].intr_name = - HAVE_LLVM >= 0x0305 ? "llvm.AMDGPU.rsq.clamped.f32" : "llvm.AMDGPU.rsq"; - bld_base->op_actions[TGSI_OPCODE_RSQ].emit = build_tgsi_intrinsic_nomem; - bld_base->op_actions[TGSI_OPCODE_SGE].emit = emit_cmp; - bld_base->op_actions[TGSI_OPCODE_SEQ].emit = emit_cmp; - bld_base->op_actions[TGSI_OPCODE_SHL].emit = emit_shl; - bld_base->op_actions[TGSI_OPCODE_SLE].emit = emit_cmp; - bld_base->op_actions[TGSI_OPCODE_SLT].emit = emit_cmp; - bld_base->op_actions[TGSI_OPCODE_SNE].emit = emit_cmp; - bld_base->op_actions[TGSI_OPCODE_SGT].emit = emit_cmp; - bld_base->op_actions[TGSI_OPCODE_SIN].emit = build_tgsi_intrinsic_nomem; - bld_base->op_actions[TGSI_OPCODE_SIN].intr_name = "llvm.sin.f32"; - bld_base->op_actions[TGSI_OPCODE_SQRT].emit = build_tgsi_intrinsic_nomem; - bld_base->op_actions[TGSI_OPCODE_SQRT].intr_name = "llvm.sqrt.f32"; - bld_base->op_actions[TGSI_OPCODE_SSG].emit = emit_ssg; - bld_base->op_actions[TGSI_OPCODE_TRUNC].emit = build_tgsi_intrinsic_nomem; - bld_base->op_actions[TGSI_OPCODE_TRUNC].intr_name = "llvm.AMDGPU.trunc"; - bld_base->op_actions[TGSI_OPCODE_UADD].emit = emit_uadd; - bld_base->op_actions[TGSI_OPCODE_UBFE].emit = build_tgsi_intrinsic_nomem; - bld_base->op_actions[TGSI_OPCODE_UBFE].intr_name = "llvm.AMDGPU.bfe.u32"; - bld_base->op_actions[TGSI_OPCODE_UDIV].emit = emit_udiv; - bld_base->op_actions[TGSI_OPCODE_UMAX].emit = build_tgsi_intrinsic_nomem; - bld_base->op_actions[TGSI_OPCODE_UMAX].intr_name = "llvm.AMDGPU.umax"; - bld_base->op_actions[TGSI_OPCODE_UMIN].emit = build_tgsi_intrinsic_nomem; - bld_base->op_actions[TGSI_OPCODE_UMIN].intr_name = "llvm.AMDGPU.umin"; - bld_base->op_actions[TGSI_OPCODE_UMOD].emit = emit_umod; - bld_base->op_actions[TGSI_OPCODE_USEQ].emit = emit_icmp; - bld_base->op_actions[TGSI_OPCODE_USGE].emit = emit_icmp; - bld_base->op_actions[TGSI_OPCODE_USHR].emit = emit_ushr; - bld_base->op_actions[TGSI_OPCODE_USLT].emit = emit_icmp; - bld_base->op_actions[TGSI_OPCODE_USNE].emit = emit_icmp; - bld_base->op_actions[TGSI_OPCODE_U2F].emit = emit_u2f; - bld_base->op_actions[TGSI_OPCODE_XOR].emit = emit_xor; - bld_base->op_actions[TGSI_OPCODE_UCMP].emit = emit_ucmp; -} - -void radeon_llvm_create_func(struct radeon_llvm_context * ctx, - LLVMTypeRef *ParamTypes, unsigned ParamCount) -{ - LLVMTypeRef main_fn_type; - LLVMBasicBlockRef main_fn_body; - - /* Setup the function */ - main_fn_type = LLVMFunctionType(LLVMVoidTypeInContext(ctx->gallivm.context), - ParamTypes, ParamCount, 0); - ctx->main_fn = LLVMAddFunction(ctx->gallivm.module, "main", main_fn_type); - main_fn_body = LLVMAppendBasicBlockInContext(ctx->gallivm.context, - ctx->main_fn, "main_body"); - LLVMPositionBuilderAtEnd(ctx->gallivm.builder, main_fn_body); -} - -void radeon_llvm_finalize_module(struct radeon_llvm_context * ctx) -{ - struct gallivm_state * gallivm = ctx->soa.bld_base.base.gallivm; - /* End the main function with Return*/ - LLVMBuildRetVoid(gallivm->builder); - - /* Create the pass manager */ - ctx->gallivm.passmgr = LLVMCreateFunctionPassManagerForModule( - gallivm->module); - - /* This pass should eliminate all the load and store instructions */ - LLVMAddPromoteMemoryToRegisterPass(gallivm->passmgr); - - /* Add some optimization passes */ - LLVMAddScalarReplAggregatesPass(gallivm->passmgr); - LLVMAddLICMPass(gallivm->passmgr); - LLVMAddAggressiveDCEPass(gallivm->passmgr); - LLVMAddCFGSimplificationPass(gallivm->passmgr); - LLVMAddInstructionCombiningPass(gallivm->passmgr); - - /* Run the pass */ - LLVMRunFunctionPassManager(gallivm->passmgr, ctx->main_fn); - - LLVMDisposeBuilder(gallivm->builder); - LLVMDisposePassManager(gallivm->passmgr); - -} - -void radeon_llvm_dispose(struct radeon_llvm_context * ctx) -{ - LLVMDisposeModule(ctx->soa.bld_base.base.gallivm->module); - LLVMContextDispose(ctx->soa.bld_base.base.gallivm->context); - FREE(ctx->arrays); - ctx->arrays = NULL; - FREE(ctx->temps); - ctx->temps = NULL; - ctx->temps_count = 0; - FREE(ctx->loop); - ctx->loop = NULL; - ctx->loop_depth_max = 0; - FREE(ctx->branch); - ctx->branch = NULL; - ctx->branch_depth_max = 0; -} diff --git a/lib/mesa/src/gallium/drivers/radeonsi/Makefile.am b/lib/mesa/src/gallium/drivers/radeonsi/Makefile.am index aa79c5e01..f972f2041 100644 --- a/lib/mesa/src/gallium/drivers/radeonsi/Makefile.am +++ b/lib/mesa/src/gallium/drivers/radeonsi/Makefile.am @@ -25,9 +25,21 @@ include $(top_srcdir)/src/gallium/Automake.inc AM_CFLAGS = \ $(GALLIUM_DRIVER_CFLAGS) \ + -I$(top_srcdir)/src/amd/common \ $(RADEON_CFLAGS) \ $(LLVM_CFLAGS) noinst_LTLIBRARIES = libradeonsi.la -libradeonsi_la_SOURCES = $(C_SOURCES) +libradeonsi_la_SOURCES = $(C_SOURCES) $(GENERATED_SOURCES) + +if REGEN_SOURCES +sid_tables.h: $(srcdir)/sid_tables.py $(top_srcdir)/src/amd/common/sid.h + $(AM_V_GEN) $(PYTHON2) $(srcdir)/sid_tables.py $(top_srcdir)/src/amd/common/sid.h > $@ +endif + +EXTRA_DIST = \ + sid_tables.py + +BUILT_SOURCES =\ + sid_tables.h diff --git a/lib/mesa/src/gallium/drivers/radeonsi/Makefile.in b/lib/mesa/src/gallium/drivers/radeonsi/Makefile.in index 0d3571287..eca8bb83f 100644 --- a/lib/mesa/src/gallium/drivers/radeonsi/Makefile.in +++ b/lib/mesa/src/gallium/drivers/radeonsi/Makefile.in @@ -105,7 +105,8 @@ libradeonsi_la_LIBADD = am__objects_1 = cik_sdma.lo si_blit.lo si_compute.lo si_cp_dma.lo \ si_debug.lo si_descriptors.lo si_dma.lo si_hw_context.lo \ si_pipe.lo si_pm4.lo si_perfcounter.lo si_shader.lo \ - si_state.lo si_state_draw.lo si_state_shaders.lo si_uvd.lo + si_shader_tgsi_alu.lo si_shader_tgsi_setup.lo si_state.lo \ + si_state_draw.lo si_state_shaders.lo si_uvd.lo am__objects_2 = am_libradeonsi_la_OBJECTS = $(am__objects_1) $(am__objects_2) libradeonsi_la_OBJECTS = $(am_libradeonsi_la_OBJECTS) @@ -225,6 +226,8 @@ GLESv2_LIB_DEPS = @GLESv2_LIB_DEPS@ GLESv2_PC_LIB_PRIV = @GLESv2_PC_LIB_PRIV@ GLPROTO_CFLAGS = @GLPROTO_CFLAGS@ GLPROTO_LIBS = @GLPROTO_LIBS@ +GLVND_CFLAGS = @GLVND_CFLAGS@ +GLVND_LIBS = @GLVND_LIBS@ GLX_TLS = @GLX_TLS@ GL_LIB = @GL_LIB@ GL_LIB_DEPS = @GL_LIB_DEPS@ @@ -256,11 +259,10 @@ LIBELF_CFLAGS = @LIBELF_CFLAGS@ LIBELF_LIBS = @LIBELF_LIBS@ LIBOBJS = @LIBOBJS@ LIBS = @LIBS@ +LIBSENSORS_LDFLAGS = @LIBSENSORS_LDFLAGS@ LIBSHA1_CFLAGS = @LIBSHA1_CFLAGS@ LIBSHA1_LIBS = @LIBSHA1_LIBS@ LIBTOOL = @LIBTOOL@ -LIBUDEV_CFLAGS = @LIBUDEV_CFLAGS@ -LIBUDEV_LIBS = @LIBUDEV_LIBS@ LIB_DIR = @LIB_DIR@ LIB_EXT = @LIB_EXT@ LIPO = @LIPO@ @@ -323,6 +325,8 @@ PKG_CONFIG_PATH = @PKG_CONFIG_PATH@ POSIX_SHELL = @POSIX_SHELL@ PRESENTPROTO_CFLAGS = @PRESENTPROTO_CFLAGS@ PRESENTPROTO_LIBS = @PRESENTPROTO_LIBS@ +PTHREADSTUBS_CFLAGS = @PTHREADSTUBS_CFLAGS@ +PTHREADSTUBS_LIBS = @PTHREADSTUBS_LIBS@ PTHREAD_CC = @PTHREAD_CC@ PTHREAD_CFLAGS = @PTHREAD_CFLAGS@ PTHREAD_LIBS = @PTHREAD_LIBS@ @@ -343,11 +347,19 @@ SIMPENROSE_CFLAGS = @SIMPENROSE_CFLAGS@ SIMPENROSE_LIBS = @SIMPENROSE_LIBS@ SSE41_CFLAGS = @SSE41_CFLAGS@ STRIP = @STRIP@ +SWR_AVX2_CXXFLAGS = @SWR_AVX2_CXXFLAGS@ +SWR_AVX_CXXFLAGS = @SWR_AVX_CXXFLAGS@ +SWR_CXX11_CXXFLAGS = @SWR_CXX11_CXXFLAGS@ +TIMESTAMP_CMD = @TIMESTAMP_CMD@ +VALGRIND_CFLAGS = @VALGRIND_CFLAGS@ +VALGRIND_LIBS = @VALGRIND_LIBS@ VA_CFLAGS = @VA_CFLAGS@ VA_LIBS = @VA_LIBS@ VA_LIB_INSTALL_DIR = @VA_LIB_INSTALL_DIR@ VA_MAJOR = @VA_MAJOR@ VA_MINOR = @VA_MINOR@ +VC4_CFLAGS = @VC4_CFLAGS@ +VC4_LIBS = @VC4_LIBS@ VDPAU_CFLAGS = @VDPAU_CFLAGS@ VDPAU_LIBS = @VDPAU_LIBS@ VDPAU_LIB_INSTALL_DIR = @VDPAU_LIB_INSTALL_DIR@ @@ -359,6 +371,7 @@ VISIBILITY_CFLAGS = @VISIBILITY_CFLAGS@ VISIBILITY_CXXFLAGS = @VISIBILITY_CXXFLAGS@ VL_CFLAGS = @VL_CFLAGS@ VL_LIBS = @VL_LIBS@ +VULKAN_ICD_INSTALL_DIR = @VULKAN_ICD_INSTALL_DIR@ WAYLAND_CFLAGS = @WAYLAND_CFLAGS@ WAYLAND_LIBS = @WAYLAND_LIBS@ WAYLAND_SCANNER = @WAYLAND_SCANNER@ @@ -382,6 +395,7 @@ XVMC_LIBS = @XVMC_LIBS@ XVMC_LIB_INSTALL_DIR = @XVMC_LIB_INSTALL_DIR@ XVMC_MAJOR = @XVMC_MAJOR@ XVMC_MINOR = @XVMC_MINOR@ +XXD = @XXD@ YACC = @YACC@ YFLAGS = @YFLAGS@ abs_builddir = @abs_builddir@ @@ -451,7 +465,6 @@ C_SOURCES := \ si_cp_dma.c \ si_debug.c \ si_descriptors.c \ - sid.h \ si_dma.c \ si_hw_context.c \ si_pipe.c \ @@ -462,6 +475,9 @@ C_SOURCES := \ si_public.h \ si_shader.c \ si_shader.h \ + si_shader_internal.h \ + si_shader_tgsi_alu.c \ + si_shader_tgsi_setup.c \ si_state.c \ si_state_draw.c \ si_state_shaders.c \ @@ -538,6 +554,7 @@ GALLIUM_PIPE_LOADER_WINSYS_LIBS = \ $(am__append_1) $(am__append_2) AM_CFLAGS = \ $(GALLIUM_DRIVER_CFLAGS) \ + -I$(top_srcdir)/src/amd/common \ $(RADEON_CFLAGS) \ $(LLVM_CFLAGS) @@ -617,6 +634,8 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/si_pipe.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/si_pm4.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/si_shader.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/si_shader_tgsi_alu.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/si_shader_tgsi_setup.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/si_state.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/si_state_draw.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/si_state_shaders.Plo@am__quote@ @@ -873,8 +892,8 @@ uninstall-am: tags uninstall uninstall-am -sid_tables.h: $(srcdir)/sid_tables.py $(srcdir)/sid.h - $(AM_V_GEN) $(PYTHON2) $(srcdir)/sid_tables.py $(srcdir)/sid.h > $@ +@REGEN_SOURCES_TRUE@sid_tables.h: $(srcdir)/sid_tables.py $(top_srcdir)/src/amd/common/sid.h +@REGEN_SOURCES_TRUE@ $(AM_V_GEN) $(PYTHON2) $(srcdir)/sid_tables.py $(top_srcdir)/src/amd/common/sid.h > $@ # Tell versions [3.59,3.63) of GNU make to not export all variables. # Otherwise a system limit (for SysV at least) may be exceeded. diff --git a/lib/mesa/src/gallium/drivers/radeonsi/sid.h b/lib/mesa/src/gallium/drivers/radeonsi/sid.h deleted file mode 100644 index d1db7e245..000000000 --- a/lib/mesa/src/gallium/drivers/radeonsi/sid.h +++ /dev/null @@ -1,11111 +0,0 @@ -/* - * Southern Islands Register documentation - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef SID_H -#define SID_H - -/* si values */ -#define SI_CONFIG_REG_OFFSET 0x00008000 -#define SI_CONFIG_REG_END 0x0000B000 -#define SI_SH_REG_OFFSET 0x0000B000 -#define SI_SH_REG_END 0x0000C000 -#define SI_CONTEXT_REG_OFFSET 0x00028000 -#define SI_CONTEXT_REG_END 0x00029000 -#define CIK_UCONFIG_REG_OFFSET 0x00030000 -#define CIK_UCONFIG_REG_END 0x00031000 - -#define EVENT_TYPE_CACHE_FLUSH 0x6 -#define EVENT_TYPE_PS_PARTIAL_FLUSH 0x10 -#define EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT 0x14 -#define EVENT_TYPE_ZPASS_DONE 0x15 -#define EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT 0x16 -#define EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH 0x1f -#define EVENT_TYPE_SAMPLE_STREAMOUTSTATS 0x20 -#define EVENT_TYPE(x) ((x) << 0) -#define EVENT_INDEX(x) ((x) << 8) - /* 0 - any non-TS event - * 1 - ZPASS_DONE - * 2 - SAMPLE_PIPELINESTAT - * 3 - SAMPLE_STREAMOUTSTAT* - * 4 - *S_PARTIAL_FLUSH - * 5 - TS events - */ -#define EVENT_WRITE_INV_L2 0x100000 - - -#define PREDICATION_OP_CLEAR 0x0 -#define PREDICATION_OP_ZPASS 0x1 -#define PREDICATION_OP_PRIMCOUNT 0x2 - -#define PRED_OP(x) ((x) << 16) - -#define PREDICATION_CONTINUE (1 << 31) - -#define PREDICATION_HINT_WAIT (0 << 12) -#define PREDICATION_HINT_NOWAIT_DRAW (1 << 12) - -#define PREDICATION_DRAW_NOT_VISIBLE (0 << 8) -#define PREDICATION_DRAW_VISIBLE (1 << 8) - -#define R600_TEXEL_PITCH_ALIGNMENT_MASK 0x7 - -#define PKT3_NOP 0x10 -#define PKT3_SET_BASE 0x11 -#define PKT3_CLEAR_STATE 0x12 -#define PKT3_INDEX_BUFFER_SIZE 0x13 -#define PKT3_DISPATCH_DIRECT 0x15 -#define PKT3_DISPATCH_INDIRECT 0x16 -#define PKT3_OCCLUSION_QUERY 0x1F /* new for CIK */ -#define PKT3_SET_PREDICATION 0x20 -#define PKT3_COND_EXEC 0x22 -#define PKT3_PRED_EXEC 0x23 -#define PKT3_DRAW_INDIRECT 0x24 -#define PKT3_DRAW_INDEX_INDIRECT 0x25 -#define PKT3_INDEX_BASE 0x26 -#define PKT3_DRAW_INDEX_2 0x27 -#define PKT3_CONTEXT_CONTROL 0x28 -#define PKT3_INDEX_TYPE 0x2A -#define PKT3_DRAW_INDIRECT_MULTI 0x2C -#define PKT3_DRAW_INDEX_AUTO 0x2D -#define PKT3_DRAW_INDEX_IMMD 0x2E /* not on CIK */ -#define PKT3_NUM_INSTANCES 0x2F -#define PKT3_DRAW_INDEX_MULTI_AUTO 0x30 -#define PKT3_INDIRECT_BUFFER 0x32 -#define PKT3_STRMOUT_BUFFER_UPDATE 0x34 -#define PKT3_DRAW_INDEX_OFFSET_2 0x35 -#define PKT3_DRAW_PREAMBLE 0x36 /* new on CIK, required on GFX7.2 and later */ -#define PKT3_WRITE_DATA 0x37 -#define PKT3_WRITE_DATA_DST_SEL(x) ((x) << 8) -#define PKT3_WRITE_DATA_DST_SEL_REG 0 -#define PKT3_WRITE_DATA_DST_SEL_MEM_SYNC 1 -#define PKT3_WRITE_DATA_DST_SEL_TC_L2 2 -#define PKT3_WRITE_DATA_DST_SEL_GDS 3 -#define PKT3_WRITE_DATA_DST_SEL_RESERVED_4 4 -#define PKT3_WRITE_DATA_DST_SEL_MEM_ASYNC 5 -#define PKT3_WR_ONE_ADDR (1 << 16) -#define PKT3_WRITE_DATA_WR_CONFIRM (1 << 20) -#define PKT3_WRITE_DATA_ENGINE_SEL(x) ((x) << 30) -#define PKT3_WRITE_DATA_ENGINE_SEL_ME 0 -#define PKT3_WRITE_DATA_ENGINE_SEL_PFP 1 -#define PKT3_WRITE_DATA_ENGINE_SEL_CE 2 -#define PKT3_DRAW_INDEX_INDIRECT_MULTI 0x38 -#define PKT3_MEM_SEMAPHORE 0x39 -#define PKT3_MPEG_INDEX 0x3A /* not on CIK */ -#define PKT3_WAIT_REG_MEM 0x3C -#define WAIT_REG_MEM_EQUAL 3 -#define PKT3_MEM_WRITE 0x3D /* not on CIK */ -#define PKT3_COPY_DATA 0x40 -#define COPY_DATA_SRC_SEL(x) ((x) & 0xf) -#define COPY_DATA_REG 0 -#define COPY_DATA_MEM 1 -#define COPY_DATA_DST_SEL(x) (((x) & 0xf) << 8) -#define COPY_DATA_WR_CONFIRM (1 << 20) -#define PKT3_SURFACE_SYNC 0x43 /* deprecated on CIK, use ACQUIRE_MEM */ -#define PKT3_ME_INITIALIZE 0x44 /* not on CIK */ -#define PKT3_COND_WRITE 0x45 -#define PKT3_EVENT_WRITE 0x46 -#define PKT3_EVENT_WRITE_EOP 0x47 -#define PKT3_EVENT_WRITE_EOS 0x48 -#define PKT3_ONE_REG_WRITE 0x57 /* not on CIK */ -#define PKT3_ACQUIRE_MEM 0x58 /* new for CIK */ -#define PKT3_SET_CONFIG_REG 0x68 -#define PKT3_SET_CONTEXT_REG 0x69 -#define PKT3_SET_SH_REG 0x76 -#define PKT3_SET_SH_REG_OFFSET 0x77 -#define PKT3_SET_UCONFIG_REG 0x79 /* new for CIK */ - -#define PKT_TYPE_S(x) (((x) & 0x3) << 30) -#define PKT_TYPE_G(x) (((x) >> 30) & 0x3) -#define PKT_TYPE_C 0x3FFFFFFF -#define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16) -#define PKT_COUNT_G(x) (((x) >> 16) & 0x3FFF) -#define PKT_COUNT_C 0xC000FFFF -#define PKT0_BASE_INDEX_S(x) (((x) & 0xFFFF) << 0) -#define PKT0_BASE_INDEX_G(x) (((x) >> 0) & 0xFFFF) -#define PKT0_BASE_INDEX_C 0xFFFF0000 -#define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8) -#define PKT3_IT_OPCODE_G(x) (((x) >> 8) & 0xFF) -#define PKT3_IT_OPCODE_C 0xFFFF00FF -#define PKT3_PREDICATE(x) (((x) >> 0) & 0x1) -#define PKT3_SHADER_TYPE_S(x) (((x) & 0x1) << 1) -#define PKT0(index, count) (PKT_TYPE_S(0) | PKT0_BASE_INDEX_S(index) | PKT_COUNT_S(count)) -#define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate)) - -#define PKT3_CP_DMA 0x41 -/* 1. header - * 2. SRC_ADDR_LO [31:0] or DATA [31:0] - * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] | SRC_ADDR_HI [15:0] - * 4. DST_ADDR_LO [31:0] - * 5. DST_ADDR_HI [15:0] - * 6. COMMAND [29:22] | BYTE_COUNT [20:0] - */ -#define PKT3_CP_DMA_CP_SYNC (1 << 31) -#define PKT3_CP_DMA_SRC_SEL(x) ((x) << 29) -/* 0 - SRC_ADDR - * 1 - GDS (program SAS to 1 as well) - * 2 - DATA - * 3 - SRC_ADDR using TC L2 (DMA_DATA only) - */ -#define PKT3_CP_DMA_DST_SEL(x) ((x) << 20) -/* 0 - DST_ADDR - * 1 - GDS (program DAS to 1 as well) - * 3 - DST_ADDR using TC L2 (DMA_DATA only) - */ -/* COMMAND */ -#define PKT3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23) -/* 0 - none - * 1 - 8 in 16 - * 2 - 8 in 32 - * 3 - 8 in 64 - */ -#define PKT3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) -/* 0 - none - * 1 - 8 in 16 - * 2 - 8 in 32 - * 3 - 8 in 64 - */ -#define PKT3_CP_DMA_CMD_SAS (1 << 26) -/* 0 - memory - * 1 - register - */ -#define PKT3_CP_DMA_CMD_DAS (1 << 27) -/* 0 - memory - * 1 - register - */ -#define PKT3_CP_DMA_CMD_SAIC (1 << 28) -#define PKT3_CP_DMA_CMD_DAIC (1 << 29) -#define PKT3_CP_DMA_CMD_RAW_WAIT (1 << 30) - -#define PKT3_DMA_DATA 0x50 /* new for CIK */ -/* 1. header - * 2. CP_SYNC [31] | SRC_SEL [30:29] | DST_SEL [21:20] | ENGINE [0] - * 2. SRC_ADDR_LO [31:0] or DATA [31:0] - * 3. SRC_ADDR_HI [31:0] - * 4. DST_ADDR_LO [31:0] - * 5. DST_ADDR_HI [31:0] - * 6. COMMAND [29:22] | BYTE_COUNT [20:0] - */ - - -#define R_000E4C_SRBM_STATUS2 0x000E4C -#define S_000E4C_SDMA_RQ_PENDING(x) (((x) & 0x1) << 0) -#define G_000E4C_SDMA_RQ_PENDING(x) (((x) >> 0) & 0x1) -#define C_000E4C_SDMA_RQ_PENDING 0xFFFFFFFE -#define S_000E4C_TST_RQ_PENDING(x) (((x) & 0x1) << 1) -#define G_000E4C_TST_RQ_PENDING(x) (((x) >> 1) & 0x1) -#define C_000E4C_TST_RQ_PENDING 0xFFFFFFFD -#define S_000E4C_SDMA1_RQ_PENDING(x) (((x) & 0x1) << 2) -#define G_000E4C_SDMA1_RQ_PENDING(x) (((x) >> 2) & 0x1) -#define C_000E4C_SDMA1_RQ_PENDING 0xFFFFFFFB -#define S_000E4C_VCE0_RQ_PENDING(x) (((x) & 0x1) << 3) -#define G_000E4C_VCE0_RQ_PENDING(x) (((x) >> 3) & 0x1) -#define C_000E4C_VCE0_RQ_PENDING 0xFFFFFFF7 -#define S_000E4C_VP8_BUSY(x) (((x) & 0x1) << 4) -#define G_000E4C_VP8_BUSY(x) (((x) >> 4) & 0x1) -#define C_000E4C_VP8_BUSY 0xFFFFFFEF -#define S_000E4C_SDMA_BUSY(x) (((x) & 0x1) << 5) -#define G_000E4C_SDMA_BUSY(x) (((x) >> 5) & 0x1) -#define C_000E4C_SDMA_BUSY 0xFFFFFFDF -#define S_000E4C_SDMA1_BUSY(x) (((x) & 0x1) << 6) -#define G_000E4C_SDMA1_BUSY(x) (((x) >> 6) & 0x1) -#define C_000E4C_SDMA1_BUSY 0xFFFFFFBF -#define S_000E4C_VCE0_BUSY(x) (((x) & 0x1) << 7) -#define G_000E4C_VCE0_BUSY(x) (((x) >> 7) & 0x1) -#define C_000E4C_VCE0_BUSY 0xFFFFFF7F -#define S_000E4C_XDMA_BUSY(x) (((x) & 0x1) << 8) -#define G_000E4C_XDMA_BUSY(x) (((x) >> 8) & 0x1) -#define C_000E4C_XDMA_BUSY 0xFFFFFEFF -#define S_000E4C_CHUB_BUSY(x) (((x) & 0x1) << 9) -#define G_000E4C_CHUB_BUSY(x) (((x) >> 9) & 0x1) -#define C_000E4C_CHUB_BUSY 0xFFFFFDFF -#define S_000E4C_SDMA2_BUSY(x) (((x) & 0x1) << 10) -#define G_000E4C_SDMA2_BUSY(x) (((x) >> 10) & 0x1) -#define C_000E4C_SDMA2_BUSY 0xFFFFFBFF -#define S_000E4C_SDMA3_BUSY(x) (((x) & 0x1) << 11) -#define G_000E4C_SDMA3_BUSY(x) (((x) >> 11) & 0x1) -#define C_000E4C_SDMA3_BUSY 0xFFFFF7FF -#define S_000E4C_SAMSCP_BUSY(x) (((x) & 0x1) << 12) -#define G_000E4C_SAMSCP_BUSY(x) (((x) >> 12) & 0x1) -#define C_000E4C_SAMSCP_BUSY 0xFFFFEFFF -#define S_000E4C_ISP_BUSY(x) (((x) & 0x1) << 13) -#define G_000E4C_ISP_BUSY(x) (((x) >> 13) & 0x1) -#define C_000E4C_ISP_BUSY 0xFFFFDFFF -#define S_000E4C_VCE1_BUSY(x) (((x) & 0x1) << 14) -#define G_000E4C_VCE1_BUSY(x) (((x) >> 14) & 0x1) -#define C_000E4C_VCE1_BUSY 0xFFFFBFFF -#define S_000E4C_ODE_BUSY(x) (((x) & 0x1) << 15) -#define G_000E4C_ODE_BUSY(x) (((x) >> 15) & 0x1) -#define C_000E4C_ODE_BUSY 0xFFFF7FFF -#define S_000E4C_SDMA2_RQ_PENDING(x) (((x) & 0x1) << 16) -#define G_000E4C_SDMA2_RQ_PENDING(x) (((x) >> 16) & 0x1) -#define C_000E4C_SDMA2_RQ_PENDING 0xFFFEFFFF -#define S_000E4C_SDMA3_RQ_PENDING(x) (((x) & 0x1) << 17) -#define G_000E4C_SDMA3_RQ_PENDING(x) (((x) >> 17) & 0x1) -#define C_000E4C_SDMA3_RQ_PENDING 0xFFFDFFFF -#define S_000E4C_SAMSCP_RQ_PENDING(x) (((x) & 0x1) << 18) -#define G_000E4C_SAMSCP_RQ_PENDING(x) (((x) >> 18) & 0x1) -#define C_000E4C_SAMSCP_RQ_PENDING 0xFFFBFFFF -#define S_000E4C_ISP_RQ_PENDING(x) (((x) & 0x1) << 19) -#define G_000E4C_ISP_RQ_PENDING(x) (((x) >> 19) & 0x1) -#define C_000E4C_ISP_RQ_PENDING 0xFFF7FFFF -#define S_000E4C_VCE1_RQ_PENDING(x) (((x) & 0x1) << 20) -#define G_000E4C_VCE1_RQ_PENDING(x) (((x) >> 20) & 0x1) -#define C_000E4C_VCE1_RQ_PENDING 0xFFEFFFFF -#define R_000E50_SRBM_STATUS 0x000E50 -#define S_000E50_UVD_RQ_PENDING(x) (((x) & 0x1) << 1) -#define G_000E50_UVD_RQ_PENDING(x) (((x) >> 1) & 0x1) -#define C_000E50_UVD_RQ_PENDING 0xFFFFFFFD -#define S_000E50_SAMMSP_RQ_PENDING(x) (((x) & 0x1) << 2) -#define G_000E50_SAMMSP_RQ_PENDING(x) (((x) >> 2) & 0x1) -#define C_000E50_SAMMSP_RQ_PENDING 0xFFFFFFFB -#define S_000E50_ACP_RQ_PENDING(x) (((x) & 0x1) << 3) -#define G_000E50_ACP_RQ_PENDING(x) (((x) >> 3) & 0x1) -#define C_000E50_ACP_RQ_PENDING 0xFFFFFFF7 -#define S_000E50_SMU_RQ_PENDING(x) (((x) & 0x1) << 4) -#define G_000E50_SMU_RQ_PENDING(x) (((x) >> 4) & 0x1) -#define C_000E50_SMU_RQ_PENDING 0xFFFFFFEF -#define S_000E50_GRBM_RQ_PENDING(x) (((x) & 0x1) << 5) -#define G_000E50_GRBM_RQ_PENDING(x) (((x) >> 5) & 0x1) -#define C_000E50_GRBM_RQ_PENDING 0xFFFFFFDF -#define S_000E50_HI_RQ_PENDING(x) (((x) & 0x1) << 6) -#define G_000E50_HI_RQ_PENDING(x) (((x) >> 6) & 0x1) -#define C_000E50_HI_RQ_PENDING 0xFFFFFFBF -#define S_000E50_VMC_BUSY(x) (((x) & 0x1) << 8) -#define G_000E50_VMC_BUSY(x) (((x) >> 8) & 0x1) -#define C_000E50_VMC_BUSY 0xFFFFFEFF -#define S_000E50_MCB_BUSY(x) (((x) & 0x1) << 9) -#define G_000E50_MCB_BUSY(x) (((x) >> 9) & 0x1) -#define C_000E50_MCB_BUSY 0xFFFFFDFF -#define S_000E50_MCB_NON_DISPLAY_BUSY(x) (((x) & 0x1) << 10) -#define G_000E50_MCB_NON_DISPLAY_BUSY(x) (((x) >> 10) & 0x1) -#define C_000E50_MCB_NON_DISPLAY_BUSY 0xFFFFFBFF -#define S_000E50_MCC_BUSY(x) (((x) & 0x1) << 11) -#define G_000E50_MCC_BUSY(x) (((x) >> 11) & 0x1) -#define C_000E50_MCC_BUSY 0xFFFFF7FF -#define S_000E50_MCD_BUSY(x) (((x) & 0x1) << 12) -#define G_000E50_MCD_BUSY(x) (((x) >> 12) & 0x1) -#define C_000E50_MCD_BUSY 0xFFFFEFFF -#define S_000E50_VMC1_BUSY(x) (((x) & 0x1) << 13) -#define G_000E50_VMC1_BUSY(x) (((x) >> 13) & 0x1) -#define C_000E50_VMC1_BUSY 0xFFFFDFFF -#define S_000E50_SEM_BUSY(x) (((x) & 0x1) << 14) -#define G_000E50_SEM_BUSY(x) (((x) >> 14) & 0x1) -#define C_000E50_SEM_BUSY 0xFFFFBFFF -#define S_000E50_ACP_BUSY(x) (((x) & 0x1) << 16) -#define G_000E50_ACP_BUSY(x) (((x) >> 16) & 0x1) -#define C_000E50_ACP_BUSY 0xFFFEFFFF -#define S_000E50_IH_BUSY(x) (((x) & 0x1) << 17) -#define G_000E50_IH_BUSY(x) (((x) >> 17) & 0x1) -#define C_000E50_IH_BUSY 0xFFFDFFFF -#define S_000E50_UVD_BUSY(x) (((x) & 0x1) << 19) -#define G_000E50_UVD_BUSY(x) (((x) >> 19) & 0x1) -#define C_000E50_UVD_BUSY 0xFFF7FFFF -#define S_000E50_SAMMSP_BUSY(x) (((x) & 0x1) << 20) -#define G_000E50_SAMMSP_BUSY(x) (((x) >> 20) & 0x1) -#define C_000E50_SAMMSP_BUSY 0xFFEFFFFF -#define S_000E50_GCATCL2_BUSY(x) (((x) & 0x1) << 21) -#define G_000E50_GCATCL2_BUSY(x) (((x) >> 21) & 0x1) -#define C_000E50_GCATCL2_BUSY 0xFFDFFFFF -#define S_000E50_OSATCL2_BUSY(x) (((x) & 0x1) << 22) -#define G_000E50_OSATCL2_BUSY(x) (((x) >> 22) & 0x1) -#define C_000E50_OSATCL2_BUSY 0xFFBFFFFF -#define S_000E50_BIF_BUSY(x) (((x) & 0x1) << 29) -#define G_000E50_BIF_BUSY(x) (((x) >> 29) & 0x1) -#define C_000E50_BIF_BUSY 0xDFFFFFFF -#define R_000E54_SRBM_STATUS3 0x000E54 -#define S_000E54_MCC0_BUSY(x) (((x) & 0x1) << 0) -#define G_000E54_MCC0_BUSY(x) (((x) >> 0) & 0x1) -#define C_000E54_MCC0_BUSY 0xFFFFFFFE -#define S_000E54_MCC1_BUSY(x) (((x) & 0x1) << 1) -#define G_000E54_MCC1_BUSY(x) (((x) >> 1) & 0x1) -#define C_000E54_MCC1_BUSY 0xFFFFFFFD -#define S_000E54_MCC2_BUSY(x) (((x) & 0x1) << 2) -#define G_000E54_MCC2_BUSY(x) (((x) >> 2) & 0x1) -#define C_000E54_MCC2_BUSY 0xFFFFFFFB -#define S_000E54_MCC3_BUSY(x) (((x) & 0x1) << 3) -#define G_000E54_MCC3_BUSY(x) (((x) >> 3) & 0x1) -#define C_000E54_MCC3_BUSY 0xFFFFFFF7 -#define S_000E54_MCC4_BUSY(x) (((x) & 0x1) << 4) -#define G_000E54_MCC4_BUSY(x) (((x) >> 4) & 0x1) -#define C_000E54_MCC4_BUSY 0xFFFFFFEF -#define S_000E54_MCC5_BUSY(x) (((x) & 0x1) << 5) -#define G_000E54_MCC5_BUSY(x) (((x) >> 5) & 0x1) -#define C_000E54_MCC5_BUSY 0xFFFFFFDF -#define S_000E54_MCC6_BUSY(x) (((x) & 0x1) << 6) -#define G_000E54_MCC6_BUSY(x) (((x) >> 6) & 0x1) -#define C_000E54_MCC6_BUSY 0xFFFFFFBF -#define S_000E54_MCC7_BUSY(x) (((x) & 0x1) << 7) -#define G_000E54_MCC7_BUSY(x) (((x) >> 7) & 0x1) -#define C_000E54_MCC7_BUSY 0xFFFFFF7F -#define S_000E54_MCD0_BUSY(x) (((x) & 0x1) << 8) -#define G_000E54_MCD0_BUSY(x) (((x) >> 8) & 0x1) -#define C_000E54_MCD0_BUSY 0xFFFFFEFF -#define S_000E54_MCD1_BUSY(x) (((x) & 0x1) << 9) -#define G_000E54_MCD1_BUSY(x) (((x) >> 9) & 0x1) -#define C_000E54_MCD1_BUSY 0xFFFFFDFF -#define S_000E54_MCD2_BUSY(x) (((x) & 0x1) << 10) -#define G_000E54_MCD2_BUSY(x) (((x) >> 10) & 0x1) -#define C_000E54_MCD2_BUSY 0xFFFFFBFF -#define S_000E54_MCD3_BUSY(x) (((x) & 0x1) << 11) -#define G_000E54_MCD3_BUSY(x) (((x) >> 11) & 0x1) -#define C_000E54_MCD3_BUSY 0xFFFFF7FF -#define S_000E54_MCD4_BUSY(x) (((x) & 0x1) << 12) -#define G_000E54_MCD4_BUSY(x) (((x) >> 12) & 0x1) -#define C_000E54_MCD4_BUSY 0xFFFFEFFF -#define S_000E54_MCD5_BUSY(x) (((x) & 0x1) << 13) -#define G_000E54_MCD5_BUSY(x) (((x) >> 13) & 0x1) -#define C_000E54_MCD5_BUSY 0xFFFFDFFF -#define S_000E54_MCD6_BUSY(x) (((x) & 0x1) << 14) -#define G_000E54_MCD6_BUSY(x) (((x) >> 14) & 0x1) -#define C_000E54_MCD6_BUSY 0xFFFFBFFF -#define S_000E54_MCD7_BUSY(x) (((x) & 0x1) << 15) -#define G_000E54_MCD7_BUSY(x) (((x) >> 15) & 0x1) -#define C_000E54_MCD7_BUSY 0xFFFF7FFF -#define R_00D034_SDMA0_STATUS_REG 0x00D034 -#define S_00D034_IDLE(x) (((x) & 0x1) << 0) -#define G_00D034_IDLE(x) (((x) >> 0) & 0x1) -#define C_00D034_IDLE 0xFFFFFFFE -#define S_00D034_REG_IDLE(x) (((x) & 0x1) << 1) -#define G_00D034_REG_IDLE(x) (((x) >> 1) & 0x1) -#define C_00D034_REG_IDLE 0xFFFFFFFD -#define S_00D034_RB_EMPTY(x) (((x) & 0x1) << 2) -#define G_00D034_RB_EMPTY(x) (((x) >> 2) & 0x1) -#define C_00D034_RB_EMPTY 0xFFFFFFFB -#define S_00D034_RB_FULL(x) (((x) & 0x1) << 3) -#define G_00D034_RB_FULL(x) (((x) >> 3) & 0x1) -#define C_00D034_RB_FULL 0xFFFFFFF7 -#define S_00D034_RB_CMD_IDLE(x) (((x) & 0x1) << 4) -#define G_00D034_RB_CMD_IDLE(x) (((x) >> 4) & 0x1) -#define C_00D034_RB_CMD_IDLE 0xFFFFFFEF -#define S_00D034_RB_CMD_FULL(x) (((x) & 0x1) << 5) -#define G_00D034_RB_CMD_FULL(x) (((x) >> 5) & 0x1) -#define C_00D034_RB_CMD_FULL 0xFFFFFFDF -#define S_00D034_IB_CMD_IDLE(x) (((x) & 0x1) << 6) -#define G_00D034_IB_CMD_IDLE(x) (((x) >> 6) & 0x1) -#define C_00D034_IB_CMD_IDLE 0xFFFFFFBF -#define S_00D034_IB_CMD_FULL(x) (((x) & 0x1) << 7) -#define G_00D034_IB_CMD_FULL(x) (((x) >> 7) & 0x1) -#define C_00D034_IB_CMD_FULL 0xFFFFFF7F -#define S_00D034_BLOCK_IDLE(x) (((x) & 0x1) << 8) -#define G_00D034_BLOCK_IDLE(x) (((x) >> 8) & 0x1) -#define C_00D034_BLOCK_IDLE 0xFFFFFEFF -#define S_00D034_INSIDE_IB(x) (((x) & 0x1) << 9) -#define G_00D034_INSIDE_IB(x) (((x) >> 9) & 0x1) -#define C_00D034_INSIDE_IB 0xFFFFFDFF -#define S_00D034_EX_IDLE(x) (((x) & 0x1) << 10) -#define G_00D034_EX_IDLE(x) (((x) >> 10) & 0x1) -#define C_00D034_EX_IDLE 0xFFFFFBFF -#define S_00D034_EX_IDLE_POLL_TIMER_EXPIRE(x) (((x) & 0x1) << 11) -#define G_00D034_EX_IDLE_POLL_TIMER_EXPIRE(x) (((x) >> 11) & 0x1) -#define C_00D034_EX_IDLE_POLL_TIMER_EXPIRE 0xFFFFF7FF -#define S_00D034_PACKET_READY(x) (((x) & 0x1) << 12) -#define G_00D034_PACKET_READY(x) (((x) >> 12) & 0x1) -#define C_00D034_PACKET_READY 0xFFFFEFFF -#define S_00D034_MC_WR_IDLE(x) (((x) & 0x1) << 13) -#define G_00D034_MC_WR_IDLE(x) (((x) >> 13) & 0x1) -#define C_00D034_MC_WR_IDLE 0xFFFFDFFF -#define S_00D034_SRBM_IDLE(x) (((x) & 0x1) << 14) -#define G_00D034_SRBM_IDLE(x) (((x) >> 14) & 0x1) -#define C_00D034_SRBM_IDLE 0xFFFFBFFF -#define S_00D034_CONTEXT_EMPTY(x) (((x) & 0x1) << 15) -#define G_00D034_CONTEXT_EMPTY(x) (((x) >> 15) & 0x1) -#define C_00D034_CONTEXT_EMPTY 0xFFFF7FFF -#define S_00D034_DELTA_RPTR_FULL(x) (((x) & 0x1) << 16) -#define G_00D034_DELTA_RPTR_FULL(x) (((x) >> 16) & 0x1) -#define C_00D034_DELTA_RPTR_FULL 0xFFFEFFFF -#define S_00D034_RB_MC_RREQ_IDLE(x) (((x) & 0x1) << 17) -#define G_00D034_RB_MC_RREQ_IDLE(x) (((x) >> 17) & 0x1) -#define C_00D034_RB_MC_RREQ_IDLE 0xFFFDFFFF -#define S_00D034_IB_MC_RREQ_IDLE(x) (((x) & 0x1) << 18) -#define G_00D034_IB_MC_RREQ_IDLE(x) (((x) >> 18) & 0x1) -#define C_00D034_IB_MC_RREQ_IDLE 0xFFFBFFFF -#define S_00D034_MC_RD_IDLE(x) (((x) & 0x1) << 19) -#define G_00D034_MC_RD_IDLE(x) (((x) >> 19) & 0x1) -#define C_00D034_MC_RD_IDLE 0xFFF7FFFF -#define S_00D034_DELTA_RPTR_EMPTY(x) (((x) & 0x1) << 20) -#define G_00D034_DELTA_RPTR_EMPTY(x) (((x) >> 20) & 0x1) -#define C_00D034_DELTA_RPTR_EMPTY 0xFFEFFFFF -#define S_00D034_MC_RD_RET_STALL(x) (((x) & 0x1) << 21) -#define G_00D034_MC_RD_RET_STALL(x) (((x) >> 21) & 0x1) -#define C_00D034_MC_RD_RET_STALL 0xFFDFFFFF -#define S_00D034_MC_RD_NO_POLL_IDLE(x) (((x) & 0x1) << 22) -#define G_00D034_MC_RD_NO_POLL_IDLE(x) (((x) >> 22) & 0x1) -#define C_00D034_MC_RD_NO_POLL_IDLE 0xFFBFFFFF -#define S_00D034_PREV_CMD_IDLE(x) (((x) & 0x1) << 25) -#define G_00D034_PREV_CMD_IDLE(x) (((x) >> 25) & 0x1) -#define C_00D034_PREV_CMD_IDLE 0xFDFFFFFF -#define S_00D034_SEM_IDLE(x) (((x) & 0x1) << 26) -#define G_00D034_SEM_IDLE(x) (((x) >> 26) & 0x1) -#define C_00D034_SEM_IDLE 0xFBFFFFFF -#define S_00D034_SEM_REQ_STALL(x) (((x) & 0x1) << 27) -#define G_00D034_SEM_REQ_STALL(x) (((x) >> 27) & 0x1) -#define C_00D034_SEM_REQ_STALL 0xF7FFFFFF -#define S_00D034_SEM_RESP_STATE(x) (((x) & 0x03) << 28) -#define G_00D034_SEM_RESP_STATE(x) (((x) >> 28) & 0x03) -#define C_00D034_SEM_RESP_STATE 0xCFFFFFFF -#define S_00D034_INT_IDLE(x) (((x) & 0x1) << 30) -#define G_00D034_INT_IDLE(x) (((x) >> 30) & 0x1) -#define C_00D034_INT_IDLE 0xBFFFFFFF -#define S_00D034_INT_REQ_STALL(x) (((x) & 0x1) << 31) -#define G_00D034_INT_REQ_STALL(x) (((x) >> 31) & 0x1) -#define C_00D034_INT_REQ_STALL 0x7FFFFFFF -#define R_00D834_SDMA1_STATUS_REG 0x00D834 -#define R_008008_GRBM_STATUS2 0x008008 -#define S_008008_ME0PIPE1_CMDFIFO_AVAIL(x) (((x) & 0x0F) << 0) -#define G_008008_ME0PIPE1_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x0F) -#define C_008008_ME0PIPE1_CMDFIFO_AVAIL 0xFFFFFFF0 -#define S_008008_ME0PIPE1_CF_RQ_PENDING(x) (((x) & 0x1) << 4) -#define G_008008_ME0PIPE1_CF_RQ_PENDING(x) (((x) >> 4) & 0x1) -#define C_008008_ME0PIPE1_CF_RQ_PENDING 0xFFFFFFEF -#define S_008008_ME0PIPE1_PF_RQ_PENDING(x) (((x) & 0x1) << 5) -#define G_008008_ME0PIPE1_PF_RQ_PENDING(x) (((x) >> 5) & 0x1) -#define C_008008_ME0PIPE1_PF_RQ_PENDING 0xFFFFFFDF -#define S_008008_ME1PIPE0_RQ_PENDING(x) (((x) & 0x1) << 6) -#define G_008008_ME1PIPE0_RQ_PENDING(x) (((x) >> 6) & 0x1) -#define C_008008_ME1PIPE0_RQ_PENDING 0xFFFFFFBF -#define S_008008_ME1PIPE1_RQ_PENDING(x) (((x) & 0x1) << 7) -#define G_008008_ME1PIPE1_RQ_PENDING(x) (((x) >> 7) & 0x1) -#define C_008008_ME1PIPE1_RQ_PENDING 0xFFFFFF7F -#define S_008008_ME1PIPE2_RQ_PENDING(x) (((x) & 0x1) << 8) -#define G_008008_ME1PIPE2_RQ_PENDING(x) (((x) >> 8) & 0x1) -#define C_008008_ME1PIPE2_RQ_PENDING 0xFFFFFEFF -#define S_008008_ME1PIPE3_RQ_PENDING(x) (((x) & 0x1) << 9) -#define G_008008_ME1PIPE3_RQ_PENDING(x) (((x) >> 9) & 0x1) -#define C_008008_ME1PIPE3_RQ_PENDING 0xFFFFFDFF -#define S_008008_ME2PIPE0_RQ_PENDING(x) (((x) & 0x1) << 10) -#define G_008008_ME2PIPE0_RQ_PENDING(x) (((x) >> 10) & 0x1) -#define C_008008_ME2PIPE0_RQ_PENDING 0xFFFFFBFF -#define S_008008_ME2PIPE1_RQ_PENDING(x) (((x) & 0x1) << 11) -#define G_008008_ME2PIPE1_RQ_PENDING(x) (((x) >> 11) & 0x1) -#define C_008008_ME2PIPE1_RQ_PENDING 0xFFFFF7FF -#define S_008008_ME2PIPE2_RQ_PENDING(x) (((x) & 0x1) << 12) -#define G_008008_ME2PIPE2_RQ_PENDING(x) (((x) >> 12) & 0x1) -#define C_008008_ME2PIPE2_RQ_PENDING 0xFFFFEFFF -#define S_008008_ME2PIPE3_RQ_PENDING(x) (((x) & 0x1) << 13) -#define G_008008_ME2PIPE3_RQ_PENDING(x) (((x) >> 13) & 0x1) -#define C_008008_ME2PIPE3_RQ_PENDING 0xFFFFDFFF -#define S_008008_RLC_RQ_PENDING(x) (((x) & 0x1) << 14) -#define G_008008_RLC_RQ_PENDING(x) (((x) >> 14) & 0x1) -#define C_008008_RLC_RQ_PENDING 0xFFFFBFFF -#define S_008008_RLC_BUSY(x) (((x) & 0x1) << 24) -#define G_008008_RLC_BUSY(x) (((x) >> 24) & 0x1) -#define C_008008_RLC_BUSY 0xFEFFFFFF -#define S_008008_TC_BUSY(x) (((x) & 0x1) << 25) -#define G_008008_TC_BUSY(x) (((x) >> 25) & 0x1) -#define C_008008_TC_BUSY 0xFDFFFFFF -#define S_008008_TCC_CC_RESIDENT(x) (((x) & 0x1) << 26) -#define G_008008_TCC_CC_RESIDENT(x) (((x) >> 26) & 0x1) -#define C_008008_TCC_CC_RESIDENT 0xFBFFFFFF -#define S_008008_CPF_BUSY(x) (((x) & 0x1) << 28) -#define G_008008_CPF_BUSY(x) (((x) >> 28) & 0x1) -#define C_008008_CPF_BUSY 0xEFFFFFFF -#define S_008008_CPC_BUSY(x) (((x) & 0x1) << 29) -#define G_008008_CPC_BUSY(x) (((x) >> 29) & 0x1) -#define C_008008_CPC_BUSY 0xDFFFFFFF -#define S_008008_CPG_BUSY(x) (((x) & 0x1) << 30) -#define G_008008_CPG_BUSY(x) (((x) >> 30) & 0x1) -#define C_008008_CPG_BUSY 0xBFFFFFFF -#define R_008010_GRBM_STATUS 0x008010 -#define S_008010_ME0PIPE0_CMDFIFO_AVAIL(x) (((x) & 0x0F) << 0) -#define G_008010_ME0PIPE0_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x0F) -#define C_008010_ME0PIPE0_CMDFIFO_AVAIL 0xFFFFFFF0 -#define S_008010_SRBM_RQ_PENDING(x) (((x) & 0x1) << 5) -#define G_008010_SRBM_RQ_PENDING(x) (((x) >> 5) & 0x1) -#define C_008010_SRBM_RQ_PENDING 0xFFFFFFDF -#define S_008010_ME0PIPE0_CF_RQ_PENDING(x) (((x) & 0x1) << 7) -#define G_008010_ME0PIPE0_CF_RQ_PENDING(x) (((x) >> 7) & 0x1) -#define C_008010_ME0PIPE0_CF_RQ_PENDING 0xFFFFFF7F -#define S_008010_ME0PIPE0_PF_RQ_PENDING(x) (((x) & 0x1) << 8) -#define G_008010_ME0PIPE0_PF_RQ_PENDING(x) (((x) >> 8) & 0x1) -#define C_008010_ME0PIPE0_PF_RQ_PENDING 0xFFFFFEFF -#define S_008010_GDS_DMA_RQ_PENDING(x) (((x) & 0x1) << 9) -#define G_008010_GDS_DMA_RQ_PENDING(x) (((x) >> 9) & 0x1) -#define C_008010_GDS_DMA_RQ_PENDING 0xFFFFFDFF -#define S_008010_DB_CLEAN(x) (((x) & 0x1) << 12) -#define G_008010_DB_CLEAN(x) (((x) >> 12) & 0x1) -#define C_008010_DB_CLEAN 0xFFFFEFFF -#define S_008010_CB_CLEAN(x) (((x) & 0x1) << 13) -#define G_008010_CB_CLEAN(x) (((x) >> 13) & 0x1) -#define C_008010_CB_CLEAN 0xFFFFDFFF -#define S_008010_TA_BUSY(x) (((x) & 0x1) << 14) -#define G_008010_TA_BUSY(x) (((x) >> 14) & 0x1) -#define C_008010_TA_BUSY 0xFFFFBFFF -#define S_008010_GDS_BUSY(x) (((x) & 0x1) << 15) -#define G_008010_GDS_BUSY(x) (((x) >> 15) & 0x1) -#define C_008010_GDS_BUSY 0xFFFF7FFF -#define S_008010_WD_BUSY_NO_DMA(x) (((x) & 0x1) << 16) -#define G_008010_WD_BUSY_NO_DMA(x) (((x) >> 16) & 0x1) -#define C_008010_WD_BUSY_NO_DMA 0xFFFEFFFF -#define S_008010_VGT_BUSY(x) (((x) & 0x1) << 17) -#define G_008010_VGT_BUSY(x) (((x) >> 17) & 0x1) -#define C_008010_VGT_BUSY 0xFFFDFFFF -#define S_008010_IA_BUSY_NO_DMA(x) (((x) & 0x1) << 18) -#define G_008010_IA_BUSY_NO_DMA(x) (((x) >> 18) & 0x1) -#define C_008010_IA_BUSY_NO_DMA 0xFFFBFFFF -#define S_008010_IA_BUSY(x) (((x) & 0x1) << 19) -#define G_008010_IA_BUSY(x) (((x) >> 19) & 0x1) -#define C_008010_IA_BUSY 0xFFF7FFFF -#define S_008010_SX_BUSY(x) (((x) & 0x1) << 20) -#define G_008010_SX_BUSY(x) (((x) >> 20) & 0x1) -#define C_008010_SX_BUSY 0xFFEFFFFF -#define S_008010_WD_BUSY(x) (((x) & 0x1) << 21) -#define G_008010_WD_BUSY(x) (((x) >> 21) & 0x1) -#define C_008010_WD_BUSY 0xFFDFFFFF -#define S_008010_SPI_BUSY(x) (((x) & 0x1) << 22) -#define G_008010_SPI_BUSY(x) (((x) >> 22) & 0x1) -#define C_008010_SPI_BUSY 0xFFBFFFFF -#define S_008010_BCI_BUSY(x) (((x) & 0x1) << 23) -#define G_008010_BCI_BUSY(x) (((x) >> 23) & 0x1) -#define C_008010_BCI_BUSY 0xFF7FFFFF -#define S_008010_SC_BUSY(x) (((x) & 0x1) << 24) -#define G_008010_SC_BUSY(x) (((x) >> 24) & 0x1) -#define C_008010_SC_BUSY 0xFEFFFFFF -#define S_008010_PA_BUSY(x) (((x) & 0x1) << 25) -#define G_008010_PA_BUSY(x) (((x) >> 25) & 0x1) -#define C_008010_PA_BUSY 0xFDFFFFFF -#define S_008010_DB_BUSY(x) (((x) & 0x1) << 26) -#define G_008010_DB_BUSY(x) (((x) >> 26) & 0x1) -#define C_008010_DB_BUSY 0xFBFFFFFF -#define S_008010_CP_COHERENCY_BUSY(x) (((x) & 0x1) << 28) -#define G_008010_CP_COHERENCY_BUSY(x) (((x) >> 28) & 0x1) -#define C_008010_CP_COHERENCY_BUSY 0xEFFFFFFF -#define S_008010_CP_BUSY(x) (((x) & 0x1) << 29) -#define G_008010_CP_BUSY(x) (((x) >> 29) & 0x1) -#define C_008010_CP_BUSY 0xDFFFFFFF -#define S_008010_CB_BUSY(x) (((x) & 0x1) << 30) -#define G_008010_CB_BUSY(x) (((x) >> 30) & 0x1) -#define C_008010_CB_BUSY 0xBFFFFFFF -#define S_008010_GUI_ACTIVE(x) (((x) & 0x1) << 31) -#define G_008010_GUI_ACTIVE(x) (((x) >> 31) & 0x1) -#define C_008010_GUI_ACTIVE 0x7FFFFFFF -#define GRBM_GFX_INDEX 0x802C -#define INSTANCE_INDEX(x) ((x) << 0) -#define SH_INDEX(x) ((x) << 8) -#define SE_INDEX(x) ((x) << 16) -#define SH_BROADCAST_WRITES (1 << 29) -#define INSTANCE_BROADCAST_WRITES (1 << 30) -#define SE_BROADCAST_WRITES (1 << 31) -#define R_0084FC_CP_STRMOUT_CNTL 0x0084FC -#define S_0084FC_OFFSET_UPDATE_DONE(x) (((x) & 0x1) << 0) -#define R_0085F0_CP_COHER_CNTL 0x0085F0 -#define S_0085F0_DEST_BASE_0_ENA(x) (((x) & 0x1) << 0) -#define G_0085F0_DEST_BASE_0_ENA(x) (((x) >> 0) & 0x1) -#define C_0085F0_DEST_BASE_0_ENA 0xFFFFFFFE -#define S_0085F0_DEST_BASE_1_ENA(x) (((x) & 0x1) << 1) -#define G_0085F0_DEST_BASE_1_ENA(x) (((x) >> 1) & 0x1) -#define C_0085F0_DEST_BASE_1_ENA 0xFFFFFFFD -#define S_0085F0_CB0_DEST_BASE_ENA_SHIFT 6 -#define S_0085F0_CB0_DEST_BASE_ENA(x) (((x) & 0x1) << 6) -#define G_0085F0_CB0_DEST_BASE_ENA(x) (((x) >> 6) & 0x1) -#define C_0085F0_CB0_DEST_BASE_ENA 0xFFFFFFBF -#define S_0085F0_CB1_DEST_BASE_ENA(x) (((x) & 0x1) << 7) -#define G_0085F0_CB1_DEST_BASE_ENA(x) (((x) >> 7) & 0x1) -#define C_0085F0_CB1_DEST_BASE_ENA 0xFFFFFF7F -#define S_0085F0_CB2_DEST_BASE_ENA(x) (((x) & 0x1) << 8) -#define G_0085F0_CB2_DEST_BASE_ENA(x) (((x) >> 8) & 0x1) -#define C_0085F0_CB2_DEST_BASE_ENA 0xFFFFFEFF -#define S_0085F0_CB3_DEST_BASE_ENA(x) (((x) & 0x1) << 9) -#define G_0085F0_CB3_DEST_BASE_ENA(x) (((x) >> 9) & 0x1) -#define C_0085F0_CB3_DEST_BASE_ENA 0xFFFFFDFF -#define S_0085F0_CB4_DEST_BASE_ENA(x) (((x) & 0x1) << 10) -#define G_0085F0_CB4_DEST_BASE_ENA(x) (((x) >> 10) & 0x1) -#define C_0085F0_CB4_DEST_BASE_ENA 0xFFFFFBFF -#define S_0085F0_CB5_DEST_BASE_ENA(x) (((x) & 0x1) << 11) -#define G_0085F0_CB5_DEST_BASE_ENA(x) (((x) >> 11) & 0x1) -#define C_0085F0_CB5_DEST_BASE_ENA 0xFFFFF7FF -#define S_0085F0_CB6_DEST_BASE_ENA(x) (((x) & 0x1) << 12) -#define G_0085F0_CB6_DEST_BASE_ENA(x) (((x) >> 12) & 0x1) -#define C_0085F0_CB6_DEST_BASE_ENA 0xFFFFEFFF -#define S_0085F0_CB7_DEST_BASE_ENA(x) (((x) & 0x1) << 13) -#define G_0085F0_CB7_DEST_BASE_ENA(x) (((x) >> 13) & 0x1) -#define C_0085F0_CB7_DEST_BASE_ENA 0xFFFFDFFF -#define S_0085F0_DB_DEST_BASE_ENA(x) (((x) & 0x1) << 14) -#define G_0085F0_DB_DEST_BASE_ENA(x) (((x) >> 14) & 0x1) -#define C_0085F0_DB_DEST_BASE_ENA 0xFFFFBFFF -#define S_0085F0_DEST_BASE_2_ENA(x) (((x) & 0x1) << 19) -#define G_0085F0_DEST_BASE_2_ENA(x) (((x) >> 19) & 0x1) -#define C_0085F0_DEST_BASE_2_ENA 0xFFF7FFFF -#define S_0085F0_DEST_BASE_3_ENA(x) (((x) & 0x1) << 21) -#define G_0085F0_DEST_BASE_3_ENA(x) (((x) >> 21) & 0x1) -#define C_0085F0_DEST_BASE_3_ENA 0xFFDFFFFF -#define S_0085F0_TCL1_ACTION_ENA(x) (((x) & 0x1) << 22) -#define G_0085F0_TCL1_ACTION_ENA(x) (((x) >> 22) & 0x1) -#define C_0085F0_TCL1_ACTION_ENA 0xFFBFFFFF -#define S_0085F0_TC_ACTION_ENA(x) (((x) & 0x1) << 23) -#define G_0085F0_TC_ACTION_ENA(x) (((x) >> 23) & 0x1) -#define C_0085F0_TC_ACTION_ENA 0xFF7FFFFF -#define S_0085F0_CB_ACTION_ENA(x) (((x) & 0x1) << 25) -#define G_0085F0_CB_ACTION_ENA(x) (((x) >> 25) & 0x1) -#define C_0085F0_CB_ACTION_ENA 0xFDFFFFFF -#define S_0085F0_DB_ACTION_ENA(x) (((x) & 0x1) << 26) -#define G_0085F0_DB_ACTION_ENA(x) (((x) >> 26) & 0x1) -#define C_0085F0_DB_ACTION_ENA 0xFBFFFFFF -#define S_0085F0_SH_KCACHE_ACTION_ENA(x) (((x) & 0x1) << 27) -#define G_0085F0_SH_KCACHE_ACTION_ENA(x) (((x) >> 27) & 0x1) -#define C_0085F0_SH_KCACHE_ACTION_ENA 0xF7FFFFFF -#define S_0085F0_SH_ICACHE_ACTION_ENA(x) (((x) & 0x1) << 29) -#define G_0085F0_SH_ICACHE_ACTION_ENA(x) (((x) >> 29) & 0x1) -#define C_0085F0_SH_ICACHE_ACTION_ENA 0xDFFFFFFF -#define R_0085F4_CP_COHER_SIZE 0x0085F4 -#define R_0085F8_CP_COHER_BASE 0x0085F8 -#define R_008014_GRBM_STATUS_SE0 0x008014 -#define S_008014_DB_CLEAN(x) (((x) & 0x1) << 1) -#define G_008014_DB_CLEAN(x) (((x) >> 1) & 0x1) -#define C_008014_DB_CLEAN 0xFFFFFFFD -#define S_008014_CB_CLEAN(x) (((x) & 0x1) << 2) -#define G_008014_CB_CLEAN(x) (((x) >> 2) & 0x1) -#define C_008014_CB_CLEAN 0xFFFFFFFB -#define S_008014_BCI_BUSY(x) (((x) & 0x1) << 22) -#define G_008014_BCI_BUSY(x) (((x) >> 22) & 0x1) -#define C_008014_BCI_BUSY 0xFFBFFFFF -#define S_008014_VGT_BUSY(x) (((x) & 0x1) << 23) -#define G_008014_VGT_BUSY(x) (((x) >> 23) & 0x1) -#define C_008014_VGT_BUSY 0xFF7FFFFF -#define S_008014_PA_BUSY(x) (((x) & 0x1) << 24) -#define G_008014_PA_BUSY(x) (((x) >> 24) & 0x1) -#define C_008014_PA_BUSY 0xFEFFFFFF -#define S_008014_TA_BUSY(x) (((x) & 0x1) << 25) -#define G_008014_TA_BUSY(x) (((x) >> 25) & 0x1) -#define C_008014_TA_BUSY 0xFDFFFFFF -#define S_008014_SX_BUSY(x) (((x) & 0x1) << 26) -#define G_008014_SX_BUSY(x) (((x) >> 26) & 0x1) -#define C_008014_SX_BUSY 0xFBFFFFFF -#define S_008014_SPI_BUSY(x) (((x) & 0x1) << 27) -#define G_008014_SPI_BUSY(x) (((x) >> 27) & 0x1) -#define C_008014_SPI_BUSY 0xF7FFFFFF -#define S_008014_SC_BUSY(x) (((x) & 0x1) << 29) -#define G_008014_SC_BUSY(x) (((x) >> 29) & 0x1) -#define C_008014_SC_BUSY 0xDFFFFFFF -#define S_008014_DB_BUSY(x) (((x) & 0x1) << 30) -#define G_008014_DB_BUSY(x) (((x) >> 30) & 0x1) -#define C_008014_DB_BUSY 0xBFFFFFFF -#define S_008014_CB_BUSY(x) (((x) & 0x1) << 31) -#define G_008014_CB_BUSY(x) (((x) >> 31) & 0x1) -#define C_008014_CB_BUSY 0x7FFFFFFF -#define R_008018_GRBM_STATUS_SE1 0x008018 -#define S_008018_DB_CLEAN(x) (((x) & 0x1) << 1) -#define G_008018_DB_CLEAN(x) (((x) >> 1) & 0x1) -#define C_008018_DB_CLEAN 0xFFFFFFFD -#define S_008018_CB_CLEAN(x) (((x) & 0x1) << 2) -#define G_008018_CB_CLEAN(x) (((x) >> 2) & 0x1) -#define C_008018_CB_CLEAN 0xFFFFFFFB -#define S_008018_BCI_BUSY(x) (((x) & 0x1) << 22) -#define G_008018_BCI_BUSY(x) (((x) >> 22) & 0x1) -#define C_008018_BCI_BUSY 0xFFBFFFFF -#define S_008018_VGT_BUSY(x) (((x) & 0x1) << 23) -#define G_008018_VGT_BUSY(x) (((x) >> 23) & 0x1) -#define C_008018_VGT_BUSY 0xFF7FFFFF -#define S_008018_PA_BUSY(x) (((x) & 0x1) << 24) -#define G_008018_PA_BUSY(x) (((x) >> 24) & 0x1) -#define C_008018_PA_BUSY 0xFEFFFFFF -#define S_008018_TA_BUSY(x) (((x) & 0x1) << 25) -#define G_008018_TA_BUSY(x) (((x) >> 25) & 0x1) -#define C_008018_TA_BUSY 0xFDFFFFFF -#define S_008018_SX_BUSY(x) (((x) & 0x1) << 26) -#define G_008018_SX_BUSY(x) (((x) >> 26) & 0x1) -#define C_008018_SX_BUSY 0xFBFFFFFF -#define S_008018_SPI_BUSY(x) (((x) & 0x1) << 27) -#define G_008018_SPI_BUSY(x) (((x) >> 27) & 0x1) -#define C_008018_SPI_BUSY 0xF7FFFFFF -#define S_008018_SC_BUSY(x) (((x) & 0x1) << 29) -#define G_008018_SC_BUSY(x) (((x) >> 29) & 0x1) -#define C_008018_SC_BUSY 0xDFFFFFFF -#define S_008018_DB_BUSY(x) (((x) & 0x1) << 30) -#define G_008018_DB_BUSY(x) (((x) >> 30) & 0x1) -#define C_008018_DB_BUSY 0xBFFFFFFF -#define S_008018_CB_BUSY(x) (((x) & 0x1) << 31) -#define G_008018_CB_BUSY(x) (((x) >> 31) & 0x1) -#define C_008018_CB_BUSY 0x7FFFFFFF -#define R_008038_GRBM_STATUS_SE2 0x008038 -#define S_008038_DB_CLEAN(x) (((x) & 0x1) << 1) -#define G_008038_DB_CLEAN(x) (((x) >> 1) & 0x1) -#define C_008038_DB_CLEAN 0xFFFFFFFD -#define S_008038_CB_CLEAN(x) (((x) & 0x1) << 2) -#define G_008038_CB_CLEAN(x) (((x) >> 2) & 0x1) -#define C_008038_CB_CLEAN 0xFFFFFFFB -#define S_008038_BCI_BUSY(x) (((x) & 0x1) << 22) -#define G_008038_BCI_BUSY(x) (((x) >> 22) & 0x1) -#define C_008038_BCI_BUSY 0xFFBFFFFF -#define S_008038_VGT_BUSY(x) (((x) & 0x1) << 23) -#define G_008038_VGT_BUSY(x) (((x) >> 23) & 0x1) -#define C_008038_VGT_BUSY 0xFF7FFFFF -#define S_008038_PA_BUSY(x) (((x) & 0x1) << 24) -#define G_008038_PA_BUSY(x) (((x) >> 24) & 0x1) -#define C_008038_PA_BUSY 0xFEFFFFFF -#define S_008038_TA_BUSY(x) (((x) & 0x1) << 25) -#define G_008038_TA_BUSY(x) (((x) >> 25) & 0x1) -#define C_008038_TA_BUSY 0xFDFFFFFF -#define S_008038_SX_BUSY(x) (((x) & 0x1) << 26) -#define G_008038_SX_BUSY(x) (((x) >> 26) & 0x1) -#define C_008038_SX_BUSY 0xFBFFFFFF -#define S_008038_SPI_BUSY(x) (((x) & 0x1) << 27) -#define G_008038_SPI_BUSY(x) (((x) >> 27) & 0x1) -#define C_008038_SPI_BUSY 0xF7FFFFFF -#define S_008038_SC_BUSY(x) (((x) & 0x1) << 29) -#define G_008038_SC_BUSY(x) (((x) >> 29) & 0x1) -#define C_008038_SC_BUSY 0xDFFFFFFF -#define S_008038_DB_BUSY(x) (((x) & 0x1) << 30) -#define G_008038_DB_BUSY(x) (((x) >> 30) & 0x1) -#define C_008038_DB_BUSY 0xBFFFFFFF -#define S_008038_CB_BUSY(x) (((x) & 0x1) << 31) -#define G_008038_CB_BUSY(x) (((x) >> 31) & 0x1) -#define C_008038_CB_BUSY 0x7FFFFFFF -#define R_00803C_GRBM_STATUS_SE3 0x00803C -#define S_00803C_DB_CLEAN(x) (((x) & 0x1) << 1) -#define G_00803C_DB_CLEAN(x) (((x) >> 1) & 0x1) -#define C_00803C_DB_CLEAN 0xFFFFFFFD -#define S_00803C_CB_CLEAN(x) (((x) & 0x1) << 2) -#define G_00803C_CB_CLEAN(x) (((x) >> 2) & 0x1) -#define C_00803C_CB_CLEAN 0xFFFFFFFB -#define S_00803C_BCI_BUSY(x) (((x) & 0x1) << 22) -#define G_00803C_BCI_BUSY(x) (((x) >> 22) & 0x1) -#define C_00803C_BCI_BUSY 0xFFBFFFFF -#define S_00803C_VGT_BUSY(x) (((x) & 0x1) << 23) -#define G_00803C_VGT_BUSY(x) (((x) >> 23) & 0x1) -#define C_00803C_VGT_BUSY 0xFF7FFFFF -#define S_00803C_PA_BUSY(x) (((x) & 0x1) << 24) -#define G_00803C_PA_BUSY(x) (((x) >> 24) & 0x1) -#define C_00803C_PA_BUSY 0xFEFFFFFF -#define S_00803C_TA_BUSY(x) (((x) & 0x1) << 25) -#define G_00803C_TA_BUSY(x) (((x) >> 25) & 0x1) -#define C_00803C_TA_BUSY 0xFDFFFFFF -#define S_00803C_SX_BUSY(x) (((x) & 0x1) << 26) -#define G_00803C_SX_BUSY(x) (((x) >> 26) & 0x1) -#define C_00803C_SX_BUSY 0xFBFFFFFF -#define S_00803C_SPI_BUSY(x) (((x) & 0x1) << 27) -#define G_00803C_SPI_BUSY(x) (((x) >> 27) & 0x1) -#define C_00803C_SPI_BUSY 0xF7FFFFFF -#define S_00803C_SC_BUSY(x) (((x) & 0x1) << 29) -#define G_00803C_SC_BUSY(x) (((x) >> 29) & 0x1) -#define C_00803C_SC_BUSY 0xDFFFFFFF -#define S_00803C_DB_BUSY(x) (((x) & 0x1) << 30) -#define G_00803C_DB_BUSY(x) (((x) >> 30) & 0x1) -#define C_00803C_DB_BUSY 0xBFFFFFFF -#define S_00803C_CB_BUSY(x) (((x) & 0x1) << 31) -#define G_00803C_CB_BUSY(x) (((x) >> 31) & 0x1) -#define C_00803C_CB_BUSY 0x7FFFFFFF -/* CIK */ -#define R_0300FC_CP_STRMOUT_CNTL 0x0300FC -#define S_0300FC_OFFSET_UPDATE_DONE(x) (((x) & 0x1) << 0) -#define G_0300FC_OFFSET_UPDATE_DONE(x) (((x) >> 0) & 0x1) -#define C_0300FC_OFFSET_UPDATE_DONE 0xFFFFFFFE -#define R_0301E4_CP_COHER_BASE_HI 0x0301E4 -#define S_0301E4_COHER_BASE_HI_256B(x) (((x) & 0xFF) << 0) -#define G_0301E4_COHER_BASE_HI_256B(x) (((x) >> 0) & 0xFF) -#define C_0301E4_COHER_BASE_HI_256B 0xFFFFFF00 -#define R_0301EC_CP_COHER_START_DELAY 0x0301EC -#define S_0301EC_START_DELAY_COUNT(x) (((x) & 0x3F) << 0) -#define G_0301EC_START_DELAY_COUNT(x) (((x) >> 0) & 0x3F) -#define C_0301EC_START_DELAY_COUNT 0xFFFFFFC0 -#define R_0301F0_CP_COHER_CNTL 0x0301F0 -#define S_0301F0_DEST_BASE_0_ENA(x) (((x) & 0x1) << 0) -#define G_0301F0_DEST_BASE_0_ENA(x) (((x) >> 0) & 0x1) -#define C_0301F0_DEST_BASE_0_ENA 0xFFFFFFFE -#define S_0301F0_DEST_BASE_1_ENA(x) (((x) & 0x1) << 1) -#define G_0301F0_DEST_BASE_1_ENA(x) (((x) >> 1) & 0x1) -#define C_0301F0_DEST_BASE_1_ENA 0xFFFFFFFD -/* VI */ -#define S_0301F0_TC_SD_ACTION_ENA(x) (((x) & 0x1) << 2) -#define G_0301F0_TC_SD_ACTION_ENA(x) (((x) >> 2) & 0x1) -#define C_0301F0_TC_SD_ACTION_ENA 0xFFFFFFFB -#define S_0301F0_TC_NC_ACTION_ENA(x) (((x) & 0x1) << 3) -#define G_0301F0_TC_NC_ACTION_ENA(x) (((x) >> 3) & 0x1) -#define C_0301F0_TC_NC_ACTION_ENA 0xFFFFFFF7 -/* */ -#define S_0301F0_CB0_DEST_BASE_ENA(x) (((x) & 0x1) << 6) -#define G_0301F0_CB0_DEST_BASE_ENA(x) (((x) >> 6) & 0x1) -#define C_0301F0_CB0_DEST_BASE_ENA 0xFFFFFFBF -#define S_0301F0_CB1_DEST_BASE_ENA(x) (((x) & 0x1) << 7) -#define G_0301F0_CB1_DEST_BASE_ENA(x) (((x) >> 7) & 0x1) -#define C_0301F0_CB1_DEST_BASE_ENA 0xFFFFFF7F -#define S_0301F0_CB2_DEST_BASE_ENA(x) (((x) & 0x1) << 8) -#define G_0301F0_CB2_DEST_BASE_ENA(x) (((x) >> 8) & 0x1) -#define C_0301F0_CB2_DEST_BASE_ENA 0xFFFFFEFF -#define S_0301F0_CB3_DEST_BASE_ENA(x) (((x) & 0x1) << 9) -#define G_0301F0_CB3_DEST_BASE_ENA(x) (((x) >> 9) & 0x1) -#define C_0301F0_CB3_DEST_BASE_ENA 0xFFFFFDFF -#define S_0301F0_CB4_DEST_BASE_ENA(x) (((x) & 0x1) << 10) -#define G_0301F0_CB4_DEST_BASE_ENA(x) (((x) >> 10) & 0x1) -#define C_0301F0_CB4_DEST_BASE_ENA 0xFFFFFBFF -#define S_0301F0_CB5_DEST_BASE_ENA(x) (((x) & 0x1) << 11) -#define G_0301F0_CB5_DEST_BASE_ENA(x) (((x) >> 11) & 0x1) -#define C_0301F0_CB5_DEST_BASE_ENA 0xFFFFF7FF -#define S_0301F0_CB6_DEST_BASE_ENA(x) (((x) & 0x1) << 12) -#define G_0301F0_CB6_DEST_BASE_ENA(x) (((x) >> 12) & 0x1) -#define C_0301F0_CB6_DEST_BASE_ENA 0xFFFFEFFF -#define S_0301F0_CB7_DEST_BASE_ENA(x) (((x) & 0x1) << 13) -#define G_0301F0_CB7_DEST_BASE_ENA(x) (((x) >> 13) & 0x1) -#define C_0301F0_CB7_DEST_BASE_ENA 0xFFFFDFFF -#define S_0301F0_DB_DEST_BASE_ENA(x) (((x) & 0x1) << 14) -#define G_0301F0_DB_DEST_BASE_ENA(x) (((x) >> 14) & 0x1) -#define C_0301F0_DB_DEST_BASE_ENA 0xFFFFBFFF -#define S_0301F0_TCL1_VOL_ACTION_ENA(x) (((x) & 0x1) << 15) -#define G_0301F0_TCL1_VOL_ACTION_ENA(x) (((x) >> 15) & 0x1) -#define C_0301F0_TCL1_VOL_ACTION_ENA 0xFFFF7FFF -#define S_0301F0_TC_VOL_ACTION_ENA(x) (((x) & 0x1) << 16) /* not on VI */ -#define G_0301F0_TC_VOL_ACTION_ENA(x) (((x) >> 16) & 0x1) -#define C_0301F0_TC_VOL_ACTION_ENA 0xFFFEFFFF -#define S_0301F0_TC_WB_ACTION_ENA(x) (((x) & 0x1) << 18) -#define G_0301F0_TC_WB_ACTION_ENA(x) (((x) >> 18) & 0x1) -#define C_0301F0_TC_WB_ACTION_ENA 0xFFFBFFFF -#define S_0301F0_DEST_BASE_2_ENA(x) (((x) & 0x1) << 19) -#define G_0301F0_DEST_BASE_2_ENA(x) (((x) >> 19) & 0x1) -#define C_0301F0_DEST_BASE_2_ENA 0xFFF7FFFF -#define S_0301F0_DEST_BASE_3_ENA(x) (((x) & 0x1) << 21) -#define G_0301F0_DEST_BASE_3_ENA(x) (((x) >> 21) & 0x1) -#define C_0301F0_DEST_BASE_3_ENA 0xFFDFFFFF -#define S_0301F0_TCL1_ACTION_ENA(x) (((x) & 0x1) << 22) -#define G_0301F0_TCL1_ACTION_ENA(x) (((x) >> 22) & 0x1) -#define C_0301F0_TCL1_ACTION_ENA 0xFFBFFFFF -#define S_0301F0_TC_ACTION_ENA(x) (((x) & 0x1) << 23) -#define G_0301F0_TC_ACTION_ENA(x) (((x) >> 23) & 0x1) -#define C_0301F0_TC_ACTION_ENA 0xFF7FFFFF -#define S_0301F0_CB_ACTION_ENA(x) (((x) & 0x1) << 25) -#define G_0301F0_CB_ACTION_ENA(x) (((x) >> 25) & 0x1) -#define C_0301F0_CB_ACTION_ENA 0xFDFFFFFF -#define S_0301F0_DB_ACTION_ENA(x) (((x) & 0x1) << 26) -#define G_0301F0_DB_ACTION_ENA(x) (((x) >> 26) & 0x1) -#define C_0301F0_DB_ACTION_ENA 0xFBFFFFFF -#define S_0301F0_SH_KCACHE_ACTION_ENA(x) (((x) & 0x1) << 27) -#define G_0301F0_SH_KCACHE_ACTION_ENA(x) (((x) >> 27) & 0x1) -#define C_0301F0_SH_KCACHE_ACTION_ENA 0xF7FFFFFF -#define S_0301F0_SH_KCACHE_VOL_ACTION_ENA(x) (((x) & 0x1) << 28) -#define G_0301F0_SH_KCACHE_VOL_ACTION_ENA(x) (((x) >> 28) & 0x1) -#define C_0301F0_SH_KCACHE_VOL_ACTION_ENA 0xEFFFFFFF -#define S_0301F0_SH_ICACHE_ACTION_ENA(x) (((x) & 0x1) << 29) -#define G_0301F0_SH_ICACHE_ACTION_ENA(x) (((x) >> 29) & 0x1) -#define C_0301F0_SH_ICACHE_ACTION_ENA 0xDFFFFFFF -/* VI */ -#define S_0301F0_SH_KCACHE_WB_ACTION_ENA(x) (((x) & 0x1) << 30) -#define G_0301F0_SH_KCACHE_WB_ACTION_ENA(x) (((x) >> 30) & 0x1) -#define C_0301F0_SH_KCACHE_WB_ACTION_ENA 0xBFFFFFFF -#define S_0301F0_SH_SD_ACTION_ENA(x) (((x) & 0x1) << 31) -#define G_0301F0_SH_SD_ACTION_ENA(x) (((x) >> 31) & 0x1) -#define C_0301F0_SH_SD_ACTION_ENA 0x7FFFFFFF -/* */ -#define R_0301F4_CP_COHER_SIZE 0x0301F4 -#define R_0301F8_CP_COHER_BASE 0x0301F8 -#define R_0301FC_CP_COHER_STATUS 0x0301FC -#define S_0301FC_MATCHING_GFX_CNTX(x) (((x) & 0xFF) << 0) -#define G_0301FC_MATCHING_GFX_CNTX(x) (((x) >> 0) & 0xFF) -#define C_0301FC_MATCHING_GFX_CNTX 0xFFFFFF00 -#define S_0301FC_MEID(x) (((x) & 0x03) << 24) -#define G_0301FC_MEID(x) (((x) >> 24) & 0x03) -#define C_0301FC_MEID 0xFCFFFFFF -#define S_0301FC_PHASE1_STATUS(x) (((x) & 0x1) << 30) -#define G_0301FC_PHASE1_STATUS(x) (((x) >> 30) & 0x1) -#define C_0301FC_PHASE1_STATUS 0xBFFFFFFF -#define S_0301FC_STATUS(x) (((x) & 0x1) << 31) -#define G_0301FC_STATUS(x) (((x) >> 31) & 0x1) -#define C_0301FC_STATUS 0x7FFFFFFF -#define R_008210_CP_CPC_STATUS 0x008210 -#define S_008210_MEC1_BUSY(x) (((x) & 0x1) << 0) -#define G_008210_MEC1_BUSY(x) (((x) >> 0) & 0x1) -#define C_008210_MEC1_BUSY 0xFFFFFFFE -#define S_008210_MEC2_BUSY(x) (((x) & 0x1) << 1) -#define G_008210_MEC2_BUSY(x) (((x) >> 1) & 0x1) -#define C_008210_MEC2_BUSY 0xFFFFFFFD -#define S_008210_DC0_BUSY(x) (((x) & 0x1) << 2) -#define G_008210_DC0_BUSY(x) (((x) >> 2) & 0x1) -#define C_008210_DC0_BUSY 0xFFFFFFFB -#define S_008210_DC1_BUSY(x) (((x) & 0x1) << 3) -#define G_008210_DC1_BUSY(x) (((x) >> 3) & 0x1) -#define C_008210_DC1_BUSY 0xFFFFFFF7 -#define S_008210_RCIU1_BUSY(x) (((x) & 0x1) << 4) -#define G_008210_RCIU1_BUSY(x) (((x) >> 4) & 0x1) -#define C_008210_RCIU1_BUSY 0xFFFFFFEF -#define S_008210_RCIU2_BUSY(x) (((x) & 0x1) << 5) -#define G_008210_RCIU2_BUSY(x) (((x) >> 5) & 0x1) -#define C_008210_RCIU2_BUSY 0xFFFFFFDF -#define S_008210_ROQ1_BUSY(x) (((x) & 0x1) << 6) -#define G_008210_ROQ1_BUSY(x) (((x) >> 6) & 0x1) -#define C_008210_ROQ1_BUSY 0xFFFFFFBF -#define S_008210_ROQ2_BUSY(x) (((x) & 0x1) << 7) -#define G_008210_ROQ2_BUSY(x) (((x) >> 7) & 0x1) -#define C_008210_ROQ2_BUSY 0xFFFFFF7F -#define S_008210_TCIU_BUSY(x) (((x) & 0x1) << 10) -#define G_008210_TCIU_BUSY(x) (((x) >> 10) & 0x1) -#define C_008210_TCIU_BUSY 0xFFFFFBFF -#define S_008210_SCRATCH_RAM_BUSY(x) (((x) & 0x1) << 11) -#define G_008210_SCRATCH_RAM_BUSY(x) (((x) >> 11) & 0x1) -#define C_008210_SCRATCH_RAM_BUSY 0xFFFFF7FF -#define S_008210_QU_BUSY(x) (((x) & 0x1) << 12) -#define G_008210_QU_BUSY(x) (((x) >> 12) & 0x1) -#define C_008210_QU_BUSY 0xFFFFEFFF -#define S_008210_ATCL2IU_BUSY(x) (((x) & 0x1) << 13) -#define G_008210_ATCL2IU_BUSY(x) (((x) >> 13) & 0x1) -#define C_008210_ATCL2IU_BUSY 0xFFFFDFFF -#define S_008210_CPG_CPC_BUSY(x) (((x) & 0x1) << 29) -#define G_008210_CPG_CPC_BUSY(x) (((x) >> 29) & 0x1) -#define C_008210_CPG_CPC_BUSY 0xDFFFFFFF -#define S_008210_CPF_CPC_BUSY(x) (((x) & 0x1) << 30) -#define G_008210_CPF_CPC_BUSY(x) (((x) >> 30) & 0x1) -#define C_008210_CPF_CPC_BUSY 0xBFFFFFFF -#define S_008210_CPC_BUSY(x) (((x) & 0x1) << 31) -#define G_008210_CPC_BUSY(x) (((x) >> 31) & 0x1) -#define C_008210_CPC_BUSY 0x7FFFFFFF -#define R_008214_CP_CPC_BUSY_STAT 0x008214 -#define S_008214_MEC1_LOAD_BUSY(x) (((x) & 0x1) << 0) -#define G_008214_MEC1_LOAD_BUSY(x) (((x) >> 0) & 0x1) -#define C_008214_MEC1_LOAD_BUSY 0xFFFFFFFE -#define S_008214_MEC1_SEMAPOHRE_BUSY(x) (((x) & 0x1) << 1) -#define G_008214_MEC1_SEMAPOHRE_BUSY(x) (((x) >> 1) & 0x1) -#define C_008214_MEC1_SEMAPOHRE_BUSY 0xFFFFFFFD -#define S_008214_MEC1_MUTEX_BUSY(x) (((x) & 0x1) << 2) -#define G_008214_MEC1_MUTEX_BUSY(x) (((x) >> 2) & 0x1) -#define C_008214_MEC1_MUTEX_BUSY 0xFFFFFFFB -#define S_008214_MEC1_MESSAGE_BUSY(x) (((x) & 0x1) << 3) -#define G_008214_MEC1_MESSAGE_BUSY(x) (((x) >> 3) & 0x1) -#define C_008214_MEC1_MESSAGE_BUSY 0xFFFFFFF7 -#define S_008214_MEC1_EOP_QUEUE_BUSY(x) (((x) & 0x1) << 4) -#define G_008214_MEC1_EOP_QUEUE_BUSY(x) (((x) >> 4) & 0x1) -#define C_008214_MEC1_EOP_QUEUE_BUSY 0xFFFFFFEF -#define S_008214_MEC1_IQ_QUEUE_BUSY(x) (((x) & 0x1) << 5) -#define G_008214_MEC1_IQ_QUEUE_BUSY(x) (((x) >> 5) & 0x1) -#define C_008214_MEC1_IQ_QUEUE_BUSY 0xFFFFFFDF -#define S_008214_MEC1_IB_QUEUE_BUSY(x) (((x) & 0x1) << 6) -#define G_008214_MEC1_IB_QUEUE_BUSY(x) (((x) >> 6) & 0x1) -#define C_008214_MEC1_IB_QUEUE_BUSY 0xFFFFFFBF -#define S_008214_MEC1_TC_BUSY(x) (((x) & 0x1) << 7) -#define G_008214_MEC1_TC_BUSY(x) (((x) >> 7) & 0x1) -#define C_008214_MEC1_TC_BUSY 0xFFFFFF7F -#define S_008214_MEC1_DMA_BUSY(x) (((x) & 0x1) << 8) -#define G_008214_MEC1_DMA_BUSY(x) (((x) >> 8) & 0x1) -#define C_008214_MEC1_DMA_BUSY 0xFFFFFEFF -#define S_008214_MEC1_PARTIAL_FLUSH_BUSY(x) (((x) & 0x1) << 9) -#define G_008214_MEC1_PARTIAL_FLUSH_BUSY(x) (((x) >> 9) & 0x1) -#define C_008214_MEC1_PARTIAL_FLUSH_BUSY 0xFFFFFDFF -#define S_008214_MEC1_PIPE0_BUSY(x) (((x) & 0x1) << 10) -#define G_008214_MEC1_PIPE0_BUSY(x) (((x) >> 10) & 0x1) -#define C_008214_MEC1_PIPE0_BUSY 0xFFFFFBFF -#define S_008214_MEC1_PIPE1_BUSY(x) (((x) & 0x1) << 11) -#define G_008214_MEC1_PIPE1_BUSY(x) (((x) >> 11) & 0x1) -#define C_008214_MEC1_PIPE1_BUSY 0xFFFFF7FF -#define S_008214_MEC1_PIPE2_BUSY(x) (((x) & 0x1) << 12) -#define G_008214_MEC1_PIPE2_BUSY(x) (((x) >> 12) & 0x1) -#define C_008214_MEC1_PIPE2_BUSY 0xFFFFEFFF -#define S_008214_MEC1_PIPE3_BUSY(x) (((x) & 0x1) << 13) -#define G_008214_MEC1_PIPE3_BUSY(x) (((x) >> 13) & 0x1) -#define C_008214_MEC1_PIPE3_BUSY 0xFFFFDFFF -#define S_008214_MEC2_LOAD_BUSY(x) (((x) & 0x1) << 16) -#define G_008214_MEC2_LOAD_BUSY(x) (((x) >> 16) & 0x1) -#define C_008214_MEC2_LOAD_BUSY 0xFFFEFFFF -#define S_008214_MEC2_SEMAPOHRE_BUSY(x) (((x) & 0x1) << 17) -#define G_008214_MEC2_SEMAPOHRE_BUSY(x) (((x) >> 17) & 0x1) -#define C_008214_MEC2_SEMAPOHRE_BUSY 0xFFFDFFFF -#define S_008214_MEC2_MUTEX_BUSY(x) (((x) & 0x1) << 18) -#define G_008214_MEC2_MUTEX_BUSY(x) (((x) >> 18) & 0x1) -#define C_008214_MEC2_MUTEX_BUSY 0xFFFBFFFF -#define S_008214_MEC2_MESSAGE_BUSY(x) (((x) & 0x1) << 19) -#define G_008214_MEC2_MESSAGE_BUSY(x) (((x) >> 19) & 0x1) -#define C_008214_MEC2_MESSAGE_BUSY 0xFFF7FFFF -#define S_008214_MEC2_EOP_QUEUE_BUSY(x) (((x) & 0x1) << 20) -#define G_008214_MEC2_EOP_QUEUE_BUSY(x) (((x) >> 20) & 0x1) -#define C_008214_MEC2_EOP_QUEUE_BUSY 0xFFEFFFFF -#define S_008214_MEC2_IQ_QUEUE_BUSY(x) (((x) & 0x1) << 21) -#define G_008214_MEC2_IQ_QUEUE_BUSY(x) (((x) >> 21) & 0x1) -#define C_008214_MEC2_IQ_QUEUE_BUSY 0xFFDFFFFF -#define S_008214_MEC2_IB_QUEUE_BUSY(x) (((x) & 0x1) << 22) -#define G_008214_MEC2_IB_QUEUE_BUSY(x) (((x) >> 22) & 0x1) -#define C_008214_MEC2_IB_QUEUE_BUSY 0xFFBFFFFF -#define S_008214_MEC2_TC_BUSY(x) (((x) & 0x1) << 23) -#define G_008214_MEC2_TC_BUSY(x) (((x) >> 23) & 0x1) -#define C_008214_MEC2_TC_BUSY 0xFF7FFFFF -#define S_008214_MEC2_DMA_BUSY(x) (((x) & 0x1) << 24) -#define G_008214_MEC2_DMA_BUSY(x) (((x) >> 24) & 0x1) -#define C_008214_MEC2_DMA_BUSY 0xFEFFFFFF -#define S_008214_MEC2_PARTIAL_FLUSH_BUSY(x) (((x) & 0x1) << 25) -#define G_008214_MEC2_PARTIAL_FLUSH_BUSY(x) (((x) >> 25) & 0x1) -#define C_008214_MEC2_PARTIAL_FLUSH_BUSY 0xFDFFFFFF -#define S_008214_MEC2_PIPE0_BUSY(x) (((x) & 0x1) << 26) -#define G_008214_MEC2_PIPE0_BUSY(x) (((x) >> 26) & 0x1) -#define C_008214_MEC2_PIPE0_BUSY 0xFBFFFFFF -#define S_008214_MEC2_PIPE1_BUSY(x) (((x) & 0x1) << 27) -#define G_008214_MEC2_PIPE1_BUSY(x) (((x) >> 27) & 0x1) -#define C_008214_MEC2_PIPE1_BUSY 0xF7FFFFFF -#define S_008214_MEC2_PIPE2_BUSY(x) (((x) & 0x1) << 28) -#define G_008214_MEC2_PIPE2_BUSY(x) (((x) >> 28) & 0x1) -#define C_008214_MEC2_PIPE2_BUSY 0xEFFFFFFF -#define S_008214_MEC2_PIPE3_BUSY(x) (((x) & 0x1) << 29) -#define G_008214_MEC2_PIPE3_BUSY(x) (((x) >> 29) & 0x1) -#define C_008214_MEC2_PIPE3_BUSY 0xDFFFFFFF -#define R_008218_CP_CPC_STALLED_STAT1 0x008218 -#define S_008218_RCIU_TX_FREE_STALL(x) (((x) & 0x1) << 3) -#define G_008218_RCIU_TX_FREE_STALL(x) (((x) >> 3) & 0x1) -#define C_008218_RCIU_TX_FREE_STALL 0xFFFFFFF7 -#define S_008218_RCIU_PRIV_VIOLATION(x) (((x) & 0x1) << 4) -#define G_008218_RCIU_PRIV_VIOLATION(x) (((x) >> 4) & 0x1) -#define C_008218_RCIU_PRIV_VIOLATION 0xFFFFFFEF -#define S_008218_TCIU_TX_FREE_STALL(x) (((x) & 0x1) << 6) -#define G_008218_TCIU_TX_FREE_STALL(x) (((x) >> 6) & 0x1) -#define C_008218_TCIU_TX_FREE_STALL 0xFFFFFFBF -#define S_008218_MEC1_DECODING_PACKET(x) (((x) & 0x1) << 8) -#define G_008218_MEC1_DECODING_PACKET(x) (((x) >> 8) & 0x1) -#define C_008218_MEC1_DECODING_PACKET 0xFFFFFEFF -#define S_008218_MEC1_WAIT_ON_RCIU(x) (((x) & 0x1) << 9) -#define G_008218_MEC1_WAIT_ON_RCIU(x) (((x) >> 9) & 0x1) -#define C_008218_MEC1_WAIT_ON_RCIU 0xFFFFFDFF -#define S_008218_MEC1_WAIT_ON_RCIU_READ(x) (((x) & 0x1) << 10) -#define G_008218_MEC1_WAIT_ON_RCIU_READ(x) (((x) >> 10) & 0x1) -#define C_008218_MEC1_WAIT_ON_RCIU_READ 0xFFFFFBFF -#define S_008218_MEC1_WAIT_ON_ROQ_DATA(x) (((x) & 0x1) << 13) -#define G_008218_MEC1_WAIT_ON_ROQ_DATA(x) (((x) >> 13) & 0x1) -#define C_008218_MEC1_WAIT_ON_ROQ_DATA 0xFFFFDFFF -#define S_008218_MEC2_DECODING_PACKET(x) (((x) & 0x1) << 16) -#define G_008218_MEC2_DECODING_PACKET(x) (((x) >> 16) & 0x1) -#define C_008218_MEC2_DECODING_PACKET 0xFFFEFFFF -#define S_008218_MEC2_WAIT_ON_RCIU(x) (((x) & 0x1) << 17) -#define G_008218_MEC2_WAIT_ON_RCIU(x) (((x) >> 17) & 0x1) -#define C_008218_MEC2_WAIT_ON_RCIU 0xFFFDFFFF -#define S_008218_MEC2_WAIT_ON_RCIU_READ(x) (((x) & 0x1) << 18) -#define G_008218_MEC2_WAIT_ON_RCIU_READ(x) (((x) >> 18) & 0x1) -#define C_008218_MEC2_WAIT_ON_RCIU_READ 0xFFFBFFFF -#define S_008218_MEC2_WAIT_ON_ROQ_DATA(x) (((x) & 0x1) << 21) -#define G_008218_MEC2_WAIT_ON_ROQ_DATA(x) (((x) >> 21) & 0x1) -#define C_008218_MEC2_WAIT_ON_ROQ_DATA 0xFFDFFFFF -#define S_008218_ATCL2IU_WAITING_ON_FREE(x) (((x) & 0x1) << 22) -#define G_008218_ATCL2IU_WAITING_ON_FREE(x) (((x) >> 22) & 0x1) -#define C_008218_ATCL2IU_WAITING_ON_FREE 0xFFBFFFFF -#define S_008218_ATCL2IU_WAITING_ON_TAGS(x) (((x) & 0x1) << 23) -#define G_008218_ATCL2IU_WAITING_ON_TAGS(x) (((x) >> 23) & 0x1) -#define C_008218_ATCL2IU_WAITING_ON_TAGS 0xFF7FFFFF -#define S_008218_ATCL1_WAITING_ON_TRANS(x) (((x) & 0x1) << 24) -#define G_008218_ATCL1_WAITING_ON_TRANS(x) (((x) >> 24) & 0x1) -#define C_008218_ATCL1_WAITING_ON_TRANS 0xFEFFFFFF -#define R_00821C_CP_CPF_STATUS 0x00821C -#define S_00821C_POST_WPTR_GFX_BUSY(x) (((x) & 0x1) << 0) -#define G_00821C_POST_WPTR_GFX_BUSY(x) (((x) >> 0) & 0x1) -#define C_00821C_POST_WPTR_GFX_BUSY 0xFFFFFFFE -#define S_00821C_CSF_BUSY(x) (((x) & 0x1) << 1) -#define G_00821C_CSF_BUSY(x) (((x) >> 1) & 0x1) -#define C_00821C_CSF_BUSY 0xFFFFFFFD -#define S_00821C_ROQ_ALIGN_BUSY(x) (((x) & 0x1) << 4) -#define G_00821C_ROQ_ALIGN_BUSY(x) (((x) >> 4) & 0x1) -#define C_00821C_ROQ_ALIGN_BUSY 0xFFFFFFEF -#define S_00821C_ROQ_RING_BUSY(x) (((x) & 0x1) << 5) -#define G_00821C_ROQ_RING_BUSY(x) (((x) >> 5) & 0x1) -#define C_00821C_ROQ_RING_BUSY 0xFFFFFFDF -#define S_00821C_ROQ_INDIRECT1_BUSY(x) (((x) & 0x1) << 6) -#define G_00821C_ROQ_INDIRECT1_BUSY(x) (((x) >> 6) & 0x1) -#define C_00821C_ROQ_INDIRECT1_BUSY 0xFFFFFFBF -#define S_00821C_ROQ_INDIRECT2_BUSY(x) (((x) & 0x1) << 7) -#define G_00821C_ROQ_INDIRECT2_BUSY(x) (((x) >> 7) & 0x1) -#define C_00821C_ROQ_INDIRECT2_BUSY 0xFFFFFF7F -#define S_00821C_ROQ_STATE_BUSY(x) (((x) & 0x1) << 8) -#define G_00821C_ROQ_STATE_BUSY(x) (((x) >> 8) & 0x1) -#define C_00821C_ROQ_STATE_BUSY 0xFFFFFEFF -#define S_00821C_ROQ_CE_RING_BUSY(x) (((x) & 0x1) << 9) -#define G_00821C_ROQ_CE_RING_BUSY(x) (((x) >> 9) & 0x1) -#define C_00821C_ROQ_CE_RING_BUSY 0xFFFFFDFF -#define S_00821C_ROQ_CE_INDIRECT1_BUSY(x) (((x) & 0x1) << 10) -#define G_00821C_ROQ_CE_INDIRECT1_BUSY(x) (((x) >> 10) & 0x1) -#define C_00821C_ROQ_CE_INDIRECT1_BUSY 0xFFFFFBFF -#define S_00821C_ROQ_CE_INDIRECT2_BUSY(x) (((x) & 0x1) << 11) -#define G_00821C_ROQ_CE_INDIRECT2_BUSY(x) (((x) >> 11) & 0x1) -#define C_00821C_ROQ_CE_INDIRECT2_BUSY 0xFFFFF7FF -#define S_00821C_SEMAPHORE_BUSY(x) (((x) & 0x1) << 12) -#define G_00821C_SEMAPHORE_BUSY(x) (((x) >> 12) & 0x1) -#define C_00821C_SEMAPHORE_BUSY 0xFFFFEFFF -#define S_00821C_INTERRUPT_BUSY(x) (((x) & 0x1) << 13) -#define G_00821C_INTERRUPT_BUSY(x) (((x) >> 13) & 0x1) -#define C_00821C_INTERRUPT_BUSY 0xFFFFDFFF -#define S_00821C_TCIU_BUSY(x) (((x) & 0x1) << 14) -#define G_00821C_TCIU_BUSY(x) (((x) >> 14) & 0x1) -#define C_00821C_TCIU_BUSY 0xFFFFBFFF -#define S_00821C_HQD_BUSY(x) (((x) & 0x1) << 15) -#define G_00821C_HQD_BUSY(x) (((x) >> 15) & 0x1) -#define C_00821C_HQD_BUSY 0xFFFF7FFF -#define S_00821C_PRT_BUSY(x) (((x) & 0x1) << 16) -#define G_00821C_PRT_BUSY(x) (((x) >> 16) & 0x1) -#define C_00821C_PRT_BUSY 0xFFFEFFFF -#define S_00821C_ATCL2IU_BUSY(x) (((x) & 0x1) << 17) -#define G_00821C_ATCL2IU_BUSY(x) (((x) >> 17) & 0x1) -#define C_00821C_ATCL2IU_BUSY 0xFFFDFFFF -#define S_00821C_CPF_GFX_BUSY(x) (((x) & 0x1) << 26) -#define G_00821C_CPF_GFX_BUSY(x) (((x) >> 26) & 0x1) -#define C_00821C_CPF_GFX_BUSY 0xFBFFFFFF -#define S_00821C_CPF_CMP_BUSY(x) (((x) & 0x1) << 27) -#define G_00821C_CPF_CMP_BUSY(x) (((x) >> 27) & 0x1) -#define C_00821C_CPF_CMP_BUSY 0xF7FFFFFF -#define S_00821C_GRBM_CPF_STAT_BUSY(x) (((x) & 0x03) << 28) -#define G_00821C_GRBM_CPF_STAT_BUSY(x) (((x) >> 28) & 0x03) -#define C_00821C_GRBM_CPF_STAT_BUSY 0xCFFFFFFF -#define S_00821C_CPC_CPF_BUSY(x) (((x) & 0x1) << 30) -#define G_00821C_CPC_CPF_BUSY(x) (((x) >> 30) & 0x1) -#define C_00821C_CPC_CPF_BUSY 0xBFFFFFFF -#define S_00821C_CPF_BUSY(x) (((x) & 0x1) << 31) -#define G_00821C_CPF_BUSY(x) (((x) >> 31) & 0x1) -#define C_00821C_CPF_BUSY 0x7FFFFFFF -#define R_008220_CP_CPF_BUSY_STAT 0x008220 -#define S_008220_REG_BUS_FIFO_BUSY(x) (((x) & 0x1) << 0) -#define G_008220_REG_BUS_FIFO_BUSY(x) (((x) >> 0) & 0x1) -#define C_008220_REG_BUS_FIFO_BUSY 0xFFFFFFFE -#define S_008220_CSF_RING_BUSY(x) (((x) & 0x1) << 1) -#define G_008220_CSF_RING_BUSY(x) (((x) >> 1) & 0x1) -#define C_008220_CSF_RING_BUSY 0xFFFFFFFD -#define S_008220_CSF_INDIRECT1_BUSY(x) (((x) & 0x1) << 2) -#define G_008220_CSF_INDIRECT1_BUSY(x) (((x) >> 2) & 0x1) -#define C_008220_CSF_INDIRECT1_BUSY 0xFFFFFFFB -#define S_008220_CSF_INDIRECT2_BUSY(x) (((x) & 0x1) << 3) -#define G_008220_CSF_INDIRECT2_BUSY(x) (((x) >> 3) & 0x1) -#define C_008220_CSF_INDIRECT2_BUSY 0xFFFFFFF7 -#define S_008220_CSF_STATE_BUSY(x) (((x) & 0x1) << 4) -#define G_008220_CSF_STATE_BUSY(x) (((x) >> 4) & 0x1) -#define C_008220_CSF_STATE_BUSY 0xFFFFFFEF -#define S_008220_CSF_CE_INDR1_BUSY(x) (((x) & 0x1) << 5) -#define G_008220_CSF_CE_INDR1_BUSY(x) (((x) >> 5) & 0x1) -#define C_008220_CSF_CE_INDR1_BUSY 0xFFFFFFDF -#define S_008220_CSF_CE_INDR2_BUSY(x) (((x) & 0x1) << 6) -#define G_008220_CSF_CE_INDR2_BUSY(x) (((x) >> 6) & 0x1) -#define C_008220_CSF_CE_INDR2_BUSY 0xFFFFFFBF -#define S_008220_CSF_ARBITER_BUSY(x) (((x) & 0x1) << 7) -#define G_008220_CSF_ARBITER_BUSY(x) (((x) >> 7) & 0x1) -#define C_008220_CSF_ARBITER_BUSY 0xFFFFFF7F -#define S_008220_CSF_INPUT_BUSY(x) (((x) & 0x1) << 8) -#define G_008220_CSF_INPUT_BUSY(x) (((x) >> 8) & 0x1) -#define C_008220_CSF_INPUT_BUSY 0xFFFFFEFF -#define S_008220_OUTSTANDING_READ_TAGS(x) (((x) & 0x1) << 9) -#define G_008220_OUTSTANDING_READ_TAGS(x) (((x) >> 9) & 0x1) -#define C_008220_OUTSTANDING_READ_TAGS 0xFFFFFDFF -#define S_008220_HPD_PROCESSING_EOP_BUSY(x) (((x) & 0x1) << 11) -#define G_008220_HPD_PROCESSING_EOP_BUSY(x) (((x) >> 11) & 0x1) -#define C_008220_HPD_PROCESSING_EOP_BUSY 0xFFFFF7FF -#define S_008220_HQD_DISPATCH_BUSY(x) (((x) & 0x1) << 12) -#define G_008220_HQD_DISPATCH_BUSY(x) (((x) >> 12) & 0x1) -#define C_008220_HQD_DISPATCH_BUSY 0xFFFFEFFF -#define S_008220_HQD_IQ_TIMER_BUSY(x) (((x) & 0x1) << 13) -#define G_008220_HQD_IQ_TIMER_BUSY(x) (((x) >> 13) & 0x1) -#define C_008220_HQD_IQ_TIMER_BUSY 0xFFFFDFFF -#define S_008220_HQD_DMA_OFFLOAD_BUSY(x) (((x) & 0x1) << 14) -#define G_008220_HQD_DMA_OFFLOAD_BUSY(x) (((x) >> 14) & 0x1) -#define C_008220_HQD_DMA_OFFLOAD_BUSY 0xFFFFBFFF -#define S_008220_HQD_WAIT_SEMAPHORE_BUSY(x) (((x) & 0x1) << 15) -#define G_008220_HQD_WAIT_SEMAPHORE_BUSY(x) (((x) >> 15) & 0x1) -#define C_008220_HQD_WAIT_SEMAPHORE_BUSY 0xFFFF7FFF -#define S_008220_HQD_SIGNAL_SEMAPHORE_BUSY(x) (((x) & 0x1) << 16) -#define G_008220_HQD_SIGNAL_SEMAPHORE_BUSY(x) (((x) >> 16) & 0x1) -#define C_008220_HQD_SIGNAL_SEMAPHORE_BUSY 0xFFFEFFFF -#define S_008220_HQD_MESSAGE_BUSY(x) (((x) & 0x1) << 17) -#define G_008220_HQD_MESSAGE_BUSY(x) (((x) >> 17) & 0x1) -#define C_008220_HQD_MESSAGE_BUSY 0xFFFDFFFF -#define S_008220_HQD_PQ_FETCHER_BUSY(x) (((x) & 0x1) << 18) -#define G_008220_HQD_PQ_FETCHER_BUSY(x) (((x) >> 18) & 0x1) -#define C_008220_HQD_PQ_FETCHER_BUSY 0xFFFBFFFF -#define S_008220_HQD_IB_FETCHER_BUSY(x) (((x) & 0x1) << 19) -#define G_008220_HQD_IB_FETCHER_BUSY(x) (((x) >> 19) & 0x1) -#define C_008220_HQD_IB_FETCHER_BUSY 0xFFF7FFFF -#define S_008220_HQD_IQ_FETCHER_BUSY(x) (((x) & 0x1) << 20) -#define G_008220_HQD_IQ_FETCHER_BUSY(x) (((x) >> 20) & 0x1) -#define C_008220_HQD_IQ_FETCHER_BUSY 0xFFEFFFFF -#define S_008220_HQD_EOP_FETCHER_BUSY(x) (((x) & 0x1) << 21) -#define G_008220_HQD_EOP_FETCHER_BUSY(x) (((x) >> 21) & 0x1) -#define C_008220_HQD_EOP_FETCHER_BUSY 0xFFDFFFFF -#define S_008220_HQD_CONSUMED_RPTR_BUSY(x) (((x) & 0x1) << 22) -#define G_008220_HQD_CONSUMED_RPTR_BUSY(x) (((x) >> 22) & 0x1) -#define C_008220_HQD_CONSUMED_RPTR_BUSY 0xFFBFFFFF -#define S_008220_HQD_FETCHER_ARB_BUSY(x) (((x) & 0x1) << 23) -#define G_008220_HQD_FETCHER_ARB_BUSY(x) (((x) >> 23) & 0x1) -#define C_008220_HQD_FETCHER_ARB_BUSY 0xFF7FFFFF -#define S_008220_HQD_ROQ_ALIGN_BUSY(x) (((x) & 0x1) << 24) -#define G_008220_HQD_ROQ_ALIGN_BUSY(x) (((x) >> 24) & 0x1) -#define C_008220_HQD_ROQ_ALIGN_BUSY 0xFEFFFFFF -#define S_008220_HQD_ROQ_EOP_BUSY(x) (((x) & 0x1) << 25) -#define G_008220_HQD_ROQ_EOP_BUSY(x) (((x) >> 25) & 0x1) -#define C_008220_HQD_ROQ_EOP_BUSY 0xFDFFFFFF -#define S_008220_HQD_ROQ_IQ_BUSY(x) (((x) & 0x1) << 26) -#define G_008220_HQD_ROQ_IQ_BUSY(x) (((x) >> 26) & 0x1) -#define C_008220_HQD_ROQ_IQ_BUSY 0xFBFFFFFF -#define S_008220_HQD_ROQ_PQ_BUSY(x) (((x) & 0x1) << 27) -#define G_008220_HQD_ROQ_PQ_BUSY(x) (((x) >> 27) & 0x1) -#define C_008220_HQD_ROQ_PQ_BUSY 0xF7FFFFFF -#define S_008220_HQD_ROQ_IB_BUSY(x) (((x) & 0x1) << 28) -#define G_008220_HQD_ROQ_IB_BUSY(x) (((x) >> 28) & 0x1) -#define C_008220_HQD_ROQ_IB_BUSY 0xEFFFFFFF -#define S_008220_HQD_WPTR_POLL_BUSY(x) (((x) & 0x1) << 29) -#define G_008220_HQD_WPTR_POLL_BUSY(x) (((x) >> 29) & 0x1) -#define C_008220_HQD_WPTR_POLL_BUSY 0xDFFFFFFF -#define S_008220_HQD_PQ_BUSY(x) (((x) & 0x1) << 30) -#define G_008220_HQD_PQ_BUSY(x) (((x) >> 30) & 0x1) -#define C_008220_HQD_PQ_BUSY 0xBFFFFFFF -#define S_008220_HQD_IB_BUSY(x) (((x) & 0x1) << 31) -#define G_008220_HQD_IB_BUSY(x) (((x) >> 31) & 0x1) -#define C_008220_HQD_IB_BUSY 0x7FFFFFFF -#define R_008224_CP_CPF_STALLED_STAT1 0x008224 -#define S_008224_RING_FETCHING_DATA(x) (((x) & 0x1) << 0) -#define G_008224_RING_FETCHING_DATA(x) (((x) >> 0) & 0x1) -#define C_008224_RING_FETCHING_DATA 0xFFFFFFFE -#define S_008224_INDR1_FETCHING_DATA(x) (((x) & 0x1) << 1) -#define G_008224_INDR1_FETCHING_DATA(x) (((x) >> 1) & 0x1) -#define C_008224_INDR1_FETCHING_DATA 0xFFFFFFFD -#define S_008224_INDR2_FETCHING_DATA(x) (((x) & 0x1) << 2) -#define G_008224_INDR2_FETCHING_DATA(x) (((x) >> 2) & 0x1) -#define C_008224_INDR2_FETCHING_DATA 0xFFFFFFFB -#define S_008224_STATE_FETCHING_DATA(x) (((x) & 0x1) << 3) -#define G_008224_STATE_FETCHING_DATA(x) (((x) >> 3) & 0x1) -#define C_008224_STATE_FETCHING_DATA 0xFFFFFFF7 -#define S_008224_TCIU_WAITING_ON_FREE(x) (((x) & 0x1) << 5) -#define G_008224_TCIU_WAITING_ON_FREE(x) (((x) >> 5) & 0x1) -#define C_008224_TCIU_WAITING_ON_FREE 0xFFFFFFDF -#define S_008224_TCIU_WAITING_ON_TAGS(x) (((x) & 0x1) << 6) -#define G_008224_TCIU_WAITING_ON_TAGS(x) (((x) >> 6) & 0x1) -#define C_008224_TCIU_WAITING_ON_TAGS 0xFFFFFFBF -#define S_008224_ATCL2IU_WAITING_ON_FREE(x) (((x) & 0x1) << 7) -#define G_008224_ATCL2IU_WAITING_ON_FREE(x) (((x) >> 7) & 0x1) -#define C_008224_ATCL2IU_WAITING_ON_FREE 0xFFFFFF7F -#define S_008224_ATCL2IU_WAITING_ON_TAGS(x) (((x) & 0x1) << 8) -#define G_008224_ATCL2IU_WAITING_ON_TAGS(x) (((x) >> 8) & 0x1) -#define C_008224_ATCL2IU_WAITING_ON_TAGS 0xFFFFFEFF -#define S_008224_ATCL1_WAITING_ON_TRANS(x) (((x) & 0x1) << 9) -#define G_008224_ATCL1_WAITING_ON_TRANS(x) (((x) >> 9) & 0x1) -#define C_008224_ATCL1_WAITING_ON_TRANS 0xFFFFFDFF -#define R_030230_CP_COHER_SIZE_HI 0x030230 -#define S_030230_COHER_SIZE_HI_256B(x) (((x) & 0xFF) << 0) -#define G_030230_COHER_SIZE_HI_256B(x) (((x) >> 0) & 0xFF) -#define C_030230_COHER_SIZE_HI_256B 0xFFFFFF00 -/* */ -#define R_0088B0_VGT_VTX_VECT_EJECT_REG 0x0088B0 -#define S_0088B0_PRIM_COUNT(x) (((x) & 0x3FF) << 0) -#define G_0088B0_PRIM_COUNT(x) (((x) >> 0) & 0x3FF) -#define C_0088B0_PRIM_COUNT 0xFFFFFC00 -#define R_0088C4_VGT_CACHE_INVALIDATION 0x0088C4 -#define S_0088C4_VS_NO_EXTRA_BUFFER(x) (((x) & 0x1) << 5) -#define G_0088C4_VS_NO_EXTRA_BUFFER(x) (((x) >> 5) & 0x1) -#define C_0088C4_VS_NO_EXTRA_BUFFER 0xFFFFFFDF -#define S_0088C4_STREAMOUT_FULL_FLUSH(x) (((x) & 0x1) << 13) -#define G_0088C4_STREAMOUT_FULL_FLUSH(x) (((x) >> 13) & 0x1) -#define C_0088C4_STREAMOUT_FULL_FLUSH 0xFFFFDFFF -#define S_0088C4_ES_LIMIT(x) (((x) & 0x1F) << 16) -#define G_0088C4_ES_LIMIT(x) (((x) >> 16) & 0x1F) -#define C_0088C4_ES_LIMIT 0xFFE0FFFF -#define R_0088C8_VGT_ESGS_RING_SIZE 0x0088C8 -#define R_0088CC_VGT_GSVS_RING_SIZE 0x0088CC -#define R_0088D4_VGT_GS_VERTEX_REUSE 0x0088D4 -#define S_0088D4_VERT_REUSE(x) (((x) & 0x1F) << 0) -#define G_0088D4_VERT_REUSE(x) (((x) >> 0) & 0x1F) -#define C_0088D4_VERT_REUSE 0xFFFFFFE0 -#define R_008958_VGT_PRIMITIVE_TYPE 0x008958 -#define S_008958_PRIM_TYPE(x) (((x) & 0x3F) << 0) -#define G_008958_PRIM_TYPE(x) (((x) >> 0) & 0x3F) -#define C_008958_PRIM_TYPE 0xFFFFFFC0 -#define V_008958_DI_PT_NONE 0x00 -#define V_008958_DI_PT_POINTLIST 0x01 -#define V_008958_DI_PT_LINELIST 0x02 -#define V_008958_DI_PT_LINESTRIP 0x03 -#define V_008958_DI_PT_TRILIST 0x04 -#define V_008958_DI_PT_TRIFAN 0x05 -#define V_008958_DI_PT_TRISTRIP 0x06 -#define V_008958_DI_PT_UNUSED_0 0x07 -#define V_008958_DI_PT_UNUSED_1 0x08 -#define V_008958_DI_PT_PATCH 0x09 -#define V_008958_DI_PT_LINELIST_ADJ 0x0A -#define V_008958_DI_PT_LINESTRIP_ADJ 0x0B -#define V_008958_DI_PT_TRILIST_ADJ 0x0C -#define V_008958_DI_PT_TRISTRIP_ADJ 0x0D -#define V_008958_DI_PT_UNUSED_3 0x0E -#define V_008958_DI_PT_UNUSED_4 0x0F -#define V_008958_DI_PT_TRI_WITH_WFLAGS 0x10 -#define V_008958_DI_PT_RECTLIST 0x11 -#define V_008958_DI_PT_LINELOOP 0x12 -#define V_008958_DI_PT_QUADLIST 0x13 -#define V_008958_DI_PT_QUADSTRIP 0x14 -#define V_008958_DI_PT_POLYGON 0x15 -#define V_008958_DI_PT_2D_COPY_RECT_LIST_V0 0x16 -#define V_008958_DI_PT_2D_COPY_RECT_LIST_V1 0x17 -#define V_008958_DI_PT_2D_COPY_RECT_LIST_V2 0x18 -#define V_008958_DI_PT_2D_COPY_RECT_LIST_V3 0x19 -#define V_008958_DI_PT_2D_FILL_RECT_LIST 0x1A -#define V_008958_DI_PT_2D_LINE_STRIP 0x1B -#define V_008958_DI_PT_2D_TRI_STRIP 0x1C -#define R_00895C_VGT_INDEX_TYPE 0x00895C -#define S_00895C_INDEX_TYPE(x) (((x) & 0x03) << 0) -#define G_00895C_INDEX_TYPE(x) (((x) >> 0) & 0x03) -#define C_00895C_INDEX_TYPE 0xFFFFFFFC -#define V_00895C_DI_INDEX_SIZE_16_BIT 0x00 -#define V_00895C_DI_INDEX_SIZE_32_BIT 0x01 -#define R_008960_VGT_STRMOUT_BUFFER_FILLED_SIZE_0 0x008960 -#define R_008964_VGT_STRMOUT_BUFFER_FILLED_SIZE_1 0x008964 -#define R_008968_VGT_STRMOUT_BUFFER_FILLED_SIZE_2 0x008968 -#define R_00896C_VGT_STRMOUT_BUFFER_FILLED_SIZE_3 0x00896C -#define R_008970_VGT_NUM_INDICES 0x008970 -#define R_008974_VGT_NUM_INSTANCES 0x008974 -#define R_008988_VGT_TF_RING_SIZE 0x008988 -#define S_008988_SIZE(x) (((x) & 0xFFFF) << 0) -#define G_008988_SIZE(x) (((x) >> 0) & 0xFFFF) -#define C_008988_SIZE 0xFFFF0000 -#define R_0089B0_VGT_HS_OFFCHIP_PARAM 0x0089B0 -#define S_0089B0_OFFCHIP_BUFFERING(x) (((x) & 0x7F) << 0) -#define G_0089B0_OFFCHIP_BUFFERING(x) (((x) >> 0) & 0x7F) -#define C_0089B0_OFFCHIP_BUFFERING 0xFFFFFF80 -#define R_0089B8_VGT_TF_MEMORY_BASE 0x0089B8 -#define R_008A14_PA_CL_ENHANCE 0x008A14 -#define S_008A14_CLIP_VTX_REORDER_ENA(x) (((x) & 0x1) << 0) -#define G_008A14_CLIP_VTX_REORDER_ENA(x) (((x) >> 0) & 0x1) -#define C_008A14_CLIP_VTX_REORDER_ENA 0xFFFFFFFE -#define S_008A14_NUM_CLIP_SEQ(x) (((x) & 0x03) << 1) -#define G_008A14_NUM_CLIP_SEQ(x) (((x) >> 1) & 0x03) -#define C_008A14_NUM_CLIP_SEQ 0xFFFFFFF9 -#define S_008A14_CLIPPED_PRIM_SEQ_STALL(x) (((x) & 0x1) << 3) -#define G_008A14_CLIPPED_PRIM_SEQ_STALL(x) (((x) >> 3) & 0x1) -#define C_008A14_CLIPPED_PRIM_SEQ_STALL 0xFFFFFFF7 -#define S_008A14_VE_NAN_PROC_DISABLE(x) (((x) & 0x1) << 4) -#define G_008A14_VE_NAN_PROC_DISABLE(x) (((x) >> 4) & 0x1) -#define C_008A14_VE_NAN_PROC_DISABLE 0xFFFFFFEF -#define R_008A60_PA_SU_LINE_STIPPLE_VALUE 0x008A60 -#define S_008A60_LINE_STIPPLE_VALUE(x) (((x) & 0xFFFFFF) << 0) -#define G_008A60_LINE_STIPPLE_VALUE(x) (((x) >> 0) & 0xFFFFFF) -#define C_008A60_LINE_STIPPLE_VALUE 0xFF000000 -#define R_008B10_PA_SC_LINE_STIPPLE_STATE 0x008B10 -#define S_008B10_CURRENT_PTR(x) (((x) & 0x0F) << 0) -#define G_008B10_CURRENT_PTR(x) (((x) >> 0) & 0x0F) -#define C_008B10_CURRENT_PTR 0xFFFFFFF0 -#define S_008B10_CURRENT_COUNT(x) (((x) & 0xFF) << 8) -#define G_008B10_CURRENT_COUNT(x) (((x) >> 8) & 0xFF) -#define C_008B10_CURRENT_COUNT 0xFFFF00FF -#define R_008670_CP_STALLED_STAT3 0x008670 -#define S_008670_CE_TO_CSF_NOT_RDY_TO_RCV(x) (((x) & 0x1) << 0) -#define G_008670_CE_TO_CSF_NOT_RDY_TO_RCV(x) (((x) >> 0) & 0x1) -#define C_008670_CE_TO_CSF_NOT_RDY_TO_RCV 0xFFFFFFFE -#define S_008670_CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV(x) (((x) & 0x1) << 1) -#define G_008670_CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV(x) (((x) >> 1) & 0x1) -#define C_008670_CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV 0xFFFFFFFD -#define S_008670_CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER(x) (((x) & 0x1) << 2) -#define G_008670_CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER(x) (((x) >> 2) & 0x1) -#define C_008670_CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER 0xFFFFFFFB -#define S_008670_CE_TO_RAM_INIT_NOT_RDY(x) (((x) & 0x1) << 3) -#define G_008670_CE_TO_RAM_INIT_NOT_RDY(x) (((x) >> 3) & 0x1) -#define C_008670_CE_TO_RAM_INIT_NOT_RDY 0xFFFFFFF7 -#define S_008670_CE_TO_RAM_DUMP_NOT_RDY(x) (((x) & 0x1) << 4) -#define G_008670_CE_TO_RAM_DUMP_NOT_RDY(x) (((x) >> 4) & 0x1) -#define C_008670_CE_TO_RAM_DUMP_NOT_RDY 0xFFFFFFEF -#define S_008670_CE_TO_RAM_WRITE_NOT_RDY(x) (((x) & 0x1) << 5) -#define G_008670_CE_TO_RAM_WRITE_NOT_RDY(x) (((x) >> 5) & 0x1) -#define C_008670_CE_TO_RAM_WRITE_NOT_RDY 0xFFFFFFDF -#define S_008670_CE_TO_INC_FIFO_NOT_RDY_TO_RCV(x) (((x) & 0x1) << 6) -#define G_008670_CE_TO_INC_FIFO_NOT_RDY_TO_RCV(x) (((x) >> 6) & 0x1) -#define C_008670_CE_TO_INC_FIFO_NOT_RDY_TO_RCV 0xFFFFFFBF -#define S_008670_CE_TO_WR_FIFO_NOT_RDY_TO_RCV(x) (((x) & 0x1) << 7) -#define G_008670_CE_TO_WR_FIFO_NOT_RDY_TO_RCV(x) (((x) >> 7) & 0x1) -#define C_008670_CE_TO_WR_FIFO_NOT_RDY_TO_RCV 0xFFFFFF7F -#define S_008670_CE_WAITING_ON_BUFFER_DATA(x) (((x) & 0x1) << 10) -#define G_008670_CE_WAITING_ON_BUFFER_DATA(x) (((x) >> 10) & 0x1) -#define C_008670_CE_WAITING_ON_BUFFER_DATA 0xFFFFFBFF -#define S_008670_CE_WAITING_ON_CE_BUFFER_FLAG(x) (((x) & 0x1) << 11) -#define G_008670_CE_WAITING_ON_CE_BUFFER_FLAG(x) (((x) >> 11) & 0x1) -#define C_008670_CE_WAITING_ON_CE_BUFFER_FLAG 0xFFFFF7FF -#define S_008670_CE_WAITING_ON_DE_COUNTER(x) (((x) & 0x1) << 12) -#define G_008670_CE_WAITING_ON_DE_COUNTER(x) (((x) >> 12) & 0x1) -#define C_008670_CE_WAITING_ON_DE_COUNTER 0xFFFFEFFF -#define S_008670_CE_WAITING_ON_DE_COUNTER_UNDERFLOW(x) (((x) & 0x1) << 13) -#define G_008670_CE_WAITING_ON_DE_COUNTER_UNDERFLOW(x) (((x) >> 13) & 0x1) -#define C_008670_CE_WAITING_ON_DE_COUNTER_UNDERFLOW 0xFFFFDFFF -#define S_008670_TCIU_WAITING_ON_FREE(x) (((x) & 0x1) << 14) -#define G_008670_TCIU_WAITING_ON_FREE(x) (((x) >> 14) & 0x1) -#define C_008670_TCIU_WAITING_ON_FREE 0xFFFFBFFF -#define S_008670_TCIU_WAITING_ON_TAGS(x) (((x) & 0x1) << 15) -#define G_008670_TCIU_WAITING_ON_TAGS(x) (((x) >> 15) & 0x1) -#define C_008670_TCIU_WAITING_ON_TAGS 0xFFFF7FFF -#define S_008670_CE_STALLED_ON_TC_WR_CONFIRM(x) (((x) & 0x1) << 16) -#define G_008670_CE_STALLED_ON_TC_WR_CONFIRM(x) (((x) >> 16) & 0x1) -#define C_008670_CE_STALLED_ON_TC_WR_CONFIRM 0xFFFEFFFF -#define S_008670_CE_STALLED_ON_ATOMIC_RTN_DATA(x) (((x) & 0x1) << 17) -#define G_008670_CE_STALLED_ON_ATOMIC_RTN_DATA(x) (((x) >> 17) & 0x1) -#define C_008670_CE_STALLED_ON_ATOMIC_RTN_DATA 0xFFFDFFFF -#define S_008670_ATCL2IU_WAITING_ON_FREE(x) (((x) & 0x1) << 18) -#define G_008670_ATCL2IU_WAITING_ON_FREE(x) (((x) >> 18) & 0x1) -#define C_008670_ATCL2IU_WAITING_ON_FREE 0xFFFBFFFF -#define S_008670_ATCL2IU_WAITING_ON_TAGS(x) (((x) & 0x1) << 19) -#define G_008670_ATCL2IU_WAITING_ON_TAGS(x) (((x) >> 19) & 0x1) -#define C_008670_ATCL2IU_WAITING_ON_TAGS 0xFFF7FFFF -#define S_008670_ATCL1_WAITING_ON_TRANS(x) (((x) & 0x1) << 20) -#define G_008670_ATCL1_WAITING_ON_TRANS(x) (((x) >> 20) & 0x1) -#define C_008670_ATCL1_WAITING_ON_TRANS 0xFFEFFFFF -#define R_008674_CP_STALLED_STAT1 0x008674 -#define S_008674_RBIU_TO_DMA_NOT_RDY_TO_RCV(x) (((x) & 0x1) << 0) -#define G_008674_RBIU_TO_DMA_NOT_RDY_TO_RCV(x) (((x) >> 0) & 0x1) -#define C_008674_RBIU_TO_DMA_NOT_RDY_TO_RCV 0xFFFFFFFE -#define S_008674_RBIU_TO_SEM_NOT_RDY_TO_RCV(x) (((x) & 0x1) << 2) -#define G_008674_RBIU_TO_SEM_NOT_RDY_TO_RCV(x) (((x) >> 2) & 0x1) -#define C_008674_RBIU_TO_SEM_NOT_RDY_TO_RCV 0xFFFFFFFB -#define S_008674_RBIU_TO_MEMWR_NOT_RDY_TO_RCV(x) (((x) & 0x1) << 4) -#define G_008674_RBIU_TO_MEMWR_NOT_RDY_TO_RCV(x) (((x) >> 4) & 0x1) -#define C_008674_RBIU_TO_MEMWR_NOT_RDY_TO_RCV 0xFFFFFFEF -#define S_008674_ME_HAS_ACTIVE_CE_BUFFER_FLAG(x) (((x) & 0x1) << 10) -#define G_008674_ME_HAS_ACTIVE_CE_BUFFER_FLAG(x) (((x) >> 10) & 0x1) -#define C_008674_ME_HAS_ACTIVE_CE_BUFFER_FLAG 0xFFFFFBFF -#define S_008674_ME_HAS_ACTIVE_DE_BUFFER_FLAG(x) (((x) & 0x1) << 11) -#define G_008674_ME_HAS_ACTIVE_DE_BUFFER_FLAG(x) (((x) >> 11) & 0x1) -#define C_008674_ME_HAS_ACTIVE_DE_BUFFER_FLAG 0xFFFFF7FF -#define S_008674_ME_STALLED_ON_TC_WR_CONFIRM(x) (((x) & 0x1) << 12) -#define G_008674_ME_STALLED_ON_TC_WR_CONFIRM(x) (((x) >> 12) & 0x1) -#define C_008674_ME_STALLED_ON_TC_WR_CONFIRM 0xFFFFEFFF -#define S_008674_ME_STALLED_ON_ATOMIC_RTN_DATA(x) (((x) & 0x1) << 13) -#define G_008674_ME_STALLED_ON_ATOMIC_RTN_DATA(x) (((x) >> 13) & 0x1) -#define C_008674_ME_STALLED_ON_ATOMIC_RTN_DATA 0xFFFFDFFF -#define S_008674_ME_WAITING_ON_TC_READ_DATA(x) (((x) & 0x1) << 14) -#define G_008674_ME_WAITING_ON_TC_READ_DATA(x) (((x) >> 14) & 0x1) -#define C_008674_ME_WAITING_ON_TC_READ_DATA 0xFFFFBFFF -#define S_008674_ME_WAITING_ON_REG_READ_DATA(x) (((x) & 0x1) << 15) -#define G_008674_ME_WAITING_ON_REG_READ_DATA(x) (((x) >> 15) & 0x1) -#define C_008674_ME_WAITING_ON_REG_READ_DATA 0xFFFF7FFF -#define S_008674_RCIU_WAITING_ON_GDS_FREE(x) (((x) & 0x1) << 23) -#define G_008674_RCIU_WAITING_ON_GDS_FREE(x) (((x) >> 23) & 0x1) -#define C_008674_RCIU_WAITING_ON_GDS_FREE 0xFF7FFFFF -#define S_008674_RCIU_WAITING_ON_GRBM_FREE(x) (((x) & 0x1) << 24) -#define G_008674_RCIU_WAITING_ON_GRBM_FREE(x) (((x) >> 24) & 0x1) -#define C_008674_RCIU_WAITING_ON_GRBM_FREE 0xFEFFFFFF -#define S_008674_RCIU_WAITING_ON_VGT_FREE(x) (((x) & 0x1) << 25) -#define G_008674_RCIU_WAITING_ON_VGT_FREE(x) (((x) >> 25) & 0x1) -#define C_008674_RCIU_WAITING_ON_VGT_FREE 0xFDFFFFFF -#define S_008674_RCIU_STALLED_ON_ME_READ(x) (((x) & 0x1) << 26) -#define G_008674_RCIU_STALLED_ON_ME_READ(x) (((x) >> 26) & 0x1) -#define C_008674_RCIU_STALLED_ON_ME_READ 0xFBFFFFFF -#define S_008674_RCIU_STALLED_ON_DMA_READ(x) (((x) & 0x1) << 27) -#define G_008674_RCIU_STALLED_ON_DMA_READ(x) (((x) >> 27) & 0x1) -#define C_008674_RCIU_STALLED_ON_DMA_READ 0xF7FFFFFF -#define S_008674_RCIU_STALLED_ON_APPEND_READ(x) (((x) & 0x1) << 28) -#define G_008674_RCIU_STALLED_ON_APPEND_READ(x) (((x) >> 28) & 0x1) -#define C_008674_RCIU_STALLED_ON_APPEND_READ 0xEFFFFFFF -#define S_008674_RCIU_HALTED_BY_REG_VIOLATION(x) (((x) & 0x1) << 29) -#define G_008674_RCIU_HALTED_BY_REG_VIOLATION(x) (((x) >> 29) & 0x1) -#define C_008674_RCIU_HALTED_BY_REG_VIOLATION 0xDFFFFFFF -#define R_008678_CP_STALLED_STAT2 0x008678 -#define S_008678_PFP_TO_CSF_NOT_RDY_TO_RCV(x) (((x) & 0x1) << 0) -#define G_008678_PFP_TO_CSF_NOT_RDY_TO_RCV(x) (((x) >> 0) & 0x1) -#define C_008678_PFP_TO_CSF_NOT_RDY_TO_RCV 0xFFFFFFFE -#define S_008678_PFP_TO_MEQ_NOT_RDY_TO_RCV(x) (((x) & 0x1) << 1) -#define G_008678_PFP_TO_MEQ_NOT_RDY_TO_RCV(x) (((x) >> 1) & 0x1) -#define C_008678_PFP_TO_MEQ_NOT_RDY_TO_RCV 0xFFFFFFFD -#define S_008678_PFP_TO_RCIU_NOT_RDY_TO_RCV(x) (((x) & 0x1) << 2) -#define G_008678_PFP_TO_RCIU_NOT_RDY_TO_RCV(x) (((x) >> 2) & 0x1) -#define C_008678_PFP_TO_RCIU_NOT_RDY_TO_RCV 0xFFFFFFFB -#define S_008678_PFP_TO_VGT_WRITES_PENDING(x) (((x) & 0x1) << 4) -#define G_008678_PFP_TO_VGT_WRITES_PENDING(x) (((x) >> 4) & 0x1) -#define C_008678_PFP_TO_VGT_WRITES_PENDING 0xFFFFFFEF -#define S_008678_PFP_RCIU_READ_PENDING(x) (((x) & 0x1) << 5) -#define G_008678_PFP_RCIU_READ_PENDING(x) (((x) >> 5) & 0x1) -#define C_008678_PFP_RCIU_READ_PENDING 0xFFFFFFDF -#define S_008678_PFP_WAITING_ON_BUFFER_DATA(x) (((x) & 0x1) << 8) -#define G_008678_PFP_WAITING_ON_BUFFER_DATA(x) (((x) >> 8) & 0x1) -#define C_008678_PFP_WAITING_ON_BUFFER_DATA 0xFFFFFEFF -#define S_008678_ME_WAIT_ON_CE_COUNTER(x) (((x) & 0x1) << 9) -#define G_008678_ME_WAIT_ON_CE_COUNTER(x) (((x) >> 9) & 0x1) -#define C_008678_ME_WAIT_ON_CE_COUNTER 0xFFFFFDFF -#define S_008678_ME_WAIT_ON_AVAIL_BUFFER(x) (((x) & 0x1) << 10) -#define G_008678_ME_WAIT_ON_AVAIL_BUFFER(x) (((x) >> 10) & 0x1) -#define C_008678_ME_WAIT_ON_AVAIL_BUFFER 0xFFFFFBFF -#define S_008678_GFX_CNTX_NOT_AVAIL_TO_ME(x) (((x) & 0x1) << 11) -#define G_008678_GFX_CNTX_NOT_AVAIL_TO_ME(x) (((x) >> 11) & 0x1) -#define C_008678_GFX_CNTX_NOT_AVAIL_TO_ME 0xFFFFF7FF -#define S_008678_ME_RCIU_NOT_RDY_TO_RCV(x) (((x) & 0x1) << 12) -#define G_008678_ME_RCIU_NOT_RDY_TO_RCV(x) (((x) >> 12) & 0x1) -#define C_008678_ME_RCIU_NOT_RDY_TO_RCV 0xFFFFEFFF -#define S_008678_ME_TO_CONST_NOT_RDY_TO_RCV(x) (((x) & 0x1) << 13) -#define G_008678_ME_TO_CONST_NOT_RDY_TO_RCV(x) (((x) >> 13) & 0x1) -#define C_008678_ME_TO_CONST_NOT_RDY_TO_RCV 0xFFFFDFFF -#define S_008678_ME_WAITING_DATA_FROM_PFP(x) (((x) & 0x1) << 14) -#define G_008678_ME_WAITING_DATA_FROM_PFP(x) (((x) >> 14) & 0x1) -#define C_008678_ME_WAITING_DATA_FROM_PFP 0xFFFFBFFF -#define S_008678_ME_WAITING_ON_PARTIAL_FLUSH(x) (((x) & 0x1) << 15) -#define G_008678_ME_WAITING_ON_PARTIAL_FLUSH(x) (((x) >> 15) & 0x1) -#define C_008678_ME_WAITING_ON_PARTIAL_FLUSH 0xFFFF7FFF -#define S_008678_MEQ_TO_ME_NOT_RDY_TO_RCV(x) (((x) & 0x1) << 16) -#define G_008678_MEQ_TO_ME_NOT_RDY_TO_RCV(x) (((x) >> 16) & 0x1) -#define C_008678_MEQ_TO_ME_NOT_RDY_TO_RCV 0xFFFEFFFF -#define S_008678_STQ_TO_ME_NOT_RDY_TO_RCV(x) (((x) & 0x1) << 17) -#define G_008678_STQ_TO_ME_NOT_RDY_TO_RCV(x) (((x) >> 17) & 0x1) -#define C_008678_STQ_TO_ME_NOT_RDY_TO_RCV 0xFFFDFFFF -#define S_008678_ME_WAITING_DATA_FROM_STQ(x) (((x) & 0x1) << 18) -#define G_008678_ME_WAITING_DATA_FROM_STQ(x) (((x) >> 18) & 0x1) -#define C_008678_ME_WAITING_DATA_FROM_STQ 0xFFFBFFFF -#define S_008678_PFP_STALLED_ON_TC_WR_CONFIRM(x) (((x) & 0x1) << 19) -#define G_008678_PFP_STALLED_ON_TC_WR_CONFIRM(x) (((x) >> 19) & 0x1) -#define C_008678_PFP_STALLED_ON_TC_WR_CONFIRM 0xFFF7FFFF -#define S_008678_PFP_STALLED_ON_ATOMIC_RTN_DATA(x) (((x) & 0x1) << 20) -#define G_008678_PFP_STALLED_ON_ATOMIC_RTN_DATA(x) (((x) >> 20) & 0x1) -#define C_008678_PFP_STALLED_ON_ATOMIC_RTN_DATA 0xFFEFFFFF -#define S_008678_EOPD_FIFO_NEEDS_SC_EOP_DONE(x) (((x) & 0x1) << 21) -#define G_008678_EOPD_FIFO_NEEDS_SC_EOP_DONE(x) (((x) >> 21) & 0x1) -#define C_008678_EOPD_FIFO_NEEDS_SC_EOP_DONE 0xFFDFFFFF -#define S_008678_EOPD_FIFO_NEEDS_WR_CONFIRM(x) (((x) & 0x1) << 22) -#define G_008678_EOPD_FIFO_NEEDS_WR_CONFIRM(x) (((x) >> 22) & 0x1) -#define C_008678_EOPD_FIFO_NEEDS_WR_CONFIRM 0xFFBFFFFF -#define S_008678_STRMO_WR_OF_PRIM_DATA_PENDING(x) (((x) & 0x1) << 23) -#define G_008678_STRMO_WR_OF_PRIM_DATA_PENDING(x) (((x) >> 23) & 0x1) -#define C_008678_STRMO_WR_OF_PRIM_DATA_PENDING 0xFF7FFFFF -#define S_008678_PIPE_STATS_WR_DATA_PENDING(x) (((x) & 0x1) << 24) -#define G_008678_PIPE_STATS_WR_DATA_PENDING(x) (((x) >> 24) & 0x1) -#define C_008678_PIPE_STATS_WR_DATA_PENDING 0xFEFFFFFF -#define S_008678_APPEND_RDY_WAIT_ON_CS_DONE(x) (((x) & 0x1) << 25) -#define G_008678_APPEND_RDY_WAIT_ON_CS_DONE(x) (((x) >> 25) & 0x1) -#define C_008678_APPEND_RDY_WAIT_ON_CS_DONE 0xFDFFFFFF -#define S_008678_APPEND_RDY_WAIT_ON_PS_DONE(x) (((x) & 0x1) << 26) -#define G_008678_APPEND_RDY_WAIT_ON_PS_DONE(x) (((x) >> 26) & 0x1) -#define C_008678_APPEND_RDY_WAIT_ON_PS_DONE 0xFBFFFFFF -#define S_008678_APPEND_WAIT_ON_WR_CONFIRM(x) (((x) & 0x1) << 27) -#define G_008678_APPEND_WAIT_ON_WR_CONFIRM(x) (((x) >> 27) & 0x1) -#define C_008678_APPEND_WAIT_ON_WR_CONFIRM 0xF7FFFFFF -#define S_008678_APPEND_ACTIVE_PARTITION(x) (((x) & 0x1) << 28) -#define G_008678_APPEND_ACTIVE_PARTITION(x) (((x) >> 28) & 0x1) -#define C_008678_APPEND_ACTIVE_PARTITION 0xEFFFFFFF -#define S_008678_APPEND_WAITING_TO_SEND_MEMWRITE(x) (((x) & 0x1) << 29) -#define G_008678_APPEND_WAITING_TO_SEND_MEMWRITE(x) (((x) >> 29) & 0x1) -#define C_008678_APPEND_WAITING_TO_SEND_MEMWRITE 0xDFFFFFFF -#define S_008678_SURF_SYNC_NEEDS_IDLE_CNTXS(x) (((x) & 0x1) << 30) -#define G_008678_SURF_SYNC_NEEDS_IDLE_CNTXS(x) (((x) >> 30) & 0x1) -#define C_008678_SURF_SYNC_NEEDS_IDLE_CNTXS 0xBFFFFFFF -#define S_008678_SURF_SYNC_NEEDS_ALL_CLEAN(x) (((x) & 0x1) << 31) -#define G_008678_SURF_SYNC_NEEDS_ALL_CLEAN(x) (((x) >> 31) & 0x1) -#define C_008678_SURF_SYNC_NEEDS_ALL_CLEAN 0x7FFFFFFF -#define R_008680_CP_STAT 0x008680 -#define S_008680_ROQ_RING_BUSY(x) (((x) & 0x1) << 9) -#define G_008680_ROQ_RING_BUSY(x) (((x) >> 9) & 0x1) -#define C_008680_ROQ_RING_BUSY 0xFFFFFDFF -#define S_008680_ROQ_INDIRECT1_BUSY(x) (((x) & 0x1) << 10) -#define G_008680_ROQ_INDIRECT1_BUSY(x) (((x) >> 10) & 0x1) -#define C_008680_ROQ_INDIRECT1_BUSY 0xFFFFFBFF -#define S_008680_ROQ_INDIRECT2_BUSY(x) (((x) & 0x1) << 11) -#define G_008680_ROQ_INDIRECT2_BUSY(x) (((x) >> 11) & 0x1) -#define C_008680_ROQ_INDIRECT2_BUSY 0xFFFFF7FF -#define S_008680_ROQ_STATE_BUSY(x) (((x) & 0x1) << 12) -#define G_008680_ROQ_STATE_BUSY(x) (((x) >> 12) & 0x1) -#define C_008680_ROQ_STATE_BUSY 0xFFFFEFFF -#define S_008680_DC_BUSY(x) (((x) & 0x1) << 13) -#define G_008680_DC_BUSY(x) (((x) >> 13) & 0x1) -#define C_008680_DC_BUSY 0xFFFFDFFF -#define S_008680_ATCL2IU_BUSY(x) (((x) & 0x1) << 14) -#define G_008680_ATCL2IU_BUSY(x) (((x) >> 14) & 0x1) -#define C_008680_ATCL2IU_BUSY 0xFFFFBFFF -#define S_008680_PFP_BUSY(x) (((x) & 0x1) << 15) -#define G_008680_PFP_BUSY(x) (((x) >> 15) & 0x1) -#define C_008680_PFP_BUSY 0xFFFF7FFF -#define S_008680_MEQ_BUSY(x) (((x) & 0x1) << 16) -#define G_008680_MEQ_BUSY(x) (((x) >> 16) & 0x1) -#define C_008680_MEQ_BUSY 0xFFFEFFFF -#define S_008680_ME_BUSY(x) (((x) & 0x1) << 17) -#define G_008680_ME_BUSY(x) (((x) >> 17) & 0x1) -#define C_008680_ME_BUSY 0xFFFDFFFF -#define S_008680_QUERY_BUSY(x) (((x) & 0x1) << 18) -#define G_008680_QUERY_BUSY(x) (((x) >> 18) & 0x1) -#define C_008680_QUERY_BUSY 0xFFFBFFFF -#define S_008680_SEMAPHORE_BUSY(x) (((x) & 0x1) << 19) -#define G_008680_SEMAPHORE_BUSY(x) (((x) >> 19) & 0x1) -#define C_008680_SEMAPHORE_BUSY 0xFFF7FFFF -#define S_008680_INTERRUPT_BUSY(x) (((x) & 0x1) << 20) -#define G_008680_INTERRUPT_BUSY(x) (((x) >> 20) & 0x1) -#define C_008680_INTERRUPT_BUSY 0xFFEFFFFF -#define S_008680_SURFACE_SYNC_BUSY(x) (((x) & 0x1) << 21) -#define G_008680_SURFACE_SYNC_BUSY(x) (((x) >> 21) & 0x1) -#define C_008680_SURFACE_SYNC_BUSY 0xFFDFFFFF -#define S_008680_DMA_BUSY(x) (((x) & 0x1) << 22) -#define G_008680_DMA_BUSY(x) (((x) >> 22) & 0x1) -#define C_008680_DMA_BUSY 0xFFBFFFFF -#define S_008680_RCIU_BUSY(x) (((x) & 0x1) << 23) -#define G_008680_RCIU_BUSY(x) (((x) >> 23) & 0x1) -#define C_008680_RCIU_BUSY 0xFF7FFFFF -#define S_008680_SCRATCH_RAM_BUSY(x) (((x) & 0x1) << 24) -#define G_008680_SCRATCH_RAM_BUSY(x) (((x) >> 24) & 0x1) -#define C_008680_SCRATCH_RAM_BUSY 0xFEFFFFFF -#define S_008680_CPC_CPG_BUSY(x) (((x) & 0x1) << 25) -#define G_008680_CPC_CPG_BUSY(x) (((x) >> 25) & 0x1) -#define C_008680_CPC_CPG_BUSY 0xFDFFFFFF -#define S_008680_CE_BUSY(x) (((x) & 0x1) << 26) -#define G_008680_CE_BUSY(x) (((x) >> 26) & 0x1) -#define C_008680_CE_BUSY 0xFBFFFFFF -#define S_008680_TCIU_BUSY(x) (((x) & 0x1) << 27) -#define G_008680_TCIU_BUSY(x) (((x) >> 27) & 0x1) -#define C_008680_TCIU_BUSY 0xF7FFFFFF -#define S_008680_ROQ_CE_RING_BUSY(x) (((x) & 0x1) << 28) -#define G_008680_ROQ_CE_RING_BUSY(x) (((x) >> 28) & 0x1) -#define C_008680_ROQ_CE_RING_BUSY 0xEFFFFFFF -#define S_008680_ROQ_CE_INDIRECT1_BUSY(x) (((x) & 0x1) << 29) -#define G_008680_ROQ_CE_INDIRECT1_BUSY(x) (((x) >> 29) & 0x1) -#define C_008680_ROQ_CE_INDIRECT1_BUSY 0xDFFFFFFF -#define S_008680_ROQ_CE_INDIRECT2_BUSY(x) (((x) & 0x1) << 30) -#define G_008680_ROQ_CE_INDIRECT2_BUSY(x) (((x) >> 30) & 0x1) -#define C_008680_ROQ_CE_INDIRECT2_BUSY 0xBFFFFFFF -#define S_008680_CP_BUSY(x) (((x) & 0x1) << 31) -#define G_008680_CP_BUSY(x) (((x) >> 31) & 0x1) -#define C_008680_CP_BUSY 0x7FFFFFFF -/* CIK */ -#define R_030800_GRBM_GFX_INDEX 0x030800 -#define S_030800_INSTANCE_INDEX(x) (((x) & 0xFF) << 0) -#define G_030800_INSTANCE_INDEX(x) (((x) >> 0) & 0xFF) -#define C_030800_INSTANCE_INDEX 0xFFFFFF00 -#define S_030800_SH_INDEX(x) (((x) & 0xFF) << 8) -#define G_030800_SH_INDEX(x) (((x) >> 8) & 0xFF) -#define C_030800_SH_INDEX 0xFFFF00FF -#define S_030800_SE_INDEX(x) (((x) & 0xFF) << 16) -#define G_030800_SE_INDEX(x) (((x) >> 16) & 0xFF) -#define C_030800_SE_INDEX 0xFF00FFFF -#define S_030800_SH_BROADCAST_WRITES(x) (((x) & 0x1) << 29) -#define G_030800_SH_BROADCAST_WRITES(x) (((x) >> 29) & 0x1) -#define C_030800_SH_BROADCAST_WRITES 0xDFFFFFFF -#define S_030800_INSTANCE_BROADCAST_WRITES(x) (((x) & 0x1) << 30) -#define G_030800_INSTANCE_BROADCAST_WRITES(x) (((x) >> 30) & 0x1) -#define C_030800_INSTANCE_BROADCAST_WRITES 0xBFFFFFFF -#define S_030800_SE_BROADCAST_WRITES(x) (((x) & 0x1) << 31) -#define G_030800_SE_BROADCAST_WRITES(x) (((x) >> 31) & 0x1) -#define C_030800_SE_BROADCAST_WRITES 0x7FFFFFFF -#define R_030900_VGT_ESGS_RING_SIZE 0x030900 -#define R_030904_VGT_GSVS_RING_SIZE 0x030904 -#define R_030908_VGT_PRIMITIVE_TYPE 0x030908 -#define S_030908_PRIM_TYPE(x) (((x) & 0x3F) << 0) -#define G_030908_PRIM_TYPE(x) (((x) >> 0) & 0x3F) -#define C_030908_PRIM_TYPE 0xFFFFFFC0 -#define V_030908_DI_PT_NONE 0x00 -#define V_030908_DI_PT_POINTLIST 0x01 -#define V_030908_DI_PT_LINELIST 0x02 -#define V_030908_DI_PT_LINESTRIP 0x03 -#define V_030908_DI_PT_TRILIST 0x04 -#define V_030908_DI_PT_TRIFAN 0x05 -#define V_030908_DI_PT_TRISTRIP 0x06 -#define V_030908_DI_PT_PATCH 0x09 -#define V_030908_DI_PT_LINELIST_ADJ 0x0A -#define V_030908_DI_PT_LINESTRIP_ADJ 0x0B -#define V_030908_DI_PT_TRILIST_ADJ 0x0C -#define V_030908_DI_PT_TRISTRIP_ADJ 0x0D -#define V_030908_DI_PT_TRI_WITH_WFLAGS 0x10 -#define V_030908_DI_PT_RECTLIST 0x11 -#define V_030908_DI_PT_LINELOOP 0x12 -#define V_030908_DI_PT_QUADLIST 0x13 -#define V_030908_DI_PT_QUADSTRIP 0x14 -#define V_030908_DI_PT_POLYGON 0x15 -#define V_030908_DI_PT_2D_COPY_RECT_LIST_V0 0x16 -#define V_030908_DI_PT_2D_COPY_RECT_LIST_V1 0x17 -#define V_030908_DI_PT_2D_COPY_RECT_LIST_V2 0x18 -#define V_030908_DI_PT_2D_COPY_RECT_LIST_V3 0x19 -#define V_030908_DI_PT_2D_FILL_RECT_LIST 0x1A -#define V_030908_DI_PT_2D_LINE_STRIP 0x1B -#define V_030908_DI_PT_2D_TRI_STRIP 0x1C -#define R_03090C_VGT_INDEX_TYPE 0x03090C -#define S_03090C_INDEX_TYPE(x) (((x) & 0x03) << 0) -#define G_03090C_INDEX_TYPE(x) (((x) >> 0) & 0x03) -#define C_03090C_INDEX_TYPE 0xFFFFFFFC -#define V_03090C_DI_INDEX_SIZE_16_BIT 0x00 -#define V_03090C_DI_INDEX_SIZE_32_BIT 0x01 -#define R_030910_VGT_STRMOUT_BUFFER_FILLED_SIZE_0 0x030910 -#define R_030914_VGT_STRMOUT_BUFFER_FILLED_SIZE_1 0x030914 -#define R_030918_VGT_STRMOUT_BUFFER_FILLED_SIZE_2 0x030918 -#define R_03091C_VGT_STRMOUT_BUFFER_FILLED_SIZE_3 0x03091C -#define R_030930_VGT_NUM_INDICES 0x030930 -#define R_030934_VGT_NUM_INSTANCES 0x030934 -#define R_030938_VGT_TF_RING_SIZE 0x030938 -#define S_030938_SIZE(x) (((x) & 0xFFFF) << 0) -#define G_030938_SIZE(x) (((x) >> 0) & 0xFFFF) -#define C_030938_SIZE 0xFFFF0000 -#define R_03093C_VGT_HS_OFFCHIP_PARAM 0x03093C -#define S_03093C_OFFCHIP_BUFFERING(x) (((x) & 0x1FF) << 0) -#define G_03093C_OFFCHIP_BUFFERING(x) (((x) >> 0) & 0x1FF) -#define C_03093C_OFFCHIP_BUFFERING 0xFFFFFE00 -#define S_03093C_OFFCHIP_GRANULARITY(x) (((x) & 0x03) << 9) -#define G_03093C_OFFCHIP_GRANULARITY(x) (((x) >> 9) & 0x03) -#define C_03093C_OFFCHIP_GRANULARITY 0xFFFFF9FF -#define V_03093C_X_8K_DWORDS 0x00 -#define V_03093C_X_4K_DWORDS 0x01 -#define V_03093C_X_2K_DWORDS 0x02 -#define V_03093C_X_1K_DWORDS 0x03 -#define R_030940_VGT_TF_MEMORY_BASE 0x030940 -#define R_030A00_PA_SU_LINE_STIPPLE_VALUE 0x030A00 -#define S_030A00_LINE_STIPPLE_VALUE(x) (((x) & 0xFFFFFF) << 0) -#define G_030A00_LINE_STIPPLE_VALUE(x) (((x) >> 0) & 0xFFFFFF) -#define C_030A00_LINE_STIPPLE_VALUE 0xFF000000 -#define R_030A04_PA_SC_LINE_STIPPLE_STATE 0x030A04 -#define S_030A04_CURRENT_PTR(x) (((x) & 0x0F) << 0) -#define G_030A04_CURRENT_PTR(x) (((x) >> 0) & 0x0F) -#define C_030A04_CURRENT_PTR 0xFFFFFFF0 -#define S_030A04_CURRENT_COUNT(x) (((x) & 0xFF) << 8) -#define G_030A04_CURRENT_COUNT(x) (((x) >> 8) & 0xFF) -#define C_030A04_CURRENT_COUNT 0xFFFF00FF -#define R_030A10_PA_SC_SCREEN_EXTENT_MIN_0 0x030A10 -#define S_030A10_X(x) (((x) & 0xFFFF) << 0) -#define G_030A10_X(x) (((x) >> 0) & 0xFFFF) -#define C_030A10_X 0xFFFF0000 -#define S_030A10_Y(x) (((x) & 0xFFFF) << 16) -#define G_030A10_Y(x) (((x) >> 16) & 0xFFFF) -#define C_030A10_Y 0x0000FFFF -#define R_030A14_PA_SC_SCREEN_EXTENT_MAX_0 0x030A14 -#define S_030A14_X(x) (((x) & 0xFFFF) << 0) -#define G_030A14_X(x) (((x) >> 0) & 0xFFFF) -#define C_030A14_X 0xFFFF0000 -#define S_030A14_Y(x) (((x) & 0xFFFF) << 16) -#define G_030A14_Y(x) (((x) >> 16) & 0xFFFF) -#define C_030A14_Y 0x0000FFFF -#define R_030A18_PA_SC_SCREEN_EXTENT_MIN_1 0x030A18 -#define S_030A18_X(x) (((x) & 0xFFFF) << 0) -#define G_030A18_X(x) (((x) >> 0) & 0xFFFF) -#define C_030A18_X 0xFFFF0000 -#define S_030A18_Y(x) (((x) & 0xFFFF) << 16) -#define G_030A18_Y(x) (((x) >> 16) & 0xFFFF) -#define C_030A18_Y 0x0000FFFF -#define R_030A2C_PA_SC_SCREEN_EXTENT_MAX_1 0x030A2C -#define S_030A2C_X(x) (((x) & 0xFFFF) << 0) -#define G_030A2C_X(x) (((x) >> 0) & 0xFFFF) -#define C_030A2C_X 0xFFFF0000 -#define S_030A2C_Y(x) (((x) & 0xFFFF) << 16) -#define G_030A2C_Y(x) (((x) >> 16) & 0xFFFF) -#define C_030A2C_Y 0x0000FFFF -/* */ -#define R_008BF0_PA_SC_ENHANCE 0x008BF0 -#define S_008BF0_ENABLE_PA_SC_OUT_OF_ORDER(x) (((x) & 0x1) << 0) -#define G_008BF0_ENABLE_PA_SC_OUT_OF_ORDER(x) (((x) >> 0) & 0x1) -#define C_008BF0_ENABLE_PA_SC_OUT_OF_ORDER 0xFFFFFFFE -#define S_008BF0_DISABLE_SC_DB_TILE_FIX(x) (((x) & 0x1) << 1) -#define G_008BF0_DISABLE_SC_DB_TILE_FIX(x) (((x) >> 1) & 0x1) -#define C_008BF0_DISABLE_SC_DB_TILE_FIX 0xFFFFFFFD -#define S_008BF0_DISABLE_AA_MASK_FULL_FIX(x) (((x) & 0x1) << 2) -#define G_008BF0_DISABLE_AA_MASK_FULL_FIX(x) (((x) >> 2) & 0x1) -#define C_008BF0_DISABLE_AA_MASK_FULL_FIX 0xFFFFFFFB -#define S_008BF0_ENABLE_1XMSAA_SAMPLE_LOCATIONS(x) (((x) & 0x1) << 3) -#define G_008BF0_ENABLE_1XMSAA_SAMPLE_LOCATIONS(x) (((x) >> 3) & 0x1) -#define C_008BF0_ENABLE_1XMSAA_SAMPLE_LOCATIONS 0xFFFFFFF7 -#define S_008BF0_ENABLE_1XMSAA_SAMPLE_LOC_CENTROID(x) (((x) & 0x1) << 4) -#define G_008BF0_ENABLE_1XMSAA_SAMPLE_LOC_CENTROID(x) (((x) >> 4) & 0x1) -#define C_008BF0_ENABLE_1XMSAA_SAMPLE_LOC_CENTROID 0xFFFFFFEF -#define S_008BF0_DISABLE_SCISSOR_FIX(x) (((x) & 0x1) << 5) -#define G_008BF0_DISABLE_SCISSOR_FIX(x) (((x) >> 5) & 0x1) -#define C_008BF0_DISABLE_SCISSOR_FIX 0xFFFFFFDF -#define S_008BF0_DISABLE_PW_BUBBLE_COLLAPSE(x) (((x) & 0x03) << 6) -#define G_008BF0_DISABLE_PW_BUBBLE_COLLAPSE(x) (((x) >> 6) & 0x03) -#define C_008BF0_DISABLE_PW_BUBBLE_COLLAPSE 0xFFFFFF3F -#define S_008BF0_SEND_UNLIT_STILES_TO_PACKER(x) (((x) & 0x1) << 8) -#define G_008BF0_SEND_UNLIT_STILES_TO_PACKER(x) (((x) >> 8) & 0x1) -#define C_008BF0_SEND_UNLIT_STILES_TO_PACKER 0xFFFFFEFF -#define S_008BF0_DISABLE_DUALGRAD_PERF_OPTIMIZATION(x) (((x) & 0x1) << 9) -#define G_008BF0_DISABLE_DUALGRAD_PERF_OPTIMIZATION(x) (((x) >> 9) & 0x1) -#define C_008BF0_DISABLE_DUALGRAD_PERF_OPTIMIZATION 0xFFFFFDFF -#define R_008C08_SQC_CACHES 0x008C08 -#define S_008C08_INST_INVALIDATE(x) (((x) & 0x1) << 0) -#define G_008C08_INST_INVALIDATE(x) (((x) >> 0) & 0x1) -#define C_008C08_INST_INVALIDATE 0xFFFFFFFE -#define S_008C08_DATA_INVALIDATE(x) (((x) & 0x1) << 1) -#define G_008C08_DATA_INVALIDATE(x) (((x) >> 1) & 0x1) -#define C_008C08_DATA_INVALIDATE 0xFFFFFFFD -/* CIK */ -#define R_030D20_SQC_CACHES 0x030D20 -#define S_030D20_INST_INVALIDATE(x) (((x) & 0x1) << 0) -#define G_030D20_INST_INVALIDATE(x) (((x) >> 0) & 0x1) -#define C_030D20_INST_INVALIDATE 0xFFFFFFFE -#define S_030D20_DATA_INVALIDATE(x) (((x) & 0x1) << 1) -#define G_030D20_DATA_INVALIDATE(x) (((x) >> 1) & 0x1) -#define C_030D20_DATA_INVALIDATE 0xFFFFFFFD -#define S_030D20_INVALIDATE_VOLATILE(x) (((x) & 0x1) << 2) -#define G_030D20_INVALIDATE_VOLATILE(x) (((x) >> 2) & 0x1) -#define C_030D20_INVALIDATE_VOLATILE 0xFFFFFFFB -/* */ -#define R_008C0C_SQ_RANDOM_WAVE_PRI 0x008C0C -#define S_008C0C_RET(x) (((x) & 0x7F) << 0) -#define G_008C0C_RET(x) (((x) >> 0) & 0x7F) -#define C_008C0C_RET 0xFFFFFF80 -#define S_008C0C_RUI(x) (((x) & 0x07) << 7) -#define G_008C0C_RUI(x) (((x) >> 7) & 0x07) -#define C_008C0C_RUI 0xFFFFFC7F -#define S_008C0C_RNG(x) (((x) & 0x7FF) << 10) -#define G_008C0C_RNG(x) (((x) >> 10) & 0x7FF) -#define C_008C0C_RNG 0xFFE003FF -#if 0 -/* CIK */ -#define R_008DFC_SQ_FLAT_1 0x008DFC -#define S_008DFC_ADDR(x) (((x) & 0xFF) << 0) -#define G_008DFC_ADDR(x) (((x) >> 0) & 0xFF) -#define C_008DFC_ADDR 0xFFFFFF00 -#define V_008DFC_SQ_VGPR 0x00 -#define S_008DFC_DATA(x) (((x) & 0xFF) << 8) -#define G_008DFC_DATA(x) (((x) >> 8) & 0xFF) -#define C_008DFC_DATA 0xFFFF00FF -#define V_008DFC_SQ_VGPR 0x00 -#define S_008DFC_TFE(x) (((x) & 0x1) << 23) -#define G_008DFC_TFE(x) (((x) >> 23) & 0x1) -#define C_008DFC_TFE 0xFF7FFFFF -#define S_008DFC_VDST(x) (((x) & 0xFF) << 24) -#define G_008DFC_VDST(x) (((x) >> 24) & 0xFF) -#define C_008DFC_VDST 0x00FFFFFF -#define V_008DFC_SQ_VGPR 0x00 -/* */ -#define R_008DFC_SQ_INST 0x008DFC -#define R_030D20_SQC_CACHES 0x030D20 -#define S_030D20_TARGET_INST(x) (((x) & 0x1) << 0) -#define G_030D20_TARGET_INST(x) (((x) >> 0) & 0x1) -#define C_030D20_TARGET_INST 0xFFFFFFFE -#define S_030D20_TARGET_DATA(x) (((x) & 0x1) << 1) -#define G_030D20_TARGET_DATA(x) (((x) >> 1) & 0x1) -#define C_030D20_TARGET_DATA 0xFFFFFFFD -#define S_030D20_INVALIDATE(x) (((x) & 0x1) << 2) -#define G_030D20_INVALIDATE(x) (((x) >> 2) & 0x1) -#define C_030D20_INVALIDATE 0xFFFFFFFB -#define S_030D20_WRITEBACK(x) (((x) & 0x1) << 3) -#define G_030D20_WRITEBACK(x) (((x) >> 3) & 0x1) -#define C_030D20_WRITEBACK 0xFFFFFFF7 -#define S_030D20_VOL(x) (((x) & 0x1) << 4) -#define G_030D20_VOL(x) (((x) >> 4) & 0x1) -#define C_030D20_VOL 0xFFFFFFEF -#define S_030D20_COMPLETE(x) (((x) & 0x1) << 16) -#define G_030D20_COMPLETE(x) (((x) >> 16) & 0x1) -#define C_030D20_COMPLETE 0xFFFEFFFF -#define R_030D24_SQC_WRITEBACK 0x030D24 -#define S_030D24_DWB(x) (((x) & 0x1) << 0) -#define G_030D24_DWB(x) (((x) >> 0) & 0x1) -#define C_030D24_DWB 0xFFFFFFFE -#define S_030D24_DIRTY(x) (((x) & 0x1) << 1) -#define G_030D24_DIRTY(x) (((x) >> 1) & 0x1) -#define C_030D24_DIRTY 0xFFFFFFFD -#define R_008DFC_SQ_VOP1 0x008DFC -#define S_008DFC_SRC0(x) (((x) & 0x1FF) << 0) -#define G_008DFC_SRC0(x) (((x) >> 0) & 0x1FF) -#define C_008DFC_SRC0 0xFFFFFE00 -#define V_008DFC_SQ_SGPR 0x00 -/* CIK */ -#define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68 -#define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69 -/* */ -#define V_008DFC_SQ_VCC_LO 0x6A -#define V_008DFC_SQ_VCC_HI 0x6B -#define V_008DFC_SQ_TBA_LO 0x6C -#define V_008DFC_SQ_TBA_HI 0x6D -#define V_008DFC_SQ_TMA_LO 0x6E -#define V_008DFC_SQ_TMA_HI 0x6F -#define V_008DFC_SQ_TTMP0 0x70 -#define V_008DFC_SQ_TTMP1 0x71 -#define V_008DFC_SQ_TTMP2 0x72 -#define V_008DFC_SQ_TTMP3 0x73 -#define V_008DFC_SQ_TTMP4 0x74 -#define V_008DFC_SQ_TTMP5 0x75 -#define V_008DFC_SQ_TTMP6 0x76 -#define V_008DFC_SQ_TTMP7 0x77 -#define V_008DFC_SQ_TTMP8 0x78 -#define V_008DFC_SQ_TTMP9 0x79 -#define V_008DFC_SQ_TTMP10 0x7A -#define V_008DFC_SQ_TTMP11 0x7B -#define V_008DFC_SQ_M0 0x7C -#define V_008DFC_SQ_EXEC_LO 0x7E -#define V_008DFC_SQ_EXEC_HI 0x7F -#define V_008DFC_SQ_SRC_0 0x80 -#define V_008DFC_SQ_SRC_1_INT 0x81 -#define V_008DFC_SQ_SRC_2_INT 0x82 -#define V_008DFC_SQ_SRC_3_INT 0x83 -#define V_008DFC_SQ_SRC_4_INT 0x84 -#define V_008DFC_SQ_SRC_5_INT 0x85 -#define V_008DFC_SQ_SRC_6_INT 0x86 -#define V_008DFC_SQ_SRC_7_INT 0x87 -#define V_008DFC_SQ_SRC_8_INT 0x88 -#define V_008DFC_SQ_SRC_9_INT 0x89 -#define V_008DFC_SQ_SRC_10_INT 0x8A -#define V_008DFC_SQ_SRC_11_INT 0x8B -#define V_008DFC_SQ_SRC_12_INT 0x8C -#define V_008DFC_SQ_SRC_13_INT 0x8D -#define V_008DFC_SQ_SRC_14_INT 0x8E -#define V_008DFC_SQ_SRC_15_INT 0x8F -#define V_008DFC_SQ_SRC_16_INT 0x90 -#define V_008DFC_SQ_SRC_17_INT 0x91 -#define V_008DFC_SQ_SRC_18_INT 0x92 -#define V_008DFC_SQ_SRC_19_INT 0x93 -#define V_008DFC_SQ_SRC_20_INT 0x94 -#define V_008DFC_SQ_SRC_21_INT 0x95 -#define V_008DFC_SQ_SRC_22_INT 0x96 -#define V_008DFC_SQ_SRC_23_INT 0x97 -#define V_008DFC_SQ_SRC_24_INT 0x98 -#define V_008DFC_SQ_SRC_25_INT 0x99 -#define V_008DFC_SQ_SRC_26_INT 0x9A -#define V_008DFC_SQ_SRC_27_INT 0x9B -#define V_008DFC_SQ_SRC_28_INT 0x9C -#define V_008DFC_SQ_SRC_29_INT 0x9D -#define V_008DFC_SQ_SRC_30_INT 0x9E -#define V_008DFC_SQ_SRC_31_INT 0x9F -#define V_008DFC_SQ_SRC_32_INT 0xA0 -#define V_008DFC_SQ_SRC_33_INT 0xA1 -#define V_008DFC_SQ_SRC_34_INT 0xA2 -#define V_008DFC_SQ_SRC_35_INT 0xA3 -#define V_008DFC_SQ_SRC_36_INT 0xA4 -#define V_008DFC_SQ_SRC_37_INT 0xA5 -#define V_008DFC_SQ_SRC_38_INT 0xA6 -#define V_008DFC_SQ_SRC_39_INT 0xA7 -#define V_008DFC_SQ_SRC_40_INT 0xA8 -#define V_008DFC_SQ_SRC_41_INT 0xA9 -#define V_008DFC_SQ_SRC_42_INT 0xAA -#define V_008DFC_SQ_SRC_43_INT 0xAB -#define V_008DFC_SQ_SRC_44_INT 0xAC -#define V_008DFC_SQ_SRC_45_INT 0xAD -#define V_008DFC_SQ_SRC_46_INT 0xAE -#define V_008DFC_SQ_SRC_47_INT 0xAF -#define V_008DFC_SQ_SRC_48_INT 0xB0 -#define V_008DFC_SQ_SRC_49_INT 0xB1 -#define V_008DFC_SQ_SRC_50_INT 0xB2 -#define V_008DFC_SQ_SRC_51_INT 0xB3 -#define V_008DFC_SQ_SRC_52_INT 0xB4 -#define V_008DFC_SQ_SRC_53_INT 0xB5 -#define V_008DFC_SQ_SRC_54_INT 0xB6 -#define V_008DFC_SQ_SRC_55_INT 0xB7 -#define V_008DFC_SQ_SRC_56_INT 0xB8 -#define V_008DFC_SQ_SRC_57_INT 0xB9 -#define V_008DFC_SQ_SRC_58_INT 0xBA -#define V_008DFC_SQ_SRC_59_INT 0xBB -#define V_008DFC_SQ_SRC_60_INT 0xBC -#define V_008DFC_SQ_SRC_61_INT 0xBD -#define V_008DFC_SQ_SRC_62_INT 0xBE -#define V_008DFC_SQ_SRC_63_INT 0xBF -#define V_008DFC_SQ_SRC_64_INT 0xC0 -#define V_008DFC_SQ_SRC_M_1_INT 0xC1 -#define V_008DFC_SQ_SRC_M_2_INT 0xC2 -#define V_008DFC_SQ_SRC_M_3_INT 0xC3 -#define V_008DFC_SQ_SRC_M_4_INT 0xC4 -#define V_008DFC_SQ_SRC_M_5_INT 0xC5 -#define V_008DFC_SQ_SRC_M_6_INT 0xC6 -#define V_008DFC_SQ_SRC_M_7_INT 0xC7 -#define V_008DFC_SQ_SRC_M_8_INT 0xC8 -#define V_008DFC_SQ_SRC_M_9_INT 0xC9 -#define V_008DFC_SQ_SRC_M_10_INT 0xCA -#define V_008DFC_SQ_SRC_M_11_INT 0xCB -#define V_008DFC_SQ_SRC_M_12_INT 0xCC -#define V_008DFC_SQ_SRC_M_13_INT 0xCD -#define V_008DFC_SQ_SRC_M_14_INT 0xCE -#define V_008DFC_SQ_SRC_M_15_INT 0xCF -#define V_008DFC_SQ_SRC_M_16_INT 0xD0 -#define V_008DFC_SQ_SRC_0_5 0xF0 -#define V_008DFC_SQ_SRC_M_0_5 0xF1 -#define V_008DFC_SQ_SRC_1 0xF2 -#define V_008DFC_SQ_SRC_M_1 0xF3 -#define V_008DFC_SQ_SRC_2 0xF4 -#define V_008DFC_SQ_SRC_M_2 0xF5 -#define V_008DFC_SQ_SRC_4 0xF6 -#define V_008DFC_SQ_SRC_M_4 0xF7 -#define V_008DFC_SQ_SRC_VCCZ 0xFB -#define V_008DFC_SQ_SRC_EXECZ 0xFC -#define V_008DFC_SQ_SRC_SCC 0xFD -#define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE -#define V_008DFC_SQ_SRC_VGPR 0x100 -#define S_008DFC_OP(x) (((x) & 0xFF) << 9) -#define G_008DFC_OP(x) (((x) >> 9) & 0xFF) -#define C_008DFC_OP 0xFFFE01FF -#define V_008DFC_SQ_V_NOP 0x00 -#define V_008DFC_SQ_V_MOV_B32 0x01 -#define V_008DFC_SQ_V_READFIRSTLANE_B32 0x02 -#define V_008DFC_SQ_V_CVT_I32_F64 0x03 -#define V_008DFC_SQ_V_CVT_F64_I32 0x04 -#define V_008DFC_SQ_V_CVT_F32_I32 0x05 -#define V_008DFC_SQ_V_CVT_F32_U32 0x06 -#define V_008DFC_SQ_V_CVT_U32_F32 0x07 -#define V_008DFC_SQ_V_CVT_I32_F32 0x08 -#define V_008DFC_SQ_V_MOV_FED_B32 0x09 -#define V_008DFC_SQ_V_CVT_F16_F32 0x0A -#define V_008DFC_SQ_V_CVT_F32_F16 0x0B -#define V_008DFC_SQ_V_CVT_RPI_I32_F32 0x0C -#define V_008DFC_SQ_V_CVT_FLR_I32_F32 0x0D -#define V_008DFC_SQ_V_CVT_OFF_F32_I4 0x0E -#define V_008DFC_SQ_V_CVT_F32_F64 0x0F -#define V_008DFC_SQ_V_CVT_F64_F32 0x10 -#define V_008DFC_SQ_V_CVT_F32_UBYTE0 0x11 -#define V_008DFC_SQ_V_CVT_F32_UBYTE1 0x12 -#define V_008DFC_SQ_V_CVT_F32_UBYTE2 0x13 -#define V_008DFC_SQ_V_CVT_F32_UBYTE3 0x14 -#define V_008DFC_SQ_V_CVT_U32_F64 0x15 -#define V_008DFC_SQ_V_CVT_F64_U32 0x16 -/* CIK */ -#define V_008DFC_SQ_V_TRUNC_F64 0x17 -#define V_008DFC_SQ_V_CEIL_F64 0x18 -#define V_008DFC_SQ_V_RNDNE_F64 0x19 -#define V_008DFC_SQ_V_FLOOR_F64 0x1A -/* */ -#define V_008DFC_SQ_V_FRACT_F32 0x20 -#define V_008DFC_SQ_V_TRUNC_F32 0x21 -#define V_008DFC_SQ_V_CEIL_F32 0x22 -#define V_008DFC_SQ_V_RNDNE_F32 0x23 -#define V_008DFC_SQ_V_FLOOR_F32 0x24 -#define V_008DFC_SQ_V_EXP_F32 0x25 -#define V_008DFC_SQ_V_LOG_CLAMP_F32 0x26 -#define V_008DFC_SQ_V_LOG_F32 0x27 -#define V_008DFC_SQ_V_RCP_CLAMP_F32 0x28 -#define V_008DFC_SQ_V_RCP_LEGACY_F32 0x29 -#define V_008DFC_SQ_V_RCP_F32 0x2A -#define V_008DFC_SQ_V_RCP_IFLAG_F32 0x2B -#define V_008DFC_SQ_V_RSQ_CLAMP_F32 0x2C -#define V_008DFC_SQ_V_RSQ_LEGACY_F32 0x2D -#define V_008DFC_SQ_V_RSQ_F32 0x2E -#define V_008DFC_SQ_V_RCP_F64 0x2F -#define V_008DFC_SQ_V_RCP_CLAMP_F64 0x30 -#define V_008DFC_SQ_V_RSQ_F64 0x31 -#define V_008DFC_SQ_V_RSQ_CLAMP_F64 0x32 -#define V_008DFC_SQ_V_SQRT_F32 0x33 -#define V_008DFC_SQ_V_SQRT_F64 0x34 -#define V_008DFC_SQ_V_SIN_F32 0x35 -#define V_008DFC_SQ_V_COS_F32 0x36 -#define V_008DFC_SQ_V_NOT_B32 0x37 -#define V_008DFC_SQ_V_BFREV_B32 0x38 -#define V_008DFC_SQ_V_FFBH_U32 0x39 -#define V_008DFC_SQ_V_FFBL_B32 0x3A -#define V_008DFC_SQ_V_FFBH_I32 0x3B -#define V_008DFC_SQ_V_FREXP_EXP_I32_F64 0x3C -#define V_008DFC_SQ_V_FREXP_MANT_F64 0x3D -#define V_008DFC_SQ_V_FRACT_F64 0x3E -#define V_008DFC_SQ_V_FREXP_EXP_I32_F32 0x3F -#define V_008DFC_SQ_V_FREXP_MANT_F32 0x40 -#define V_008DFC_SQ_V_CLREXCP 0x41 -#define V_008DFC_SQ_V_MOVRELD_B32 0x42 -#define V_008DFC_SQ_V_MOVRELS_B32 0x43 -#define V_008DFC_SQ_V_MOVRELSD_B32 0x44 -/* CIK */ -#define V_008DFC_SQ_V_LOG_LEGACY_F32 0x45 -#define V_008DFC_SQ_V_EXP_LEGACY_F32 0x46 -/* */ -#define S_008DFC_VDST(x) (((x) & 0xFF) << 17) -#define G_008DFC_VDST(x) (((x) >> 17) & 0xFF) -#define C_008DFC_VDST 0xFE01FFFF -#define V_008DFC_SQ_VGPR 0x00 -#define S_008DFC_ENCODING(x) (((x) & 0x7F) << 25) -#define G_008DFC_ENCODING(x) (((x) >> 25) & 0x7F) -#define C_008DFC_ENCODING 0x01FFFFFF -#define V_008DFC_SQ_ENC_VOP1_FIELD 0x3F -#define R_008DFC_SQ_MIMG_1 0x008DFC -#define S_008DFC_VADDR(x) (((x) & 0xFF) << 0) -#define G_008DFC_VADDR(x) (((x) >> 0) & 0xFF) -#define C_008DFC_VADDR 0xFFFFFF00 -#define V_008DFC_SQ_VGPR 0x00 -#define S_008DFC_VDATA(x) (((x) & 0xFF) << 8) -#define G_008DFC_VDATA(x) (((x) >> 8) & 0xFF) -#define C_008DFC_VDATA 0xFFFF00FF -#define V_008DFC_SQ_VGPR 0x00 -#define S_008DFC_SRSRC(x) (((x) & 0x1F) << 16) -#define G_008DFC_SRSRC(x) (((x) >> 16) & 0x1F) -#define C_008DFC_SRSRC 0xFFE0FFFF -#define S_008DFC_SSAMP(x) (((x) & 0x1F) << 21) -#define G_008DFC_SSAMP(x) (((x) >> 21) & 0x1F) -#define C_008DFC_SSAMP 0xFC1FFFFF -#define R_008DFC_SQ_VOP3_1 0x008DFC -#define S_008DFC_SRC0(x) (((x) & 0x1FF) << 0) -#define G_008DFC_SRC0(x) (((x) >> 0) & 0x1FF) -#define C_008DFC_SRC0 0xFFFFFE00 -#define V_008DFC_SQ_SGPR 0x00 -/* CIK */ -#define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68 -#define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69 -/* */ -#define V_008DFC_SQ_VCC_LO 0x6A -#define V_008DFC_SQ_VCC_HI 0x6B -#define V_008DFC_SQ_TBA_LO 0x6C -#define V_008DFC_SQ_TBA_HI 0x6D -#define V_008DFC_SQ_TMA_LO 0x6E -#define V_008DFC_SQ_TMA_HI 0x6F -#define V_008DFC_SQ_TTMP0 0x70 -#define V_008DFC_SQ_TTMP1 0x71 -#define V_008DFC_SQ_TTMP2 0x72 -#define V_008DFC_SQ_TTMP3 0x73 -#define V_008DFC_SQ_TTMP4 0x74 -#define V_008DFC_SQ_TTMP5 0x75 -#define V_008DFC_SQ_TTMP6 0x76 -#define V_008DFC_SQ_TTMP7 0x77 -#define V_008DFC_SQ_TTMP8 0x78 -#define V_008DFC_SQ_TTMP9 0x79 -#define V_008DFC_SQ_TTMP10 0x7A -#define V_008DFC_SQ_TTMP11 0x7B -#define V_008DFC_SQ_M0 0x7C -#define V_008DFC_SQ_EXEC_LO 0x7E -#define V_008DFC_SQ_EXEC_HI 0x7F -#define V_008DFC_SQ_SRC_0 0x80 -#define V_008DFC_SQ_SRC_1_INT 0x81 -#define V_008DFC_SQ_SRC_2_INT 0x82 -#define V_008DFC_SQ_SRC_3_INT 0x83 -#define V_008DFC_SQ_SRC_4_INT 0x84 -#define V_008DFC_SQ_SRC_5_INT 0x85 -#define V_008DFC_SQ_SRC_6_INT 0x86 -#define V_008DFC_SQ_SRC_7_INT 0x87 -#define V_008DFC_SQ_SRC_8_INT 0x88 -#define V_008DFC_SQ_SRC_9_INT 0x89 -#define V_008DFC_SQ_SRC_10_INT 0x8A -#define V_008DFC_SQ_SRC_11_INT 0x8B -#define V_008DFC_SQ_SRC_12_INT 0x8C -#define V_008DFC_SQ_SRC_13_INT 0x8D -#define V_008DFC_SQ_SRC_14_INT 0x8E -#define V_008DFC_SQ_SRC_15_INT 0x8F -#define V_008DFC_SQ_SRC_16_INT 0x90 -#define V_008DFC_SQ_SRC_17_INT 0x91 -#define V_008DFC_SQ_SRC_18_INT 0x92 -#define V_008DFC_SQ_SRC_19_INT 0x93 -#define V_008DFC_SQ_SRC_20_INT 0x94 -#define V_008DFC_SQ_SRC_21_INT 0x95 -#define V_008DFC_SQ_SRC_22_INT 0x96 -#define V_008DFC_SQ_SRC_23_INT 0x97 -#define V_008DFC_SQ_SRC_24_INT 0x98 -#define V_008DFC_SQ_SRC_25_INT 0x99 -#define V_008DFC_SQ_SRC_26_INT 0x9A -#define V_008DFC_SQ_SRC_27_INT 0x9B -#define V_008DFC_SQ_SRC_28_INT 0x9C -#define V_008DFC_SQ_SRC_29_INT 0x9D -#define V_008DFC_SQ_SRC_30_INT 0x9E -#define V_008DFC_SQ_SRC_31_INT 0x9F -#define V_008DFC_SQ_SRC_32_INT 0xA0 -#define V_008DFC_SQ_SRC_33_INT 0xA1 -#define V_008DFC_SQ_SRC_34_INT 0xA2 -#define V_008DFC_SQ_SRC_35_INT 0xA3 -#define V_008DFC_SQ_SRC_36_INT 0xA4 -#define V_008DFC_SQ_SRC_37_INT 0xA5 -#define V_008DFC_SQ_SRC_38_INT 0xA6 -#define V_008DFC_SQ_SRC_39_INT 0xA7 -#define V_008DFC_SQ_SRC_40_INT 0xA8 -#define V_008DFC_SQ_SRC_41_INT 0xA9 -#define V_008DFC_SQ_SRC_42_INT 0xAA -#define V_008DFC_SQ_SRC_43_INT 0xAB -#define V_008DFC_SQ_SRC_44_INT 0xAC -#define V_008DFC_SQ_SRC_45_INT 0xAD -#define V_008DFC_SQ_SRC_46_INT 0xAE -#define V_008DFC_SQ_SRC_47_INT 0xAF -#define V_008DFC_SQ_SRC_48_INT 0xB0 -#define V_008DFC_SQ_SRC_49_INT 0xB1 -#define V_008DFC_SQ_SRC_50_INT 0xB2 -#define V_008DFC_SQ_SRC_51_INT 0xB3 -#define V_008DFC_SQ_SRC_52_INT 0xB4 -#define V_008DFC_SQ_SRC_53_INT 0xB5 -#define V_008DFC_SQ_SRC_54_INT 0xB6 -#define V_008DFC_SQ_SRC_55_INT 0xB7 -#define V_008DFC_SQ_SRC_56_INT 0xB8 -#define V_008DFC_SQ_SRC_57_INT 0xB9 -#define V_008DFC_SQ_SRC_58_INT 0xBA -#define V_008DFC_SQ_SRC_59_INT 0xBB -#define V_008DFC_SQ_SRC_60_INT 0xBC -#define V_008DFC_SQ_SRC_61_INT 0xBD -#define V_008DFC_SQ_SRC_62_INT 0xBE -#define V_008DFC_SQ_SRC_63_INT 0xBF -#define V_008DFC_SQ_SRC_64_INT 0xC0 -#define V_008DFC_SQ_SRC_M_1_INT 0xC1 -#define V_008DFC_SQ_SRC_M_2_INT 0xC2 -#define V_008DFC_SQ_SRC_M_3_INT 0xC3 -#define V_008DFC_SQ_SRC_M_4_INT 0xC4 -#define V_008DFC_SQ_SRC_M_5_INT 0xC5 -#define V_008DFC_SQ_SRC_M_6_INT 0xC6 -#define V_008DFC_SQ_SRC_M_7_INT 0xC7 -#define V_008DFC_SQ_SRC_M_8_INT 0xC8 -#define V_008DFC_SQ_SRC_M_9_INT 0xC9 -#define V_008DFC_SQ_SRC_M_10_INT 0xCA -#define V_008DFC_SQ_SRC_M_11_INT 0xCB -#define V_008DFC_SQ_SRC_M_12_INT 0xCC -#define V_008DFC_SQ_SRC_M_13_INT 0xCD -#define V_008DFC_SQ_SRC_M_14_INT 0xCE -#define V_008DFC_SQ_SRC_M_15_INT 0xCF -#define V_008DFC_SQ_SRC_M_16_INT 0xD0 -#define V_008DFC_SQ_SRC_0_5 0xF0 -#define V_008DFC_SQ_SRC_M_0_5 0xF1 -#define V_008DFC_SQ_SRC_1 0xF2 -#define V_008DFC_SQ_SRC_M_1 0xF3 -#define V_008DFC_SQ_SRC_2 0xF4 -#define V_008DFC_SQ_SRC_M_2 0xF5 -#define V_008DFC_SQ_SRC_4 0xF6 -#define V_008DFC_SQ_SRC_M_4 0xF7 -#define V_008DFC_SQ_SRC_VCCZ 0xFB -#define V_008DFC_SQ_SRC_EXECZ 0xFC -#define V_008DFC_SQ_SRC_SCC 0xFD -#define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE -#define V_008DFC_SQ_SRC_VGPR 0x100 -#define S_008DFC_SRC1(x) (((x) & 0x1FF) << 9) -#define G_008DFC_SRC1(x) (((x) >> 9) & 0x1FF) -#define C_008DFC_SRC1 0xFFFC01FF -#define V_008DFC_SQ_SGPR 0x00 -/* CIK */ -#define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68 -#define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69 -/* */ -#define V_008DFC_SQ_VCC_LO 0x6A -#define V_008DFC_SQ_VCC_HI 0x6B -#define V_008DFC_SQ_TBA_LO 0x6C -#define V_008DFC_SQ_TBA_HI 0x6D -#define V_008DFC_SQ_TMA_LO 0x6E -#define V_008DFC_SQ_TMA_HI 0x6F -#define V_008DFC_SQ_TTMP0 0x70 -#define V_008DFC_SQ_TTMP1 0x71 -#define V_008DFC_SQ_TTMP2 0x72 -#define V_008DFC_SQ_TTMP3 0x73 -#define V_008DFC_SQ_TTMP4 0x74 -#define V_008DFC_SQ_TTMP5 0x75 -#define V_008DFC_SQ_TTMP6 0x76 -#define V_008DFC_SQ_TTMP7 0x77 -#define V_008DFC_SQ_TTMP8 0x78 -#define V_008DFC_SQ_TTMP9 0x79 -#define V_008DFC_SQ_TTMP10 0x7A -#define V_008DFC_SQ_TTMP11 0x7B -#define V_008DFC_SQ_M0 0x7C -#define V_008DFC_SQ_EXEC_LO 0x7E -#define V_008DFC_SQ_EXEC_HI 0x7F -#define V_008DFC_SQ_SRC_0 0x80 -#define V_008DFC_SQ_SRC_1_INT 0x81 -#define V_008DFC_SQ_SRC_2_INT 0x82 -#define V_008DFC_SQ_SRC_3_INT 0x83 -#define V_008DFC_SQ_SRC_4_INT 0x84 -#define V_008DFC_SQ_SRC_5_INT 0x85 -#define V_008DFC_SQ_SRC_6_INT 0x86 -#define V_008DFC_SQ_SRC_7_INT 0x87 -#define V_008DFC_SQ_SRC_8_INT 0x88 -#define V_008DFC_SQ_SRC_9_INT 0x89 -#define V_008DFC_SQ_SRC_10_INT 0x8A -#define V_008DFC_SQ_SRC_11_INT 0x8B -#define V_008DFC_SQ_SRC_12_INT 0x8C -#define V_008DFC_SQ_SRC_13_INT 0x8D -#define V_008DFC_SQ_SRC_14_INT 0x8E -#define V_008DFC_SQ_SRC_15_INT 0x8F -#define V_008DFC_SQ_SRC_16_INT 0x90 -#define V_008DFC_SQ_SRC_17_INT 0x91 -#define V_008DFC_SQ_SRC_18_INT 0x92 -#define V_008DFC_SQ_SRC_19_INT 0x93 -#define V_008DFC_SQ_SRC_20_INT 0x94 -#define V_008DFC_SQ_SRC_21_INT 0x95 -#define V_008DFC_SQ_SRC_22_INT 0x96 -#define V_008DFC_SQ_SRC_23_INT 0x97 -#define V_008DFC_SQ_SRC_24_INT 0x98 -#define V_008DFC_SQ_SRC_25_INT 0x99 -#define V_008DFC_SQ_SRC_26_INT 0x9A -#define V_008DFC_SQ_SRC_27_INT 0x9B -#define V_008DFC_SQ_SRC_28_INT 0x9C -#define V_008DFC_SQ_SRC_29_INT 0x9D -#define V_008DFC_SQ_SRC_30_INT 0x9E -#define V_008DFC_SQ_SRC_31_INT 0x9F -#define V_008DFC_SQ_SRC_32_INT 0xA0 -#define V_008DFC_SQ_SRC_33_INT 0xA1 -#define V_008DFC_SQ_SRC_34_INT 0xA2 -#define V_008DFC_SQ_SRC_35_INT 0xA3 -#define V_008DFC_SQ_SRC_36_INT 0xA4 -#define V_008DFC_SQ_SRC_37_INT 0xA5 -#define V_008DFC_SQ_SRC_38_INT 0xA6 -#define V_008DFC_SQ_SRC_39_INT 0xA7 -#define V_008DFC_SQ_SRC_40_INT 0xA8 -#define V_008DFC_SQ_SRC_41_INT 0xA9 -#define V_008DFC_SQ_SRC_42_INT 0xAA -#define V_008DFC_SQ_SRC_43_INT 0xAB -#define V_008DFC_SQ_SRC_44_INT 0xAC -#define V_008DFC_SQ_SRC_45_INT 0xAD -#define V_008DFC_SQ_SRC_46_INT 0xAE -#define V_008DFC_SQ_SRC_47_INT 0xAF -#define V_008DFC_SQ_SRC_48_INT 0xB0 -#define V_008DFC_SQ_SRC_49_INT 0xB1 -#define V_008DFC_SQ_SRC_50_INT 0xB2 -#define V_008DFC_SQ_SRC_51_INT 0xB3 -#define V_008DFC_SQ_SRC_52_INT 0xB4 -#define V_008DFC_SQ_SRC_53_INT 0xB5 -#define V_008DFC_SQ_SRC_54_INT 0xB6 -#define V_008DFC_SQ_SRC_55_INT 0xB7 -#define V_008DFC_SQ_SRC_56_INT 0xB8 -#define V_008DFC_SQ_SRC_57_INT 0xB9 -#define V_008DFC_SQ_SRC_58_INT 0xBA -#define V_008DFC_SQ_SRC_59_INT 0xBB -#define V_008DFC_SQ_SRC_60_INT 0xBC -#define V_008DFC_SQ_SRC_61_INT 0xBD -#define V_008DFC_SQ_SRC_62_INT 0xBE -#define V_008DFC_SQ_SRC_63_INT 0xBF -#define V_008DFC_SQ_SRC_64_INT 0xC0 -#define V_008DFC_SQ_SRC_M_1_INT 0xC1 -#define V_008DFC_SQ_SRC_M_2_INT 0xC2 -#define V_008DFC_SQ_SRC_M_3_INT 0xC3 -#define V_008DFC_SQ_SRC_M_4_INT 0xC4 -#define V_008DFC_SQ_SRC_M_5_INT 0xC5 -#define V_008DFC_SQ_SRC_M_6_INT 0xC6 -#define V_008DFC_SQ_SRC_M_7_INT 0xC7 -#define V_008DFC_SQ_SRC_M_8_INT 0xC8 -#define V_008DFC_SQ_SRC_M_9_INT 0xC9 -#define V_008DFC_SQ_SRC_M_10_INT 0xCA -#define V_008DFC_SQ_SRC_M_11_INT 0xCB -#define V_008DFC_SQ_SRC_M_12_INT 0xCC -#define V_008DFC_SQ_SRC_M_13_INT 0xCD -#define V_008DFC_SQ_SRC_M_14_INT 0xCE -#define V_008DFC_SQ_SRC_M_15_INT 0xCF -#define V_008DFC_SQ_SRC_M_16_INT 0xD0 -#define V_008DFC_SQ_SRC_0_5 0xF0 -#define V_008DFC_SQ_SRC_M_0_5 0xF1 -#define V_008DFC_SQ_SRC_1 0xF2 -#define V_008DFC_SQ_SRC_M_1 0xF3 -#define V_008DFC_SQ_SRC_2 0xF4 -#define V_008DFC_SQ_SRC_M_2 0xF5 -#define V_008DFC_SQ_SRC_4 0xF6 -#define V_008DFC_SQ_SRC_M_4 0xF7 -#define V_008DFC_SQ_SRC_VCCZ 0xFB -#define V_008DFC_SQ_SRC_EXECZ 0xFC -#define V_008DFC_SQ_SRC_SCC 0xFD -#define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE -#define V_008DFC_SQ_SRC_VGPR 0x100 -#define S_008DFC_SRC2(x) (((x) & 0x1FF) << 18) -#define G_008DFC_SRC2(x) (((x) >> 18) & 0x1FF) -#define C_008DFC_SRC2 0xF803FFFF -#define V_008DFC_SQ_SGPR 0x00 -/* CIK */ -#define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68 -#define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69 -/* */ -#define V_008DFC_SQ_VCC_LO 0x6A -#define V_008DFC_SQ_VCC_HI 0x6B -#define V_008DFC_SQ_TBA_LO 0x6C -#define V_008DFC_SQ_TBA_HI 0x6D -#define V_008DFC_SQ_TMA_LO 0x6E -#define V_008DFC_SQ_TMA_HI 0x6F -#define V_008DFC_SQ_TTMP0 0x70 -#define V_008DFC_SQ_TTMP1 0x71 -#define V_008DFC_SQ_TTMP2 0x72 -#define V_008DFC_SQ_TTMP3 0x73 -#define V_008DFC_SQ_TTMP4 0x74 -#define V_008DFC_SQ_TTMP5 0x75 -#define V_008DFC_SQ_TTMP6 0x76 -#define V_008DFC_SQ_TTMP7 0x77 -#define V_008DFC_SQ_TTMP8 0x78 -#define V_008DFC_SQ_TTMP9 0x79 -#define V_008DFC_SQ_TTMP10 0x7A -#define V_008DFC_SQ_TTMP11 0x7B -#define V_008DFC_SQ_M0 0x7C -#define V_008DFC_SQ_EXEC_LO 0x7E -#define V_008DFC_SQ_EXEC_HI 0x7F -#define V_008DFC_SQ_SRC_0 0x80 -#define V_008DFC_SQ_SRC_1_INT 0x81 -#define V_008DFC_SQ_SRC_2_INT 0x82 -#define V_008DFC_SQ_SRC_3_INT 0x83 -#define V_008DFC_SQ_SRC_4_INT 0x84 -#define V_008DFC_SQ_SRC_5_INT 0x85 -#define V_008DFC_SQ_SRC_6_INT 0x86 -#define V_008DFC_SQ_SRC_7_INT 0x87 -#define V_008DFC_SQ_SRC_8_INT 0x88 -#define V_008DFC_SQ_SRC_9_INT 0x89 -#define V_008DFC_SQ_SRC_10_INT 0x8A -#define V_008DFC_SQ_SRC_11_INT 0x8B -#define V_008DFC_SQ_SRC_12_INT 0x8C -#define V_008DFC_SQ_SRC_13_INT 0x8D -#define V_008DFC_SQ_SRC_14_INT 0x8E -#define V_008DFC_SQ_SRC_15_INT 0x8F -#define V_008DFC_SQ_SRC_16_INT 0x90 -#define V_008DFC_SQ_SRC_17_INT 0x91 -#define V_008DFC_SQ_SRC_18_INT 0x92 -#define V_008DFC_SQ_SRC_19_INT 0x93 -#define V_008DFC_SQ_SRC_20_INT 0x94 -#define V_008DFC_SQ_SRC_21_INT 0x95 -#define V_008DFC_SQ_SRC_22_INT 0x96 -#define V_008DFC_SQ_SRC_23_INT 0x97 -#define V_008DFC_SQ_SRC_24_INT 0x98 -#define V_008DFC_SQ_SRC_25_INT 0x99 -#define V_008DFC_SQ_SRC_26_INT 0x9A -#define V_008DFC_SQ_SRC_27_INT 0x9B -#define V_008DFC_SQ_SRC_28_INT 0x9C -#define V_008DFC_SQ_SRC_29_INT 0x9D -#define V_008DFC_SQ_SRC_30_INT 0x9E -#define V_008DFC_SQ_SRC_31_INT 0x9F -#define V_008DFC_SQ_SRC_32_INT 0xA0 -#define V_008DFC_SQ_SRC_33_INT 0xA1 -#define V_008DFC_SQ_SRC_34_INT 0xA2 -#define V_008DFC_SQ_SRC_35_INT 0xA3 -#define V_008DFC_SQ_SRC_36_INT 0xA4 -#define V_008DFC_SQ_SRC_37_INT 0xA5 -#define V_008DFC_SQ_SRC_38_INT 0xA6 -#define V_008DFC_SQ_SRC_39_INT 0xA7 -#define V_008DFC_SQ_SRC_40_INT 0xA8 -#define V_008DFC_SQ_SRC_41_INT 0xA9 -#define V_008DFC_SQ_SRC_42_INT 0xAA -#define V_008DFC_SQ_SRC_43_INT 0xAB -#define V_008DFC_SQ_SRC_44_INT 0xAC -#define V_008DFC_SQ_SRC_45_INT 0xAD -#define V_008DFC_SQ_SRC_46_INT 0xAE -#define V_008DFC_SQ_SRC_47_INT 0xAF -#define V_008DFC_SQ_SRC_48_INT 0xB0 -#define V_008DFC_SQ_SRC_49_INT 0xB1 -#define V_008DFC_SQ_SRC_50_INT 0xB2 -#define V_008DFC_SQ_SRC_51_INT 0xB3 -#define V_008DFC_SQ_SRC_52_INT 0xB4 -#define V_008DFC_SQ_SRC_53_INT 0xB5 -#define V_008DFC_SQ_SRC_54_INT 0xB6 -#define V_008DFC_SQ_SRC_55_INT 0xB7 -#define V_008DFC_SQ_SRC_56_INT 0xB8 -#define V_008DFC_SQ_SRC_57_INT 0xB9 -#define V_008DFC_SQ_SRC_58_INT 0xBA -#define V_008DFC_SQ_SRC_59_INT 0xBB -#define V_008DFC_SQ_SRC_60_INT 0xBC -#define V_008DFC_SQ_SRC_61_INT 0xBD -#define V_008DFC_SQ_SRC_62_INT 0xBE -#define V_008DFC_SQ_SRC_63_INT 0xBF -#define V_008DFC_SQ_SRC_64_INT 0xC0 -#define V_008DFC_SQ_SRC_M_1_INT 0xC1 -#define V_008DFC_SQ_SRC_M_2_INT 0xC2 -#define V_008DFC_SQ_SRC_M_3_INT 0xC3 -#define V_008DFC_SQ_SRC_M_4_INT 0xC4 -#define V_008DFC_SQ_SRC_M_5_INT 0xC5 -#define V_008DFC_SQ_SRC_M_6_INT 0xC6 -#define V_008DFC_SQ_SRC_M_7_INT 0xC7 -#define V_008DFC_SQ_SRC_M_8_INT 0xC8 -#define V_008DFC_SQ_SRC_M_9_INT 0xC9 -#define V_008DFC_SQ_SRC_M_10_INT 0xCA -#define V_008DFC_SQ_SRC_M_11_INT 0xCB -#define V_008DFC_SQ_SRC_M_12_INT 0xCC -#define V_008DFC_SQ_SRC_M_13_INT 0xCD -#define V_008DFC_SQ_SRC_M_14_INT 0xCE -#define V_008DFC_SQ_SRC_M_15_INT 0xCF -#define V_008DFC_SQ_SRC_M_16_INT 0xD0 -#define V_008DFC_SQ_SRC_0_5 0xF0 -#define V_008DFC_SQ_SRC_M_0_5 0xF1 -#define V_008DFC_SQ_SRC_1 0xF2 -#define V_008DFC_SQ_SRC_M_1 0xF3 -#define V_008DFC_SQ_SRC_2 0xF4 -#define V_008DFC_SQ_SRC_M_2 0xF5 -#define V_008DFC_SQ_SRC_4 0xF6 -#define V_008DFC_SQ_SRC_M_4 0xF7 -#define V_008DFC_SQ_SRC_VCCZ 0xFB -#define V_008DFC_SQ_SRC_EXECZ 0xFC -#define V_008DFC_SQ_SRC_SCC 0xFD -#define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE -#define V_008DFC_SQ_SRC_VGPR 0x100 -#define S_008DFC_OMOD(x) (((x) & 0x03) << 27) -#define G_008DFC_OMOD(x) (((x) >> 27) & 0x03) -#define C_008DFC_OMOD 0xE7FFFFFF -#define V_008DFC_SQ_OMOD_OFF 0x00 -#define V_008DFC_SQ_OMOD_M2 0x01 -#define V_008DFC_SQ_OMOD_M4 0x02 -#define V_008DFC_SQ_OMOD_D2 0x03 -#define S_008DFC_NEG(x) (((x) & 0x07) << 29) -#define G_008DFC_NEG(x) (((x) >> 29) & 0x07) -#define C_008DFC_NEG 0x1FFFFFFF -#define R_008DFC_SQ_MUBUF_1 0x008DFC -#define S_008DFC_VADDR(x) (((x) & 0xFF) << 0) -#define G_008DFC_VADDR(x) (((x) >> 0) & 0xFF) -#define C_008DFC_VADDR 0xFFFFFF00 -#define V_008DFC_SQ_VGPR 0x00 -#define S_008DFC_VDATA(x) (((x) & 0xFF) << 8) -#define G_008DFC_VDATA(x) (((x) >> 8) & 0xFF) -#define C_008DFC_VDATA 0xFFFF00FF -#define V_008DFC_SQ_VGPR 0x00 -#define S_008DFC_SRSRC(x) (((x) & 0x1F) << 16) -#define G_008DFC_SRSRC(x) (((x) >> 16) & 0x1F) -#define C_008DFC_SRSRC 0xFFE0FFFF -#define S_008DFC_SLC(x) (((x) & 0x1) << 22) -#define G_008DFC_SLC(x) (((x) >> 22) & 0x1) -#define C_008DFC_SLC 0xFFBFFFFF -#define S_008DFC_TFE(x) (((x) & 0x1) << 23) -#define G_008DFC_TFE(x) (((x) >> 23) & 0x1) -#define C_008DFC_TFE 0xFF7FFFFF -#define S_008DFC_SOFFSET(x) (((x) & 0xFF) << 24) -#define G_008DFC_SOFFSET(x) (((x) >> 24) & 0xFF) -#define C_008DFC_SOFFSET 0x00FFFFFF -#define V_008DFC_SQ_SGPR 0x00 -/* CIK */ -#define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68 -#define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69 -/* */ -#define V_008DFC_SQ_VCC_LO 0x6A -#define V_008DFC_SQ_VCC_HI 0x6B -#define V_008DFC_SQ_TBA_LO 0x6C -#define V_008DFC_SQ_TBA_HI 0x6D -#define V_008DFC_SQ_TMA_LO 0x6E -#define V_008DFC_SQ_TMA_HI 0x6F -#define V_008DFC_SQ_TTMP0 0x70 -#define V_008DFC_SQ_TTMP1 0x71 -#define V_008DFC_SQ_TTMP2 0x72 -#define V_008DFC_SQ_TTMP3 0x73 -#define V_008DFC_SQ_TTMP4 0x74 -#define V_008DFC_SQ_TTMP5 0x75 -#define V_008DFC_SQ_TTMP6 0x76 -#define V_008DFC_SQ_TTMP7 0x77 -#define V_008DFC_SQ_TTMP8 0x78 -#define V_008DFC_SQ_TTMP9 0x79 -#define V_008DFC_SQ_TTMP10 0x7A -#define V_008DFC_SQ_TTMP11 0x7B -#define V_008DFC_SQ_M0 0x7C -#define V_008DFC_SQ_EXEC_LO 0x7E -#define V_008DFC_SQ_EXEC_HI 0x7F -#define V_008DFC_SQ_SRC_0 0x80 -#define V_008DFC_SQ_SRC_1_INT 0x81 -#define V_008DFC_SQ_SRC_2_INT 0x82 -#define V_008DFC_SQ_SRC_3_INT 0x83 -#define V_008DFC_SQ_SRC_4_INT 0x84 -#define V_008DFC_SQ_SRC_5_INT 0x85 -#define V_008DFC_SQ_SRC_6_INT 0x86 -#define V_008DFC_SQ_SRC_7_INT 0x87 -#define V_008DFC_SQ_SRC_8_INT 0x88 -#define V_008DFC_SQ_SRC_9_INT 0x89 -#define V_008DFC_SQ_SRC_10_INT 0x8A -#define V_008DFC_SQ_SRC_11_INT 0x8B -#define V_008DFC_SQ_SRC_12_INT 0x8C -#define V_008DFC_SQ_SRC_13_INT 0x8D -#define V_008DFC_SQ_SRC_14_INT 0x8E -#define V_008DFC_SQ_SRC_15_INT 0x8F -#define V_008DFC_SQ_SRC_16_INT 0x90 -#define V_008DFC_SQ_SRC_17_INT 0x91 -#define V_008DFC_SQ_SRC_18_INT 0x92 -#define V_008DFC_SQ_SRC_19_INT 0x93 -#define V_008DFC_SQ_SRC_20_INT 0x94 -#define V_008DFC_SQ_SRC_21_INT 0x95 -#define V_008DFC_SQ_SRC_22_INT 0x96 -#define V_008DFC_SQ_SRC_23_INT 0x97 -#define V_008DFC_SQ_SRC_24_INT 0x98 -#define V_008DFC_SQ_SRC_25_INT 0x99 -#define V_008DFC_SQ_SRC_26_INT 0x9A -#define V_008DFC_SQ_SRC_27_INT 0x9B -#define V_008DFC_SQ_SRC_28_INT 0x9C -#define V_008DFC_SQ_SRC_29_INT 0x9D -#define V_008DFC_SQ_SRC_30_INT 0x9E -#define V_008DFC_SQ_SRC_31_INT 0x9F -#define V_008DFC_SQ_SRC_32_INT 0xA0 -#define V_008DFC_SQ_SRC_33_INT 0xA1 -#define V_008DFC_SQ_SRC_34_INT 0xA2 -#define V_008DFC_SQ_SRC_35_INT 0xA3 -#define V_008DFC_SQ_SRC_36_INT 0xA4 -#define V_008DFC_SQ_SRC_37_INT 0xA5 -#define V_008DFC_SQ_SRC_38_INT 0xA6 -#define V_008DFC_SQ_SRC_39_INT 0xA7 -#define V_008DFC_SQ_SRC_40_INT 0xA8 -#define V_008DFC_SQ_SRC_41_INT 0xA9 -#define V_008DFC_SQ_SRC_42_INT 0xAA -#define V_008DFC_SQ_SRC_43_INT 0xAB -#define V_008DFC_SQ_SRC_44_INT 0xAC -#define V_008DFC_SQ_SRC_45_INT 0xAD -#define V_008DFC_SQ_SRC_46_INT 0xAE -#define V_008DFC_SQ_SRC_47_INT 0xAF -#define V_008DFC_SQ_SRC_48_INT 0xB0 -#define V_008DFC_SQ_SRC_49_INT 0xB1 -#define V_008DFC_SQ_SRC_50_INT 0xB2 -#define V_008DFC_SQ_SRC_51_INT 0xB3 -#define V_008DFC_SQ_SRC_52_INT 0xB4 -#define V_008DFC_SQ_SRC_53_INT 0xB5 -#define V_008DFC_SQ_SRC_54_INT 0xB6 -#define V_008DFC_SQ_SRC_55_INT 0xB7 -#define V_008DFC_SQ_SRC_56_INT 0xB8 -#define V_008DFC_SQ_SRC_57_INT 0xB9 -#define V_008DFC_SQ_SRC_58_INT 0xBA -#define V_008DFC_SQ_SRC_59_INT 0xBB -#define V_008DFC_SQ_SRC_60_INT 0xBC -#define V_008DFC_SQ_SRC_61_INT 0xBD -#define V_008DFC_SQ_SRC_62_INT 0xBE -#define V_008DFC_SQ_SRC_63_INT 0xBF -#define V_008DFC_SQ_SRC_64_INT 0xC0 -#define V_008DFC_SQ_SRC_M_1_INT 0xC1 -#define V_008DFC_SQ_SRC_M_2_INT 0xC2 -#define V_008DFC_SQ_SRC_M_3_INT 0xC3 -#define V_008DFC_SQ_SRC_M_4_INT 0xC4 -#define V_008DFC_SQ_SRC_M_5_INT 0xC5 -#define V_008DFC_SQ_SRC_M_6_INT 0xC6 -#define V_008DFC_SQ_SRC_M_7_INT 0xC7 -#define V_008DFC_SQ_SRC_M_8_INT 0xC8 -#define V_008DFC_SQ_SRC_M_9_INT 0xC9 -#define V_008DFC_SQ_SRC_M_10_INT 0xCA -#define V_008DFC_SQ_SRC_M_11_INT 0xCB -#define V_008DFC_SQ_SRC_M_12_INT 0xCC -#define V_008DFC_SQ_SRC_M_13_INT 0xCD -#define V_008DFC_SQ_SRC_M_14_INT 0xCE -#define V_008DFC_SQ_SRC_M_15_INT 0xCF -#define V_008DFC_SQ_SRC_M_16_INT 0xD0 -#define V_008DFC_SQ_SRC_0_5 0xF0 -#define V_008DFC_SQ_SRC_M_0_5 0xF1 -#define V_008DFC_SQ_SRC_1 0xF2 -#define V_008DFC_SQ_SRC_M_1 0xF3 -#define V_008DFC_SQ_SRC_2 0xF4 -#define V_008DFC_SQ_SRC_M_2 0xF5 -#define V_008DFC_SQ_SRC_4 0xF6 -#define V_008DFC_SQ_SRC_M_4 0xF7 -#define V_008DFC_SQ_SRC_VCCZ 0xFB -#define V_008DFC_SQ_SRC_EXECZ 0xFC -#define V_008DFC_SQ_SRC_SCC 0xFD -#define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE -#define R_008DFC_SQ_DS_0 0x008DFC -#define S_008DFC_OFFSET0(x) (((x) & 0xFF) << 0) -#define G_008DFC_OFFSET0(x) (((x) >> 0) & 0xFF) -#define C_008DFC_OFFSET0 0xFFFFFF00 -#define S_008DFC_OFFSET1(x) (((x) & 0xFF) << 8) -#define G_008DFC_OFFSET1(x) (((x) >> 8) & 0xFF) -#define C_008DFC_OFFSET1 0xFFFF00FF -#define S_008DFC_GDS(x) (((x) & 0x1) << 17) -#define G_008DFC_GDS(x) (((x) >> 17) & 0x1) -#define C_008DFC_GDS 0xFFFDFFFF -#define S_008DFC_OP(x) (((x) & 0xFF) << 18) -#define G_008DFC_OP(x) (((x) >> 18) & 0xFF) -#define C_008DFC_OP 0xFC03FFFF -#define V_008DFC_SQ_DS_ADD_U32 0x00 -#define V_008DFC_SQ_DS_SUB_U32 0x01 -#define V_008DFC_SQ_DS_RSUB_U32 0x02 -#define V_008DFC_SQ_DS_INC_U32 0x03 -#define V_008DFC_SQ_DS_DEC_U32 0x04 -#define V_008DFC_SQ_DS_MIN_I32 0x05 -#define V_008DFC_SQ_DS_MAX_I32 0x06 -#define V_008DFC_SQ_DS_MIN_U32 0x07 -#define V_008DFC_SQ_DS_MAX_U32 0x08 -#define V_008DFC_SQ_DS_AND_B32 0x09 -#define V_008DFC_SQ_DS_OR_B32 0x0A -#define V_008DFC_SQ_DS_XOR_B32 0x0B -#define V_008DFC_SQ_DS_MSKOR_B32 0x0C -#define V_008DFC_SQ_DS_WRITE_B32 0x0D -#define V_008DFC_SQ_DS_WRITE2_B32 0x0E -#define V_008DFC_SQ_DS_WRITE2ST64_B32 0x0F -#define V_008DFC_SQ_DS_CMPST_B32 0x10 -#define V_008DFC_SQ_DS_CMPST_F32 0x11 -#define V_008DFC_SQ_DS_MIN_F32 0x12 -#define V_008DFC_SQ_DS_MAX_F32 0x13 -/* CIK */ -#define V_008DFC_SQ_DS_NOP 0x14 -/* */ -#define V_008DFC_SQ_DS_GWS_INIT 0x19 -#define V_008DFC_SQ_DS_GWS_SEMA_V 0x1A -#define V_008DFC_SQ_DS_GWS_SEMA_BR 0x1B -#define V_008DFC_SQ_DS_GWS_SEMA_P 0x1C -#define V_008DFC_SQ_DS_GWS_BARRIER 0x1D -#define V_008DFC_SQ_DS_WRITE_B8 0x1E -#define V_008DFC_SQ_DS_WRITE_B16 0x1F -#define V_008DFC_SQ_DS_ADD_RTN_U32 0x20 -#define V_008DFC_SQ_DS_SUB_RTN_U32 0x21 -#define V_008DFC_SQ_DS_RSUB_RTN_U32 0x22 -#define V_008DFC_SQ_DS_INC_RTN_U32 0x23 -#define V_008DFC_SQ_DS_DEC_RTN_U32 0x24 -#define V_008DFC_SQ_DS_MIN_RTN_I32 0x25 -#define V_008DFC_SQ_DS_MAX_RTN_I32 0x26 -#define V_008DFC_SQ_DS_MIN_RTN_U32 0x27 -#define V_008DFC_SQ_DS_MAX_RTN_U32 0x28 -#define V_008DFC_SQ_DS_AND_RTN_B32 0x29 -#define V_008DFC_SQ_DS_OR_RTN_B32 0x2A -#define V_008DFC_SQ_DS_XOR_RTN_B32 0x2B -#define V_008DFC_SQ_DS_MSKOR_RTN_B32 0x2C -#define V_008DFC_SQ_DS_WRXCHG_RTN_B32 0x2D -#define V_008DFC_SQ_DS_WRXCHG2_RTN_B32 0x2E -#define V_008DFC_SQ_DS_WRXCHG2ST64_RTN_B32 0x2F -#define V_008DFC_SQ_DS_CMPST_RTN_B32 0x30 -#define V_008DFC_SQ_DS_CMPST_RTN_F32 0x31 -#define V_008DFC_SQ_DS_MIN_RTN_F32 0x32 -#define V_008DFC_SQ_DS_MAX_RTN_F32 0x33 -#define V_008DFC_SQ_DS_SWIZZLE_B32 0x35 -#define V_008DFC_SQ_DS_READ_B32 0x36 -#define V_008DFC_SQ_DS_READ2_B32 0x37 -#define V_008DFC_SQ_DS_READ2ST64_B32 0x38 -#define V_008DFC_SQ_DS_READ_I8 0x39 -#define V_008DFC_SQ_DS_READ_U8 0x3A -#define V_008DFC_SQ_DS_READ_I16 0x3B -#define V_008DFC_SQ_DS_READ_U16 0x3C -#define V_008DFC_SQ_DS_CONSUME 0x3D -#define V_008DFC_SQ_DS_APPEND 0x3E -#define V_008DFC_SQ_DS_ORDERED_COUNT 0x3F -#define V_008DFC_SQ_DS_ADD_U64 0x40 -#define V_008DFC_SQ_DS_SUB_U64 0x41 -#define V_008DFC_SQ_DS_RSUB_U64 0x42 -#define V_008DFC_SQ_DS_INC_U64 0x43 -#define V_008DFC_SQ_DS_DEC_U64 0x44 -#define V_008DFC_SQ_DS_MIN_I64 0x45 -#define V_008DFC_SQ_DS_MAX_I64 0x46 -#define V_008DFC_SQ_DS_MIN_U64 0x47 -#define V_008DFC_SQ_DS_MAX_U64 0x48 -#define V_008DFC_SQ_DS_AND_B64 0x49 -#define V_008DFC_SQ_DS_OR_B64 0x4A -#define V_008DFC_SQ_DS_XOR_B64 0x4B -#define V_008DFC_SQ_DS_MSKOR_B64 0x4C -#define V_008DFC_SQ_DS_WRITE_B64 0x4D -#define V_008DFC_SQ_DS_WRITE2_B64 0x4E -#define V_008DFC_SQ_DS_WRITE2ST64_B64 0x4F -#define V_008DFC_SQ_DS_CMPST_B64 0x50 -#define V_008DFC_SQ_DS_CMPST_F64 0x51 -#define V_008DFC_SQ_DS_MIN_F64 0x52 -#define V_008DFC_SQ_DS_MAX_F64 0x53 -#define V_008DFC_SQ_DS_ADD_RTN_U64 0x60 -#define V_008DFC_SQ_DS_SUB_RTN_U64 0x61 -#define V_008DFC_SQ_DS_RSUB_RTN_U64 0x62 -#define V_008DFC_SQ_DS_INC_RTN_U64 0x63 -#define V_008DFC_SQ_DS_DEC_RTN_U64 0x64 -#define V_008DFC_SQ_DS_MIN_RTN_I64 0x65 -#define V_008DFC_SQ_DS_MAX_RTN_I64 0x66 -#define V_008DFC_SQ_DS_MIN_RTN_U64 0x67 -#define V_008DFC_SQ_DS_MAX_RTN_U64 0x68 -#define V_008DFC_SQ_DS_AND_RTN_B64 0x69 -#define V_008DFC_SQ_DS_OR_RTN_B64 0x6A -#define V_008DFC_SQ_DS_XOR_RTN_B64 0x6B -#define V_008DFC_SQ_DS_MSKOR_RTN_B64 0x6C -#define V_008DFC_SQ_DS_WRXCHG_RTN_B64 0x6D -#define V_008DFC_SQ_DS_WRXCHG2_RTN_B64 0x6E -#define V_008DFC_SQ_DS_WRXCHG2ST64_RTN_B64 0x6F -#define V_008DFC_SQ_DS_CMPST_RTN_B64 0x70 -#define V_008DFC_SQ_DS_CMPST_RTN_F64 0x71 -#define V_008DFC_SQ_DS_MIN_RTN_F64 0x72 -#define V_008DFC_SQ_DS_MAX_RTN_F64 0x73 -#define V_008DFC_SQ_DS_READ_B64 0x76 -#define V_008DFC_SQ_DS_READ2_B64 0x77 -#define V_008DFC_SQ_DS_READ2ST64_B64 0x78 -/* CIK */ -#define V_008DFC_SQ_DS_CONDXCHG32_RTN_B64 0x7E -/* */ -#define V_008DFC_SQ_DS_ADD_SRC2_U32 0x80 -#define V_008DFC_SQ_DS_SUB_SRC2_U32 0x81 -#define V_008DFC_SQ_DS_RSUB_SRC2_U32 0x82 -#define V_008DFC_SQ_DS_INC_SRC2_U32 0x83 -#define V_008DFC_SQ_DS_DEC_SRC2_U32 0x84 -#define V_008DFC_SQ_DS_MIN_SRC2_I32 0x85 -#define V_008DFC_SQ_DS_MAX_SRC2_I32 0x86 -#define V_008DFC_SQ_DS_MIN_SRC2_U32 0x87 -#define V_008DFC_SQ_DS_MAX_SRC2_U32 0x88 -#define V_008DFC_SQ_DS_AND_SRC2_B32 0x89 -#define V_008DFC_SQ_DS_OR_SRC2_B32 0x8A -#define V_008DFC_SQ_DS_XOR_SRC2_B32 0x8B -#define V_008DFC_SQ_DS_WRITE_SRC2_B32 0x8D -#define V_008DFC_SQ_DS_MIN_SRC2_F32 0x92 -#define V_008DFC_SQ_DS_MAX_SRC2_F32 0x93 -#define V_008DFC_SQ_DS_ADD_SRC2_U64 0xC0 -#define V_008DFC_SQ_DS_SUB_SRC2_U64 0xC1 -#define V_008DFC_SQ_DS_RSUB_SRC2_U64 0xC2 -#define V_008DFC_SQ_DS_INC_SRC2_U64 0xC3 -#define V_008DFC_SQ_DS_DEC_SRC2_U64 0xC4 -#define V_008DFC_SQ_DS_MIN_SRC2_I64 0xC5 -#define V_008DFC_SQ_DS_MAX_SRC2_I64 0xC6 -#define V_008DFC_SQ_DS_MIN_SRC2_U64 0xC7 -#define V_008DFC_SQ_DS_MAX_SRC2_U64 0xC8 -#define V_008DFC_SQ_DS_AND_SRC2_B64 0xC9 -#define V_008DFC_SQ_DS_OR_SRC2_B64 0xCA -#define V_008DFC_SQ_DS_XOR_SRC2_B64 0xCB -#define V_008DFC_SQ_DS_WRITE_SRC2_B64 0xCD -#define V_008DFC_SQ_DS_MIN_SRC2_F64 0xD2 -#define V_008DFC_SQ_DS_MAX_SRC2_F64 0xD3 -/* CIK */ -#define V_008DFC_SQ_DS_WRITE_B96 0xDE -#define V_008DFC_SQ_DS_WRITE_B128 0xDF -#define V_008DFC_SQ_DS_CONDXCHG32_RTN_B128 0xFD -#define V_008DFC_SQ_DS_READ_B96 0xFE -#define V_008DFC_SQ_DS_READ_B128 0xFF -/* */ -#define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26) -#define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F) -#define C_008DFC_ENCODING 0x03FFFFFF -#define V_008DFC_SQ_ENC_DS_FIELD 0x36 -#define R_008DFC_SQ_SOPC 0x008DFC -#define S_008DFC_SSRC0(x) (((x) & 0xFF) << 0) -#define G_008DFC_SSRC0(x) (((x) >> 0) & 0xFF) -#define C_008DFC_SSRC0 0xFFFFFF00 -#define V_008DFC_SQ_SGPR 0x00 -/* CIK */ -#define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68 -#define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69 -/* */ -#define V_008DFC_SQ_VCC_LO 0x6A -#define V_008DFC_SQ_VCC_HI 0x6B -#define V_008DFC_SQ_TBA_LO 0x6C -#define V_008DFC_SQ_TBA_HI 0x6D -#define V_008DFC_SQ_TMA_LO 0x6E -#define V_008DFC_SQ_TMA_HI 0x6F -#define V_008DFC_SQ_TTMP0 0x70 -#define V_008DFC_SQ_TTMP1 0x71 -#define V_008DFC_SQ_TTMP2 0x72 -#define V_008DFC_SQ_TTMP3 0x73 -#define V_008DFC_SQ_TTMP4 0x74 -#define V_008DFC_SQ_TTMP5 0x75 -#define V_008DFC_SQ_TTMP6 0x76 -#define V_008DFC_SQ_TTMP7 0x77 -#define V_008DFC_SQ_TTMP8 0x78 -#define V_008DFC_SQ_TTMP9 0x79 -#define V_008DFC_SQ_TTMP10 0x7A -#define V_008DFC_SQ_TTMP11 0x7B -#define V_008DFC_SQ_M0 0x7C -#define V_008DFC_SQ_EXEC_LO 0x7E -#define V_008DFC_SQ_EXEC_HI 0x7F -#define V_008DFC_SQ_SRC_0 0x80 -#define V_008DFC_SQ_SRC_1_INT 0x81 -#define V_008DFC_SQ_SRC_2_INT 0x82 -#define V_008DFC_SQ_SRC_3_INT 0x83 -#define V_008DFC_SQ_SRC_4_INT 0x84 -#define V_008DFC_SQ_SRC_5_INT 0x85 -#define V_008DFC_SQ_SRC_6_INT 0x86 -#define V_008DFC_SQ_SRC_7_INT 0x87 -#define V_008DFC_SQ_SRC_8_INT 0x88 -#define V_008DFC_SQ_SRC_9_INT 0x89 -#define V_008DFC_SQ_SRC_10_INT 0x8A -#define V_008DFC_SQ_SRC_11_INT 0x8B -#define V_008DFC_SQ_SRC_12_INT 0x8C -#define V_008DFC_SQ_SRC_13_INT 0x8D -#define V_008DFC_SQ_SRC_14_INT 0x8E -#define V_008DFC_SQ_SRC_15_INT 0x8F -#define V_008DFC_SQ_SRC_16_INT 0x90 -#define V_008DFC_SQ_SRC_17_INT 0x91 -#define V_008DFC_SQ_SRC_18_INT 0x92 -#define V_008DFC_SQ_SRC_19_INT 0x93 -#define V_008DFC_SQ_SRC_20_INT 0x94 -#define V_008DFC_SQ_SRC_21_INT 0x95 -#define V_008DFC_SQ_SRC_22_INT 0x96 -#define V_008DFC_SQ_SRC_23_INT 0x97 -#define V_008DFC_SQ_SRC_24_INT 0x98 -#define V_008DFC_SQ_SRC_25_INT 0x99 -#define V_008DFC_SQ_SRC_26_INT 0x9A -#define V_008DFC_SQ_SRC_27_INT 0x9B -#define V_008DFC_SQ_SRC_28_INT 0x9C -#define V_008DFC_SQ_SRC_29_INT 0x9D -#define V_008DFC_SQ_SRC_30_INT 0x9E -#define V_008DFC_SQ_SRC_31_INT 0x9F -#define V_008DFC_SQ_SRC_32_INT 0xA0 -#define V_008DFC_SQ_SRC_33_INT 0xA1 -#define V_008DFC_SQ_SRC_34_INT 0xA2 -#define V_008DFC_SQ_SRC_35_INT 0xA3 -#define V_008DFC_SQ_SRC_36_INT 0xA4 -#define V_008DFC_SQ_SRC_37_INT 0xA5 -#define V_008DFC_SQ_SRC_38_INT 0xA6 -#define V_008DFC_SQ_SRC_39_INT 0xA7 -#define V_008DFC_SQ_SRC_40_INT 0xA8 -#define V_008DFC_SQ_SRC_41_INT 0xA9 -#define V_008DFC_SQ_SRC_42_INT 0xAA -#define V_008DFC_SQ_SRC_43_INT 0xAB -#define V_008DFC_SQ_SRC_44_INT 0xAC -#define V_008DFC_SQ_SRC_45_INT 0xAD -#define V_008DFC_SQ_SRC_46_INT 0xAE -#define V_008DFC_SQ_SRC_47_INT 0xAF -#define V_008DFC_SQ_SRC_48_INT 0xB0 -#define V_008DFC_SQ_SRC_49_INT 0xB1 -#define V_008DFC_SQ_SRC_50_INT 0xB2 -#define V_008DFC_SQ_SRC_51_INT 0xB3 -#define V_008DFC_SQ_SRC_52_INT 0xB4 -#define V_008DFC_SQ_SRC_53_INT 0xB5 -#define V_008DFC_SQ_SRC_54_INT 0xB6 -#define V_008DFC_SQ_SRC_55_INT 0xB7 -#define V_008DFC_SQ_SRC_56_INT 0xB8 -#define V_008DFC_SQ_SRC_57_INT 0xB9 -#define V_008DFC_SQ_SRC_58_INT 0xBA -#define V_008DFC_SQ_SRC_59_INT 0xBB -#define V_008DFC_SQ_SRC_60_INT 0xBC -#define V_008DFC_SQ_SRC_61_INT 0xBD -#define V_008DFC_SQ_SRC_62_INT 0xBE -#define V_008DFC_SQ_SRC_63_INT 0xBF -#define V_008DFC_SQ_SRC_64_INT 0xC0 -#define V_008DFC_SQ_SRC_M_1_INT 0xC1 -#define V_008DFC_SQ_SRC_M_2_INT 0xC2 -#define V_008DFC_SQ_SRC_M_3_INT 0xC3 -#define V_008DFC_SQ_SRC_M_4_INT 0xC4 -#define V_008DFC_SQ_SRC_M_5_INT 0xC5 -#define V_008DFC_SQ_SRC_M_6_INT 0xC6 -#define V_008DFC_SQ_SRC_M_7_INT 0xC7 -#define V_008DFC_SQ_SRC_M_8_INT 0xC8 -#define V_008DFC_SQ_SRC_M_9_INT 0xC9 -#define V_008DFC_SQ_SRC_M_10_INT 0xCA -#define V_008DFC_SQ_SRC_M_11_INT 0xCB -#define V_008DFC_SQ_SRC_M_12_INT 0xCC -#define V_008DFC_SQ_SRC_M_13_INT 0xCD -#define V_008DFC_SQ_SRC_M_14_INT 0xCE -#define V_008DFC_SQ_SRC_M_15_INT 0xCF -#define V_008DFC_SQ_SRC_M_16_INT 0xD0 -#define V_008DFC_SQ_SRC_0_5 0xF0 -#define V_008DFC_SQ_SRC_M_0_5 0xF1 -#define V_008DFC_SQ_SRC_1 0xF2 -#define V_008DFC_SQ_SRC_M_1 0xF3 -#define V_008DFC_SQ_SRC_2 0xF4 -#define V_008DFC_SQ_SRC_M_2 0xF5 -#define V_008DFC_SQ_SRC_4 0xF6 -#define V_008DFC_SQ_SRC_M_4 0xF7 -#define V_008DFC_SQ_SRC_VCCZ 0xFB -#define V_008DFC_SQ_SRC_EXECZ 0xFC -#define V_008DFC_SQ_SRC_SCC 0xFD -#define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE -#define S_008DFC_SSRC1(x) (((x) & 0xFF) << 8) -#define G_008DFC_SSRC1(x) (((x) >> 8) & 0xFF) -#define C_008DFC_SSRC1 0xFFFF00FF -#define V_008DFC_SQ_SGPR 0x00 -/* CIK */ -#define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68 -#define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69 -/* */ -#define V_008DFC_SQ_VCC_LO 0x6A -#define V_008DFC_SQ_VCC_HI 0x6B -#define V_008DFC_SQ_TBA_LO 0x6C -#define V_008DFC_SQ_TBA_HI 0x6D -#define V_008DFC_SQ_TMA_LO 0x6E -#define V_008DFC_SQ_TMA_HI 0x6F -#define V_008DFC_SQ_TTMP0 0x70 -#define V_008DFC_SQ_TTMP1 0x71 -#define V_008DFC_SQ_TTMP2 0x72 -#define V_008DFC_SQ_TTMP3 0x73 -#define V_008DFC_SQ_TTMP4 0x74 -#define V_008DFC_SQ_TTMP5 0x75 -#define V_008DFC_SQ_TTMP6 0x76 -#define V_008DFC_SQ_TTMP7 0x77 -#define V_008DFC_SQ_TTMP8 0x78 -#define V_008DFC_SQ_TTMP9 0x79 -#define V_008DFC_SQ_TTMP10 0x7A -#define V_008DFC_SQ_TTMP11 0x7B -#define V_008DFC_SQ_M0 0x7C -#define V_008DFC_SQ_EXEC_LO 0x7E -#define V_008DFC_SQ_EXEC_HI 0x7F -#define V_008DFC_SQ_SRC_0 0x80 -#define V_008DFC_SQ_SRC_1_INT 0x81 -#define V_008DFC_SQ_SRC_2_INT 0x82 -#define V_008DFC_SQ_SRC_3_INT 0x83 -#define V_008DFC_SQ_SRC_4_INT 0x84 -#define V_008DFC_SQ_SRC_5_INT 0x85 -#define V_008DFC_SQ_SRC_6_INT 0x86 -#define V_008DFC_SQ_SRC_7_INT 0x87 -#define V_008DFC_SQ_SRC_8_INT 0x88 -#define V_008DFC_SQ_SRC_9_INT 0x89 -#define V_008DFC_SQ_SRC_10_INT 0x8A -#define V_008DFC_SQ_SRC_11_INT 0x8B -#define V_008DFC_SQ_SRC_12_INT 0x8C -#define V_008DFC_SQ_SRC_13_INT 0x8D -#define V_008DFC_SQ_SRC_14_INT 0x8E -#define V_008DFC_SQ_SRC_15_INT 0x8F -#define V_008DFC_SQ_SRC_16_INT 0x90 -#define V_008DFC_SQ_SRC_17_INT 0x91 -#define V_008DFC_SQ_SRC_18_INT 0x92 -#define V_008DFC_SQ_SRC_19_INT 0x93 -#define V_008DFC_SQ_SRC_20_INT 0x94 -#define V_008DFC_SQ_SRC_21_INT 0x95 -#define V_008DFC_SQ_SRC_22_INT 0x96 -#define V_008DFC_SQ_SRC_23_INT 0x97 -#define V_008DFC_SQ_SRC_24_INT 0x98 -#define V_008DFC_SQ_SRC_25_INT 0x99 -#define V_008DFC_SQ_SRC_26_INT 0x9A -#define V_008DFC_SQ_SRC_27_INT 0x9B -#define V_008DFC_SQ_SRC_28_INT 0x9C -#define V_008DFC_SQ_SRC_29_INT 0x9D -#define V_008DFC_SQ_SRC_30_INT 0x9E -#define V_008DFC_SQ_SRC_31_INT 0x9F -#define V_008DFC_SQ_SRC_32_INT 0xA0 -#define V_008DFC_SQ_SRC_33_INT 0xA1 -#define V_008DFC_SQ_SRC_34_INT 0xA2 -#define V_008DFC_SQ_SRC_35_INT 0xA3 -#define V_008DFC_SQ_SRC_36_INT 0xA4 -#define V_008DFC_SQ_SRC_37_INT 0xA5 -#define V_008DFC_SQ_SRC_38_INT 0xA6 -#define V_008DFC_SQ_SRC_39_INT 0xA7 -#define V_008DFC_SQ_SRC_40_INT 0xA8 -#define V_008DFC_SQ_SRC_41_INT 0xA9 -#define V_008DFC_SQ_SRC_42_INT 0xAA -#define V_008DFC_SQ_SRC_43_INT 0xAB -#define V_008DFC_SQ_SRC_44_INT 0xAC -#define V_008DFC_SQ_SRC_45_INT 0xAD -#define V_008DFC_SQ_SRC_46_INT 0xAE -#define V_008DFC_SQ_SRC_47_INT 0xAF -#define V_008DFC_SQ_SRC_48_INT 0xB0 -#define V_008DFC_SQ_SRC_49_INT 0xB1 -#define V_008DFC_SQ_SRC_50_INT 0xB2 -#define V_008DFC_SQ_SRC_51_INT 0xB3 -#define V_008DFC_SQ_SRC_52_INT 0xB4 -#define V_008DFC_SQ_SRC_53_INT 0xB5 -#define V_008DFC_SQ_SRC_54_INT 0xB6 -#define V_008DFC_SQ_SRC_55_INT 0xB7 -#define V_008DFC_SQ_SRC_56_INT 0xB8 -#define V_008DFC_SQ_SRC_57_INT 0xB9 -#define V_008DFC_SQ_SRC_58_INT 0xBA -#define V_008DFC_SQ_SRC_59_INT 0xBB -#define V_008DFC_SQ_SRC_60_INT 0xBC -#define V_008DFC_SQ_SRC_61_INT 0xBD -#define V_008DFC_SQ_SRC_62_INT 0xBE -#define V_008DFC_SQ_SRC_63_INT 0xBF -#define V_008DFC_SQ_SRC_64_INT 0xC0 -#define V_008DFC_SQ_SRC_M_1_INT 0xC1 -#define V_008DFC_SQ_SRC_M_2_INT 0xC2 -#define V_008DFC_SQ_SRC_M_3_INT 0xC3 -#define V_008DFC_SQ_SRC_M_4_INT 0xC4 -#define V_008DFC_SQ_SRC_M_5_INT 0xC5 -#define V_008DFC_SQ_SRC_M_6_INT 0xC6 -#define V_008DFC_SQ_SRC_M_7_INT 0xC7 -#define V_008DFC_SQ_SRC_M_8_INT 0xC8 -#define V_008DFC_SQ_SRC_M_9_INT 0xC9 -#define V_008DFC_SQ_SRC_M_10_INT 0xCA -#define V_008DFC_SQ_SRC_M_11_INT 0xCB -#define V_008DFC_SQ_SRC_M_12_INT 0xCC -#define V_008DFC_SQ_SRC_M_13_INT 0xCD -#define V_008DFC_SQ_SRC_M_14_INT 0xCE -#define V_008DFC_SQ_SRC_M_15_INT 0xCF -#define V_008DFC_SQ_SRC_M_16_INT 0xD0 -#define V_008DFC_SQ_SRC_0_5 0xF0 -#define V_008DFC_SQ_SRC_M_0_5 0xF1 -#define V_008DFC_SQ_SRC_1 0xF2 -#define V_008DFC_SQ_SRC_M_1 0xF3 -#define V_008DFC_SQ_SRC_2 0xF4 -#define V_008DFC_SQ_SRC_M_2 0xF5 -#define V_008DFC_SQ_SRC_4 0xF6 -#define V_008DFC_SQ_SRC_M_4 0xF7 -#define V_008DFC_SQ_SRC_VCCZ 0xFB -#define V_008DFC_SQ_SRC_EXECZ 0xFC -#define V_008DFC_SQ_SRC_SCC 0xFD -#define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE -#define S_008DFC_OP(x) (((x) & 0x7F) << 16) -#define G_008DFC_OP(x) (((x) >> 16) & 0x7F) -#define C_008DFC_OP 0xFF80FFFF -#define V_008DFC_SQ_S_CMP_EQ_I32 0x00 -#define V_008DFC_SQ_S_CMP_LG_I32 0x01 -#define V_008DFC_SQ_S_CMP_GT_I32 0x02 -#define V_008DFC_SQ_S_CMP_GE_I32 0x03 -#define V_008DFC_SQ_S_CMP_LT_I32 0x04 -#define V_008DFC_SQ_S_CMP_LE_I32 0x05 -#define V_008DFC_SQ_S_CMP_EQ_U32 0x06 -#define V_008DFC_SQ_S_CMP_LG_U32 0x07 -#define V_008DFC_SQ_S_CMP_GT_U32 0x08 -#define V_008DFC_SQ_S_CMP_GE_U32 0x09 -#define V_008DFC_SQ_S_CMP_LT_U32 0x0A -#define V_008DFC_SQ_S_CMP_LE_U32 0x0B -#define V_008DFC_SQ_S_BITCMP0_B32 0x0C -#define V_008DFC_SQ_S_BITCMP1_B32 0x0D -#define V_008DFC_SQ_S_BITCMP0_B64 0x0E -#define V_008DFC_SQ_S_BITCMP1_B64 0x0F -#define V_008DFC_SQ_S_SETVSKIP 0x10 -#define S_008DFC_ENCODING(x) (((x) & 0x1FF) << 23) -#define G_008DFC_ENCODING(x) (((x) >> 23) & 0x1FF) -#define C_008DFC_ENCODING 0x007FFFFF -#define V_008DFC_SQ_ENC_SOPC_FIELD 0x17E -#endif -#define R_008DFC_SQ_EXP_0 0x008DFC -#define S_008DFC_EN(x) (((x) & 0x0F) << 0) -#define G_008DFC_EN(x) (((x) >> 0) & 0x0F) -#define C_008DFC_EN 0xFFFFFFF0 -#define S_008DFC_TGT(x) (((x) & 0x3F) << 4) -#define G_008DFC_TGT(x) (((x) >> 4) & 0x3F) -#define C_008DFC_TGT 0xFFFFFC0F -#define V_008DFC_SQ_EXP_MRT 0x00 -#define V_008DFC_SQ_EXP_MRTZ 0x08 -#define V_008DFC_SQ_EXP_NULL 0x09 -#define V_008DFC_SQ_EXP_POS 0x0C -#define V_008DFC_SQ_EXP_PARAM 0x20 -#define S_008DFC_COMPR(x) (((x) & 0x1) << 10) -#define G_008DFC_COMPR(x) (((x) >> 10) & 0x1) -#define C_008DFC_COMPR 0xFFFFFBFF -#define S_008DFC_DONE(x) (((x) & 0x1) << 11) -#define G_008DFC_DONE(x) (((x) >> 11) & 0x1) -#define C_008DFC_DONE 0xFFFFF7FF -#define S_008DFC_VM(x) (((x) & 0x1) << 12) -#define G_008DFC_VM(x) (((x) >> 12) & 0x1) -#define C_008DFC_VM 0xFFFFEFFF -#define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26) -#define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F) -#define C_008DFC_ENCODING 0x03FFFFFF -#define V_008DFC_SQ_ENC_EXP_FIELD 0x3E -#if 0 -#define R_008DFC_SQ_MIMG_0 0x008DFC -#define S_008DFC_DMASK(x) (((x) & 0x0F) << 8) -#define G_008DFC_DMASK(x) (((x) >> 8) & 0x0F) -#define C_008DFC_DMASK 0xFFFFF0FF -#define S_008DFC_UNORM(x) (((x) & 0x1) << 12) -#define G_008DFC_UNORM(x) (((x) >> 12) & 0x1) -#define C_008DFC_UNORM 0xFFFFEFFF -#define S_008DFC_GLC(x) (((x) & 0x1) << 13) -#define G_008DFC_GLC(x) (((x) >> 13) & 0x1) -#define C_008DFC_GLC 0xFFFFDFFF -#define S_008DFC_DA(x) (((x) & 0x1) << 14) -#define G_008DFC_DA(x) (((x) >> 14) & 0x1) -#define C_008DFC_DA 0xFFFFBFFF -#define S_008DFC_R128(x) (((x) & 0x1) << 15) -#define G_008DFC_R128(x) (((x) >> 15) & 0x1) -#define C_008DFC_R128 0xFFFF7FFF -#define S_008DFC_TFE(x) (((x) & 0x1) << 16) -#define G_008DFC_TFE(x) (((x) >> 16) & 0x1) -#define C_008DFC_TFE 0xFFFEFFFF -#define S_008DFC_LWE(x) (((x) & 0x1) << 17) -#define G_008DFC_LWE(x) (((x) >> 17) & 0x1) -#define C_008DFC_LWE 0xFFFDFFFF -#define S_008DFC_OP(x) (((x) & 0x7F) << 18) -#define G_008DFC_OP(x) (((x) >> 18) & 0x7F) -#define C_008DFC_OP 0xFE03FFFF -#define V_008DFC_SQ_IMAGE_LOAD 0x00 -#define V_008DFC_SQ_IMAGE_LOAD_MIP 0x01 -#define V_008DFC_SQ_IMAGE_LOAD_PCK 0x02 -#define V_008DFC_SQ_IMAGE_LOAD_PCK_SGN 0x03 -#define V_008DFC_SQ_IMAGE_LOAD_MIP_PCK 0x04 -#define V_008DFC_SQ_IMAGE_LOAD_MIP_PCK_SGN 0x05 -#define V_008DFC_SQ_IMAGE_STORE 0x08 -#define V_008DFC_SQ_IMAGE_STORE_MIP 0x09 -#define V_008DFC_SQ_IMAGE_STORE_PCK 0x0A -#define V_008DFC_SQ_IMAGE_STORE_MIP_PCK 0x0B -#define V_008DFC_SQ_IMAGE_GET_RESINFO 0x0E -#define V_008DFC_SQ_IMAGE_ATOMIC_SWAP 0x0F -#define V_008DFC_SQ_IMAGE_ATOMIC_CMPSWAP 0x10 -#define V_008DFC_SQ_IMAGE_ATOMIC_ADD 0x11 -#define V_008DFC_SQ_IMAGE_ATOMIC_SUB 0x12 -#define V_008DFC_SQ_IMAGE_ATOMIC_RSUB 0x13 /* not on CIK */ -#define V_008DFC_SQ_IMAGE_ATOMIC_SMIN 0x14 -#define V_008DFC_SQ_IMAGE_ATOMIC_UMIN 0x15 -#define V_008DFC_SQ_IMAGE_ATOMIC_SMAX 0x16 -#define V_008DFC_SQ_IMAGE_ATOMIC_UMAX 0x17 -#define V_008DFC_SQ_IMAGE_ATOMIC_AND 0x18 -#define V_008DFC_SQ_IMAGE_ATOMIC_OR 0x19 -#define V_008DFC_SQ_IMAGE_ATOMIC_XOR 0x1A -#define V_008DFC_SQ_IMAGE_ATOMIC_INC 0x1B -#define V_008DFC_SQ_IMAGE_ATOMIC_DEC 0x1C -#define V_008DFC_SQ_IMAGE_ATOMIC_FCMPSWAP 0x1D -#define V_008DFC_SQ_IMAGE_ATOMIC_FMIN 0x1E -#define V_008DFC_SQ_IMAGE_ATOMIC_FMAX 0x1F -#define V_008DFC_SQ_IMAGE_SAMPLE 0x20 -#define V_008DFC_SQ_IMAGE_SAMPLE_CL 0x21 -#define V_008DFC_SQ_IMAGE_SAMPLE_D 0x22 -#define V_008DFC_SQ_IMAGE_SAMPLE_D_CL 0x23 -#define V_008DFC_SQ_IMAGE_SAMPLE_L 0x24 -#define V_008DFC_SQ_IMAGE_SAMPLE_B 0x25 -#define V_008DFC_SQ_IMAGE_SAMPLE_B_CL 0x26 -#define V_008DFC_SQ_IMAGE_SAMPLE_LZ 0x27 -#define V_008DFC_SQ_IMAGE_SAMPLE_C 0x28 -#define V_008DFC_SQ_IMAGE_SAMPLE_C_CL 0x29 -#define V_008DFC_SQ_IMAGE_SAMPLE_C_D 0x2A -#define V_008DFC_SQ_IMAGE_SAMPLE_C_D_CL 0x2B -#define V_008DFC_SQ_IMAGE_SAMPLE_C_L 0x2C -#define V_008DFC_SQ_IMAGE_SAMPLE_C_B 0x2D -#define V_008DFC_SQ_IMAGE_SAMPLE_C_B_CL 0x2E -#define V_008DFC_SQ_IMAGE_SAMPLE_C_LZ 0x2F -#define V_008DFC_SQ_IMAGE_SAMPLE_O 0x30 -#define V_008DFC_SQ_IMAGE_SAMPLE_CL_O 0x31 -#define V_008DFC_SQ_IMAGE_SAMPLE_D_O 0x32 -#define V_008DFC_SQ_IMAGE_SAMPLE_D_CL_O 0x33 -#define V_008DFC_SQ_IMAGE_SAMPLE_L_O 0x34 -#define V_008DFC_SQ_IMAGE_SAMPLE_B_O 0x35 -#define V_008DFC_SQ_IMAGE_SAMPLE_B_CL_O 0x36 -#define V_008DFC_SQ_IMAGE_SAMPLE_LZ_O 0x37 -#define V_008DFC_SQ_IMAGE_SAMPLE_C_O 0x38 -#define V_008DFC_SQ_IMAGE_SAMPLE_C_CL_O 0x39 -#define V_008DFC_SQ_IMAGE_SAMPLE_C_D_O 0x3A -#define V_008DFC_SQ_IMAGE_SAMPLE_C_D_CL_O 0x3B -#define V_008DFC_SQ_IMAGE_SAMPLE_C_L_O 0x3C -#define V_008DFC_SQ_IMAGE_SAMPLE_C_B_O 0x3D -#define V_008DFC_SQ_IMAGE_SAMPLE_C_B_CL_O 0x3E -#define V_008DFC_SQ_IMAGE_SAMPLE_C_LZ_O 0x3F -#define V_008DFC_SQ_IMAGE_GATHER4 0x40 -#define V_008DFC_SQ_IMAGE_GATHER4_CL 0x41 -#define V_008DFC_SQ_IMAGE_GATHER4_L 0x44 -#define V_008DFC_SQ_IMAGE_GATHER4_B 0x45 -#define V_008DFC_SQ_IMAGE_GATHER4_B_CL 0x46 -#define V_008DFC_SQ_IMAGE_GATHER4_LZ 0x47 -#define V_008DFC_SQ_IMAGE_GATHER4_C 0x48 -#define V_008DFC_SQ_IMAGE_GATHER4_C_CL 0x49 -#define V_008DFC_SQ_IMAGE_GATHER4_C_L 0x4C -#define V_008DFC_SQ_IMAGE_GATHER4_C_B 0x4D -#define V_008DFC_SQ_IMAGE_GATHER4_C_B_CL 0x4E -#define V_008DFC_SQ_IMAGE_GATHER4_C_LZ 0x4F -#define V_008DFC_SQ_IMAGE_GATHER4_O 0x50 -#define V_008DFC_SQ_IMAGE_GATHER4_CL_O 0x51 -#define V_008DFC_SQ_IMAGE_GATHER4_L_O 0x54 -#define V_008DFC_SQ_IMAGE_GATHER4_B_O 0x55 -#define V_008DFC_SQ_IMAGE_GATHER4_B_CL_O 0x56 -#define V_008DFC_SQ_IMAGE_GATHER4_LZ_O 0x57 -#define V_008DFC_SQ_IMAGE_GATHER4_C_O 0x58 -#define V_008DFC_SQ_IMAGE_GATHER4_C_CL_O 0x59 -#define V_008DFC_SQ_IMAGE_GATHER4_C_L_O 0x5C -#define V_008DFC_SQ_IMAGE_GATHER4_C_B_O 0x5D -#define V_008DFC_SQ_IMAGE_GATHER4_C_B_CL_O 0x5E -#define V_008DFC_SQ_IMAGE_GATHER4_C_LZ_O 0x5F -#define V_008DFC_SQ_IMAGE_GET_LOD 0x60 -#define V_008DFC_SQ_IMAGE_SAMPLE_CD 0x68 -#define V_008DFC_SQ_IMAGE_SAMPLE_CD_CL 0x69 -#define V_008DFC_SQ_IMAGE_SAMPLE_C_CD 0x6A -#define V_008DFC_SQ_IMAGE_SAMPLE_C_CD_CL 0x6B -#define V_008DFC_SQ_IMAGE_SAMPLE_CD_O 0x6C -#define V_008DFC_SQ_IMAGE_SAMPLE_CD_CL_O 0x6D -#define V_008DFC_SQ_IMAGE_SAMPLE_C_CD_O 0x6E -#define V_008DFC_SQ_IMAGE_SAMPLE_C_CD_CL_O 0x6F -#define S_008DFC_SLC(x) (((x) & 0x1) << 25) -#define G_008DFC_SLC(x) (((x) >> 25) & 0x1) -#define C_008DFC_SLC 0xFDFFFFFF -#define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26) -#define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F) -#define C_008DFC_ENCODING 0x03FFFFFF -#define V_008DFC_SQ_ENC_MIMG_FIELD 0x3C -#define R_008DFC_SQ_SOPP 0x008DFC -#define S_008DFC_SIMM16(x) (((x) & 0xFFFF) << 0) -#define G_008DFC_SIMM16(x) (((x) >> 0) & 0xFFFF) -#define C_008DFC_SIMM16 0xFFFF0000 -#define S_008DFC_OP(x) (((x) & 0x7F) << 16) -#define G_008DFC_OP(x) (((x) >> 16) & 0x7F) -#define C_008DFC_OP 0xFF80FFFF -#define V_008DFC_SQ_S_NOP 0x00 -#define V_008DFC_SQ_S_ENDPGM 0x01 -#define V_008DFC_SQ_S_BRANCH 0x02 -#define V_008DFC_SQ_S_CBRANCH_SCC0 0x04 -#define V_008DFC_SQ_S_CBRANCH_SCC1 0x05 -#define V_008DFC_SQ_S_CBRANCH_VCCZ 0x06 -#define V_008DFC_SQ_S_CBRANCH_VCCNZ 0x07 -#define V_008DFC_SQ_S_CBRANCH_EXECZ 0x08 -#define V_008DFC_SQ_S_CBRANCH_EXECNZ 0x09 -#define V_008DFC_SQ_S_BARRIER 0x0A -/* CIK */ -#define V_008DFC_SQ_S_SETKILL 0x0B -/* */ -#define V_008DFC_SQ_S_WAITCNT 0x0C -#define V_008DFC_SQ_S_SETHALT 0x0D -#define V_008DFC_SQ_S_SLEEP 0x0E -#define V_008DFC_SQ_S_SETPRIO 0x0F -#define V_008DFC_SQ_S_SENDMSG 0x10 -#define V_008DFC_SQ_S_SENDMSGHALT 0x11 -#define V_008DFC_SQ_S_TRAP 0x12 -#define V_008DFC_SQ_S_ICACHE_INV 0x13 -#define V_008DFC_SQ_S_INCPERFLEVEL 0x14 -#define V_008DFC_SQ_S_DECPERFLEVEL 0x15 -#define V_008DFC_SQ_S_TTRACEDATA 0x16 -/* CIK */ -#define V_008DFC_SQ_S_CBRANCH_CDBGSYS 0x17 -#define V_008DFC_SQ_S_CBRANCH_CDBGUSER 0x18 -#define V_008DFC_SQ_S_CBRANCH_CDBGSYS_OR_USER 0x19 -#define V_008DFC_SQ_S_CBRANCH_CDBGSYS_AND_USER 0x1A -/* */ -#define S_008DFC_ENCODING(x) (((x) & 0x1FF) << 23) -#define G_008DFC_ENCODING(x) (((x) >> 23) & 0x1FF) -#define C_008DFC_ENCODING 0x007FFFFF -#define V_008DFC_SQ_ENC_SOPP_FIELD 0x17F -#define R_008DFC_SQ_VINTRP 0x008DFC -#define S_008DFC_VSRC(x) (((x) & 0xFF) << 0) -#define G_008DFC_VSRC(x) (((x) >> 0) & 0xFF) -#define C_008DFC_VSRC 0xFFFFFF00 -#define V_008DFC_SQ_VGPR 0x00 -#define S_008DFC_ATTRCHAN(x) (((x) & 0x03) << 8) -#define G_008DFC_ATTRCHAN(x) (((x) >> 8) & 0x03) -#define C_008DFC_ATTRCHAN 0xFFFFFCFF -#define V_008DFC_SQ_CHAN_X 0x00 -#define V_008DFC_SQ_CHAN_Y 0x01 -#define V_008DFC_SQ_CHAN_Z 0x02 -#define V_008DFC_SQ_CHAN_W 0x03 -#define S_008DFC_ATTR(x) (((x) & 0x3F) << 10) -#define G_008DFC_ATTR(x) (((x) >> 10) & 0x3F) -#define C_008DFC_ATTR 0xFFFF03FF -#define V_008DFC_SQ_ATTR 0x00 -#define S_008DFC_OP(x) (((x) & 0x03) << 16) -#define G_008DFC_OP(x) (((x) >> 16) & 0x03) -#define C_008DFC_OP 0xFFFCFFFF -#define V_008DFC_SQ_V_INTERP_P1_F32 0x00 -#define V_008DFC_SQ_V_INTERP_P2_F32 0x01 -#define V_008DFC_SQ_V_INTERP_MOV_F32 0x02 -#define S_008DFC_VDST(x) (((x) & 0xFF) << 18) -#define G_008DFC_VDST(x) (((x) >> 18) & 0xFF) -#define C_008DFC_VDST 0xFC03FFFF -#define V_008DFC_SQ_VGPR 0x00 -#define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26) -#define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F) -#define C_008DFC_ENCODING 0x03FFFFFF -#define V_008DFC_SQ_ENC_VINTRP_FIELD 0x32 -#define R_008DFC_SQ_MTBUF_0 0x008DFC -#define S_008DFC_OFFSET(x) (((x) & 0xFFF) << 0) -#define G_008DFC_OFFSET(x) (((x) >> 0) & 0xFFF) -#define C_008DFC_OFFSET 0xFFFFF000 -#define S_008DFC_OFFEN(x) (((x) & 0x1) << 12) -#define G_008DFC_OFFEN(x) (((x) >> 12) & 0x1) -#define C_008DFC_OFFEN 0xFFFFEFFF -#define S_008DFC_IDXEN(x) (((x) & 0x1) << 13) -#define G_008DFC_IDXEN(x) (((x) >> 13) & 0x1) -#define C_008DFC_IDXEN 0xFFFFDFFF -#define S_008DFC_GLC(x) (((x) & 0x1) << 14) -#define G_008DFC_GLC(x) (((x) >> 14) & 0x1) -#define C_008DFC_GLC 0xFFFFBFFF -#define S_008DFC_ADDR64(x) (((x) & 0x1) << 15) -#define G_008DFC_ADDR64(x) (((x) >> 15) & 0x1) -#define C_008DFC_ADDR64 0xFFFF7FFF -#define S_008DFC_OP(x) (((x) & 0x07) << 16) -#define G_008DFC_OP(x) (((x) >> 16) & 0x07) -#define C_008DFC_OP 0xFFF8FFFF -#define V_008DFC_SQ_TBUFFER_LOAD_FORMAT_X 0x00 -#define V_008DFC_SQ_TBUFFER_LOAD_FORMAT_XY 0x01 -#define V_008DFC_SQ_TBUFFER_LOAD_FORMAT_XYZ 0x02 -#define V_008DFC_SQ_TBUFFER_LOAD_FORMAT_XYZW 0x03 -#define V_008DFC_SQ_TBUFFER_STORE_FORMAT_X 0x04 -#define V_008DFC_SQ_TBUFFER_STORE_FORMAT_XY 0x05 -#define V_008DFC_SQ_TBUFFER_STORE_FORMAT_XYZ 0x06 -#define V_008DFC_SQ_TBUFFER_STORE_FORMAT_XYZW 0x07 -#define S_008DFC_DFMT(x) (((x) & 0x0F) << 19) -#define G_008DFC_DFMT(x) (((x) >> 19) & 0x0F) -#define C_008DFC_DFMT 0xFF87FFFF -#define S_008DFC_NFMT(x) (((x) & 0x07) << 23) -#define G_008DFC_NFMT(x) (((x) >> 23) & 0x07) -#define C_008DFC_NFMT 0xFC7FFFFF -#define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26) -#define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F) -#define C_008DFC_ENCODING 0x03FFFFFF -#define V_008DFC_SQ_ENC_MTBUF_FIELD 0x3A -#define R_008DFC_SQ_SMRD 0x008DFC -#define S_008DFC_OFFSET(x) (((x) & 0xFF) << 0) -#define G_008DFC_OFFSET(x) (((x) >> 0) & 0xFF) -#define C_008DFC_OFFSET 0xFFFFFF00 -#define V_008DFC_SQ_SGPR 0x00 -/* CIK */ -#define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68 -#define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69 -/* */ -#define V_008DFC_SQ_VCC_LO 0x6A -#define V_008DFC_SQ_VCC_HI 0x6B -#define V_008DFC_SQ_TBA_LO 0x6C -#define V_008DFC_SQ_TBA_HI 0x6D -#define V_008DFC_SQ_TMA_LO 0x6E -#define V_008DFC_SQ_TMA_HI 0x6F -#define V_008DFC_SQ_TTMP0 0x70 -#define V_008DFC_SQ_TTMP1 0x71 -#define V_008DFC_SQ_TTMP2 0x72 -#define V_008DFC_SQ_TTMP3 0x73 -#define V_008DFC_SQ_TTMP4 0x74 -#define V_008DFC_SQ_TTMP5 0x75 -#define V_008DFC_SQ_TTMP6 0x76 -#define V_008DFC_SQ_TTMP7 0x77 -#define V_008DFC_SQ_TTMP8 0x78 -#define V_008DFC_SQ_TTMP9 0x79 -#define V_008DFC_SQ_TTMP10 0x7A -#define V_008DFC_SQ_TTMP11 0x7B -/* CIK */ -#define V_008DFC_SQ_SRC_LITERAL 0xFF -/* */ -#define S_008DFC_IMM(x) (((x) & 0x1) << 8) -#define G_008DFC_IMM(x) (((x) >> 8) & 0x1) -#define C_008DFC_IMM 0xFFFFFEFF -#define S_008DFC_SBASE(x) (((x) & 0x3F) << 9) -#define G_008DFC_SBASE(x) (((x) >> 9) & 0x3F) -#define C_008DFC_SBASE 0xFFFF81FF -#define S_008DFC_SDST(x) (((x) & 0x7F) << 15) -#define G_008DFC_SDST(x) (((x) >> 15) & 0x7F) -#define C_008DFC_SDST 0xFFC07FFF -#define V_008DFC_SQ_SGPR 0x00 -/* CIK */ -#define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68 -#define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69 -/* */ -#define V_008DFC_SQ_VCC_LO 0x6A -#define V_008DFC_SQ_VCC_HI 0x6B -#define V_008DFC_SQ_TBA_LO 0x6C -#define V_008DFC_SQ_TBA_HI 0x6D -#define V_008DFC_SQ_TMA_LO 0x6E -#define V_008DFC_SQ_TMA_HI 0x6F -#define V_008DFC_SQ_TTMP0 0x70 -#define V_008DFC_SQ_TTMP1 0x71 -#define V_008DFC_SQ_TTMP2 0x72 -#define V_008DFC_SQ_TTMP3 0x73 -#define V_008DFC_SQ_TTMP4 0x74 -#define V_008DFC_SQ_TTMP5 0x75 -#define V_008DFC_SQ_TTMP6 0x76 -#define V_008DFC_SQ_TTMP7 0x77 -#define V_008DFC_SQ_TTMP8 0x78 -#define V_008DFC_SQ_TTMP9 0x79 -#define V_008DFC_SQ_TTMP10 0x7A -#define V_008DFC_SQ_TTMP11 0x7B -#define V_008DFC_SQ_M0 0x7C -#define V_008DFC_SQ_EXEC_LO 0x7E -#define V_008DFC_SQ_EXEC_HI 0x7F -#define S_008DFC_OP(x) (((x) & 0x1F) << 22) -#define G_008DFC_OP(x) (((x) >> 22) & 0x1F) -#define C_008DFC_OP 0xF83FFFFF -#define V_008DFC_SQ_S_LOAD_DWORD 0x00 -#define V_008DFC_SQ_S_LOAD_DWORDX2 0x01 -#define V_008DFC_SQ_S_LOAD_DWORDX4 0x02 -#define V_008DFC_SQ_S_LOAD_DWORDX8 0x03 -#define V_008DFC_SQ_S_LOAD_DWORDX16 0x04 -#define V_008DFC_SQ_S_BUFFER_LOAD_DWORD 0x08 -#define V_008DFC_SQ_S_BUFFER_LOAD_DWORDX2 0x09 -#define V_008DFC_SQ_S_BUFFER_LOAD_DWORDX4 0x0A -#define V_008DFC_SQ_S_BUFFER_LOAD_DWORDX8 0x0B -#define V_008DFC_SQ_S_BUFFER_LOAD_DWORDX16 0x0C -/* CIK */ -#define V_008DFC_SQ_S_DCACHE_INV_VOL 0x1D -/* */ -#define V_008DFC_SQ_S_MEMTIME 0x1E -#define V_008DFC_SQ_S_DCACHE_INV 0x1F -#define S_008DFC_ENCODING(x) (((x) & 0x1F) << 27) -#define G_008DFC_ENCODING(x) (((x) >> 27) & 0x1F) -#define C_008DFC_ENCODING 0x07FFFFFF -#define V_008DFC_SQ_ENC_SMRD_FIELD 0x18 -/* CIK */ -#define R_008DFC_SQ_FLAT_0 0x008DFC -#define S_008DFC_GLC(x) (((x) & 0x1) << 16) -#define G_008DFC_GLC(x) (((x) >> 16) & 0x1) -#define C_008DFC_GLC 0xFFFEFFFF -#define S_008DFC_SLC(x) (((x) & 0x1) << 17) -#define G_008DFC_SLC(x) (((x) >> 17) & 0x1) -#define C_008DFC_SLC 0xFFFDFFFF -#define S_008DFC_OP(x) (((x) & 0x7F) << 18) -#define G_008DFC_OP(x) (((x) >> 18) & 0x7F) -#define C_008DFC_OP 0xFE03FFFF -#define V_008DFC_SQ_FLAT_LOAD_UBYTE 0x08 -#define V_008DFC_SQ_FLAT_LOAD_SBYTE 0x09 -#define V_008DFC_SQ_FLAT_LOAD_USHORT 0x0A -#define V_008DFC_SQ_FLAT_LOAD_SSHORT 0x0B -#define V_008DFC_SQ_FLAT_LOAD_DWORD 0x0C -#define V_008DFC_SQ_FLAT_LOAD_DWORDX2 0x0D -#define V_008DFC_SQ_FLAT_LOAD_DWORDX4 0x0E -#define V_008DFC_SQ_FLAT_LOAD_DWORDX3 0x0F -#define V_008DFC_SQ_FLAT_STORE_BYTE 0x18 -#define V_008DFC_SQ_FLAT_STORE_SHORT 0x1A -#define V_008DFC_SQ_FLAT_STORE_DWORD 0x1C -#define V_008DFC_SQ_FLAT_STORE_DWORDX2 0x1D -#define V_008DFC_SQ_FLAT_STORE_DWORDX4 0x1E -#define V_008DFC_SQ_FLAT_STORE_DWORDX3 0x1F -#define V_008DFC_SQ_FLAT_ATOMIC_SWAP 0x30 -#define V_008DFC_SQ_FLAT_ATOMIC_CMPSWAP 0x31 -#define V_008DFC_SQ_FLAT_ATOMIC_ADD 0x32 -#define V_008DFC_SQ_FLAT_ATOMIC_SUB 0x33 -#define V_008DFC_SQ_FLAT_ATOMIC_SMIN 0x35 -#define V_008DFC_SQ_FLAT_ATOMIC_UMIN 0x36 -#define V_008DFC_SQ_FLAT_ATOMIC_SMAX 0x37 -#define V_008DFC_SQ_FLAT_ATOMIC_UMAX 0x38 -#define V_008DFC_SQ_FLAT_ATOMIC_AND 0x39 -#define V_008DFC_SQ_FLAT_ATOMIC_OR 0x3A -#define V_008DFC_SQ_FLAT_ATOMIC_XOR 0x3B -#define V_008DFC_SQ_FLAT_ATOMIC_INC 0x3C -#define V_008DFC_SQ_FLAT_ATOMIC_DEC 0x3D -#define V_008DFC_SQ_FLAT_ATOMIC_FCMPSWAP 0x3E -#define V_008DFC_SQ_FLAT_ATOMIC_FMIN 0x3F -#define V_008DFC_SQ_FLAT_ATOMIC_FMAX 0x40 -#define V_008DFC_SQ_FLAT_ATOMIC_SWAP_X2 0x50 -#define V_008DFC_SQ_FLAT_ATOMIC_CMPSWAP_X2 0x51 -#define V_008DFC_SQ_FLAT_ATOMIC_ADD_X2 0x52 -#define V_008DFC_SQ_FLAT_ATOMIC_SUB_X2 0x53 -#define V_008DFC_SQ_FLAT_ATOMIC_SMIN_X2 0x55 -#define V_008DFC_SQ_FLAT_ATOMIC_UMIN_X2 0x56 -#define V_008DFC_SQ_FLAT_ATOMIC_SMAX_X2 0x57 -#define V_008DFC_SQ_FLAT_ATOMIC_UMAX_X2 0x58 -#define V_008DFC_SQ_FLAT_ATOMIC_AND_X2 0x59 -#define V_008DFC_SQ_FLAT_ATOMIC_OR_X2 0x5A -#define V_008DFC_SQ_FLAT_ATOMIC_XOR_X2 0x5B -#define V_008DFC_SQ_FLAT_ATOMIC_INC_X2 0x5C -#define V_008DFC_SQ_FLAT_ATOMIC_DEC_X2 0x5D -#define V_008DFC_SQ_FLAT_ATOMIC_FCMPSWAP_X2 0x5E -#define V_008DFC_SQ_FLAT_ATOMIC_FMIN_X2 0x5F -#define V_008DFC_SQ_FLAT_ATOMIC_FMAX_X2 0x60 -#define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26) -#define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F) -#define C_008DFC_ENCODING 0x03FFFFFF -#define V_008DFC_SQ_ENC_FLAT_FIELD 0x37 -/* */ -#define R_008DFC_SQ_EXP_1 0x008DFC -#define S_008DFC_VSRC0(x) (((x) & 0xFF) << 0) -#define G_008DFC_VSRC0(x) (((x) >> 0) & 0xFF) -#define C_008DFC_VSRC0 0xFFFFFF00 -#define V_008DFC_SQ_VGPR 0x00 -#define S_008DFC_VSRC1(x) (((x) & 0xFF) << 8) -#define G_008DFC_VSRC1(x) (((x) >> 8) & 0xFF) -#define C_008DFC_VSRC1 0xFFFF00FF -#define V_008DFC_SQ_VGPR 0x00 -#define S_008DFC_VSRC2(x) (((x) & 0xFF) << 16) -#define G_008DFC_VSRC2(x) (((x) >> 16) & 0xFF) -#define C_008DFC_VSRC2 0xFF00FFFF -#define V_008DFC_SQ_VGPR 0x00 -#define S_008DFC_VSRC3(x) (((x) & 0xFF) << 24) -#define G_008DFC_VSRC3(x) (((x) >> 24) & 0xFF) -#define C_008DFC_VSRC3 0x00FFFFFF -#define V_008DFC_SQ_VGPR 0x00 -#define R_008DFC_SQ_DS_1 0x008DFC -#define S_008DFC_ADDR(x) (((x) & 0xFF) << 0) -#define G_008DFC_ADDR(x) (((x) >> 0) & 0xFF) -#define C_008DFC_ADDR 0xFFFFFF00 -#define V_008DFC_SQ_VGPR 0x00 -#define S_008DFC_DATA0(x) (((x) & 0xFF) << 8) -#define G_008DFC_DATA0(x) (((x) >> 8) & 0xFF) -#define C_008DFC_DATA0 0xFFFF00FF -#define V_008DFC_SQ_VGPR 0x00 -#define S_008DFC_DATA1(x) (((x) & 0xFF) << 16) -#define G_008DFC_DATA1(x) (((x) >> 16) & 0xFF) -#define C_008DFC_DATA1 0xFF00FFFF -#define V_008DFC_SQ_VGPR 0x00 -#define S_008DFC_VDST(x) (((x) & 0xFF) << 24) -#define G_008DFC_VDST(x) (((x) >> 24) & 0xFF) -#define C_008DFC_VDST 0x00FFFFFF -#define V_008DFC_SQ_VGPR 0x00 -#define R_008DFC_SQ_VOPC 0x008DFC -#define S_008DFC_SRC0(x) (((x) & 0x1FF) << 0) -#define G_008DFC_SRC0(x) (((x) >> 0) & 0x1FF) -#define C_008DFC_SRC0 0xFFFFFE00 -#define V_008DFC_SQ_SGPR 0x00 -#define V_008DFC_SQ_VCC_LO 0x6A -#define V_008DFC_SQ_VCC_HI 0x6B -#define V_008DFC_SQ_TBA_LO 0x6C -#define V_008DFC_SQ_TBA_HI 0x6D -#define V_008DFC_SQ_TMA_LO 0x6E -#define V_008DFC_SQ_TMA_HI 0x6F -#define V_008DFC_SQ_TTMP0 0x70 -#define V_008DFC_SQ_TTMP1 0x71 -#define V_008DFC_SQ_TTMP2 0x72 -#define V_008DFC_SQ_TTMP3 0x73 -#define V_008DFC_SQ_TTMP4 0x74 -#define V_008DFC_SQ_TTMP5 0x75 -#define V_008DFC_SQ_TTMP6 0x76 -#define V_008DFC_SQ_TTMP7 0x77 -#define V_008DFC_SQ_TTMP8 0x78 -#define V_008DFC_SQ_TTMP9 0x79 -#define V_008DFC_SQ_TTMP10 0x7A -#define V_008DFC_SQ_TTMP11 0x7B -#define V_008DFC_SQ_M0 0x7C -#define V_008DFC_SQ_EXEC_LO 0x7E -#define V_008DFC_SQ_EXEC_HI 0x7F -#define V_008DFC_SQ_SRC_0 0x80 -#define V_008DFC_SQ_SRC_1_INT 0x81 -#define V_008DFC_SQ_SRC_2_INT 0x82 -#define V_008DFC_SQ_SRC_3_INT 0x83 -#define V_008DFC_SQ_SRC_4_INT 0x84 -#define V_008DFC_SQ_SRC_5_INT 0x85 -#define V_008DFC_SQ_SRC_6_INT 0x86 -#define V_008DFC_SQ_SRC_7_INT 0x87 -#define V_008DFC_SQ_SRC_8_INT 0x88 -#define V_008DFC_SQ_SRC_9_INT 0x89 -#define V_008DFC_SQ_SRC_10_INT 0x8A -#define V_008DFC_SQ_SRC_11_INT 0x8B -#define V_008DFC_SQ_SRC_12_INT 0x8C -#define V_008DFC_SQ_SRC_13_INT 0x8D -#define V_008DFC_SQ_SRC_14_INT 0x8E -#define V_008DFC_SQ_SRC_15_INT 0x8F -#define V_008DFC_SQ_SRC_16_INT 0x90 -#define V_008DFC_SQ_SRC_17_INT 0x91 -#define V_008DFC_SQ_SRC_18_INT 0x92 -#define V_008DFC_SQ_SRC_19_INT 0x93 -#define V_008DFC_SQ_SRC_20_INT 0x94 -#define V_008DFC_SQ_SRC_21_INT 0x95 -#define V_008DFC_SQ_SRC_22_INT 0x96 -#define V_008DFC_SQ_SRC_23_INT 0x97 -#define V_008DFC_SQ_SRC_24_INT 0x98 -#define V_008DFC_SQ_SRC_25_INT 0x99 -#define V_008DFC_SQ_SRC_26_INT 0x9A -#define V_008DFC_SQ_SRC_27_INT 0x9B -#define V_008DFC_SQ_SRC_28_INT 0x9C -#define V_008DFC_SQ_SRC_29_INT 0x9D -#define V_008DFC_SQ_SRC_30_INT 0x9E -#define V_008DFC_SQ_SRC_31_INT 0x9F -#define V_008DFC_SQ_SRC_32_INT 0xA0 -#define V_008DFC_SQ_SRC_33_INT 0xA1 -#define V_008DFC_SQ_SRC_34_INT 0xA2 -#define V_008DFC_SQ_SRC_35_INT 0xA3 -#define V_008DFC_SQ_SRC_36_INT 0xA4 -#define V_008DFC_SQ_SRC_37_INT 0xA5 -#define V_008DFC_SQ_SRC_38_INT 0xA6 -#define V_008DFC_SQ_SRC_39_INT 0xA7 -#define V_008DFC_SQ_SRC_40_INT 0xA8 -#define V_008DFC_SQ_SRC_41_INT 0xA9 -#define V_008DFC_SQ_SRC_42_INT 0xAA -#define V_008DFC_SQ_SRC_43_INT 0xAB -#define V_008DFC_SQ_SRC_44_INT 0xAC -#define V_008DFC_SQ_SRC_45_INT 0xAD -#define V_008DFC_SQ_SRC_46_INT 0xAE -#define V_008DFC_SQ_SRC_47_INT 0xAF -#define V_008DFC_SQ_SRC_48_INT 0xB0 -#define V_008DFC_SQ_SRC_49_INT 0xB1 -#define V_008DFC_SQ_SRC_50_INT 0xB2 -#define V_008DFC_SQ_SRC_51_INT 0xB3 -#define V_008DFC_SQ_SRC_52_INT 0xB4 -#define V_008DFC_SQ_SRC_53_INT 0xB5 -#define V_008DFC_SQ_SRC_54_INT 0xB6 -#define V_008DFC_SQ_SRC_55_INT 0xB7 -#define V_008DFC_SQ_SRC_56_INT 0xB8 -#define V_008DFC_SQ_SRC_57_INT 0xB9 -#define V_008DFC_SQ_SRC_58_INT 0xBA -#define V_008DFC_SQ_SRC_59_INT 0xBB -#define V_008DFC_SQ_SRC_60_INT 0xBC -#define V_008DFC_SQ_SRC_61_INT 0xBD -#define V_008DFC_SQ_SRC_62_INT 0xBE -#define V_008DFC_SQ_SRC_63_INT 0xBF -#define V_008DFC_SQ_SRC_64_INT 0xC0 -#define V_008DFC_SQ_SRC_M_1_INT 0xC1 -#define V_008DFC_SQ_SRC_M_2_INT 0xC2 -#define V_008DFC_SQ_SRC_M_3_INT 0xC3 -#define V_008DFC_SQ_SRC_M_4_INT 0xC4 -#define V_008DFC_SQ_SRC_M_5_INT 0xC5 -#define V_008DFC_SQ_SRC_M_6_INT 0xC6 -#define V_008DFC_SQ_SRC_M_7_INT 0xC7 -#define V_008DFC_SQ_SRC_M_8_INT 0xC8 -#define V_008DFC_SQ_SRC_M_9_INT 0xC9 -#define V_008DFC_SQ_SRC_M_10_INT 0xCA -#define V_008DFC_SQ_SRC_M_11_INT 0xCB -#define V_008DFC_SQ_SRC_M_12_INT 0xCC -#define V_008DFC_SQ_SRC_M_13_INT 0xCD -#define V_008DFC_SQ_SRC_M_14_INT 0xCE -#define V_008DFC_SQ_SRC_M_15_INT 0xCF -#define V_008DFC_SQ_SRC_M_16_INT 0xD0 -#define V_008DFC_SQ_SRC_0_5 0xF0 -#define V_008DFC_SQ_SRC_M_0_5 0xF1 -#define V_008DFC_SQ_SRC_1 0xF2 -#define V_008DFC_SQ_SRC_M_1 0xF3 -#define V_008DFC_SQ_SRC_2 0xF4 -#define V_008DFC_SQ_SRC_M_2 0xF5 -#define V_008DFC_SQ_SRC_4 0xF6 -#define V_008DFC_SQ_SRC_M_4 0xF7 -#define V_008DFC_SQ_SRC_VCCZ 0xFB -#define V_008DFC_SQ_SRC_EXECZ 0xFC -#define V_008DFC_SQ_SRC_SCC 0xFD -#define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE -#define V_008DFC_SQ_SRC_VGPR 0x100 -#define S_008DFC_VSRC1(x) (((x) & 0xFF) << 9) -#define G_008DFC_VSRC1(x) (((x) >> 9) & 0xFF) -#define C_008DFC_VSRC1 0xFFFE01FF -#define V_008DFC_SQ_VGPR 0x00 -#define S_008DFC_OP(x) (((x) & 0xFF) << 17) -#define G_008DFC_OP(x) (((x) >> 17) & 0xFF) -#define C_008DFC_OP 0xFE01FFFF -#define V_008DFC_SQ_V_CMP_F_F32 0x00 -#define V_008DFC_SQ_V_CMP_LT_F32 0x01 -#define V_008DFC_SQ_V_CMP_EQ_F32 0x02 -#define V_008DFC_SQ_V_CMP_LE_F32 0x03 -#define V_008DFC_SQ_V_CMP_GT_F32 0x04 -#define V_008DFC_SQ_V_CMP_LG_F32 0x05 -#define V_008DFC_SQ_V_CMP_GE_F32 0x06 -#define V_008DFC_SQ_V_CMP_O_F32 0x07 -#define V_008DFC_SQ_V_CMP_U_F32 0x08 -#define V_008DFC_SQ_V_CMP_NGE_F32 0x09 -#define V_008DFC_SQ_V_CMP_NLG_F32 0x0A -#define V_008DFC_SQ_V_CMP_NGT_F32 0x0B -#define V_008DFC_SQ_V_CMP_NLE_F32 0x0C -#define V_008DFC_SQ_V_CMP_NEQ_F32 0x0D -#define V_008DFC_SQ_V_CMP_NLT_F32 0x0E -#define V_008DFC_SQ_V_CMP_TRU_F32 0x0F -#define V_008DFC_SQ_V_CMPX_F_F32 0x10 -#define V_008DFC_SQ_V_CMPX_LT_F32 0x11 -#define V_008DFC_SQ_V_CMPX_EQ_F32 0x12 -#define V_008DFC_SQ_V_CMPX_LE_F32 0x13 -#define V_008DFC_SQ_V_CMPX_GT_F32 0x14 -#define V_008DFC_SQ_V_CMPX_LG_F32 0x15 -#define V_008DFC_SQ_V_CMPX_GE_F32 0x16 -#define V_008DFC_SQ_V_CMPX_O_F32 0x17 -#define V_008DFC_SQ_V_CMPX_U_F32 0x18 -#define V_008DFC_SQ_V_CMPX_NGE_F32 0x19 -#define V_008DFC_SQ_V_CMPX_NLG_F32 0x1A -#define V_008DFC_SQ_V_CMPX_NGT_F32 0x1B -#define V_008DFC_SQ_V_CMPX_NLE_F32 0x1C -#define V_008DFC_SQ_V_CMPX_NEQ_F32 0x1D -#define V_008DFC_SQ_V_CMPX_NLT_F32 0x1E -#define V_008DFC_SQ_V_CMPX_TRU_F32 0x1F -#define V_008DFC_SQ_V_CMP_F_F64 0x20 -#define V_008DFC_SQ_V_CMP_LT_F64 0x21 -#define V_008DFC_SQ_V_CMP_EQ_F64 0x22 -#define V_008DFC_SQ_V_CMP_LE_F64 0x23 -#define V_008DFC_SQ_V_CMP_GT_F64 0x24 -#define V_008DFC_SQ_V_CMP_LG_F64 0x25 -#define V_008DFC_SQ_V_CMP_GE_F64 0x26 -#define V_008DFC_SQ_V_CMP_O_F64 0x27 -#define V_008DFC_SQ_V_CMP_U_F64 0x28 -#define V_008DFC_SQ_V_CMP_NGE_F64 0x29 -#define V_008DFC_SQ_V_CMP_NLG_F64 0x2A -#define V_008DFC_SQ_V_CMP_NGT_F64 0x2B -#define V_008DFC_SQ_V_CMP_NLE_F64 0x2C -#define V_008DFC_SQ_V_CMP_NEQ_F64 0x2D -#define V_008DFC_SQ_V_CMP_NLT_F64 0x2E -#define V_008DFC_SQ_V_CMP_TRU_F64 0x2F -#define V_008DFC_SQ_V_CMPX_F_F64 0x30 -#define V_008DFC_SQ_V_CMPX_LT_F64 0x31 -#define V_008DFC_SQ_V_CMPX_EQ_F64 0x32 -#define V_008DFC_SQ_V_CMPX_LE_F64 0x33 -#define V_008DFC_SQ_V_CMPX_GT_F64 0x34 -#define V_008DFC_SQ_V_CMPX_LG_F64 0x35 -#define V_008DFC_SQ_V_CMPX_GE_F64 0x36 -#define V_008DFC_SQ_V_CMPX_O_F64 0x37 -#define V_008DFC_SQ_V_CMPX_U_F64 0x38 -#define V_008DFC_SQ_V_CMPX_NGE_F64 0x39 -#define V_008DFC_SQ_V_CMPX_NLG_F64 0x3A -#define V_008DFC_SQ_V_CMPX_NGT_F64 0x3B -#define V_008DFC_SQ_V_CMPX_NLE_F64 0x3C -#define V_008DFC_SQ_V_CMPX_NEQ_F64 0x3D -#define V_008DFC_SQ_V_CMPX_NLT_F64 0x3E -#define V_008DFC_SQ_V_CMPX_TRU_F64 0x3F -#define V_008DFC_SQ_V_CMPS_F_F32 0x40 -#define V_008DFC_SQ_V_CMPS_LT_F32 0x41 -#define V_008DFC_SQ_V_CMPS_EQ_F32 0x42 -#define V_008DFC_SQ_V_CMPS_LE_F32 0x43 -#define V_008DFC_SQ_V_CMPS_GT_F32 0x44 -#define V_008DFC_SQ_V_CMPS_LG_F32 0x45 -#define V_008DFC_SQ_V_CMPS_GE_F32 0x46 -#define V_008DFC_SQ_V_CMPS_O_F32 0x47 -#define V_008DFC_SQ_V_CMPS_U_F32 0x48 -#define V_008DFC_SQ_V_CMPS_NGE_F32 0x49 -#define V_008DFC_SQ_V_CMPS_NLG_F32 0x4A -#define V_008DFC_SQ_V_CMPS_NGT_F32 0x4B -#define V_008DFC_SQ_V_CMPS_NLE_F32 0x4C -#define V_008DFC_SQ_V_CMPS_NEQ_F32 0x4D -#define V_008DFC_SQ_V_CMPS_NLT_F32 0x4E -#define V_008DFC_SQ_V_CMPS_TRU_F32 0x4F -#define V_008DFC_SQ_V_CMPSX_F_F32 0x50 -#define V_008DFC_SQ_V_CMPSX_LT_F32 0x51 -#define V_008DFC_SQ_V_CMPSX_EQ_F32 0x52 -#define V_008DFC_SQ_V_CMPSX_LE_F32 0x53 -#define V_008DFC_SQ_V_CMPSX_GT_F32 0x54 -#define V_008DFC_SQ_V_CMPSX_LG_F32 0x55 -#define V_008DFC_SQ_V_CMPSX_GE_F32 0x56 -#define V_008DFC_SQ_V_CMPSX_O_F32 0x57 -#define V_008DFC_SQ_V_CMPSX_U_F32 0x58 -#define V_008DFC_SQ_V_CMPSX_NGE_F32 0x59 -#define V_008DFC_SQ_V_CMPSX_NLG_F32 0x5A -#define V_008DFC_SQ_V_CMPSX_NGT_F32 0x5B -#define V_008DFC_SQ_V_CMPSX_NLE_F32 0x5C -#define V_008DFC_SQ_V_CMPSX_NEQ_F32 0x5D -#define V_008DFC_SQ_V_CMPSX_NLT_F32 0x5E -#define V_008DFC_SQ_V_CMPSX_TRU_F32 0x5F -#define V_008DFC_SQ_V_CMPS_F_F64 0x60 -#define V_008DFC_SQ_V_CMPS_LT_F64 0x61 -#define V_008DFC_SQ_V_CMPS_EQ_F64 0x62 -#define V_008DFC_SQ_V_CMPS_LE_F64 0x63 -#define V_008DFC_SQ_V_CMPS_GT_F64 0x64 -#define V_008DFC_SQ_V_CMPS_LG_F64 0x65 -#define V_008DFC_SQ_V_CMPS_GE_F64 0x66 -#define V_008DFC_SQ_V_CMPS_O_F64 0x67 -#define V_008DFC_SQ_V_CMPS_U_F64 0x68 -#define V_008DFC_SQ_V_CMPS_NGE_F64 0x69 -#define V_008DFC_SQ_V_CMPS_NLG_F64 0x6A -#define V_008DFC_SQ_V_CMPS_NGT_F64 0x6B -#define V_008DFC_SQ_V_CMPS_NLE_F64 0x6C -#define V_008DFC_SQ_V_CMPS_NEQ_F64 0x6D -#define V_008DFC_SQ_V_CMPS_NLT_F64 0x6E -#define V_008DFC_SQ_V_CMPS_TRU_F64 0x6F -#define V_008DFC_SQ_V_CMPSX_F_F64 0x70 -#define V_008DFC_SQ_V_CMPSX_LT_F64 0x71 -#define V_008DFC_SQ_V_CMPSX_EQ_F64 0x72 -#define V_008DFC_SQ_V_CMPSX_LE_F64 0x73 -#define V_008DFC_SQ_V_CMPSX_GT_F64 0x74 -#define V_008DFC_SQ_V_CMPSX_LG_F64 0x75 -#define V_008DFC_SQ_V_CMPSX_GE_F64 0x76 -#define V_008DFC_SQ_V_CMPSX_O_F64 0x77 -#define V_008DFC_SQ_V_CMPSX_U_F64 0x78 -#define V_008DFC_SQ_V_CMPSX_NGE_F64 0x79 -#define V_008DFC_SQ_V_CMPSX_NLG_F64 0x7A -#define V_008DFC_SQ_V_CMPSX_NGT_F64 0x7B -#define V_008DFC_SQ_V_CMPSX_NLE_F64 0x7C -#define V_008DFC_SQ_V_CMPSX_NEQ_F64 0x7D -#define V_008DFC_SQ_V_CMPSX_NLT_F64 0x7E -#define V_008DFC_SQ_V_CMPSX_TRU_F64 0x7F -#define V_008DFC_SQ_V_CMP_F_I32 0x80 -#define V_008DFC_SQ_V_CMP_LT_I32 0x81 -#define V_008DFC_SQ_V_CMP_EQ_I32 0x82 -#define V_008DFC_SQ_V_CMP_LE_I32 0x83 -#define V_008DFC_SQ_V_CMP_GT_I32 0x84 -#define V_008DFC_SQ_V_CMP_NE_I32 0x85 -#define V_008DFC_SQ_V_CMP_GE_I32 0x86 -#define V_008DFC_SQ_V_CMP_T_I32 0x87 -#define V_008DFC_SQ_V_CMP_CLASS_F32 0x88 -#define V_008DFC_SQ_V_CMPX_F_I32 0x90 -#define V_008DFC_SQ_V_CMPX_LT_I32 0x91 -#define V_008DFC_SQ_V_CMPX_EQ_I32 0x92 -#define V_008DFC_SQ_V_CMPX_LE_I32 0x93 -#define V_008DFC_SQ_V_CMPX_GT_I32 0x94 -#define V_008DFC_SQ_V_CMPX_NE_I32 0x95 -#define V_008DFC_SQ_V_CMPX_GE_I32 0x96 -#define V_008DFC_SQ_V_CMPX_T_I32 0x97 -#define V_008DFC_SQ_V_CMPX_CLASS_F32 0x98 -#define V_008DFC_SQ_V_CMP_F_I64 0xA0 -#define V_008DFC_SQ_V_CMP_LT_I64 0xA1 -#define V_008DFC_SQ_V_CMP_EQ_I64 0xA2 -#define V_008DFC_SQ_V_CMP_LE_I64 0xA3 -#define V_008DFC_SQ_V_CMP_GT_I64 0xA4 -#define V_008DFC_SQ_V_CMP_NE_I64 0xA5 -#define V_008DFC_SQ_V_CMP_GE_I64 0xA6 -#define V_008DFC_SQ_V_CMP_T_I64 0xA7 -#define V_008DFC_SQ_V_CMP_CLASS_F64 0xA8 -#define V_008DFC_SQ_V_CMPX_F_I64 0xB0 -#define V_008DFC_SQ_V_CMPX_LT_I64 0xB1 -#define V_008DFC_SQ_V_CMPX_EQ_I64 0xB2 -#define V_008DFC_SQ_V_CMPX_LE_I64 0xB3 -#define V_008DFC_SQ_V_CMPX_GT_I64 0xB4 -#define V_008DFC_SQ_V_CMPX_NE_I64 0xB5 -#define V_008DFC_SQ_V_CMPX_GE_I64 0xB6 -#define V_008DFC_SQ_V_CMPX_T_I64 0xB7 -#define V_008DFC_SQ_V_CMPX_CLASS_F64 0xB8 -#define V_008DFC_SQ_V_CMP_F_U32 0xC0 -#define V_008DFC_SQ_V_CMP_LT_U32 0xC1 -#define V_008DFC_SQ_V_CMP_EQ_U32 0xC2 -#define V_008DFC_SQ_V_CMP_LE_U32 0xC3 -#define V_008DFC_SQ_V_CMP_GT_U32 0xC4 -#define V_008DFC_SQ_V_CMP_NE_U32 0xC5 -#define V_008DFC_SQ_V_CMP_GE_U32 0xC6 -#define V_008DFC_SQ_V_CMP_T_U32 0xC7 -#define V_008DFC_SQ_V_CMPX_F_U32 0xD0 -#define V_008DFC_SQ_V_CMPX_LT_U32 0xD1 -#define V_008DFC_SQ_V_CMPX_EQ_U32 0xD2 -#define V_008DFC_SQ_V_CMPX_LE_U32 0xD3 -#define V_008DFC_SQ_V_CMPX_GT_U32 0xD4 -#define V_008DFC_SQ_V_CMPX_NE_U32 0xD5 -#define V_008DFC_SQ_V_CMPX_GE_U32 0xD6 -#define V_008DFC_SQ_V_CMPX_T_U32 0xD7 -#define V_008DFC_SQ_V_CMP_F_U64 0xE0 -#define V_008DFC_SQ_V_CMP_LT_U64 0xE1 -#define V_008DFC_SQ_V_CMP_EQ_U64 0xE2 -#define V_008DFC_SQ_V_CMP_LE_U64 0xE3 -#define V_008DFC_SQ_V_CMP_GT_U64 0xE4 -#define V_008DFC_SQ_V_CMP_NE_U64 0xE5 -#define V_008DFC_SQ_V_CMP_GE_U64 0xE6 -#define V_008DFC_SQ_V_CMP_T_U64 0xE7 -#define V_008DFC_SQ_V_CMPX_F_U64 0xF0 -#define V_008DFC_SQ_V_CMPX_LT_U64 0xF1 -#define V_008DFC_SQ_V_CMPX_EQ_U64 0xF2 -#define V_008DFC_SQ_V_CMPX_LE_U64 0xF3 -#define V_008DFC_SQ_V_CMPX_GT_U64 0xF4 -#define V_008DFC_SQ_V_CMPX_NE_U64 0xF5 -#define V_008DFC_SQ_V_CMPX_GE_U64 0xF6 -#define V_008DFC_SQ_V_CMPX_T_U64 0xF7 -#define S_008DFC_ENCODING(x) (((x) & 0x7F) << 25) -#define G_008DFC_ENCODING(x) (((x) >> 25) & 0x7F) -#define C_008DFC_ENCODING 0x01FFFFFF -#define V_008DFC_SQ_ENC_VOPC_FIELD 0x3E -#define R_008DFC_SQ_SOP1 0x008DFC -#define S_008DFC_SSRC0(x) (((x) & 0xFF) << 0) -#define G_008DFC_SSRC0(x) (((x) >> 0) & 0xFF) -#define C_008DFC_SSRC0 0xFFFFFF00 -#define V_008DFC_SQ_SGPR 0x00 -/* CIK */ -#define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68 -#define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69 -/* */ -#define V_008DFC_SQ_VCC_LO 0x6A -#define V_008DFC_SQ_VCC_HI 0x6B -#define V_008DFC_SQ_TBA_LO 0x6C -#define V_008DFC_SQ_TBA_HI 0x6D -#define V_008DFC_SQ_TMA_LO 0x6E -#define V_008DFC_SQ_TMA_HI 0x6F -#define V_008DFC_SQ_TTMP0 0x70 -#define V_008DFC_SQ_TTMP1 0x71 -#define V_008DFC_SQ_TTMP2 0x72 -#define V_008DFC_SQ_TTMP3 0x73 -#define V_008DFC_SQ_TTMP4 0x74 -#define V_008DFC_SQ_TTMP5 0x75 -#define V_008DFC_SQ_TTMP6 0x76 -#define V_008DFC_SQ_TTMP7 0x77 -#define V_008DFC_SQ_TTMP8 0x78 -#define V_008DFC_SQ_TTMP9 0x79 -#define V_008DFC_SQ_TTMP10 0x7A -#define V_008DFC_SQ_TTMP11 0x7B -#define V_008DFC_SQ_M0 0x7C -#define V_008DFC_SQ_EXEC_LO 0x7E -#define V_008DFC_SQ_EXEC_HI 0x7F -#define V_008DFC_SQ_SRC_0 0x80 -#define V_008DFC_SQ_SRC_1_INT 0x81 -#define V_008DFC_SQ_SRC_2_INT 0x82 -#define V_008DFC_SQ_SRC_3_INT 0x83 -#define V_008DFC_SQ_SRC_4_INT 0x84 -#define V_008DFC_SQ_SRC_5_INT 0x85 -#define V_008DFC_SQ_SRC_6_INT 0x86 -#define V_008DFC_SQ_SRC_7_INT 0x87 -#define V_008DFC_SQ_SRC_8_INT 0x88 -#define V_008DFC_SQ_SRC_9_INT 0x89 -#define V_008DFC_SQ_SRC_10_INT 0x8A -#define V_008DFC_SQ_SRC_11_INT 0x8B -#define V_008DFC_SQ_SRC_12_INT 0x8C -#define V_008DFC_SQ_SRC_13_INT 0x8D -#define V_008DFC_SQ_SRC_14_INT 0x8E -#define V_008DFC_SQ_SRC_15_INT 0x8F -#define V_008DFC_SQ_SRC_16_INT 0x90 -#define V_008DFC_SQ_SRC_17_INT 0x91 -#define V_008DFC_SQ_SRC_18_INT 0x92 -#define V_008DFC_SQ_SRC_19_INT 0x93 -#define V_008DFC_SQ_SRC_20_INT 0x94 -#define V_008DFC_SQ_SRC_21_INT 0x95 -#define V_008DFC_SQ_SRC_22_INT 0x96 -#define V_008DFC_SQ_SRC_23_INT 0x97 -#define V_008DFC_SQ_SRC_24_INT 0x98 -#define V_008DFC_SQ_SRC_25_INT 0x99 -#define V_008DFC_SQ_SRC_26_INT 0x9A -#define V_008DFC_SQ_SRC_27_INT 0x9B -#define V_008DFC_SQ_SRC_28_INT 0x9C -#define V_008DFC_SQ_SRC_29_INT 0x9D -#define V_008DFC_SQ_SRC_30_INT 0x9E -#define V_008DFC_SQ_SRC_31_INT 0x9F -#define V_008DFC_SQ_SRC_32_INT 0xA0 -#define V_008DFC_SQ_SRC_33_INT 0xA1 -#define V_008DFC_SQ_SRC_34_INT 0xA2 -#define V_008DFC_SQ_SRC_35_INT 0xA3 -#define V_008DFC_SQ_SRC_36_INT 0xA4 -#define V_008DFC_SQ_SRC_37_INT 0xA5 -#define V_008DFC_SQ_SRC_38_INT 0xA6 -#define V_008DFC_SQ_SRC_39_INT 0xA7 -#define V_008DFC_SQ_SRC_40_INT 0xA8 -#define V_008DFC_SQ_SRC_41_INT 0xA9 -#define V_008DFC_SQ_SRC_42_INT 0xAA -#define V_008DFC_SQ_SRC_43_INT 0xAB -#define V_008DFC_SQ_SRC_44_INT 0xAC -#define V_008DFC_SQ_SRC_45_INT 0xAD -#define V_008DFC_SQ_SRC_46_INT 0xAE -#define V_008DFC_SQ_SRC_47_INT 0xAF -#define V_008DFC_SQ_SRC_48_INT 0xB0 -#define V_008DFC_SQ_SRC_49_INT 0xB1 -#define V_008DFC_SQ_SRC_50_INT 0xB2 -#define V_008DFC_SQ_SRC_51_INT 0xB3 -#define V_008DFC_SQ_SRC_52_INT 0xB4 -#define V_008DFC_SQ_SRC_53_INT 0xB5 -#define V_008DFC_SQ_SRC_54_INT 0xB6 -#define V_008DFC_SQ_SRC_55_INT 0xB7 -#define V_008DFC_SQ_SRC_56_INT 0xB8 -#define V_008DFC_SQ_SRC_57_INT 0xB9 -#define V_008DFC_SQ_SRC_58_INT 0xBA -#define V_008DFC_SQ_SRC_59_INT 0xBB -#define V_008DFC_SQ_SRC_60_INT 0xBC -#define V_008DFC_SQ_SRC_61_INT 0xBD -#define V_008DFC_SQ_SRC_62_INT 0xBE -#define V_008DFC_SQ_SRC_63_INT 0xBF -#define V_008DFC_SQ_SRC_64_INT 0xC0 -#define V_008DFC_SQ_SRC_M_1_INT 0xC1 -#define V_008DFC_SQ_SRC_M_2_INT 0xC2 -#define V_008DFC_SQ_SRC_M_3_INT 0xC3 -#define V_008DFC_SQ_SRC_M_4_INT 0xC4 -#define V_008DFC_SQ_SRC_M_5_INT 0xC5 -#define V_008DFC_SQ_SRC_M_6_INT 0xC6 -#define V_008DFC_SQ_SRC_M_7_INT 0xC7 -#define V_008DFC_SQ_SRC_M_8_INT 0xC8 -#define V_008DFC_SQ_SRC_M_9_INT 0xC9 -#define V_008DFC_SQ_SRC_M_10_INT 0xCA -#define V_008DFC_SQ_SRC_M_11_INT 0xCB -#define V_008DFC_SQ_SRC_M_12_INT 0xCC -#define V_008DFC_SQ_SRC_M_13_INT 0xCD -#define V_008DFC_SQ_SRC_M_14_INT 0xCE -#define V_008DFC_SQ_SRC_M_15_INT 0xCF -#define V_008DFC_SQ_SRC_M_16_INT 0xD0 -#define V_008DFC_SQ_SRC_0_5 0xF0 -#define V_008DFC_SQ_SRC_M_0_5 0xF1 -#define V_008DFC_SQ_SRC_1 0xF2 -#define V_008DFC_SQ_SRC_M_1 0xF3 -#define V_008DFC_SQ_SRC_2 0xF4 -#define V_008DFC_SQ_SRC_M_2 0xF5 -#define V_008DFC_SQ_SRC_4 0xF6 -#define V_008DFC_SQ_SRC_M_4 0xF7 -#define V_008DFC_SQ_SRC_VCCZ 0xFB -#define V_008DFC_SQ_SRC_EXECZ 0xFC -#define V_008DFC_SQ_SRC_SCC 0xFD -#define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE -#define S_008DFC_OP(x) (((x) & 0xFF) << 8) -#define G_008DFC_OP(x) (((x) >> 8) & 0xFF) -#define C_008DFC_OP 0xFFFF00FF -#define V_008DFC_SQ_S_MOV_B32 0x03 -#define V_008DFC_SQ_S_MOV_B64 0x04 -#define V_008DFC_SQ_S_CMOV_B32 0x05 -#define V_008DFC_SQ_S_CMOV_B64 0x06 -#define V_008DFC_SQ_S_NOT_B32 0x07 -#define V_008DFC_SQ_S_NOT_B64 0x08 -#define V_008DFC_SQ_S_WQM_B32 0x09 -#define V_008DFC_SQ_S_WQM_B64 0x0A -#define V_008DFC_SQ_S_BREV_B32 0x0B -#define V_008DFC_SQ_S_BREV_B64 0x0C -#define V_008DFC_SQ_S_BCNT0_I32_B32 0x0D -#define V_008DFC_SQ_S_BCNT0_I32_B64 0x0E -#define V_008DFC_SQ_S_BCNT1_I32_B32 0x0F -#define V_008DFC_SQ_S_BCNT1_I32_B64 0x10 -#define V_008DFC_SQ_S_FF0_I32_B32 0x11 -#define V_008DFC_SQ_S_FF0_I32_B64 0x12 -#define V_008DFC_SQ_S_FF1_I32_B32 0x13 -#define V_008DFC_SQ_S_FF1_I32_B64 0x14 -#define V_008DFC_SQ_S_FLBIT_I32_B32 0x15 -#define V_008DFC_SQ_S_FLBIT_I32_B64 0x16 -#define V_008DFC_SQ_S_FLBIT_I32 0x17 -#define V_008DFC_SQ_S_FLBIT_I32_I64 0x18 -#define V_008DFC_SQ_S_SEXT_I32_I8 0x19 -#define V_008DFC_SQ_S_SEXT_I32_I16 0x1A -#define V_008DFC_SQ_S_BITSET0_B32 0x1B -#define V_008DFC_SQ_S_BITSET0_B64 0x1C -#define V_008DFC_SQ_S_BITSET1_B32 0x1D -#define V_008DFC_SQ_S_BITSET1_B64 0x1E -#define V_008DFC_SQ_S_GETPC_B64 0x1F -#define V_008DFC_SQ_S_SETPC_B64 0x20 -#define V_008DFC_SQ_S_SWAPPC_B64 0x21 -#define V_008DFC_SQ_S_RFE_B64 0x22 -#define V_008DFC_SQ_S_AND_SAVEEXEC_B64 0x24 -#define V_008DFC_SQ_S_OR_SAVEEXEC_B64 0x25 -#define V_008DFC_SQ_S_XOR_SAVEEXEC_B64 0x26 -#define V_008DFC_SQ_S_ANDN2_SAVEEXEC_B64 0x27 -#define V_008DFC_SQ_S_ORN2_SAVEEXEC_B64 0x28 -#define V_008DFC_SQ_S_NAND_SAVEEXEC_B64 0x29 -#define V_008DFC_SQ_S_NOR_SAVEEXEC_B64 0x2A -#define V_008DFC_SQ_S_XNOR_SAVEEXEC_B64 0x2B -#define V_008DFC_SQ_S_QUADMASK_B32 0x2C -#define V_008DFC_SQ_S_QUADMASK_B64 0x2D -#define V_008DFC_SQ_S_MOVRELS_B32 0x2E -#define V_008DFC_SQ_S_MOVRELS_B64 0x2F -#define V_008DFC_SQ_S_MOVRELD_B32 0x30 -#define V_008DFC_SQ_S_MOVRELD_B64 0x31 -#define V_008DFC_SQ_S_CBRANCH_JOIN 0x32 -#define V_008DFC_SQ_S_MOV_REGRD_B32 0x33 -#define V_008DFC_SQ_S_ABS_I32 0x34 -#define V_008DFC_SQ_S_MOV_FED_B32 0x35 -#define S_008DFC_SDST(x) (((x) & 0x7F) << 16) -#define G_008DFC_SDST(x) (((x) >> 16) & 0x7F) -#define C_008DFC_SDST 0xFF80FFFF -#define V_008DFC_SQ_SGPR 0x00 -/* CIK */ -#define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68 -#define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69 -/* */ -#define V_008DFC_SQ_VCC_LO 0x6A -#define V_008DFC_SQ_VCC_HI 0x6B -#define V_008DFC_SQ_TBA_LO 0x6C -#define V_008DFC_SQ_TBA_HI 0x6D -#define V_008DFC_SQ_TMA_LO 0x6E -#define V_008DFC_SQ_TMA_HI 0x6F -#define V_008DFC_SQ_TTMP0 0x70 -#define V_008DFC_SQ_TTMP1 0x71 -#define V_008DFC_SQ_TTMP2 0x72 -#define V_008DFC_SQ_TTMP3 0x73 -#define V_008DFC_SQ_TTMP4 0x74 -#define V_008DFC_SQ_TTMP5 0x75 -#define V_008DFC_SQ_TTMP6 0x76 -#define V_008DFC_SQ_TTMP7 0x77 -#define V_008DFC_SQ_TTMP8 0x78 -#define V_008DFC_SQ_TTMP9 0x79 -#define V_008DFC_SQ_TTMP10 0x7A -#define V_008DFC_SQ_TTMP11 0x7B -#define V_008DFC_SQ_M0 0x7C -#define V_008DFC_SQ_EXEC_LO 0x7E -#define V_008DFC_SQ_EXEC_HI 0x7F -#define S_008DFC_ENCODING(x) (((x) & 0x1FF) << 23) -#define G_008DFC_ENCODING(x) (((x) >> 23) & 0x1FF) -#define C_008DFC_ENCODING 0x007FFFFF -#define V_008DFC_SQ_ENC_SOP1_FIELD 0x17D -#define R_008DFC_SQ_MTBUF_1 0x008DFC -#define S_008DFC_VADDR(x) (((x) & 0xFF) << 0) -#define G_008DFC_VADDR(x) (((x) >> 0) & 0xFF) -#define C_008DFC_VADDR 0xFFFFFF00 -#define V_008DFC_SQ_VGPR 0x00 -#define S_008DFC_VDATA(x) (((x) & 0xFF) << 8) -#define G_008DFC_VDATA(x) (((x) >> 8) & 0xFF) -#define C_008DFC_VDATA 0xFFFF00FF -#define V_008DFC_SQ_VGPR 0x00 -#define S_008DFC_SRSRC(x) (((x) & 0x1F) << 16) -#define G_008DFC_SRSRC(x) (((x) >> 16) & 0x1F) -#define C_008DFC_SRSRC 0xFFE0FFFF -#define S_008DFC_SLC(x) (((x) & 0x1) << 22) -#define G_008DFC_SLC(x) (((x) >> 22) & 0x1) -#define C_008DFC_SLC 0xFFBFFFFF -#define S_008DFC_TFE(x) (((x) & 0x1) << 23) -#define G_008DFC_TFE(x) (((x) >> 23) & 0x1) -#define C_008DFC_TFE 0xFF7FFFFF -#define S_008DFC_SOFFSET(x) (((x) & 0xFF) << 24) -#define G_008DFC_SOFFSET(x) (((x) >> 24) & 0xFF) -#define C_008DFC_SOFFSET 0x00FFFFFF -#define V_008DFC_SQ_SGPR 0x00 -/* CIK */ -#define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68 -#define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69 -/* */ -#define V_008DFC_SQ_VCC_LO 0x6A -#define V_008DFC_SQ_VCC_HI 0x6B -#define V_008DFC_SQ_TBA_LO 0x6C -#define V_008DFC_SQ_TBA_HI 0x6D -#define V_008DFC_SQ_TMA_LO 0x6E -#define V_008DFC_SQ_TMA_HI 0x6F -#define V_008DFC_SQ_TTMP0 0x70 -#define V_008DFC_SQ_TTMP1 0x71 -#define V_008DFC_SQ_TTMP2 0x72 -#define V_008DFC_SQ_TTMP3 0x73 -#define V_008DFC_SQ_TTMP4 0x74 -#define V_008DFC_SQ_TTMP5 0x75 -#define V_008DFC_SQ_TTMP6 0x76 -#define V_008DFC_SQ_TTMP7 0x77 -#define V_008DFC_SQ_TTMP8 0x78 -#define V_008DFC_SQ_TTMP9 0x79 -#define V_008DFC_SQ_TTMP10 0x7A -#define V_008DFC_SQ_TTMP11 0x7B -#define V_008DFC_SQ_M0 0x7C -#define V_008DFC_SQ_EXEC_LO 0x7E -#define V_008DFC_SQ_EXEC_HI 0x7F -#define V_008DFC_SQ_SRC_0 0x80 -#define V_008DFC_SQ_SRC_1_INT 0x81 -#define V_008DFC_SQ_SRC_2_INT 0x82 -#define V_008DFC_SQ_SRC_3_INT 0x83 -#define V_008DFC_SQ_SRC_4_INT 0x84 -#define V_008DFC_SQ_SRC_5_INT 0x85 -#define V_008DFC_SQ_SRC_6_INT 0x86 -#define V_008DFC_SQ_SRC_7_INT 0x87 -#define V_008DFC_SQ_SRC_8_INT 0x88 -#define V_008DFC_SQ_SRC_9_INT 0x89 -#define V_008DFC_SQ_SRC_10_INT 0x8A -#define V_008DFC_SQ_SRC_11_INT 0x8B -#define V_008DFC_SQ_SRC_12_INT 0x8C -#define V_008DFC_SQ_SRC_13_INT 0x8D -#define V_008DFC_SQ_SRC_14_INT 0x8E -#define V_008DFC_SQ_SRC_15_INT 0x8F -#define V_008DFC_SQ_SRC_16_INT 0x90 -#define V_008DFC_SQ_SRC_17_INT 0x91 -#define V_008DFC_SQ_SRC_18_INT 0x92 -#define V_008DFC_SQ_SRC_19_INT 0x93 -#define V_008DFC_SQ_SRC_20_INT 0x94 -#define V_008DFC_SQ_SRC_21_INT 0x95 -#define V_008DFC_SQ_SRC_22_INT 0x96 -#define V_008DFC_SQ_SRC_23_INT 0x97 -#define V_008DFC_SQ_SRC_24_INT 0x98 -#define V_008DFC_SQ_SRC_25_INT 0x99 -#define V_008DFC_SQ_SRC_26_INT 0x9A -#define V_008DFC_SQ_SRC_27_INT 0x9B -#define V_008DFC_SQ_SRC_28_INT 0x9C -#define V_008DFC_SQ_SRC_29_INT 0x9D -#define V_008DFC_SQ_SRC_30_INT 0x9E -#define V_008DFC_SQ_SRC_31_INT 0x9F -#define V_008DFC_SQ_SRC_32_INT 0xA0 -#define V_008DFC_SQ_SRC_33_INT 0xA1 -#define V_008DFC_SQ_SRC_34_INT 0xA2 -#define V_008DFC_SQ_SRC_35_INT 0xA3 -#define V_008DFC_SQ_SRC_36_INT 0xA4 -#define V_008DFC_SQ_SRC_37_INT 0xA5 -#define V_008DFC_SQ_SRC_38_INT 0xA6 -#define V_008DFC_SQ_SRC_39_INT 0xA7 -#define V_008DFC_SQ_SRC_40_INT 0xA8 -#define V_008DFC_SQ_SRC_41_INT 0xA9 -#define V_008DFC_SQ_SRC_42_INT 0xAA -#define V_008DFC_SQ_SRC_43_INT 0xAB -#define V_008DFC_SQ_SRC_44_INT 0xAC -#define V_008DFC_SQ_SRC_45_INT 0xAD -#define V_008DFC_SQ_SRC_46_INT 0xAE -#define V_008DFC_SQ_SRC_47_INT 0xAF -#define V_008DFC_SQ_SRC_48_INT 0xB0 -#define V_008DFC_SQ_SRC_49_INT 0xB1 -#define V_008DFC_SQ_SRC_50_INT 0xB2 -#define V_008DFC_SQ_SRC_51_INT 0xB3 -#define V_008DFC_SQ_SRC_52_INT 0xB4 -#define V_008DFC_SQ_SRC_53_INT 0xB5 -#define V_008DFC_SQ_SRC_54_INT 0xB6 -#define V_008DFC_SQ_SRC_55_INT 0xB7 -#define V_008DFC_SQ_SRC_56_INT 0xB8 -#define V_008DFC_SQ_SRC_57_INT 0xB9 -#define V_008DFC_SQ_SRC_58_INT 0xBA -#define V_008DFC_SQ_SRC_59_INT 0xBB -#define V_008DFC_SQ_SRC_60_INT 0xBC -#define V_008DFC_SQ_SRC_61_INT 0xBD -#define V_008DFC_SQ_SRC_62_INT 0xBE -#define V_008DFC_SQ_SRC_63_INT 0xBF -#define V_008DFC_SQ_SRC_64_INT 0xC0 -#define V_008DFC_SQ_SRC_M_1_INT 0xC1 -#define V_008DFC_SQ_SRC_M_2_INT 0xC2 -#define V_008DFC_SQ_SRC_M_3_INT 0xC3 -#define V_008DFC_SQ_SRC_M_4_INT 0xC4 -#define V_008DFC_SQ_SRC_M_5_INT 0xC5 -#define V_008DFC_SQ_SRC_M_6_INT 0xC6 -#define V_008DFC_SQ_SRC_M_7_INT 0xC7 -#define V_008DFC_SQ_SRC_M_8_INT 0xC8 -#define V_008DFC_SQ_SRC_M_9_INT 0xC9 -#define V_008DFC_SQ_SRC_M_10_INT 0xCA -#define V_008DFC_SQ_SRC_M_11_INT 0xCB -#define V_008DFC_SQ_SRC_M_12_INT 0xCC -#define V_008DFC_SQ_SRC_M_13_INT 0xCD -#define V_008DFC_SQ_SRC_M_14_INT 0xCE -#define V_008DFC_SQ_SRC_M_15_INT 0xCF -#define V_008DFC_SQ_SRC_M_16_INT 0xD0 -#define V_008DFC_SQ_SRC_0_5 0xF0 -#define V_008DFC_SQ_SRC_M_0_5 0xF1 -#define V_008DFC_SQ_SRC_1 0xF2 -#define V_008DFC_SQ_SRC_M_1 0xF3 -#define V_008DFC_SQ_SRC_2 0xF4 -#define V_008DFC_SQ_SRC_M_2 0xF5 -#define V_008DFC_SQ_SRC_4 0xF6 -#define V_008DFC_SQ_SRC_M_4 0xF7 -#define V_008DFC_SQ_SRC_VCCZ 0xFB -#define V_008DFC_SQ_SRC_EXECZ 0xFC -#define V_008DFC_SQ_SRC_SCC 0xFD -#define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE -#define R_008DFC_SQ_SOP2 0x008DFC -#define S_008DFC_SSRC0(x) (((x) & 0xFF) << 0) -#define G_008DFC_SSRC0(x) (((x) >> 0) & 0xFF) -#define C_008DFC_SSRC0 0xFFFFFF00 -#define V_008DFC_SQ_SGPR 0x00 -/* CIK */ -#define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68 -#define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69 -/* */ -#define V_008DFC_SQ_VCC_LO 0x6A -#define V_008DFC_SQ_VCC_HI 0x6B -#define V_008DFC_SQ_TBA_LO 0x6C -#define V_008DFC_SQ_TBA_HI 0x6D -#define V_008DFC_SQ_TMA_LO 0x6E -#define V_008DFC_SQ_TMA_HI 0x6F -#define V_008DFC_SQ_TTMP0 0x70 -#define V_008DFC_SQ_TTMP1 0x71 -#define V_008DFC_SQ_TTMP2 0x72 -#define V_008DFC_SQ_TTMP3 0x73 -#define V_008DFC_SQ_TTMP4 0x74 -#define V_008DFC_SQ_TTMP5 0x75 -#define V_008DFC_SQ_TTMP6 0x76 -#define V_008DFC_SQ_TTMP7 0x77 -#define V_008DFC_SQ_TTMP8 0x78 -#define V_008DFC_SQ_TTMP9 0x79 -#define V_008DFC_SQ_TTMP10 0x7A -#define V_008DFC_SQ_TTMP11 0x7B -#define V_008DFC_SQ_M0 0x7C -#define V_008DFC_SQ_EXEC_LO 0x7E -#define V_008DFC_SQ_EXEC_HI 0x7F -#define V_008DFC_SQ_SRC_0 0x80 -#define V_008DFC_SQ_SRC_1_INT 0x81 -#define V_008DFC_SQ_SRC_2_INT 0x82 -#define V_008DFC_SQ_SRC_3_INT 0x83 -#define V_008DFC_SQ_SRC_4_INT 0x84 -#define V_008DFC_SQ_SRC_5_INT 0x85 -#define V_008DFC_SQ_SRC_6_INT 0x86 -#define V_008DFC_SQ_SRC_7_INT 0x87 -#define V_008DFC_SQ_SRC_8_INT 0x88 -#define V_008DFC_SQ_SRC_9_INT 0x89 -#define V_008DFC_SQ_SRC_10_INT 0x8A -#define V_008DFC_SQ_SRC_11_INT 0x8B -#define V_008DFC_SQ_SRC_12_INT 0x8C -#define V_008DFC_SQ_SRC_13_INT 0x8D -#define V_008DFC_SQ_SRC_14_INT 0x8E -#define V_008DFC_SQ_SRC_15_INT 0x8F -#define V_008DFC_SQ_SRC_16_INT 0x90 -#define V_008DFC_SQ_SRC_17_INT 0x91 -#define V_008DFC_SQ_SRC_18_INT 0x92 -#define V_008DFC_SQ_SRC_19_INT 0x93 -#define V_008DFC_SQ_SRC_20_INT 0x94 -#define V_008DFC_SQ_SRC_21_INT 0x95 -#define V_008DFC_SQ_SRC_22_INT 0x96 -#define V_008DFC_SQ_SRC_23_INT 0x97 -#define V_008DFC_SQ_SRC_24_INT 0x98 -#define V_008DFC_SQ_SRC_25_INT 0x99 -#define V_008DFC_SQ_SRC_26_INT 0x9A -#define V_008DFC_SQ_SRC_27_INT 0x9B -#define V_008DFC_SQ_SRC_28_INT 0x9C -#define V_008DFC_SQ_SRC_29_INT 0x9D -#define V_008DFC_SQ_SRC_30_INT 0x9E -#define V_008DFC_SQ_SRC_31_INT 0x9F -#define V_008DFC_SQ_SRC_32_INT 0xA0 -#define V_008DFC_SQ_SRC_33_INT 0xA1 -#define V_008DFC_SQ_SRC_34_INT 0xA2 -#define V_008DFC_SQ_SRC_35_INT 0xA3 -#define V_008DFC_SQ_SRC_36_INT 0xA4 -#define V_008DFC_SQ_SRC_37_INT 0xA5 -#define V_008DFC_SQ_SRC_38_INT 0xA6 -#define V_008DFC_SQ_SRC_39_INT 0xA7 -#define V_008DFC_SQ_SRC_40_INT 0xA8 -#define V_008DFC_SQ_SRC_41_INT 0xA9 -#define V_008DFC_SQ_SRC_42_INT 0xAA -#define V_008DFC_SQ_SRC_43_INT 0xAB -#define V_008DFC_SQ_SRC_44_INT 0xAC -#define V_008DFC_SQ_SRC_45_INT 0xAD -#define V_008DFC_SQ_SRC_46_INT 0xAE -#define V_008DFC_SQ_SRC_47_INT 0xAF -#define V_008DFC_SQ_SRC_48_INT 0xB0 -#define V_008DFC_SQ_SRC_49_INT 0xB1 -#define V_008DFC_SQ_SRC_50_INT 0xB2 -#define V_008DFC_SQ_SRC_51_INT 0xB3 -#define V_008DFC_SQ_SRC_52_INT 0xB4 -#define V_008DFC_SQ_SRC_53_INT 0xB5 -#define V_008DFC_SQ_SRC_54_INT 0xB6 -#define V_008DFC_SQ_SRC_55_INT 0xB7 -#define V_008DFC_SQ_SRC_56_INT 0xB8 -#define V_008DFC_SQ_SRC_57_INT 0xB9 -#define V_008DFC_SQ_SRC_58_INT 0xBA -#define V_008DFC_SQ_SRC_59_INT 0xBB -#define V_008DFC_SQ_SRC_60_INT 0xBC -#define V_008DFC_SQ_SRC_61_INT 0xBD -#define V_008DFC_SQ_SRC_62_INT 0xBE -#define V_008DFC_SQ_SRC_63_INT 0xBF -#define V_008DFC_SQ_SRC_64_INT 0xC0 -#define V_008DFC_SQ_SRC_M_1_INT 0xC1 -#define V_008DFC_SQ_SRC_M_2_INT 0xC2 -#define V_008DFC_SQ_SRC_M_3_INT 0xC3 -#define V_008DFC_SQ_SRC_M_4_INT 0xC4 -#define V_008DFC_SQ_SRC_M_5_INT 0xC5 -#define V_008DFC_SQ_SRC_M_6_INT 0xC6 -#define V_008DFC_SQ_SRC_M_7_INT 0xC7 -#define V_008DFC_SQ_SRC_M_8_INT 0xC8 -#define V_008DFC_SQ_SRC_M_9_INT 0xC9 -#define V_008DFC_SQ_SRC_M_10_INT 0xCA -#define V_008DFC_SQ_SRC_M_11_INT 0xCB -#define V_008DFC_SQ_SRC_M_12_INT 0xCC -#define V_008DFC_SQ_SRC_M_13_INT 0xCD -#define V_008DFC_SQ_SRC_M_14_INT 0xCE -#define V_008DFC_SQ_SRC_M_15_INT 0xCF -#define V_008DFC_SQ_SRC_M_16_INT 0xD0 -#define V_008DFC_SQ_SRC_0_5 0xF0 -#define V_008DFC_SQ_SRC_M_0_5 0xF1 -#define V_008DFC_SQ_SRC_1 0xF2 -#define V_008DFC_SQ_SRC_M_1 0xF3 -#define V_008DFC_SQ_SRC_2 0xF4 -#define V_008DFC_SQ_SRC_M_2 0xF5 -#define V_008DFC_SQ_SRC_4 0xF6 -#define V_008DFC_SQ_SRC_M_4 0xF7 -#define V_008DFC_SQ_SRC_VCCZ 0xFB -#define V_008DFC_SQ_SRC_EXECZ 0xFC -#define V_008DFC_SQ_SRC_SCC 0xFD -#define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE -#define S_008DFC_SSRC1(x) (((x) & 0xFF) << 8) -#define G_008DFC_SSRC1(x) (((x) >> 8) & 0xFF) -#define C_008DFC_SSRC1 0xFFFF00FF -#define V_008DFC_SQ_SGPR 0x00 -/* CIK */ -#define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68 -#define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69 -/* */ -#define V_008DFC_SQ_VCC_LO 0x6A -#define V_008DFC_SQ_VCC_HI 0x6B -#define V_008DFC_SQ_TBA_LO 0x6C -#define V_008DFC_SQ_TBA_HI 0x6D -#define V_008DFC_SQ_TMA_LO 0x6E -#define V_008DFC_SQ_TMA_HI 0x6F -#define V_008DFC_SQ_TTMP0 0x70 -#define V_008DFC_SQ_TTMP1 0x71 -#define V_008DFC_SQ_TTMP2 0x72 -#define V_008DFC_SQ_TTMP3 0x73 -#define V_008DFC_SQ_TTMP4 0x74 -#define V_008DFC_SQ_TTMP5 0x75 -#define V_008DFC_SQ_TTMP6 0x76 -#define V_008DFC_SQ_TTMP7 0x77 -#define V_008DFC_SQ_TTMP8 0x78 -#define V_008DFC_SQ_TTMP9 0x79 -#define V_008DFC_SQ_TTMP10 0x7A -#define V_008DFC_SQ_TTMP11 0x7B -#define V_008DFC_SQ_M0 0x7C -#define V_008DFC_SQ_EXEC_LO 0x7E -#define V_008DFC_SQ_EXEC_HI 0x7F -#define V_008DFC_SQ_SRC_0 0x80 -#define V_008DFC_SQ_SRC_1_INT 0x81 -#define V_008DFC_SQ_SRC_2_INT 0x82 -#define V_008DFC_SQ_SRC_3_INT 0x83 -#define V_008DFC_SQ_SRC_4_INT 0x84 -#define V_008DFC_SQ_SRC_5_INT 0x85 -#define V_008DFC_SQ_SRC_6_INT 0x86 -#define V_008DFC_SQ_SRC_7_INT 0x87 -#define V_008DFC_SQ_SRC_8_INT 0x88 -#define V_008DFC_SQ_SRC_9_INT 0x89 -#define V_008DFC_SQ_SRC_10_INT 0x8A -#define V_008DFC_SQ_SRC_11_INT 0x8B -#define V_008DFC_SQ_SRC_12_INT 0x8C -#define V_008DFC_SQ_SRC_13_INT 0x8D -#define V_008DFC_SQ_SRC_14_INT 0x8E -#define V_008DFC_SQ_SRC_15_INT 0x8F -#define V_008DFC_SQ_SRC_16_INT 0x90 -#define V_008DFC_SQ_SRC_17_INT 0x91 -#define V_008DFC_SQ_SRC_18_INT 0x92 -#define V_008DFC_SQ_SRC_19_INT 0x93 -#define V_008DFC_SQ_SRC_20_INT 0x94 -#define V_008DFC_SQ_SRC_21_INT 0x95 -#define V_008DFC_SQ_SRC_22_INT 0x96 -#define V_008DFC_SQ_SRC_23_INT 0x97 -#define V_008DFC_SQ_SRC_24_INT 0x98 -#define V_008DFC_SQ_SRC_25_INT 0x99 -#define V_008DFC_SQ_SRC_26_INT 0x9A -#define V_008DFC_SQ_SRC_27_INT 0x9B -#define V_008DFC_SQ_SRC_28_INT 0x9C -#define V_008DFC_SQ_SRC_29_INT 0x9D -#define V_008DFC_SQ_SRC_30_INT 0x9E -#define V_008DFC_SQ_SRC_31_INT 0x9F -#define V_008DFC_SQ_SRC_32_INT 0xA0 -#define V_008DFC_SQ_SRC_33_INT 0xA1 -#define V_008DFC_SQ_SRC_34_INT 0xA2 -#define V_008DFC_SQ_SRC_35_INT 0xA3 -#define V_008DFC_SQ_SRC_36_INT 0xA4 -#define V_008DFC_SQ_SRC_37_INT 0xA5 -#define V_008DFC_SQ_SRC_38_INT 0xA6 -#define V_008DFC_SQ_SRC_39_INT 0xA7 -#define V_008DFC_SQ_SRC_40_INT 0xA8 -#define V_008DFC_SQ_SRC_41_INT 0xA9 -#define V_008DFC_SQ_SRC_42_INT 0xAA -#define V_008DFC_SQ_SRC_43_INT 0xAB -#define V_008DFC_SQ_SRC_44_INT 0xAC -#define V_008DFC_SQ_SRC_45_INT 0xAD -#define V_008DFC_SQ_SRC_46_INT 0xAE -#define V_008DFC_SQ_SRC_47_INT 0xAF -#define V_008DFC_SQ_SRC_48_INT 0xB0 -#define V_008DFC_SQ_SRC_49_INT 0xB1 -#define V_008DFC_SQ_SRC_50_INT 0xB2 -#define V_008DFC_SQ_SRC_51_INT 0xB3 -#define V_008DFC_SQ_SRC_52_INT 0xB4 -#define V_008DFC_SQ_SRC_53_INT 0xB5 -#define V_008DFC_SQ_SRC_54_INT 0xB6 -#define V_008DFC_SQ_SRC_55_INT 0xB7 -#define V_008DFC_SQ_SRC_56_INT 0xB8 -#define V_008DFC_SQ_SRC_57_INT 0xB9 -#define V_008DFC_SQ_SRC_58_INT 0xBA -#define V_008DFC_SQ_SRC_59_INT 0xBB -#define V_008DFC_SQ_SRC_60_INT 0xBC -#define V_008DFC_SQ_SRC_61_INT 0xBD -#define V_008DFC_SQ_SRC_62_INT 0xBE -#define V_008DFC_SQ_SRC_63_INT 0xBF -#define V_008DFC_SQ_SRC_64_INT 0xC0 -#define V_008DFC_SQ_SRC_M_1_INT 0xC1 -#define V_008DFC_SQ_SRC_M_2_INT 0xC2 -#define V_008DFC_SQ_SRC_M_3_INT 0xC3 -#define V_008DFC_SQ_SRC_M_4_INT 0xC4 -#define V_008DFC_SQ_SRC_M_5_INT 0xC5 -#define V_008DFC_SQ_SRC_M_6_INT 0xC6 -#define V_008DFC_SQ_SRC_M_7_INT 0xC7 -#define V_008DFC_SQ_SRC_M_8_INT 0xC8 -#define V_008DFC_SQ_SRC_M_9_INT 0xC9 -#define V_008DFC_SQ_SRC_M_10_INT 0xCA -#define V_008DFC_SQ_SRC_M_11_INT 0xCB -#define V_008DFC_SQ_SRC_M_12_INT 0xCC -#define V_008DFC_SQ_SRC_M_13_INT 0xCD -#define V_008DFC_SQ_SRC_M_14_INT 0xCE -#define V_008DFC_SQ_SRC_M_15_INT 0xCF -#define V_008DFC_SQ_SRC_M_16_INT 0xD0 -#define V_008DFC_SQ_SRC_0_5 0xF0 -#define V_008DFC_SQ_SRC_M_0_5 0xF1 -#define V_008DFC_SQ_SRC_1 0xF2 -#define V_008DFC_SQ_SRC_M_1 0xF3 -#define V_008DFC_SQ_SRC_2 0xF4 -#define V_008DFC_SQ_SRC_M_2 0xF5 -#define V_008DFC_SQ_SRC_4 0xF6 -#define V_008DFC_SQ_SRC_M_4 0xF7 -#define V_008DFC_SQ_SRC_VCCZ 0xFB -#define V_008DFC_SQ_SRC_EXECZ 0xFC -#define V_008DFC_SQ_SRC_SCC 0xFD -#define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE -#define S_008DFC_SDST(x) (((x) & 0x7F) << 16) -#define G_008DFC_SDST(x) (((x) >> 16) & 0x7F) -#define C_008DFC_SDST 0xFF80FFFF -#define V_008DFC_SQ_SGPR 0x00 -/* CIK */ -#define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68 -#define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69 -/* */ -#define V_008DFC_SQ_VCC_LO 0x6A -#define V_008DFC_SQ_VCC_HI 0x6B -#define V_008DFC_SQ_TBA_LO 0x6C -#define V_008DFC_SQ_TBA_HI 0x6D -#define V_008DFC_SQ_TMA_LO 0x6E -#define V_008DFC_SQ_TMA_HI 0x6F -#define V_008DFC_SQ_TTMP0 0x70 -#define V_008DFC_SQ_TTMP1 0x71 -#define V_008DFC_SQ_TTMP2 0x72 -#define V_008DFC_SQ_TTMP3 0x73 -#define V_008DFC_SQ_TTMP4 0x74 -#define V_008DFC_SQ_TTMP5 0x75 -#define V_008DFC_SQ_TTMP6 0x76 -#define V_008DFC_SQ_TTMP7 0x77 -#define V_008DFC_SQ_TTMP8 0x78 -#define V_008DFC_SQ_TTMP9 0x79 -#define V_008DFC_SQ_TTMP10 0x7A -#define V_008DFC_SQ_TTMP11 0x7B -#define V_008DFC_SQ_M0 0x7C -#define V_008DFC_SQ_EXEC_LO 0x7E -#define V_008DFC_SQ_EXEC_HI 0x7F -#define S_008DFC_OP(x) (((x) & 0x7F) << 23) -#define G_008DFC_OP(x) (((x) >> 23) & 0x7F) -#define C_008DFC_OP 0xC07FFFFF -#define V_008DFC_SQ_S_ADD_U32 0x00 -#define V_008DFC_SQ_S_SUB_U32 0x01 -#define V_008DFC_SQ_S_ADD_I32 0x02 -#define V_008DFC_SQ_S_SUB_I32 0x03 -#define V_008DFC_SQ_S_ADDC_U32 0x04 -#define V_008DFC_SQ_S_SUBB_U32 0x05 -#define V_008DFC_SQ_S_MIN_I32 0x06 -#define V_008DFC_SQ_S_MIN_U32 0x07 -#define V_008DFC_SQ_S_MAX_I32 0x08 -#define V_008DFC_SQ_S_MAX_U32 0x09 -#define V_008DFC_SQ_S_CSELECT_B32 0x0A -#define V_008DFC_SQ_S_CSELECT_B64 0x0B -#define V_008DFC_SQ_S_AND_B32 0x0E -#define V_008DFC_SQ_S_AND_B64 0x0F -#define V_008DFC_SQ_S_OR_B32 0x10 -#define V_008DFC_SQ_S_OR_B64 0x11 -#define V_008DFC_SQ_S_XOR_B32 0x12 -#define V_008DFC_SQ_S_XOR_B64 0x13 -#define V_008DFC_SQ_S_ANDN2_B32 0x14 -#define V_008DFC_SQ_S_ANDN2_B64 0x15 -#define V_008DFC_SQ_S_ORN2_B32 0x16 -#define V_008DFC_SQ_S_ORN2_B64 0x17 -#define V_008DFC_SQ_S_NAND_B32 0x18 -#define V_008DFC_SQ_S_NAND_B64 0x19 -#define V_008DFC_SQ_S_NOR_B32 0x1A -#define V_008DFC_SQ_S_NOR_B64 0x1B -#define V_008DFC_SQ_S_XNOR_B32 0x1C -#define V_008DFC_SQ_S_XNOR_B64 0x1D -#define V_008DFC_SQ_S_LSHL_B32 0x1E -#define V_008DFC_SQ_S_LSHL_B64 0x1F -#define V_008DFC_SQ_S_LSHR_B32 0x20 -#define V_008DFC_SQ_S_LSHR_B64 0x21 -#define V_008DFC_SQ_S_ASHR_I32 0x22 -#define V_008DFC_SQ_S_ASHR_I64 0x23 -#define V_008DFC_SQ_S_BFM_B32 0x24 -#define V_008DFC_SQ_S_BFM_B64 0x25 -#define V_008DFC_SQ_S_MUL_I32 0x26 -#define V_008DFC_SQ_S_BFE_U32 0x27 -#define V_008DFC_SQ_S_BFE_I32 0x28 -#define V_008DFC_SQ_S_BFE_U64 0x29 -#define V_008DFC_SQ_S_BFE_I64 0x2A -#define V_008DFC_SQ_S_CBRANCH_G_FORK 0x2B -#define V_008DFC_SQ_S_ABSDIFF_I32 0x2C -#define S_008DFC_ENCODING(x) (((x) & 0x03) << 30) -#define G_008DFC_ENCODING(x) (((x) >> 30) & 0x03) -#define C_008DFC_ENCODING 0x3FFFFFFF -#define V_008DFC_SQ_ENC_SOP2_FIELD 0x02 -#define R_008DFC_SQ_SOPK 0x008DFC -#define S_008DFC_SIMM16(x) (((x) & 0xFFFF) << 0) -#define G_008DFC_SIMM16(x) (((x) >> 0) & 0xFFFF) -#define C_008DFC_SIMM16 0xFFFF0000 -#define S_008DFC_SDST(x) (((x) & 0x7F) << 16) -#define G_008DFC_SDST(x) (((x) >> 16) & 0x7F) -#define C_008DFC_SDST 0xFF80FFFF -#define V_008DFC_SQ_SGPR 0x00 -/* CIK */ -#define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68 -#define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69 -/* */ -#define V_008DFC_SQ_VCC_LO 0x6A -#define V_008DFC_SQ_VCC_HI 0x6B -#define V_008DFC_SQ_TBA_LO 0x6C -#define V_008DFC_SQ_TBA_HI 0x6D -#define V_008DFC_SQ_TMA_LO 0x6E -#define V_008DFC_SQ_TMA_HI 0x6F -#define V_008DFC_SQ_TTMP0 0x70 -#define V_008DFC_SQ_TTMP1 0x71 -#define V_008DFC_SQ_TTMP2 0x72 -#define V_008DFC_SQ_TTMP3 0x73 -#define V_008DFC_SQ_TTMP4 0x74 -#define V_008DFC_SQ_TTMP5 0x75 -#define V_008DFC_SQ_TTMP6 0x76 -#define V_008DFC_SQ_TTMP7 0x77 -#define V_008DFC_SQ_TTMP8 0x78 -#define V_008DFC_SQ_TTMP9 0x79 -#define V_008DFC_SQ_TTMP10 0x7A -#define V_008DFC_SQ_TTMP11 0x7B -#define V_008DFC_SQ_M0 0x7C -#define V_008DFC_SQ_EXEC_LO 0x7E -#define V_008DFC_SQ_EXEC_HI 0x7F -#define S_008DFC_OP(x) (((x) & 0x1F) << 23) -#define G_008DFC_OP(x) (((x) >> 23) & 0x1F) -#define C_008DFC_OP 0xF07FFFFF -#define V_008DFC_SQ_S_MOVK_I32 0x00 -#define V_008DFC_SQ_S_CMOVK_I32 0x02 -#define V_008DFC_SQ_S_CMPK_EQ_I32 0x03 -#define V_008DFC_SQ_S_CMPK_LG_I32 0x04 -#define V_008DFC_SQ_S_CMPK_GT_I32 0x05 -#define V_008DFC_SQ_S_CMPK_GE_I32 0x06 -#define V_008DFC_SQ_S_CMPK_LT_I32 0x07 -#define V_008DFC_SQ_S_CMPK_LE_I32 0x08 -#define V_008DFC_SQ_S_CMPK_EQ_U32 0x09 -#define V_008DFC_SQ_S_CMPK_LG_U32 0x0A -#define V_008DFC_SQ_S_CMPK_GT_U32 0x0B -#define V_008DFC_SQ_S_CMPK_GE_U32 0x0C -#define V_008DFC_SQ_S_CMPK_LT_U32 0x0D -#define V_008DFC_SQ_S_CMPK_LE_U32 0x0E -#define V_008DFC_SQ_S_ADDK_I32 0x0F -#define V_008DFC_SQ_S_MULK_I32 0x10 -#define V_008DFC_SQ_S_CBRANCH_I_FORK 0x11 -#define V_008DFC_SQ_S_GETREG_B32 0x12 -#define V_008DFC_SQ_S_SETREG_B32 0x13 -#define V_008DFC_SQ_S_GETREG_REGRD_B32 0x14 -#define V_008DFC_SQ_S_SETREG_IMM32_B32 0x15 -#define S_008DFC_ENCODING(x) (((x) & 0x0F) << 28) -#define G_008DFC_ENCODING(x) (((x) >> 28) & 0x0F) -#define C_008DFC_ENCODING 0x0FFFFFFF -#define V_008DFC_SQ_ENC_SOPK_FIELD 0x0B -#define R_008DFC_SQ_VOP3_0 0x008DFC -#define S_008DFC_VDST(x) (((x) & 0xFF) << 0) -#define G_008DFC_VDST(x) (((x) >> 0) & 0xFF) -#define C_008DFC_VDST 0xFFFFFF00 -#define V_008DFC_SQ_VGPR 0x00 -#define S_008DFC_ABS(x) (((x) & 0x07) << 8) -#define G_008DFC_ABS(x) (((x) >> 8) & 0x07) -#define C_008DFC_ABS 0xFFFFF8FF -#define S_008DFC_CLAMP(x) (((x) & 0x1) << 11) -#define G_008DFC_CLAMP(x) (((x) >> 11) & 0x1) -#define C_008DFC_CLAMP 0xFFFFF7FF -#define S_008DFC_OP(x) (((x) & 0x1FF) << 17) -#define G_008DFC_OP(x) (((x) >> 17) & 0x1FF) -#define C_008DFC_OP 0xFC01FFFF -#define V_008DFC_SQ_V_OPC_OFFSET 0x00 -#define V_008DFC_SQ_V_OP2_OFFSET 0x100 -#define V_008DFC_SQ_V_MAD_LEGACY_F32 0x140 -#define V_008DFC_SQ_V_MAD_F32 0x141 -#define V_008DFC_SQ_V_MAD_I32_I24 0x142 -#define V_008DFC_SQ_V_MAD_U32_U24 0x143 -#define V_008DFC_SQ_V_CUBEID_F32 0x144 -#define V_008DFC_SQ_V_CUBESC_F32 0x145 -#define V_008DFC_SQ_V_CUBETC_F32 0x146 -#define V_008DFC_SQ_V_CUBEMA_F32 0x147 -#define V_008DFC_SQ_V_BFE_U32 0x148 -#define V_008DFC_SQ_V_BFE_I32 0x149 -#define V_008DFC_SQ_V_BFI_B32 0x14A -#define V_008DFC_SQ_V_FMA_F32 0x14B -#define V_008DFC_SQ_V_FMA_F64 0x14C -#define V_008DFC_SQ_V_LERP_U8 0x14D -#define V_008DFC_SQ_V_ALIGNBIT_B32 0x14E -#define V_008DFC_SQ_V_ALIGNBYTE_B32 0x14F -#define V_008DFC_SQ_V_MULLIT_F32 0x150 -#define V_008DFC_SQ_V_MIN3_F32 0x151 -#define V_008DFC_SQ_V_MIN3_I32 0x152 -#define V_008DFC_SQ_V_MIN3_U32 0x153 -#define V_008DFC_SQ_V_MAX3_F32 0x154 -#define V_008DFC_SQ_V_MAX3_I32 0x155 -#define V_008DFC_SQ_V_MAX3_U32 0x156 -#define V_008DFC_SQ_V_MED3_F32 0x157 -#define V_008DFC_SQ_V_MED3_I32 0x158 -#define V_008DFC_SQ_V_MED3_U32 0x159 -#define V_008DFC_SQ_V_SAD_U8 0x15A -#define V_008DFC_SQ_V_SAD_HI_U8 0x15B -#define V_008DFC_SQ_V_SAD_U16 0x15C -#define V_008DFC_SQ_V_SAD_U32 0x15D -#define V_008DFC_SQ_V_CVT_PK_U8_F32 0x15E -#define V_008DFC_SQ_V_DIV_FIXUP_F32 0x15F -#define V_008DFC_SQ_V_DIV_FIXUP_F64 0x160 -#define V_008DFC_SQ_V_LSHL_B64 0x161 -#define V_008DFC_SQ_V_LSHR_B64 0x162 -#define V_008DFC_SQ_V_ASHR_I64 0x163 -#define V_008DFC_SQ_V_ADD_F64 0x164 -#define V_008DFC_SQ_V_MUL_F64 0x165 -#define V_008DFC_SQ_V_MIN_F64 0x166 -#define V_008DFC_SQ_V_MAX_F64 0x167 -#define V_008DFC_SQ_V_LDEXP_F64 0x168 -#define V_008DFC_SQ_V_MUL_LO_U32 0x169 -#define V_008DFC_SQ_V_MUL_HI_U32 0x16A -#define V_008DFC_SQ_V_MUL_LO_I32 0x16B -#define V_008DFC_SQ_V_MUL_HI_I32 0x16C -#define V_008DFC_SQ_V_DIV_SCALE_F32 0x16D -#define V_008DFC_SQ_V_DIV_SCALE_F64 0x16E -#define V_008DFC_SQ_V_DIV_FMAS_F32 0x16F -#define V_008DFC_SQ_V_DIV_FMAS_F64 0x170 -#define V_008DFC_SQ_V_MSAD_U8 0x171 -#define V_008DFC_SQ_V_QSAD_U8 0x172 -#define V_008DFC_SQ_V_MQSAD_U8 0x173 -#define V_008DFC_SQ_V_TRIG_PREOP_F64 0x174 -/* CIK */ -#define V_008DFC_SQ_V_MQSAD_U32_U8 0x175 -#define V_008DFC_SQ_V_MAD_U64_U32 0x176 -#define V_008DFC_SQ_V_MAD_I64_I32 0x177 -/* */ -#define V_008DFC_SQ_V_OP1_OFFSET 0x180 -#define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26) -#define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F) -#define C_008DFC_ENCODING 0x03FFFFFF -#define V_008DFC_SQ_ENC_VOP3_FIELD 0x34 -#define R_008DFC_SQ_VOP2 0x008DFC -#define S_008DFC_SRC0(x) (((x) & 0x1FF) << 0) -#define G_008DFC_SRC0(x) (((x) >> 0) & 0x1FF) -#define C_008DFC_SRC0 0xFFFFFE00 -#define V_008DFC_SQ_SGPR 0x00 -/* CIK */ -#define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68 -#define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69 -/* */ -#define V_008DFC_SQ_VCC_LO 0x6A -#define V_008DFC_SQ_VCC_HI 0x6B -#define V_008DFC_SQ_TBA_LO 0x6C -#define V_008DFC_SQ_TBA_HI 0x6D -#define V_008DFC_SQ_TMA_LO 0x6E -#define V_008DFC_SQ_TMA_HI 0x6F -#define V_008DFC_SQ_TTMP0 0x70 -#define V_008DFC_SQ_TTMP1 0x71 -#define V_008DFC_SQ_TTMP2 0x72 -#define V_008DFC_SQ_TTMP3 0x73 -#define V_008DFC_SQ_TTMP4 0x74 -#define V_008DFC_SQ_TTMP5 0x75 -#define V_008DFC_SQ_TTMP6 0x76 -#define V_008DFC_SQ_TTMP7 0x77 -#define V_008DFC_SQ_TTMP8 0x78 -#define V_008DFC_SQ_TTMP9 0x79 -#define V_008DFC_SQ_TTMP10 0x7A -#define V_008DFC_SQ_TTMP11 0x7B -#define V_008DFC_SQ_M0 0x7C -#define V_008DFC_SQ_EXEC_LO 0x7E -#define V_008DFC_SQ_EXEC_HI 0x7F -#define V_008DFC_SQ_SRC_0 0x80 -#define V_008DFC_SQ_SRC_1_INT 0x81 -#define V_008DFC_SQ_SRC_2_INT 0x82 -#define V_008DFC_SQ_SRC_3_INT 0x83 -#define V_008DFC_SQ_SRC_4_INT 0x84 -#define V_008DFC_SQ_SRC_5_INT 0x85 -#define V_008DFC_SQ_SRC_6_INT 0x86 -#define V_008DFC_SQ_SRC_7_INT 0x87 -#define V_008DFC_SQ_SRC_8_INT 0x88 -#define V_008DFC_SQ_SRC_9_INT 0x89 -#define V_008DFC_SQ_SRC_10_INT 0x8A -#define V_008DFC_SQ_SRC_11_INT 0x8B -#define V_008DFC_SQ_SRC_12_INT 0x8C -#define V_008DFC_SQ_SRC_13_INT 0x8D -#define V_008DFC_SQ_SRC_14_INT 0x8E -#define V_008DFC_SQ_SRC_15_INT 0x8F -#define V_008DFC_SQ_SRC_16_INT 0x90 -#define V_008DFC_SQ_SRC_17_INT 0x91 -#define V_008DFC_SQ_SRC_18_INT 0x92 -#define V_008DFC_SQ_SRC_19_INT 0x93 -#define V_008DFC_SQ_SRC_20_INT 0x94 -#define V_008DFC_SQ_SRC_21_INT 0x95 -#define V_008DFC_SQ_SRC_22_INT 0x96 -#define V_008DFC_SQ_SRC_23_INT 0x97 -#define V_008DFC_SQ_SRC_24_INT 0x98 -#define V_008DFC_SQ_SRC_25_INT 0x99 -#define V_008DFC_SQ_SRC_26_INT 0x9A -#define V_008DFC_SQ_SRC_27_INT 0x9B -#define V_008DFC_SQ_SRC_28_INT 0x9C -#define V_008DFC_SQ_SRC_29_INT 0x9D -#define V_008DFC_SQ_SRC_30_INT 0x9E -#define V_008DFC_SQ_SRC_31_INT 0x9F -#define V_008DFC_SQ_SRC_32_INT 0xA0 -#define V_008DFC_SQ_SRC_33_INT 0xA1 -#define V_008DFC_SQ_SRC_34_INT 0xA2 -#define V_008DFC_SQ_SRC_35_INT 0xA3 -#define V_008DFC_SQ_SRC_36_INT 0xA4 -#define V_008DFC_SQ_SRC_37_INT 0xA5 -#define V_008DFC_SQ_SRC_38_INT 0xA6 -#define V_008DFC_SQ_SRC_39_INT 0xA7 -#define V_008DFC_SQ_SRC_40_INT 0xA8 -#define V_008DFC_SQ_SRC_41_INT 0xA9 -#define V_008DFC_SQ_SRC_42_INT 0xAA -#define V_008DFC_SQ_SRC_43_INT 0xAB -#define V_008DFC_SQ_SRC_44_INT 0xAC -#define V_008DFC_SQ_SRC_45_INT 0xAD -#define V_008DFC_SQ_SRC_46_INT 0xAE -#define V_008DFC_SQ_SRC_47_INT 0xAF -#define V_008DFC_SQ_SRC_48_INT 0xB0 -#define V_008DFC_SQ_SRC_49_INT 0xB1 -#define V_008DFC_SQ_SRC_50_INT 0xB2 -#define V_008DFC_SQ_SRC_51_INT 0xB3 -#define V_008DFC_SQ_SRC_52_INT 0xB4 -#define V_008DFC_SQ_SRC_53_INT 0xB5 -#define V_008DFC_SQ_SRC_54_INT 0xB6 -#define V_008DFC_SQ_SRC_55_INT 0xB7 -#define V_008DFC_SQ_SRC_56_INT 0xB8 -#define V_008DFC_SQ_SRC_57_INT 0xB9 -#define V_008DFC_SQ_SRC_58_INT 0xBA -#define V_008DFC_SQ_SRC_59_INT 0xBB -#define V_008DFC_SQ_SRC_60_INT 0xBC -#define V_008DFC_SQ_SRC_61_INT 0xBD -#define V_008DFC_SQ_SRC_62_INT 0xBE -#define V_008DFC_SQ_SRC_63_INT 0xBF -#define V_008DFC_SQ_SRC_64_INT 0xC0 -#define V_008DFC_SQ_SRC_M_1_INT 0xC1 -#define V_008DFC_SQ_SRC_M_2_INT 0xC2 -#define V_008DFC_SQ_SRC_M_3_INT 0xC3 -#define V_008DFC_SQ_SRC_M_4_INT 0xC4 -#define V_008DFC_SQ_SRC_M_5_INT 0xC5 -#define V_008DFC_SQ_SRC_M_6_INT 0xC6 -#define V_008DFC_SQ_SRC_M_7_INT 0xC7 -#define V_008DFC_SQ_SRC_M_8_INT 0xC8 -#define V_008DFC_SQ_SRC_M_9_INT 0xC9 -#define V_008DFC_SQ_SRC_M_10_INT 0xCA -#define V_008DFC_SQ_SRC_M_11_INT 0xCB -#define V_008DFC_SQ_SRC_M_12_INT 0xCC -#define V_008DFC_SQ_SRC_M_13_INT 0xCD -#define V_008DFC_SQ_SRC_M_14_INT 0xCE -#define V_008DFC_SQ_SRC_M_15_INT 0xCF -#define V_008DFC_SQ_SRC_M_16_INT 0xD0 -#define V_008DFC_SQ_SRC_0_5 0xF0 -#define V_008DFC_SQ_SRC_M_0_5 0xF1 -#define V_008DFC_SQ_SRC_1 0xF2 -#define V_008DFC_SQ_SRC_M_1 0xF3 -#define V_008DFC_SQ_SRC_2 0xF4 -#define V_008DFC_SQ_SRC_M_2 0xF5 -#define V_008DFC_SQ_SRC_4 0xF6 -#define V_008DFC_SQ_SRC_M_4 0xF7 -#define V_008DFC_SQ_SRC_VCCZ 0xFB -#define V_008DFC_SQ_SRC_EXECZ 0xFC -#define V_008DFC_SQ_SRC_SCC 0xFD -#define V_008DFC_SQ_SRC_LDS_DIRECT 0xFE -#define V_008DFC_SQ_SRC_VGPR 0x100 -#define S_008DFC_VSRC1(x) (((x) & 0xFF) << 9) -#define G_008DFC_VSRC1(x) (((x) >> 9) & 0xFF) -#define C_008DFC_VSRC1 0xFFFE01FF -#define V_008DFC_SQ_VGPR 0x00 -#define S_008DFC_VDST(x) (((x) & 0xFF) << 17) -#define G_008DFC_VDST(x) (((x) >> 17) & 0xFF) -#define C_008DFC_VDST 0xFE01FFFF -#define V_008DFC_SQ_VGPR 0x00 -#define S_008DFC_OP(x) (((x) & 0x3F) << 25) -#define G_008DFC_OP(x) (((x) >> 25) & 0x3F) -#define C_008DFC_OP 0x81FFFFFF -#define V_008DFC_SQ_V_CNDMASK_B32 0x00 -#define V_008DFC_SQ_V_READLANE_B32 0x01 -#define V_008DFC_SQ_V_WRITELANE_B32 0x02 -#define V_008DFC_SQ_V_ADD_F32 0x03 -#define V_008DFC_SQ_V_SUB_F32 0x04 -#define V_008DFC_SQ_V_SUBREV_F32 0x05 -#define V_008DFC_SQ_V_MAC_LEGACY_F32 0x06 -#define V_008DFC_SQ_V_MUL_LEGACY_F32 0x07 -#define V_008DFC_SQ_V_MUL_F32 0x08 -#define V_008DFC_SQ_V_MUL_I32_I24 0x09 -#define V_008DFC_SQ_V_MUL_HI_I32_I24 0x0A -#define V_008DFC_SQ_V_MUL_U32_U24 0x0B -#define V_008DFC_SQ_V_MUL_HI_U32_U24 0x0C -#define V_008DFC_SQ_V_MIN_LEGACY_F32 0x0D -#define V_008DFC_SQ_V_MAX_LEGACY_F32 0x0E -#define V_008DFC_SQ_V_MIN_F32 0x0F -#define V_008DFC_SQ_V_MAX_F32 0x10 -#define V_008DFC_SQ_V_MIN_I32 0x11 -#define V_008DFC_SQ_V_MAX_I32 0x12 -#define V_008DFC_SQ_V_MIN_U32 0x13 -#define V_008DFC_SQ_V_MAX_U32 0x14 -#define V_008DFC_SQ_V_LSHR_B32 0x15 -#define V_008DFC_SQ_V_LSHRREV_B32 0x16 -#define V_008DFC_SQ_V_ASHR_I32 0x17 -#define V_008DFC_SQ_V_ASHRREV_I32 0x18 -#define V_008DFC_SQ_V_LSHL_B32 0x19 -#define V_008DFC_SQ_V_LSHLREV_B32 0x1A -#define V_008DFC_SQ_V_AND_B32 0x1B -#define V_008DFC_SQ_V_OR_B32 0x1C -#define V_008DFC_SQ_V_XOR_B32 0x1D -#define V_008DFC_SQ_V_BFM_B32 0x1E -#define V_008DFC_SQ_V_MAC_F32 0x1F -#define V_008DFC_SQ_V_MADMK_F32 0x20 -#define V_008DFC_SQ_V_MADAK_F32 0x21 -#define V_008DFC_SQ_V_BCNT_U32_B32 0x22 -#define V_008DFC_SQ_V_MBCNT_LO_U32_B32 0x23 -#define V_008DFC_SQ_V_MBCNT_HI_U32_B32 0x24 -#define V_008DFC_SQ_V_ADD_I32 0x25 -#define V_008DFC_SQ_V_SUB_I32 0x26 -#define V_008DFC_SQ_V_SUBREV_I32 0x27 -#define V_008DFC_SQ_V_ADDC_U32 0x28 -#define V_008DFC_SQ_V_SUBB_U32 0x29 -#define V_008DFC_SQ_V_SUBBREV_U32 0x2A -#define V_008DFC_SQ_V_LDEXP_F32 0x2B -#define V_008DFC_SQ_V_CVT_PKACCUM_U8_F32 0x2C -#define V_008DFC_SQ_V_CVT_PKNORM_I16_F32 0x2D -#define V_008DFC_SQ_V_CVT_PKNORM_U16_F32 0x2E -#define V_008DFC_SQ_V_CVT_PKRTZ_F16_F32 0x2F -#define V_008DFC_SQ_V_CVT_PK_U16_U32 0x30 -#define V_008DFC_SQ_V_CVT_PK_I16_I32 0x31 -#define S_008DFC_ENCODING(x) (((x) & 0x1) << 31) -#define G_008DFC_ENCODING(x) (((x) >> 31) & 0x1) -#define C_008DFC_ENCODING 0x7FFFFFFF -#define R_008DFC_SQ_VOP3_0_SDST_ENC 0x008DFC -#define S_008DFC_VDST(x) (((x) & 0xFF) << 0) -#define G_008DFC_VDST(x) (((x) >> 0) & 0xFF) -#define C_008DFC_VDST 0xFFFFFF00 -#define V_008DFC_SQ_VGPR 0x00 -#define S_008DFC_SDST(x) (((x) & 0x7F) << 8) -#define G_008DFC_SDST(x) (((x) >> 8) & 0x7F) -#define C_008DFC_SDST 0xFFFF80FF -#define V_008DFC_SQ_SGPR 0x00 -/* CIK */ -#define V_008DFC_SQ_FLAT_SCRATCH_LO 0x68 -#define V_008DFC_SQ_FLAT_SCRATCH_HI 0x69 -/* */ -#define V_008DFC_SQ_VCC_LO 0x6A -#define V_008DFC_SQ_VCC_HI 0x6B -#define V_008DFC_SQ_TBA_LO 0x6C -#define V_008DFC_SQ_TBA_HI 0x6D -#define V_008DFC_SQ_TMA_LO 0x6E -#define V_008DFC_SQ_TMA_HI 0x6F -#define V_008DFC_SQ_TTMP0 0x70 -#define V_008DFC_SQ_TTMP1 0x71 -#define V_008DFC_SQ_TTMP2 0x72 -#define V_008DFC_SQ_TTMP3 0x73 -#define V_008DFC_SQ_TTMP4 0x74 -#define V_008DFC_SQ_TTMP5 0x75 -#define V_008DFC_SQ_TTMP6 0x76 -#define V_008DFC_SQ_TTMP7 0x77 -#define V_008DFC_SQ_TTMP8 0x78 -#define V_008DFC_SQ_TTMP9 0x79 -#define V_008DFC_SQ_TTMP10 0x7A -#define V_008DFC_SQ_TTMP11 0x7B -#define S_008DFC_OP(x) (((x) & 0x1FF) << 17) -#define G_008DFC_OP(x) (((x) >> 17) & 0x1FF) -#define C_008DFC_OP 0xFC01FFFF -#define V_008DFC_SQ_V_OPC_OFFSET 0x00 -#define V_008DFC_SQ_V_OP2_OFFSET 0x100 -#define V_008DFC_SQ_V_MAD_LEGACY_F32 0x140 -#define V_008DFC_SQ_V_MAD_F32 0x141 -#define V_008DFC_SQ_V_MAD_I32_I24 0x142 -#define V_008DFC_SQ_V_MAD_U32_U24 0x143 -#define V_008DFC_SQ_V_CUBEID_F32 0x144 -#define V_008DFC_SQ_V_CUBESC_F32 0x145 -#define V_008DFC_SQ_V_CUBETC_F32 0x146 -#define V_008DFC_SQ_V_CUBEMA_F32 0x147 -#define V_008DFC_SQ_V_BFE_U32 0x148 -#define V_008DFC_SQ_V_BFE_I32 0x149 -#define V_008DFC_SQ_V_BFI_B32 0x14A -#define V_008DFC_SQ_V_FMA_F32 0x14B -#define V_008DFC_SQ_V_FMA_F64 0x14C -#define V_008DFC_SQ_V_LERP_U8 0x14D -#define V_008DFC_SQ_V_ALIGNBIT_B32 0x14E -#define V_008DFC_SQ_V_ALIGNBYTE_B32 0x14F -#define V_008DFC_SQ_V_MULLIT_F32 0x150 -#define V_008DFC_SQ_V_MIN3_F32 0x151 -#define V_008DFC_SQ_V_MIN3_I32 0x152 -#define V_008DFC_SQ_V_MIN3_U32 0x153 -#define V_008DFC_SQ_V_MAX3_F32 0x154 -#define V_008DFC_SQ_V_MAX3_I32 0x155 -#define V_008DFC_SQ_V_MAX3_U32 0x156 -#define V_008DFC_SQ_V_MED3_F32 0x157 -#define V_008DFC_SQ_V_MED3_I32 0x158 -#define V_008DFC_SQ_V_MED3_U32 0x159 -#define V_008DFC_SQ_V_SAD_U8 0x15A -#define V_008DFC_SQ_V_SAD_HI_U8 0x15B -#define V_008DFC_SQ_V_SAD_U16 0x15C -#define V_008DFC_SQ_V_SAD_U32 0x15D -#define V_008DFC_SQ_V_CVT_PK_U8_F32 0x15E -#define V_008DFC_SQ_V_DIV_FIXUP_F32 0x15F -#define V_008DFC_SQ_V_DIV_FIXUP_F64 0x160 -#define V_008DFC_SQ_V_LSHL_B64 0x161 -#define V_008DFC_SQ_V_LSHR_B64 0x162 -#define V_008DFC_SQ_V_ASHR_I64 0x163 -#define V_008DFC_SQ_V_ADD_F64 0x164 -#define V_008DFC_SQ_V_MUL_F64 0x165 -#define V_008DFC_SQ_V_MIN_F64 0x166 -#define V_008DFC_SQ_V_MAX_F64 0x167 -#define V_008DFC_SQ_V_LDEXP_F64 0x168 -#define V_008DFC_SQ_V_MUL_LO_U32 0x169 -#define V_008DFC_SQ_V_MUL_HI_U32 0x16A -#define V_008DFC_SQ_V_MUL_LO_I32 0x16B -#define V_008DFC_SQ_V_MUL_HI_I32 0x16C -#define V_008DFC_SQ_V_DIV_SCALE_F32 0x16D -#define V_008DFC_SQ_V_DIV_SCALE_F64 0x16E -#define V_008DFC_SQ_V_DIV_FMAS_F32 0x16F -#define V_008DFC_SQ_V_DIV_FMAS_F64 0x170 -#define V_008DFC_SQ_V_MSAD_U8 0x171 -#define V_008DFC_SQ_V_QSAD_U8 0x172 -#define V_008DFC_SQ_V_MQSAD_U8 0x173 -#define V_008DFC_SQ_V_TRIG_PREOP_F64 0x174 -/* CIK */ -#define V_008DFC_SQ_V_MQSAD_U32_U8 0x175 -#define V_008DFC_SQ_V_MAD_U64_U32 0x176 -#define V_008DFC_SQ_V_MAD_I64_I32 0x177 -/* */ -#define V_008DFC_SQ_V_OP1_OFFSET 0x180 -#define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26) -#define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F) -#define C_008DFC_ENCODING 0x03FFFFFF -#define V_008DFC_SQ_ENC_VOP3_FIELD 0x34 -#define R_008DFC_SQ_MUBUF_0 0x008DFC -#define S_008DFC_OFFSET(x) (((x) & 0xFFF) << 0) -#define G_008DFC_OFFSET(x) (((x) >> 0) & 0xFFF) -#define C_008DFC_OFFSET 0xFFFFF000 -#define S_008DFC_OFFEN(x) (((x) & 0x1) << 12) -#define G_008DFC_OFFEN(x) (((x) >> 12) & 0x1) -#define C_008DFC_OFFEN 0xFFFFEFFF -#define S_008DFC_IDXEN(x) (((x) & 0x1) << 13) -#define G_008DFC_IDXEN(x) (((x) >> 13) & 0x1) -#define C_008DFC_IDXEN 0xFFFFDFFF -#define S_008DFC_GLC(x) (((x) & 0x1) << 14) -#define G_008DFC_GLC(x) (((x) >> 14) & 0x1) -#define C_008DFC_GLC 0xFFFFBFFF -#define S_008DFC_ADDR64(x) (((x) & 0x1) << 15) -#define G_008DFC_ADDR64(x) (((x) >> 15) & 0x1) -#define C_008DFC_ADDR64 0xFFFF7FFF -#define S_008DFC_LDS(x) (((x) & 0x1) << 16) -#define G_008DFC_LDS(x) (((x) >> 16) & 0x1) -#define C_008DFC_LDS 0xFFFEFFFF -#define S_008DFC_OP(x) (((x) & 0x7F) << 18) -#define G_008DFC_OP(x) (((x) >> 18) & 0x7F) -#define C_008DFC_OP 0xFE03FFFF -#define V_008DFC_SQ_BUFFER_LOAD_FORMAT_X 0x00 -#define V_008DFC_SQ_BUFFER_LOAD_FORMAT_XY 0x01 -#define V_008DFC_SQ_BUFFER_LOAD_FORMAT_XYZ 0x02 -#define V_008DFC_SQ_BUFFER_LOAD_FORMAT_XYZW 0x03 -#define V_008DFC_SQ_BUFFER_STORE_FORMAT_X 0x04 -#define V_008DFC_SQ_BUFFER_STORE_FORMAT_XY 0x05 -#define V_008DFC_SQ_BUFFER_STORE_FORMAT_XYZ 0x06 -#define V_008DFC_SQ_BUFFER_STORE_FORMAT_XYZW 0x07 -#define V_008DFC_SQ_BUFFER_LOAD_UBYTE 0x08 -#define V_008DFC_SQ_BUFFER_LOAD_SBYTE 0x09 -#define V_008DFC_SQ_BUFFER_LOAD_USHORT 0x0A -#define V_008DFC_SQ_BUFFER_LOAD_SSHORT 0x0B -#define V_008DFC_SQ_BUFFER_LOAD_DWORD 0x0C -#define V_008DFC_SQ_BUFFER_LOAD_DWORDX2 0x0D -#define V_008DFC_SQ_BUFFER_LOAD_DWORDX4 0x0E -/* CIK */ -#define V_008DFC_SQ_BUFFER_LOAD_DWORDX3 0x0F -/* */ -#define V_008DFC_SQ_BUFFER_STORE_BYTE 0x18 -#define V_008DFC_SQ_BUFFER_STORE_SHORT 0x1A -#define V_008DFC_SQ_BUFFER_STORE_DWORD 0x1C -#define V_008DFC_SQ_BUFFER_STORE_DWORDX2 0x1D -#define V_008DFC_SQ_BUFFER_STORE_DWORDX4 0x1E -/* CIK */ -#define V_008DFC_SQ_BUFFER_STORE_DWORDX3 0x1F -/* */ -#define V_008DFC_SQ_BUFFER_ATOMIC_SWAP 0x30 -#define V_008DFC_SQ_BUFFER_ATOMIC_CMPSWAP 0x31 -#define V_008DFC_SQ_BUFFER_ATOMIC_ADD 0x32 -#define V_008DFC_SQ_BUFFER_ATOMIC_SUB 0x33 -#define V_008DFC_SQ_BUFFER_ATOMIC_RSUB 0x34 /* not on CIK */ -#define V_008DFC_SQ_BUFFER_ATOMIC_SMIN 0x35 -#define V_008DFC_SQ_BUFFER_ATOMIC_UMIN 0x36 -#define V_008DFC_SQ_BUFFER_ATOMIC_SMAX 0x37 -#define V_008DFC_SQ_BUFFER_ATOMIC_UMAX 0x38 -#define V_008DFC_SQ_BUFFER_ATOMIC_AND 0x39 -#define V_008DFC_SQ_BUFFER_ATOMIC_OR 0x3A -#define V_008DFC_SQ_BUFFER_ATOMIC_XOR 0x3B -#define V_008DFC_SQ_BUFFER_ATOMIC_INC 0x3C -#define V_008DFC_SQ_BUFFER_ATOMIC_DEC 0x3D -#define V_008DFC_SQ_BUFFER_ATOMIC_FCMPSWAP 0x3E -#define V_008DFC_SQ_BUFFER_ATOMIC_FMIN 0x3F -#define V_008DFC_SQ_BUFFER_ATOMIC_FMAX 0x40 -#define V_008DFC_SQ_BUFFER_ATOMIC_SWAP_X2 0x50 -#define V_008DFC_SQ_BUFFER_ATOMIC_CMPSWAP_X2 0x51 -#define V_008DFC_SQ_BUFFER_ATOMIC_ADD_X2 0x52 -#define V_008DFC_SQ_BUFFER_ATOMIC_SUB_X2 0x53 -#define V_008DFC_SQ_BUFFER_ATOMIC_RSUB_X2 0x54 /* not on CIK */ -#define V_008DFC_SQ_BUFFER_ATOMIC_SMIN_X2 0x55 -#define V_008DFC_SQ_BUFFER_ATOMIC_UMIN_X2 0x56 -#define V_008DFC_SQ_BUFFER_ATOMIC_SMAX_X2 0x57 -#define V_008DFC_SQ_BUFFER_ATOMIC_UMAX_X2 0x58 -#define V_008DFC_SQ_BUFFER_ATOMIC_AND_X2 0x59 -#define V_008DFC_SQ_BUFFER_ATOMIC_OR_X2 0x5A -#define V_008DFC_SQ_BUFFER_ATOMIC_XOR_X2 0x5B -#define V_008DFC_SQ_BUFFER_ATOMIC_INC_X2 0x5C -#define V_008DFC_SQ_BUFFER_ATOMIC_DEC_X2 0x5D -#define V_008DFC_SQ_BUFFER_ATOMIC_FCMPSWAP_X2 0x5E -#define V_008DFC_SQ_BUFFER_ATOMIC_FMIN_X2 0x5F -#define V_008DFC_SQ_BUFFER_ATOMIC_FMAX_X2 0x60 -#define V_008DFC_SQ_BUFFER_WBINVL1_SC 0x70 -/* CIK */ -#define V_008DFC_SQ_BUFFER_WBINVL1_VOL 0x70 -/* */ -#define V_008DFC_SQ_BUFFER_WBINVL1 0x71 -#define S_008DFC_ENCODING(x) (((x) & 0x3F) << 26) -#define G_008DFC_ENCODING(x) (((x) >> 26) & 0x3F) -#define C_008DFC_ENCODING 0x03FFFFFF -#define V_008DFC_SQ_ENC_MUBUF_FIELD 0x38 -#endif -#define R_030E00_TA_CS_BC_BASE_ADDR 0x030E00 -#define R_030E04_TA_CS_BC_BASE_ADDR_HI 0x030E04 -#define S_030E04_ADDRESS(x) (((x) & 0xFF) << 0) -#define G_030E04_ADDRESS(x) (((x) >> 0) & 0xFF) -#define C_030E04_ADDRESS 0xFFFFFF00 -#define R_030F00_DB_OCCLUSION_COUNT0_LOW 0x030F00 -#define R_008F00_SQ_BUF_RSRC_WORD0 0x008F00 -#define R_030F04_DB_OCCLUSION_COUNT0_HI 0x030F04 -#define S_030F04_COUNT_HI(x) (((x) & 0x7FFFFFFF) << 0) -#define G_030F04_COUNT_HI(x) (((x) >> 0) & 0x7FFFFFFF) -#define C_030F04_COUNT_HI 0x80000000 -#define R_008F04_SQ_BUF_RSRC_WORD1 0x008F04 -#define S_008F04_BASE_ADDRESS_HI(x) (((x) & 0xFFFF) << 0) -#define G_008F04_BASE_ADDRESS_HI(x) (((x) >> 0) & 0xFFFF) -#define C_008F04_BASE_ADDRESS_HI 0xFFFF0000 -#define S_008F04_STRIDE(x) (((x) & 0x3FFF) << 16) -#define G_008F04_STRIDE(x) (((x) >> 16) & 0x3FFF) -#define C_008F04_STRIDE 0xC000FFFF -#define S_008F04_CACHE_SWIZZLE(x) (((x) & 0x1) << 30) -#define G_008F04_CACHE_SWIZZLE(x) (((x) >> 30) & 0x1) -#define C_008F04_CACHE_SWIZZLE 0xBFFFFFFF -#define S_008F04_SWIZZLE_ENABLE(x) (((x) & 0x1) << 31) -#define G_008F04_SWIZZLE_ENABLE(x) (((x) >> 31) & 0x1) -#define C_008F04_SWIZZLE_ENABLE 0x7FFFFFFF -#define R_030F08_DB_OCCLUSION_COUNT1_LOW 0x030F08 -#define R_008F08_SQ_BUF_RSRC_WORD2 0x008F08 -#define R_030F0C_DB_OCCLUSION_COUNT1_HI 0x030F0C -#define S_030F0C_COUNT_HI(x) (((x) & 0x7FFFFFFF) << 0) -#define G_030F0C_COUNT_HI(x) (((x) >> 0) & 0x7FFFFFFF) -#define C_030F0C_COUNT_HI 0x80000000 -#define R_008F0C_SQ_BUF_RSRC_WORD3 0x008F0C -#define S_008F0C_DST_SEL_X(x) (((x) & 0x07) << 0) -#define G_008F0C_DST_SEL_X(x) (((x) >> 0) & 0x07) -#define C_008F0C_DST_SEL_X 0xFFFFFFF8 -#define V_008F0C_SQ_SEL_0 0x00 -#define V_008F0C_SQ_SEL_1 0x01 -#define V_008F0C_SQ_SEL_RESERVED_0 0x02 -#define V_008F0C_SQ_SEL_RESERVED_1 0x03 -#define V_008F0C_SQ_SEL_X 0x04 -#define V_008F0C_SQ_SEL_Y 0x05 -#define V_008F0C_SQ_SEL_Z 0x06 -#define V_008F0C_SQ_SEL_W 0x07 -#define S_008F0C_DST_SEL_Y(x) (((x) & 0x07) << 3) -#define G_008F0C_DST_SEL_Y(x) (((x) >> 3) & 0x07) -#define C_008F0C_DST_SEL_Y 0xFFFFFFC7 -#define V_008F0C_SQ_SEL_0 0x00 -#define V_008F0C_SQ_SEL_1 0x01 -#define V_008F0C_SQ_SEL_RESERVED_0 0x02 -#define V_008F0C_SQ_SEL_RESERVED_1 0x03 -#define V_008F0C_SQ_SEL_X 0x04 -#define V_008F0C_SQ_SEL_Y 0x05 -#define V_008F0C_SQ_SEL_Z 0x06 -#define V_008F0C_SQ_SEL_W 0x07 -#define S_008F0C_DST_SEL_Z(x) (((x) & 0x07) << 6) -#define G_008F0C_DST_SEL_Z(x) (((x) >> 6) & 0x07) -#define C_008F0C_DST_SEL_Z 0xFFFFFE3F -#define V_008F0C_SQ_SEL_0 0x00 -#define V_008F0C_SQ_SEL_1 0x01 -#define V_008F0C_SQ_SEL_RESERVED_0 0x02 -#define V_008F0C_SQ_SEL_RESERVED_1 0x03 -#define V_008F0C_SQ_SEL_X 0x04 -#define V_008F0C_SQ_SEL_Y 0x05 -#define V_008F0C_SQ_SEL_Z 0x06 -#define V_008F0C_SQ_SEL_W 0x07 -#define S_008F0C_DST_SEL_W(x) (((x) & 0x07) << 9) -#define G_008F0C_DST_SEL_W(x) (((x) >> 9) & 0x07) -#define C_008F0C_DST_SEL_W 0xFFFFF1FF -#define V_008F0C_SQ_SEL_0 0x00 -#define V_008F0C_SQ_SEL_1 0x01 -#define V_008F0C_SQ_SEL_RESERVED_0 0x02 -#define V_008F0C_SQ_SEL_RESERVED_1 0x03 -#define V_008F0C_SQ_SEL_X 0x04 -#define V_008F0C_SQ_SEL_Y 0x05 -#define V_008F0C_SQ_SEL_Z 0x06 -#define V_008F0C_SQ_SEL_W 0x07 -#define S_008F0C_NUM_FORMAT(x) (((x) & 0x07) << 12) -#define G_008F0C_NUM_FORMAT(x) (((x) >> 12) & 0x07) -#define C_008F0C_NUM_FORMAT 0xFFFF8FFF -#define V_008F0C_BUF_NUM_FORMAT_UNORM 0x00 -#define V_008F0C_BUF_NUM_FORMAT_SNORM 0x01 -#define V_008F0C_BUF_NUM_FORMAT_USCALED 0x02 -#define V_008F0C_BUF_NUM_FORMAT_SSCALED 0x03 -#define V_008F0C_BUF_NUM_FORMAT_UINT 0x04 -#define V_008F0C_BUF_NUM_FORMAT_SINT 0x05 -#define V_008F0C_BUF_NUM_FORMAT_SNORM_OGL 0x06 -#define V_008F0C_BUF_NUM_FORMAT_FLOAT 0x07 -#define S_008F0C_DATA_FORMAT(x) (((x) & 0x0F) << 15) -#define G_008F0C_DATA_FORMAT(x) (((x) >> 15) & 0x0F) -#define C_008F0C_DATA_FORMAT 0xFFF87FFF -#define V_008F0C_BUF_DATA_FORMAT_INVALID 0x00 -#define V_008F0C_BUF_DATA_FORMAT_8 0x01 -#define V_008F0C_BUF_DATA_FORMAT_16 0x02 -#define V_008F0C_BUF_DATA_FORMAT_8_8 0x03 -#define V_008F0C_BUF_DATA_FORMAT_32 0x04 -#define V_008F0C_BUF_DATA_FORMAT_16_16 0x05 -#define V_008F0C_BUF_DATA_FORMAT_10_11_11 0x06 -#define V_008F0C_BUF_DATA_FORMAT_11_11_10 0x07 -#define V_008F0C_BUF_DATA_FORMAT_10_10_10_2 0x08 -#define V_008F0C_BUF_DATA_FORMAT_2_10_10_10 0x09 -#define V_008F0C_BUF_DATA_FORMAT_8_8_8_8 0x0A -#define V_008F0C_BUF_DATA_FORMAT_32_32 0x0B -#define V_008F0C_BUF_DATA_FORMAT_16_16_16_16 0x0C -#define V_008F0C_BUF_DATA_FORMAT_32_32_32 0x0D -#define V_008F0C_BUF_DATA_FORMAT_32_32_32_32 0x0E -#define V_008F0C_BUF_DATA_FORMAT_RESERVED_15 0x0F -#define S_008F0C_ELEMENT_SIZE(x) (((x) & 0x03) << 19) -#define G_008F0C_ELEMENT_SIZE(x) (((x) >> 19) & 0x03) -#define C_008F0C_ELEMENT_SIZE 0xFFE7FFFF -#define S_008F0C_INDEX_STRIDE(x) (((x) & 0x03) << 21) -#define G_008F0C_INDEX_STRIDE(x) (((x) >> 21) & 0x03) -#define C_008F0C_INDEX_STRIDE 0xFF9FFFFF -#define S_008F0C_ADD_TID_ENABLE(x) (((x) & 0x1) << 23) -#define G_008F0C_ADD_TID_ENABLE(x) (((x) >> 23) & 0x1) -#define C_008F0C_ADD_TID_ENABLE 0xFF7FFFFF -/* CIK */ -#define S_008F0C_ATC(x) (((x) & 0x1) << 24) -#define G_008F0C_ATC(x) (((x) >> 24) & 0x1) -#define C_008F0C_ATC 0xFEFFFFFF -/* */ -#define S_008F0C_HASH_ENABLE(x) (((x) & 0x1) << 25) -#define G_008F0C_HASH_ENABLE(x) (((x) >> 25) & 0x1) -#define C_008F0C_HASH_ENABLE 0xFDFFFFFF -#define S_008F0C_HEAP(x) (((x) & 0x1) << 26) -#define G_008F0C_HEAP(x) (((x) >> 26) & 0x1) -#define C_008F0C_HEAP 0xFBFFFFFF -/* CIK */ -#define S_008F0C_MTYPE(x) (((x) & 0x07) << 27) -#define G_008F0C_MTYPE(x) (((x) >> 27) & 0x07) -#define C_008F0C_MTYPE 0xC7FFFFFF -/* */ -#define S_008F0C_TYPE(x) (((x) & 0x03) << 30) -#define G_008F0C_TYPE(x) (((x) >> 30) & 0x03) -#define C_008F0C_TYPE 0x3FFFFFFF -#define V_008F0C_SQ_RSRC_BUF 0x00 -#define V_008F0C_SQ_RSRC_BUF_RSVD_1 0x01 -#define V_008F0C_SQ_RSRC_BUF_RSVD_2 0x02 -#define V_008F0C_SQ_RSRC_BUF_RSVD_3 0x03 -#define R_030F10_DB_OCCLUSION_COUNT2_LOW 0x030F10 -#define R_008F10_SQ_IMG_RSRC_WORD0 0x008F10 -#define R_030F14_DB_OCCLUSION_COUNT2_HI 0x030F14 -#define S_030F14_COUNT_HI(x) (((x) & 0x7FFFFFFF) << 0) -#define G_030F14_COUNT_HI(x) (((x) >> 0) & 0x7FFFFFFF) -#define C_030F14_COUNT_HI 0x80000000 -#define R_008F14_SQ_IMG_RSRC_WORD1 0x008F14 -#define S_008F14_BASE_ADDRESS_HI(x) (((x) & 0xFF) << 0) -#define G_008F14_BASE_ADDRESS_HI(x) (((x) >> 0) & 0xFF) -#define C_008F14_BASE_ADDRESS_HI 0xFFFFFF00 -#define S_008F14_MIN_LOD(x) (((x) & 0xFFF) << 8) -#define G_008F14_MIN_LOD(x) (((x) >> 8) & 0xFFF) -#define C_008F14_MIN_LOD 0xFFF000FF -#define S_008F14_DATA_FORMAT(x) (((x) & 0x3F) << 20) -#define G_008F14_DATA_FORMAT(x) (((x) >> 20) & 0x3F) -#define C_008F14_DATA_FORMAT 0xFC0FFFFF -#define V_008F14_IMG_DATA_FORMAT_INVALID 0x00 -#define V_008F14_IMG_DATA_FORMAT_8 0x01 -#define V_008F14_IMG_DATA_FORMAT_16 0x02 -#define V_008F14_IMG_DATA_FORMAT_8_8 0x03 -#define V_008F14_IMG_DATA_FORMAT_32 0x04 -#define V_008F14_IMG_DATA_FORMAT_16_16 0x05 -#define V_008F14_IMG_DATA_FORMAT_10_11_11 0x06 -#define V_008F14_IMG_DATA_FORMAT_11_11_10 0x07 -#define V_008F14_IMG_DATA_FORMAT_10_10_10_2 0x08 -#define V_008F14_IMG_DATA_FORMAT_2_10_10_10 0x09 -#define V_008F14_IMG_DATA_FORMAT_8_8_8_8 0x0A -#define V_008F14_IMG_DATA_FORMAT_32_32 0x0B -#define V_008F14_IMG_DATA_FORMAT_16_16_16_16 0x0C -#define V_008F14_IMG_DATA_FORMAT_32_32_32 0x0D -#define V_008F14_IMG_DATA_FORMAT_32_32_32_32 0x0E -#define V_008F14_IMG_DATA_FORMAT_RESERVED_15 0x0F -#define V_008F14_IMG_DATA_FORMAT_5_6_5 0x10 -#define V_008F14_IMG_DATA_FORMAT_1_5_5_5 0x11 -#define V_008F14_IMG_DATA_FORMAT_5_5_5_1 0x12 -#define V_008F14_IMG_DATA_FORMAT_4_4_4_4 0x13 -#define V_008F14_IMG_DATA_FORMAT_8_24 0x14 -#define V_008F14_IMG_DATA_FORMAT_24_8 0x15 -#define V_008F14_IMG_DATA_FORMAT_X24_8_32 0x16 -#define V_008F14_IMG_DATA_FORMAT_RESERVED_23 0x17 -#define V_008F14_IMG_DATA_FORMAT_RESERVED_24 0x18 -#define V_008F14_IMG_DATA_FORMAT_RESERVED_25 0x19 -#define V_008F14_IMG_DATA_FORMAT_RESERVED_26 0x1A -#define V_008F14_IMG_DATA_FORMAT_RESERVED_27 0x1B -#define V_008F14_IMG_DATA_FORMAT_RESERVED_28 0x1C -#define V_008F14_IMG_DATA_FORMAT_RESERVED_29 0x1D -#define V_008F14_IMG_DATA_FORMAT_RESERVED_30 0x1E -#define V_008F14_IMG_DATA_FORMAT_RESERVED_31 0x1F -#define V_008F14_IMG_DATA_FORMAT_GB_GR 0x20 -#define V_008F14_IMG_DATA_FORMAT_BG_RG 0x21 -#define V_008F14_IMG_DATA_FORMAT_5_9_9_9 0x22 -#define V_008F14_IMG_DATA_FORMAT_BC1 0x23 -#define V_008F14_IMG_DATA_FORMAT_BC2 0x24 -#define V_008F14_IMG_DATA_FORMAT_BC3 0x25 -#define V_008F14_IMG_DATA_FORMAT_BC4 0x26 -#define V_008F14_IMG_DATA_FORMAT_BC5 0x27 -#define V_008F14_IMG_DATA_FORMAT_BC6 0x28 -#define V_008F14_IMG_DATA_FORMAT_BC7 0x29 -#define V_008F14_IMG_DATA_FORMAT_RESERVED_42 0x2A -#define V_008F14_IMG_DATA_FORMAT_RESERVED_43 0x2B -#define V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1 0x2C -#define V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1 0x2D -#define V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1 0x2E -#define V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2 0x2F -#define V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2 0x30 -#define V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4 0x31 -#define V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1 0x32 -#define V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2 0x33 -#define V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2 0x34 -#define V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4 0x35 -#define V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8 0x36 -#define V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4 0x37 -#define V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8 0x38 -#define V_008F14_IMG_DATA_FORMAT_4_4 0x39 -#define V_008F14_IMG_DATA_FORMAT_6_5_5 0x3A -#define V_008F14_IMG_DATA_FORMAT_1 0x3B -#define V_008F14_IMG_DATA_FORMAT_1_REVERSED 0x3C -#define V_008F14_IMG_DATA_FORMAT_32_AS_8 0x3D -#define V_008F14_IMG_DATA_FORMAT_32_AS_8_8 0x3E -#define V_008F14_IMG_DATA_FORMAT_32_AS_32_32_32_32 0x3F -#define S_008F14_NUM_FORMAT(x) (((x) & 0x0F) << 26) -#define G_008F14_NUM_FORMAT(x) (((x) >> 26) & 0x0F) -#define C_008F14_NUM_FORMAT 0xC3FFFFFF -#define V_008F14_IMG_NUM_FORMAT_UNORM 0x00 -#define V_008F14_IMG_NUM_FORMAT_SNORM 0x01 -#define V_008F14_IMG_NUM_FORMAT_USCALED 0x02 -#define V_008F14_IMG_NUM_FORMAT_SSCALED 0x03 -#define V_008F14_IMG_NUM_FORMAT_UINT 0x04 -#define V_008F14_IMG_NUM_FORMAT_SINT 0x05 -#define V_008F14_IMG_NUM_FORMAT_SNORM_OGL 0x06 -#define V_008F14_IMG_NUM_FORMAT_FLOAT 0x07 -#define V_008F14_IMG_NUM_FORMAT_RESERVED_8 0x08 -#define V_008F14_IMG_NUM_FORMAT_SRGB 0x09 -#define V_008F14_IMG_NUM_FORMAT_UBNORM 0x0A -#define V_008F14_IMG_NUM_FORMAT_UBNORM_OGL 0x0B -#define V_008F14_IMG_NUM_FORMAT_UBINT 0x0C -#define V_008F14_IMG_NUM_FORMAT_UBSCALED 0x0D -#define V_008F14_IMG_NUM_FORMAT_RESERVED_14 0x0E -#define V_008F14_IMG_NUM_FORMAT_RESERVED_15 0x0F -/* CIK */ -#define S_008F14_MTYPE(x) (((x) & 0x03) << 30) -#define G_008F14_MTYPE(x) (((x) >> 30) & 0x03) -#define C_008F14_MTYPE 0x3FFFFFFF -/* */ -#define R_030F18_DB_OCCLUSION_COUNT3_LOW 0x030F18 -#define R_008F18_SQ_IMG_RSRC_WORD2 0x008F18 -#define S_008F18_WIDTH(x) (((x) & 0x3FFF) << 0) -#define G_008F18_WIDTH(x) (((x) >> 0) & 0x3FFF) -#define C_008F18_WIDTH 0xFFFFC000 -#define S_008F18_HEIGHT(x) (((x) & 0x3FFF) << 14) -#define G_008F18_HEIGHT(x) (((x) >> 14) & 0x3FFF) -#define C_008F18_HEIGHT 0xF0003FFF -#define S_008F18_PERF_MOD(x) (((x) & 0x07) << 28) -#define G_008F18_PERF_MOD(x) (((x) >> 28) & 0x07) -#define C_008F18_PERF_MOD 0x8FFFFFFF -#define S_008F18_INTERLACED(x) (((x) & 0x1) << 31) -#define G_008F18_INTERLACED(x) (((x) >> 31) & 0x1) -#define C_008F18_INTERLACED 0x7FFFFFFF -#define R_030F1C_DB_OCCLUSION_COUNT3_HI 0x030F1C -#define S_030F1C_COUNT_HI(x) (((x) & 0x7FFFFFFF) << 0) -#define G_030F1C_COUNT_HI(x) (((x) >> 0) & 0x7FFFFFFF) -#define C_030F1C_COUNT_HI 0x80000000 -#define R_008F1C_SQ_IMG_RSRC_WORD3 0x008F1C -#define S_008F1C_DST_SEL_X(x) (((x) & 0x07) << 0) -#define G_008F1C_DST_SEL_X(x) (((x) >> 0) & 0x07) -#define C_008F1C_DST_SEL_X 0xFFFFFFF8 -#define V_008F1C_SQ_SEL_0 0x00 -#define V_008F1C_SQ_SEL_1 0x01 -#define V_008F1C_SQ_SEL_RESERVED_0 0x02 -#define V_008F1C_SQ_SEL_RESERVED_1 0x03 -#define V_008F1C_SQ_SEL_X 0x04 -#define V_008F1C_SQ_SEL_Y 0x05 -#define V_008F1C_SQ_SEL_Z 0x06 -#define V_008F1C_SQ_SEL_W 0x07 -#define S_008F1C_DST_SEL_Y(x) (((x) & 0x07) << 3) -#define G_008F1C_DST_SEL_Y(x) (((x) >> 3) & 0x07) -#define C_008F1C_DST_SEL_Y 0xFFFFFFC7 -#define V_008F1C_SQ_SEL_0 0x00 -#define V_008F1C_SQ_SEL_1 0x01 -#define V_008F1C_SQ_SEL_RESERVED_0 0x02 -#define V_008F1C_SQ_SEL_RESERVED_1 0x03 -#define V_008F1C_SQ_SEL_X 0x04 -#define V_008F1C_SQ_SEL_Y 0x05 -#define V_008F1C_SQ_SEL_Z 0x06 -#define V_008F1C_SQ_SEL_W 0x07 -#define S_008F1C_DST_SEL_Z(x) (((x) & 0x07) << 6) -#define G_008F1C_DST_SEL_Z(x) (((x) >> 6) & 0x07) -#define C_008F1C_DST_SEL_Z 0xFFFFFE3F -#define V_008F1C_SQ_SEL_0 0x00 -#define V_008F1C_SQ_SEL_1 0x01 -#define V_008F1C_SQ_SEL_RESERVED_0 0x02 -#define V_008F1C_SQ_SEL_RESERVED_1 0x03 -#define V_008F1C_SQ_SEL_X 0x04 -#define V_008F1C_SQ_SEL_Y 0x05 -#define V_008F1C_SQ_SEL_Z 0x06 -#define V_008F1C_SQ_SEL_W 0x07 -#define S_008F1C_DST_SEL_W(x) (((x) & 0x07) << 9) -#define G_008F1C_DST_SEL_W(x) (((x) >> 9) & 0x07) -#define C_008F1C_DST_SEL_W 0xFFFFF1FF -#define V_008F1C_SQ_SEL_0 0x00 -#define V_008F1C_SQ_SEL_1 0x01 -#define V_008F1C_SQ_SEL_RESERVED_0 0x02 -#define V_008F1C_SQ_SEL_RESERVED_1 0x03 -#define V_008F1C_SQ_SEL_X 0x04 -#define V_008F1C_SQ_SEL_Y 0x05 -#define V_008F1C_SQ_SEL_Z 0x06 -#define V_008F1C_SQ_SEL_W 0x07 -#define S_008F1C_BASE_LEVEL(x) (((x) & 0x0F) << 12) -#define G_008F1C_BASE_LEVEL(x) (((x) >> 12) & 0x0F) -#define C_008F1C_BASE_LEVEL 0xFFFF0FFF -#define S_008F1C_LAST_LEVEL(x) (((x) & 0x0F) << 16) -#define G_008F1C_LAST_LEVEL(x) (((x) >> 16) & 0x0F) -#define C_008F1C_LAST_LEVEL 0xFFF0FFFF -#define S_008F1C_TILING_INDEX(x) (((x) & 0x1F) << 20) -#define G_008F1C_TILING_INDEX(x) (((x) >> 20) & 0x1F) -#define C_008F1C_TILING_INDEX 0xFE0FFFFF -#define S_008F1C_POW2_PAD(x) (((x) & 0x1) << 25) -#define G_008F1C_POW2_PAD(x) (((x) >> 25) & 0x1) -#define C_008F1C_POW2_PAD 0xFDFFFFFF -/* CIK */ -#define S_008F1C_MTYPE(x) (((x) & 0x1) << 26) -#define G_008F1C_MTYPE(x) (((x) >> 26) & 0x1) -#define C_008F1C_MTYPE 0xFBFFFFFF -#define S_008F1C_ATC(x) (((x) & 0x1) << 27) -#define G_008F1C_ATC(x) (((x) >> 27) & 0x1) -#define C_008F1C_ATC 0xF7FFFFFF -/* */ -#define S_008F1C_TYPE(x) (((x) & 0x0F) << 28) -#define G_008F1C_TYPE(x) (((x) >> 28) & 0x0F) -#define C_008F1C_TYPE 0x0FFFFFFF -#define V_008F1C_SQ_RSRC_IMG_RSVD_0 0x00 -#define V_008F1C_SQ_RSRC_IMG_RSVD_1 0x01 -#define V_008F1C_SQ_RSRC_IMG_RSVD_2 0x02 -#define V_008F1C_SQ_RSRC_IMG_RSVD_3 0x03 -#define V_008F1C_SQ_RSRC_IMG_RSVD_4 0x04 -#define V_008F1C_SQ_RSRC_IMG_RSVD_5 0x05 -#define V_008F1C_SQ_RSRC_IMG_RSVD_6 0x06 -#define V_008F1C_SQ_RSRC_IMG_RSVD_7 0x07 -#define V_008F1C_SQ_RSRC_IMG_1D 0x08 -#define V_008F1C_SQ_RSRC_IMG_2D 0x09 -#define V_008F1C_SQ_RSRC_IMG_3D 0x0A -#define V_008F1C_SQ_RSRC_IMG_CUBE 0x0B -#define V_008F1C_SQ_RSRC_IMG_1D_ARRAY 0x0C -#define V_008F1C_SQ_RSRC_IMG_2D_ARRAY 0x0D -#define V_008F1C_SQ_RSRC_IMG_2D_MSAA 0x0E -#define V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY 0x0F -#define R_008F20_SQ_IMG_RSRC_WORD4 0x008F20 -#define S_008F20_DEPTH(x) (((x) & 0x1FFF) << 0) -#define G_008F20_DEPTH(x) (((x) >> 0) & 0x1FFF) -#define C_008F20_DEPTH 0xFFFFE000 -#define S_008F20_PITCH(x) (((x) & 0x3FFF) << 13) -#define G_008F20_PITCH(x) (((x) >> 13) & 0x3FFF) -#define C_008F20_PITCH 0xF8001FFF -#define R_008F24_SQ_IMG_RSRC_WORD5 0x008F24 -#define S_008F24_BASE_ARRAY(x) (((x) & 0x1FFF) << 0) -#define G_008F24_BASE_ARRAY(x) (((x) >> 0) & 0x1FFF) -#define C_008F24_BASE_ARRAY 0xFFFFE000 -#define S_008F24_LAST_ARRAY(x) (((x) & 0x1FFF) << 13) -#define G_008F24_LAST_ARRAY(x) (((x) >> 13) & 0x1FFF) -#define C_008F24_LAST_ARRAY 0xFC001FFF -#define R_008F28_SQ_IMG_RSRC_WORD6 0x008F28 -#define S_008F28_MIN_LOD_WARN(x) (((x) & 0xFFF) << 0) -#define G_008F28_MIN_LOD_WARN(x) (((x) >> 0) & 0xFFF) -#define C_008F28_MIN_LOD_WARN 0xFFFFF000 -/* CIK */ -#define S_008F28_COUNTER_BANK_ID(x) (((x) & 0xFF) << 12) -#define G_008F28_COUNTER_BANK_ID(x) (((x) >> 12) & 0xFF) -#define C_008F28_COUNTER_BANK_ID 0xFFF00FFF -#define S_008F28_LOD_HDW_CNT_EN(x) (((x) & 0x1) << 20) -#define G_008F28_LOD_HDW_CNT_EN(x) (((x) >> 20) & 0x1) -#define C_008F28_LOD_HDW_CNT_EN 0xFFEFFFFF -/* */ -/* VI */ -#define S_008F28_COMPRESSION_EN(x) (((x) & 0x1) << 21) -#define G_008F28_COMPRESSION_EN(x) (((x) >> 21) & 0x1) -#define C_008F28_COMPRESSION_EN 0xFFDFFFFF -#define S_008F28_ALPHA_IS_ON_MSB(x) (((x) & 0x1) << 22) -#define G_008F28_ALPHA_IS_ON_MSB(x) (((x) >> 22) & 0x1) -#define C_008F28_ALPHA_IS_ON_MSB 0xFFBFFFFF -#define S_008F28_COLOR_TRANSFORM(x) (((x) & 0x1) << 23) -#define G_008F28_COLOR_TRANSFORM(x) (((x) >> 23) & 0x1) -#define C_008F28_COLOR_TRANSFORM 0xFF7FFFFF -#define S_008F28_LOST_ALPHA_BITS(x) (((x) & 0x0F) << 24) -#define G_008F28_LOST_ALPHA_BITS(x) (((x) >> 24) & 0x0F) -#define C_008F28_LOST_ALPHA_BITS 0xF0FFFFFF -#define S_008F28_LOST_COLOR_BITS(x) (((x) & 0x0F) << 28) -#define G_008F28_LOST_COLOR_BITS(x) (((x) >> 28) & 0x0F) -#define C_008F28_LOST_COLOR_BITS 0x0FFFFFFF -/* */ -#define R_008F2C_SQ_IMG_RSRC_WORD7 0x008F2C -#define R_008F30_SQ_IMG_SAMP_WORD0 0x008F30 -#define S_008F30_CLAMP_X(x) (((x) & 0x07) << 0) -#define G_008F30_CLAMP_X(x) (((x) >> 0) & 0x07) -#define C_008F30_CLAMP_X 0xFFFFFFF8 -#define V_008F30_SQ_TEX_WRAP 0x00 -#define V_008F30_SQ_TEX_MIRROR 0x01 -#define V_008F30_SQ_TEX_CLAMP_LAST_TEXEL 0x02 -#define V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL 0x03 -#define V_008F30_SQ_TEX_CLAMP_HALF_BORDER 0x04 -#define V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER 0x05 -#define V_008F30_SQ_TEX_CLAMP_BORDER 0x06 -#define V_008F30_SQ_TEX_MIRROR_ONCE_BORDER 0x07 -#define S_008F30_CLAMP_Y(x) (((x) & 0x07) << 3) -#define G_008F30_CLAMP_Y(x) (((x) >> 3) & 0x07) -#define C_008F30_CLAMP_Y 0xFFFFFFC7 -#define V_008F30_SQ_TEX_WRAP 0x00 -#define V_008F30_SQ_TEX_MIRROR 0x01 -#define V_008F30_SQ_TEX_CLAMP_LAST_TEXEL 0x02 -#define V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL 0x03 -#define V_008F30_SQ_TEX_CLAMP_HALF_BORDER 0x04 -#define V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER 0x05 -#define V_008F30_SQ_TEX_CLAMP_BORDER 0x06 -#define V_008F30_SQ_TEX_MIRROR_ONCE_BORDER 0x07 -#define S_008F30_CLAMP_Z(x) (((x) & 0x07) << 6) -#define G_008F30_CLAMP_Z(x) (((x) >> 6) & 0x07) -#define C_008F30_CLAMP_Z 0xFFFFFE3F -#define V_008F30_SQ_TEX_WRAP 0x00 -#define V_008F30_SQ_TEX_MIRROR 0x01 -#define V_008F30_SQ_TEX_CLAMP_LAST_TEXEL 0x02 -#define V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL 0x03 -#define V_008F30_SQ_TEX_CLAMP_HALF_BORDER 0x04 -#define V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER 0x05 -#define V_008F30_SQ_TEX_CLAMP_BORDER 0x06 -#define V_008F30_SQ_TEX_MIRROR_ONCE_BORDER 0x07 -#define S_008F30_DEPTH_COMPARE_FUNC(x) (((x) & 0x07) << 12) -#define G_008F30_DEPTH_COMPARE_FUNC(x) (((x) >> 12) & 0x07) -#define C_008F30_DEPTH_COMPARE_FUNC 0xFFFF8FFF -#define V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER 0x00 -#define V_008F30_SQ_TEX_DEPTH_COMPARE_LESS 0x01 -#define V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL 0x02 -#define V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL 0x03 -#define V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER 0x04 -#define V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL 0x05 -#define V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL 0x06 -#define V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS 0x07 -#define S_008F30_FORCE_UNNORMALIZED(x) (((x) & 0x1) << 15) -#define G_008F30_FORCE_UNNORMALIZED(x) (((x) >> 15) & 0x1) -#define C_008F30_FORCE_UNNORMALIZED 0xFFFF7FFF -#define S_008F30_MC_COORD_TRUNC(x) (((x) & 0x1) << 19) -#define G_008F30_MC_COORD_TRUNC(x) (((x) >> 19) & 0x1) -#define C_008F30_MC_COORD_TRUNC 0xFFF7FFFF -#define S_008F30_FORCE_DEGAMMA(x) (((x) & 0x1) << 20) -#define G_008F30_FORCE_DEGAMMA(x) (((x) >> 20) & 0x1) -#define C_008F30_FORCE_DEGAMMA 0xFFEFFFFF -#define S_008F30_TRUNC_COORD(x) (((x) & 0x1) << 27) -#define G_008F30_TRUNC_COORD(x) (((x) >> 27) & 0x1) -#define C_008F30_TRUNC_COORD 0xF7FFFFFF -#define S_008F30_DISABLE_CUBE_WRAP(x) (((x) & 0x1) << 28) -#define G_008F30_DISABLE_CUBE_WRAP(x) (((x) >> 28) & 0x1) -#define C_008F30_DISABLE_CUBE_WRAP 0xEFFFFFFF -#define S_008F30_FILTER_MODE(x) (((x) & 0x03) << 29) -#define G_008F30_FILTER_MODE(x) (((x) >> 29) & 0x03) -#define C_008F30_FILTER_MODE 0x9FFFFFFF -/* VI */ -#define S_008F30_COMPAT_MODE(x) (((x) & 0x1) << 31) -#define G_008F30_COMPAT_MODE(x) (((x) >> 31) & 0x1) -#define C_008F30_COMPAT_MODE 0x7FFFFFFF -/* */ -#define R_008F34_SQ_IMG_SAMP_WORD1 0x008F34 -#define S_008F34_MIN_LOD(x) (((x) & 0xFFF) << 0) -#define G_008F34_MIN_LOD(x) (((x) >> 0) & 0xFFF) -#define C_008F34_MIN_LOD 0xFFFFF000 -#define S_008F34_MAX_LOD(x) (((x) & 0xFFF) << 12) -#define G_008F34_MAX_LOD(x) (((x) >> 12) & 0xFFF) -#define C_008F34_MAX_LOD 0xFF000FFF -#define S_008F34_PERF_MIP(x) (((x) & 0x0F) << 24) -#define G_008F34_PERF_MIP(x) (((x) >> 24) & 0x0F) -#define C_008F34_PERF_MIP 0xF0FFFFFF -#define S_008F34_PERF_Z(x) (((x) & 0x0F) << 28) -#define G_008F34_PERF_Z(x) (((x) >> 28) & 0x0F) -#define C_008F34_PERF_Z 0x0FFFFFFF -#define R_008F38_SQ_IMG_SAMP_WORD2 0x008F38 -#define S_008F38_LOD_BIAS(x) (((x) & 0x3FFF) << 0) -#define G_008F38_LOD_BIAS(x) (((x) >> 0) & 0x3FFF) -#define C_008F38_LOD_BIAS 0xFFFFC000 -#define S_008F38_LOD_BIAS_SEC(x) (((x) & 0x3F) << 14) -#define G_008F38_LOD_BIAS_SEC(x) (((x) >> 14) & 0x3F) -#define C_008F38_LOD_BIAS_SEC 0xFFF03FFF -#define S_008F38_XY_MAG_FILTER(x) (((x) & 0x03) << 20) -#define G_008F38_XY_MAG_FILTER(x) (((x) >> 20) & 0x03) -#define C_008F38_XY_MAG_FILTER 0xFFCFFFFF -#define V_008F38_SQ_TEX_XY_FILTER_POINT 0x00 -#define V_008F38_SQ_TEX_XY_FILTER_BILINEAR 0x01 -#define S_008F38_XY_MIN_FILTER(x) (((x) & 0x03) << 22) -#define G_008F38_XY_MIN_FILTER(x) (((x) >> 22) & 0x03) -#define C_008F38_XY_MIN_FILTER 0xFF3FFFFF -#define V_008F38_SQ_TEX_XY_FILTER_POINT 0x00 -#define V_008F38_SQ_TEX_XY_FILTER_BILINEAR 0x01 -#define S_008F38_Z_FILTER(x) (((x) & 0x03) << 24) -#define G_008F38_Z_FILTER(x) (((x) >> 24) & 0x03) -#define C_008F38_Z_FILTER 0xFCFFFFFF -#define V_008F38_SQ_TEX_Z_FILTER_NONE 0x00 -#define V_008F38_SQ_TEX_Z_FILTER_POINT 0x01 -#define V_008F38_SQ_TEX_Z_FILTER_LINEAR 0x02 -#define S_008F38_MIP_FILTER(x) (((x) & 0x03) << 26) -#define G_008F38_MIP_FILTER(x) (((x) >> 26) & 0x03) -#define C_008F38_MIP_FILTER 0xF3FFFFFF -#define V_008F38_SQ_TEX_Z_FILTER_NONE 0x00 -#define V_008F38_SQ_TEX_Z_FILTER_POINT 0x01 -#define V_008F38_SQ_TEX_Z_FILTER_LINEAR 0x02 -#define S_008F38_MIP_POINT_PRECLAMP(x) (((x) & 0x1) << 28) -#define G_008F38_MIP_POINT_PRECLAMP(x) (((x) >> 28) & 0x1) -#define C_008F38_MIP_POINT_PRECLAMP 0xEFFFFFFF -#define S_008F38_DISABLE_LSB_CEIL(x) (((x) & 0x1) << 29) -#define G_008F38_DISABLE_LSB_CEIL(x) (((x) >> 29) & 0x1) -#define C_008F38_DISABLE_LSB_CEIL 0xDFFFFFFF -#define S_008F38_FILTER_PREC_FIX(x) (((x) & 0x1) << 30) -#define G_008F38_FILTER_PREC_FIX(x) (((x) >> 30) & 0x1) -#define C_008F38_FILTER_PREC_FIX 0xBFFFFFFF -#define R_008F3C_SQ_IMG_SAMP_WORD3 0x008F3C -#define S_008F3C_BORDER_COLOR_PTR(x) (((x) & 0xFFF) << 0) -#define G_008F3C_BORDER_COLOR_PTR(x) (((x) >> 0) & 0xFFF) -#define C_008F3C_BORDER_COLOR_PTR 0xFFFFF000 -#define S_008F3C_BORDER_COLOR_TYPE(x) (((x) & 0x03) << 30) -#define G_008F3C_BORDER_COLOR_TYPE(x) (((x) >> 30) & 0x03) -#define C_008F3C_BORDER_COLOR_TYPE 0x3FFFFFFF -#define V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK 0x00 -#define V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK 0x01 -#define V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE 0x02 -#define V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER 0x03 -#define R_0090DC_SPI_DYN_GPR_LOCK_EN 0x0090DC /* not on CIK */ -#define S_0090DC_VS_LOW_THRESHOLD(x) (((x) & 0x0F) << 0) -#define G_0090DC_VS_LOW_THRESHOLD(x) (((x) >> 0) & 0x0F) -#define C_0090DC_VS_LOW_THRESHOLD 0xFFFFFFF0 -#define S_0090DC_GS_LOW_THRESHOLD(x) (((x) & 0x0F) << 4) -#define G_0090DC_GS_LOW_THRESHOLD(x) (((x) >> 4) & 0x0F) -#define C_0090DC_GS_LOW_THRESHOLD 0xFFFFFF0F -#define S_0090DC_ES_LOW_THRESHOLD(x) (((x) & 0x0F) << 8) -#define G_0090DC_ES_LOW_THRESHOLD(x) (((x) >> 8) & 0x0F) -#define C_0090DC_ES_LOW_THRESHOLD 0xFFFFF0FF -#define S_0090DC_HS_LOW_THRESHOLD(x) (((x) & 0x0F) << 12) -#define G_0090DC_HS_LOW_THRESHOLD(x) (((x) >> 12) & 0x0F) -#define C_0090DC_HS_LOW_THRESHOLD 0xFFFF0FFF -#define S_0090DC_LS_LOW_THRESHOLD(x) (((x) & 0x0F) << 16) -#define G_0090DC_LS_LOW_THRESHOLD(x) (((x) >> 16) & 0x0F) -#define C_0090DC_LS_LOW_THRESHOLD 0xFFF0FFFF -#define R_0090E0_SPI_STATIC_THREAD_MGMT_1 0x0090E0 /* not on CIK */ -#define S_0090E0_PS_CU_EN(x) (((x) & 0xFFFF) << 0) -#define G_0090E0_PS_CU_EN(x) (((x) >> 0) & 0xFFFF) -#define C_0090E0_PS_CU_EN 0xFFFF0000 -#define S_0090E0_VS_CU_EN(x) (((x) & 0xFFFF) << 16) -#define G_0090E0_VS_CU_EN(x) (((x) >> 16) & 0xFFFF) -#define C_0090E0_VS_CU_EN 0x0000FFFF -#define R_0090E4_SPI_STATIC_THREAD_MGMT_2 0x0090E4 /* not on CIK */ -#define S_0090E4_GS_CU_EN(x) (((x) & 0xFFFF) << 0) -#define G_0090E4_GS_CU_EN(x) (((x) >> 0) & 0xFFFF) -#define C_0090E4_GS_CU_EN 0xFFFF0000 -#define S_0090E4_ES_CU_EN(x) (((x) & 0xFFFF) << 16) -#define G_0090E4_ES_CU_EN(x) (((x) >> 16) & 0xFFFF) -#define C_0090E4_ES_CU_EN 0x0000FFFF -#define R_0090E8_SPI_STATIC_THREAD_MGMT_3 0x0090E8 /* not on CIK */ -#define S_0090E8_LSHS_CU_EN(x) (((x) & 0xFFFF) << 0) -#define G_0090E8_LSHS_CU_EN(x) (((x) >> 0) & 0xFFFF) -#define C_0090E8_LSHS_CU_EN 0xFFFF0000 -#define R_0090EC_SPI_PS_MAX_WAVE_ID 0x0090EC -#define S_0090EC_MAX_WAVE_ID(x) (((x) & 0xFFF) << 0) -#define G_0090EC_MAX_WAVE_ID(x) (((x) >> 0) & 0xFFF) -#define C_0090EC_MAX_WAVE_ID 0xFFFFF000 -/* CIK */ -#define R_0090E8_SPI_PS_MAX_WAVE_ID 0x0090E8 -#define S_0090E8_MAX_WAVE_ID(x) (((x) & 0xFFF) << 0) -#define G_0090E8_MAX_WAVE_ID(x) (((x) >> 0) & 0xFFF) -#define C_0090E8_MAX_WAVE_ID 0xFFFFF000 -/* */ -#define R_0090F0_SPI_ARB_PRIORITY 0x0090F0 -#define S_0090F0_RING_ORDER_TS0(x) (((x) & 0x07) << 0) -#define G_0090F0_RING_ORDER_TS0(x) (((x) >> 0) & 0x07) -#define C_0090F0_RING_ORDER_TS0 0xFFFFFFF8 -#define V_0090F0_X_R0 0x00 -#define S_0090F0_RING_ORDER_TS1(x) (((x) & 0x07) << 3) -#define G_0090F0_RING_ORDER_TS1(x) (((x) >> 3) & 0x07) -#define C_0090F0_RING_ORDER_TS1 0xFFFFFFC7 -#define S_0090F0_RING_ORDER_TS2(x) (((x) & 0x07) << 6) -#define G_0090F0_RING_ORDER_TS2(x) (((x) >> 6) & 0x07) -#define C_0090F0_RING_ORDER_TS2 0xFFFFFE3F -/* CIK */ -#define R_00C700_SPI_ARB_PRIORITY 0x00C700 -#define S_00C700_PIPE_ORDER_TS0(x) (((x) & 0x07) << 0) -#define G_00C700_PIPE_ORDER_TS0(x) (((x) >> 0) & 0x07) -#define C_00C700_PIPE_ORDER_TS0 0xFFFFFFF8 -#define S_00C700_PIPE_ORDER_TS1(x) (((x) & 0x07) << 3) -#define G_00C700_PIPE_ORDER_TS1(x) (((x) >> 3) & 0x07) -#define C_00C700_PIPE_ORDER_TS1 0xFFFFFFC7 -#define S_00C700_PIPE_ORDER_TS2(x) (((x) & 0x07) << 6) -#define G_00C700_PIPE_ORDER_TS2(x) (((x) >> 6) & 0x07) -#define C_00C700_PIPE_ORDER_TS2 0xFFFFFE3F -#define S_00C700_PIPE_ORDER_TS3(x) (((x) & 0x07) << 9) -#define G_00C700_PIPE_ORDER_TS3(x) (((x) >> 9) & 0x07) -#define C_00C700_PIPE_ORDER_TS3 0xFFFFF1FF -#define S_00C700_TS0_DUR_MULT(x) (((x) & 0x03) << 12) -#define G_00C700_TS0_DUR_MULT(x) (((x) >> 12) & 0x03) -#define C_00C700_TS0_DUR_MULT 0xFFFFCFFF -#define S_00C700_TS1_DUR_MULT(x) (((x) & 0x03) << 14) -#define G_00C700_TS1_DUR_MULT(x) (((x) >> 14) & 0x03) -#define C_00C700_TS1_DUR_MULT 0xFFFF3FFF -#define S_00C700_TS2_DUR_MULT(x) (((x) & 0x03) << 16) -#define G_00C700_TS2_DUR_MULT(x) (((x) >> 16) & 0x03) -#define C_00C700_TS2_DUR_MULT 0xFFFCFFFF -#define S_00C700_TS3_DUR_MULT(x) (((x) & 0x03) << 18) -#define G_00C700_TS3_DUR_MULT(x) (((x) >> 18) & 0x03) -#define C_00C700_TS3_DUR_MULT 0xFFF3FFFF -/* */ -#define R_0090F4_SPI_ARB_CYCLES_0 0x0090F4 /* moved to 0xC704 on CIK */ -#define S_0090F4_TS0_DURATION(x) (((x) & 0xFFFF) << 0) -#define G_0090F4_TS0_DURATION(x) (((x) >> 0) & 0xFFFF) -#define C_0090F4_TS0_DURATION 0xFFFF0000 -#define S_0090F4_TS1_DURATION(x) (((x) & 0xFFFF) << 16) -#define G_0090F4_TS1_DURATION(x) (((x) >> 16) & 0xFFFF) -#define C_0090F4_TS1_DURATION 0x0000FFFF -#define R_0090F8_SPI_ARB_CYCLES_1 0x0090F8 /* moved to 0xC708 on CIK */ -#define S_0090F8_TS2_DURATION(x) (((x) & 0xFFFF) << 0) -#define G_0090F8_TS2_DURATION(x) (((x) >> 0) & 0xFFFF) -#define C_0090F8_TS2_DURATION 0xFFFF0000 -/* CIK */ -#define R_008F40_SQ_FLAT_SCRATCH_WORD0 0x008F40 -#define S_008F40_SIZE(x) (((x) & 0x7FFFF) << 0) -#define G_008F40_SIZE(x) (((x) >> 0) & 0x7FFFF) -#define C_008F40_SIZE 0xFFF80000 -#define R_008F44_SQ_FLAT_SCRATCH_WORD1 0x008F44 -#define S_008F44_OFFSET(x) (((x) & 0xFFFFFF) << 0) -#define G_008F44_OFFSET(x) (((x) >> 0) & 0xFFFFFF) -#define C_008F44_OFFSET 0xFF000000 -/* */ -#define R_030FF8_DB_ZPASS_COUNT_LOW 0x030FF8 -#define R_030FFC_DB_ZPASS_COUNT_HI 0x030FFC -#define S_030FFC_COUNT_HI(x) (((x) & 0x7FFFFFFF) << 0) -#define G_030FFC_COUNT_HI(x) (((x) >> 0) & 0x7FFFFFFF) -#define C_030FFC_COUNT_HI 0x80000000 -#define R_009100_SPI_CONFIG_CNTL 0x009100 -#define S_009100_GPR_WRITE_PRIORITY(x) (((x) & 0x1FFFFF) << 0) -#define G_009100_GPR_WRITE_PRIORITY(x) (((x) >> 0) & 0x1FFFFF) -#define C_009100_GPR_WRITE_PRIORITY 0xFFE00000 -#define S_009100_EXP_PRIORITY_ORDER(x) (((x) & 0x07) << 21) -#define G_009100_EXP_PRIORITY_ORDER(x) (((x) >> 21) & 0x07) -#define C_009100_EXP_PRIORITY_ORDER 0xFF1FFFFF -#define S_009100_ENABLE_SQG_TOP_EVENTS(x) (((x) & 0x1) << 24) -#define G_009100_ENABLE_SQG_TOP_EVENTS(x) (((x) >> 24) & 0x1) -#define C_009100_ENABLE_SQG_TOP_EVENTS 0xFEFFFFFF -#define S_009100_ENABLE_SQG_BOP_EVENTS(x) (((x) & 0x1) << 25) -#define G_009100_ENABLE_SQG_BOP_EVENTS(x) (((x) >> 25) & 0x1) -#define C_009100_ENABLE_SQG_BOP_EVENTS 0xFDFFFFFF -#define S_009100_RSRC_MGMT_RESET(x) (((x) & 0x1) << 26) -#define G_009100_RSRC_MGMT_RESET(x) (((x) >> 26) & 0x1) -#define C_009100_RSRC_MGMT_RESET 0xFBFFFFFF -#define R_00913C_SPI_CONFIG_CNTL_1 0x00913C -#define S_00913C_VTX_DONE_DELAY(x) (((x) & 0x0F) << 0) -#define G_00913C_VTX_DONE_DELAY(x) (((x) >> 0) & 0x0F) -#define C_00913C_VTX_DONE_DELAY 0xFFFFFFF0 -#define V_00913C_X_DELAY_14_CLKS 0x00 -#define V_00913C_X_DELAY_16_CLKS 0x01 -#define V_00913C_X_DELAY_18_CLKS 0x02 -#define V_00913C_X_DELAY_20_CLKS 0x03 -#define V_00913C_X_DELAY_22_CLKS 0x04 -#define V_00913C_X_DELAY_24_CLKS 0x05 -#define V_00913C_X_DELAY_26_CLKS 0x06 -#define V_00913C_X_DELAY_28_CLKS 0x07 -#define V_00913C_X_DELAY_30_CLKS 0x08 -#define V_00913C_X_DELAY_32_CLKS 0x09 -#define V_00913C_X_DELAY_34_CLKS 0x0A -#define V_00913C_X_DELAY_4_CLKS 0x0B -#define V_00913C_X_DELAY_6_CLKS 0x0C -#define V_00913C_X_DELAY_8_CLKS 0x0D -#define V_00913C_X_DELAY_10_CLKS 0x0E -#define V_00913C_X_DELAY_12_CLKS 0x0F -#define S_00913C_INTERP_ONE_PRIM_PER_ROW(x) (((x) & 0x1) << 4) -#define G_00913C_INTERP_ONE_PRIM_PER_ROW(x) (((x) >> 4) & 0x1) -#define C_00913C_INTERP_ONE_PRIM_PER_ROW 0xFFFFFFEF -#define S_00913C_PC_LIMIT_ENABLE(x) (((x) & 0x1) << 6) -#define G_00913C_PC_LIMIT_ENABLE(x) (((x) >> 6) & 0x1) -#define C_00913C_PC_LIMIT_ENABLE 0xFFFFFFBF -#define S_00913C_PC_LIMIT_STRICT(x) (((x) & 0x1) << 7) -#define G_00913C_PC_LIMIT_STRICT(x) (((x) >> 7) & 0x1) -#define C_00913C_PC_LIMIT_STRICT 0xFFFFFF7F -#define S_00913C_PC_LIMIT_SIZE(x) (((x) & 0xFFFF) << 16) -#define G_00913C_PC_LIMIT_SIZE(x) (((x) >> 16) & 0xFFFF) -#define C_00913C_PC_LIMIT_SIZE 0x0000FFFF -#define R_00936C_SPI_RESOURCE_RESERVE_CU_AB_0 0x00936C -#define S_00936C_TYPE_A(x) (((x) & 0x0F) << 0) -#define G_00936C_TYPE_A(x) (((x) >> 0) & 0x0F) -#define C_00936C_TYPE_A 0xFFFFFFF0 -#define S_00936C_VGPR_A(x) (((x) & 0x07) << 4) -#define G_00936C_VGPR_A(x) (((x) >> 4) & 0x07) -#define C_00936C_VGPR_A 0xFFFFFF8F -#define S_00936C_SGPR_A(x) (((x) & 0x07) << 7) -#define G_00936C_SGPR_A(x) (((x) >> 7) & 0x07) -#define C_00936C_SGPR_A 0xFFFFFC7F -#define S_00936C_LDS_A(x) (((x) & 0x07) << 10) -#define G_00936C_LDS_A(x) (((x) >> 10) & 0x07) -#define C_00936C_LDS_A 0xFFFFE3FF -#define S_00936C_WAVES_A(x) (((x) & 0x03) << 13) -#define G_00936C_WAVES_A(x) (((x) >> 13) & 0x03) -#define C_00936C_WAVES_A 0xFFFF9FFF -#define S_00936C_EN_A(x) (((x) & 0x1) << 15) -#define G_00936C_EN_A(x) (((x) >> 15) & 0x1) -#define C_00936C_EN_A 0xFFFF7FFF -#define S_00936C_TYPE_B(x) (((x) & 0x0F) << 16) -#define G_00936C_TYPE_B(x) (((x) >> 16) & 0x0F) -#define C_00936C_TYPE_B 0xFFF0FFFF -#define S_00936C_VGPR_B(x) (((x) & 0x07) << 20) -#define G_00936C_VGPR_B(x) (((x) >> 20) & 0x07) -#define C_00936C_VGPR_B 0xFF8FFFFF -#define S_00936C_SGPR_B(x) (((x) & 0x07) << 23) -#define G_00936C_SGPR_B(x) (((x) >> 23) & 0x07) -#define C_00936C_SGPR_B 0xFC7FFFFF -#define S_00936C_LDS_B(x) (((x) & 0x07) << 26) -#define G_00936C_LDS_B(x) (((x) >> 26) & 0x07) -#define C_00936C_LDS_B 0xE3FFFFFF -#define S_00936C_WAVES_B(x) (((x) & 0x03) << 29) -#define G_00936C_WAVES_B(x) (((x) >> 29) & 0x03) -#define C_00936C_WAVES_B 0x9FFFFFFF -#define S_00936C_EN_B(x) (((x) & 0x1) << 31) -#define G_00936C_EN_B(x) (((x) >> 31) & 0x1) -#define C_00936C_EN_B 0x7FFFFFFF -#define R_00950C_TA_CS_BC_BASE_ADDR 0x00950C -/* CIK */ -#define R_030E00_TA_CS_BC_BASE_ADDR 0x030E00 -#define R_030E04_TA_CS_BC_BASE_ADDR_HI 0x030E04 -#define S_030E04_ADDRESS(x) (((x) & 0xFF) << 0) -#define G_030E04_ADDRESS(x) (((x) >> 0) & 0xFF) -#define C_030E04_ADDRESS 0xFFFFFF00 -/* */ -#define R_009858_DB_SUBTILE_CONTROL 0x009858 -#define S_009858_MSAA1_X(x) (((x) & 0x03) << 0) -#define G_009858_MSAA1_X(x) (((x) >> 0) & 0x03) -#define C_009858_MSAA1_X 0xFFFFFFFC -#define S_009858_MSAA1_Y(x) (((x) & 0x03) << 2) -#define G_009858_MSAA1_Y(x) (((x) >> 2) & 0x03) -#define C_009858_MSAA1_Y 0xFFFFFFF3 -#define S_009858_MSAA2_X(x) (((x) & 0x03) << 4) -#define G_009858_MSAA2_X(x) (((x) >> 4) & 0x03) -#define C_009858_MSAA2_X 0xFFFFFFCF -#define S_009858_MSAA2_Y(x) (((x) & 0x03) << 6) -#define G_009858_MSAA2_Y(x) (((x) >> 6) & 0x03) -#define C_009858_MSAA2_Y 0xFFFFFF3F -#define S_009858_MSAA4_X(x) (((x) & 0x03) << 8) -#define G_009858_MSAA4_X(x) (((x) >> 8) & 0x03) -#define C_009858_MSAA4_X 0xFFFFFCFF -#define S_009858_MSAA4_Y(x) (((x) & 0x03) << 10) -#define G_009858_MSAA4_Y(x) (((x) >> 10) & 0x03) -#define C_009858_MSAA4_Y 0xFFFFF3FF -#define S_009858_MSAA8_X(x) (((x) & 0x03) << 12) -#define G_009858_MSAA8_X(x) (((x) >> 12) & 0x03) -#define C_009858_MSAA8_X 0xFFFFCFFF -#define S_009858_MSAA8_Y(x) (((x) & 0x03) << 14) -#define G_009858_MSAA8_Y(x) (((x) >> 14) & 0x03) -#define C_009858_MSAA8_Y 0xFFFF3FFF -#define S_009858_MSAA16_X(x) (((x) & 0x03) << 16) -#define G_009858_MSAA16_X(x) (((x) >> 16) & 0x03) -#define C_009858_MSAA16_X 0xFFFCFFFF -#define S_009858_MSAA16_Y(x) (((x) & 0x03) << 18) -#define G_009858_MSAA16_Y(x) (((x) >> 18) & 0x03) -#define C_009858_MSAA16_Y 0xFFF3FFFF -#define R_0098F8_GB_ADDR_CONFIG 0x0098F8 -#define S_0098F8_NUM_PIPES(x) (((x) & 0x07) << 0) -#define G_0098F8_NUM_PIPES(x) (((x) >> 0) & 0x07) -#define C_0098F8_NUM_PIPES 0xFFFFFFF8 -#define S_0098F8_PIPE_INTERLEAVE_SIZE(x) (((x) & 0x07) << 4) -#define G_0098F8_PIPE_INTERLEAVE_SIZE(x) (((x) >> 4) & 0x07) -#define C_0098F8_PIPE_INTERLEAVE_SIZE 0xFFFFFF8F -#define S_0098F8_BANK_INTERLEAVE_SIZE(x) (((x) & 0x07) << 8) -#define G_0098F8_BANK_INTERLEAVE_SIZE(x) (((x) >> 8) & 0x07) -#define C_0098F8_BANK_INTERLEAVE_SIZE 0xFFFFF8FF -#define S_0098F8_NUM_SHADER_ENGINES(x) (((x) & 0x03) << 12) -#define G_0098F8_NUM_SHADER_ENGINES(x) (((x) >> 12) & 0x03) -#define C_0098F8_NUM_SHADER_ENGINES 0xFFFFCFFF -#define S_0098F8_SHADER_ENGINE_TILE_SIZE(x) (((x) & 0x07) << 16) -#define G_0098F8_SHADER_ENGINE_TILE_SIZE(x) (((x) >> 16) & 0x07) -#define C_0098F8_SHADER_ENGINE_TILE_SIZE 0xFFF8FFFF -#define S_0098F8_NUM_GPUS(x) (((x) & 0x07) << 20) -#define G_0098F8_NUM_GPUS(x) (((x) >> 20) & 0x07) -#define C_0098F8_NUM_GPUS 0xFF8FFFFF -#define S_0098F8_MULTI_GPU_TILE_SIZE(x) (((x) & 0x03) << 24) -#define G_0098F8_MULTI_GPU_TILE_SIZE(x) (((x) >> 24) & 0x03) -#define C_0098F8_MULTI_GPU_TILE_SIZE 0xFCFFFFFF -#define S_0098F8_ROW_SIZE(x) (((x) & 0x03) << 28) -#define G_0098F8_ROW_SIZE(x) (((x) >> 28) & 0x03) -#define C_0098F8_ROW_SIZE 0xCFFFFFFF -#define S_0098F8_NUM_LOWER_PIPES(x) (((x) & 0x1) << 30) -#define G_0098F8_NUM_LOWER_PIPES(x) (((x) >> 30) & 0x1) -#define C_0098F8_NUM_LOWER_PIPES 0xBFFFFFFF -#define R_009910_GB_TILE_MODE0 0x009910 -#define S_009910_MICRO_TILE_MODE(x) (((x) & 0x03) << 0) -#define G_009910_MICRO_TILE_MODE(x) (((x) >> 0) & 0x03) -#define C_009910_MICRO_TILE_MODE 0xFFFFFFFC -#define V_009910_ADDR_SURF_DISPLAY_MICRO_TILING 0x00 -#define V_009910_ADDR_SURF_THIN_MICRO_TILING 0x01 -#define V_009910_ADDR_SURF_DEPTH_MICRO_TILING 0x02 -#define V_009910_ADDR_SURF_THICK_MICRO_TILING 0x03 -#define S_009910_ARRAY_MODE(x) (((x) & 0x0F) << 2) -#define G_009910_ARRAY_MODE(x) (((x) >> 2) & 0x0F) -#define C_009910_ARRAY_MODE 0xFFFFFFC3 -#define V_009910_ARRAY_LINEAR_GENERAL 0x00 -#define V_009910_ARRAY_LINEAR_ALIGNED 0x01 -#define V_009910_ARRAY_1D_TILED_THIN1 0x02 -#define V_009910_ARRAY_1D_TILED_THICK 0x03 -#define V_009910_ARRAY_2D_TILED_THIN1 0x04 -#define V_009910_ARRAY_2D_TILED_THICK 0x07 -#define V_009910_ARRAY_2D_TILED_XTHICK 0x08 -#define V_009910_ARRAY_3D_TILED_THIN1 0x0C -#define V_009910_ARRAY_3D_TILED_THICK 0x0D -#define V_009910_ARRAY_3D_TILED_XTHICK 0x0E -#define V_009910_ARRAY_POWER_SAVE 0x0F -#define S_009910_PIPE_CONFIG(x) (((x) & 0x1F) << 6) -#define G_009910_PIPE_CONFIG(x) (((x) >> 6) & 0x1F) -#define C_009910_PIPE_CONFIG 0xFFFFF83F -#define V_009910_ADDR_SURF_P2 0x00 -#define V_009910_ADDR_SURF_P2_RESERVED0 0x01 -#define V_009910_ADDR_SURF_P2_RESERVED1 0x02 -#define V_009910_ADDR_SURF_P2_RESERVED2 0x03 -#define V_009910_X_ADDR_SURF_P4_8X16 0x04 -#define V_009910_X_ADDR_SURF_P4_16X16 0x05 -#define V_009910_X_ADDR_SURF_P4_16X32 0x06 -#define V_009910_X_ADDR_SURF_P4_32X32 0x07 -#define V_009910_X_ADDR_SURF_P8_16X16_8X16 0x08 -#define V_009910_X_ADDR_SURF_P8_16X32_8X16 0x09 -#define V_009910_X_ADDR_SURF_P8_32X32_8X16 0x0A -#define V_009910_X_ADDR_SURF_P8_16X32_16X16 0x0B -#define V_009910_X_ADDR_SURF_P8_32X32_16X16 0x0C -#define V_009910_X_ADDR_SURF_P8_32X32_16X32 0x0D -#define V_009910_X_ADDR_SURF_P8_32X64_32X32 0x0E -#define S_009910_TILE_SPLIT(x) (((x) & 0x07) << 11) -#define G_009910_TILE_SPLIT(x) (((x) >> 11) & 0x07) -#define C_009910_TILE_SPLIT 0xFFFFC7FF -#define V_009910_ADDR_SURF_TILE_SPLIT_64B 0x00 -#define V_009910_ADDR_SURF_TILE_SPLIT_128B 0x01 -#define V_009910_ADDR_SURF_TILE_SPLIT_256B 0x02 -#define V_009910_ADDR_SURF_TILE_SPLIT_512B 0x03 -#define V_009910_ADDR_SURF_TILE_SPLIT_1KB 0x04 -#define V_009910_ADDR_SURF_TILE_SPLIT_2KB 0x05 -#define V_009910_ADDR_SURF_TILE_SPLIT_4KB 0x06 -#define S_009910_BANK_WIDTH(x) (((x) & 0x03) << 14) -#define G_009910_BANK_WIDTH(x) (((x) >> 14) & 0x03) -#define C_009910_BANK_WIDTH 0xFFFF3FFF -#define V_009910_ADDR_SURF_BANK_WIDTH_1 0x00 -#define V_009910_ADDR_SURF_BANK_WIDTH_2 0x01 -#define V_009910_ADDR_SURF_BANK_WIDTH_4 0x02 -#define V_009910_ADDR_SURF_BANK_WIDTH_8 0x03 -#define S_009910_BANK_HEIGHT(x) (((x) & 0x03) << 16) -#define G_009910_BANK_HEIGHT(x) (((x) >> 16) & 0x03) -#define C_009910_BANK_HEIGHT 0xFFFCFFFF -#define V_009910_ADDR_SURF_BANK_HEIGHT_1 0x00 -#define V_009910_ADDR_SURF_BANK_HEIGHT_2 0x01 -#define V_009910_ADDR_SURF_BANK_HEIGHT_4 0x02 -#define V_009910_ADDR_SURF_BANK_HEIGHT_8 0x03 -#define S_009910_MACRO_TILE_ASPECT(x) (((x) & 0x03) << 18) -#define G_009910_MACRO_TILE_ASPECT(x) (((x) >> 18) & 0x03) -#define C_009910_MACRO_TILE_ASPECT 0xFFF3FFFF -#define V_009910_ADDR_SURF_MACRO_ASPECT_1 0x00 -#define V_009910_ADDR_SURF_MACRO_ASPECT_2 0x01 -#define V_009910_ADDR_SURF_MACRO_ASPECT_4 0x02 -#define V_009910_ADDR_SURF_MACRO_ASPECT_8 0x03 -#define S_009910_NUM_BANKS(x) (((x) & 0x03) << 20) -#define G_009910_NUM_BANKS(x) (((x) >> 20) & 0x03) -#define C_009910_NUM_BANKS 0xFFCFFFFF -#define V_009910_ADDR_SURF_2_BANK 0x00 -#define V_009910_ADDR_SURF_4_BANK 0x01 -#define V_009910_ADDR_SURF_8_BANK 0x02 -#define V_009910_ADDR_SURF_16_BANK 0x03 -#define S_009910_MICRO_TILE_MODE_NEW(x) (((x) & 0x07) << 22) -#define G_009910_MICRO_TILE_MODE_NEW(x) (((x) >> 22) & 0x07) -#define C_009910_MICRO_TILE_MODE_NEW 0xFE3FFFFF -#define V_009910_ADDR_SURF_DISPLAY_MICRO_TILING 0x00 -#define V_009910_ADDR_SURF_THIN_MICRO_TILING 0x01 -#define V_009910_ADDR_SURF_DEPTH_MICRO_TILING 0x02 -#define V_009910_ADDR_SURF_ROTATED_MICRO_TILING 0x03 -#define S_009910_SAMPLE_SPLIT(x) (((x) & 0x03) << 25) -#define G_009910_SAMPLE_SPLIT(x) (((x) >> 25) & 0x03) -#define C_009910_SAMPLE_SPLIT 0xF9FFFFFF -#define R_009914_GB_TILE_MODE1 0x009914 -#define R_009918_GB_TILE_MODE2 0x009918 -#define R_00991C_GB_TILE_MODE3 0x00991C -#define R_009920_GB_TILE_MODE4 0x009920 -#define R_009924_GB_TILE_MODE5 0x009924 -#define R_009928_GB_TILE_MODE6 0x009928 -#define R_00992C_GB_TILE_MODE7 0x00992C -#define R_009930_GB_TILE_MODE8 0x009930 -#define R_009934_GB_TILE_MODE9 0x009934 -#define R_009938_GB_TILE_MODE10 0x009938 -#define R_00993C_GB_TILE_MODE11 0x00993C -#define R_009940_GB_TILE_MODE12 0x009940 -#define R_009944_GB_TILE_MODE13 0x009944 -#define R_009948_GB_TILE_MODE14 0x009948 -#define R_00994C_GB_TILE_MODE15 0x00994C -#define R_009950_GB_TILE_MODE16 0x009950 -#define R_009954_GB_TILE_MODE17 0x009954 -#define R_009958_GB_TILE_MODE18 0x009958 -#define R_00995C_GB_TILE_MODE19 0x00995C -#define R_009960_GB_TILE_MODE20 0x009960 -#define R_009964_GB_TILE_MODE21 0x009964 -#define R_009968_GB_TILE_MODE22 0x009968 -#define R_00996C_GB_TILE_MODE23 0x00996C -#define R_009970_GB_TILE_MODE24 0x009970 -#define R_009974_GB_TILE_MODE25 0x009974 -#define R_009978_GB_TILE_MODE26 0x009978 -#define R_00997C_GB_TILE_MODE27 0x00997C -#define R_009980_GB_TILE_MODE28 0x009980 -#define R_009984_GB_TILE_MODE29 0x009984 -#define R_009988_GB_TILE_MODE30 0x009988 -#define R_00998C_GB_TILE_MODE31 0x00998C -/* CIK */ -#define R_009990_GB_MACROTILE_MODE0 0x009990 -#define S_009990_BANK_WIDTH(x) (((x) & 0x03) << 0) -#define G_009990_BANK_WIDTH(x) (((x) >> 0) & 0x03) -#define C_009990_BANK_WIDTH 0xFFFFFFFC -#define S_009990_BANK_HEIGHT(x) (((x) & 0x03) << 2) -#define G_009990_BANK_HEIGHT(x) (((x) >> 2) & 0x03) -#define C_009990_BANK_HEIGHT 0xFFFFFFF3 -#define S_009990_MACRO_TILE_ASPECT(x) (((x) & 0x03) << 4) -#define G_009990_MACRO_TILE_ASPECT(x) (((x) >> 4) & 0x03) -#define C_009990_MACRO_TILE_ASPECT 0xFFFFFFCF -#define S_009990_NUM_BANKS(x) (((x) & 0x03) << 6) -#define G_009990_NUM_BANKS(x) (((x) >> 6) & 0x03) -#define C_009990_NUM_BANKS 0xFFFFFF3F -#define R_009994_GB_MACROTILE_MODE1 0x009994 -#define R_009998_GB_MACROTILE_MODE2 0x009998 -#define R_00999C_GB_MACROTILE_MODE3 0x00999C -#define R_0099A0_GB_MACROTILE_MODE4 0x0099A0 -#define R_0099A4_GB_MACROTILE_MODE5 0x0099A4 -#define R_0099A8_GB_MACROTILE_MODE6 0x0099A8 -#define R_0099AC_GB_MACROTILE_MODE7 0x0099AC -#define R_0099B0_GB_MACROTILE_MODE8 0x0099B0 -#define R_0099B4_GB_MACROTILE_MODE9 0x0099B4 -#define R_0099B8_GB_MACROTILE_MODE10 0x0099B8 -#define R_0099BC_GB_MACROTILE_MODE11 0x0099BC -#define R_0099C0_GB_MACROTILE_MODE12 0x0099C0 -#define R_0099C4_GB_MACROTILE_MODE13 0x0099C4 -#define R_0099C8_GB_MACROTILE_MODE14 0x0099C8 -#define R_0099CC_GB_MACROTILE_MODE15 0x0099CC -/* */ -#define R_00B000_SPI_SHADER_TBA_LO_PS 0x00B000 -#define R_00B004_SPI_SHADER_TBA_HI_PS 0x00B004 -#define S_00B004_MEM_BASE(x) (((x) & 0xFF) << 0) -#define G_00B004_MEM_BASE(x) (((x) >> 0) & 0xFF) -#define C_00B004_MEM_BASE 0xFFFFFF00 -#define R_00B008_SPI_SHADER_TMA_LO_PS 0x00B008 -#define R_00B00C_SPI_SHADER_TMA_HI_PS 0x00B00C -#define S_00B00C_MEM_BASE(x) (((x) & 0xFF) << 0) -#define G_00B00C_MEM_BASE(x) (((x) >> 0) & 0xFF) -#define C_00B00C_MEM_BASE 0xFFFFFF00 -/* CIK */ -#define R_00B01C_SPI_SHADER_PGM_RSRC3_PS 0x00B01C -#define S_00B01C_CU_EN(x) (((x) & 0xFFFF) << 0) -#define G_00B01C_CU_EN(x) (((x) >> 0) & 0xFFFF) -#define C_00B01C_CU_EN 0xFFFF0000 -#define S_00B01C_WAVE_LIMIT(x) (((x) & 0x3F) << 16) -#define G_00B01C_WAVE_LIMIT(x) (((x) >> 16) & 0x3F) -#define C_00B01C_WAVE_LIMIT 0xFFC0FFFF -#define S_00B01C_LOCK_LOW_THRESHOLD(x) (((x) & 0x0F) << 22) -#define G_00B01C_LOCK_LOW_THRESHOLD(x) (((x) >> 22) & 0x0F) -#define C_00B01C_LOCK_LOW_THRESHOLD 0xFC3FFFFF -/* */ -#define R_00B020_SPI_SHADER_PGM_LO_PS 0x00B020 -#define R_00B024_SPI_SHADER_PGM_HI_PS 0x00B024 -#define S_00B024_MEM_BASE(x) (((x) & 0xFF) << 0) -#define G_00B024_MEM_BASE(x) (((x) >> 0) & 0xFF) -#define C_00B024_MEM_BASE 0xFFFFFF00 -#define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028 -#define S_00B028_VGPRS(x) (((x) & 0x3F) << 0) -#define G_00B028_VGPRS(x) (((x) >> 0) & 0x3F) -#define C_00B028_VGPRS 0xFFFFFFC0 -#define S_00B028_SGPRS(x) (((x) & 0x0F) << 6) -#define G_00B028_SGPRS(x) (((x) >> 6) & 0x0F) -#define C_00B028_SGPRS 0xFFFFFC3F -#define S_00B028_PRIORITY(x) (((x) & 0x03) << 10) -#define G_00B028_PRIORITY(x) (((x) >> 10) & 0x03) -#define C_00B028_PRIORITY 0xFFFFF3FF -#define S_00B028_FLOAT_MODE(x) (((x) & 0xFF) << 12) -#define G_00B028_FLOAT_MODE(x) (((x) >> 12) & 0xFF) -#define C_00B028_FLOAT_MODE 0xFFF00FFF -#define S_00B028_PRIV(x) (((x) & 0x1) << 20) -#define G_00B028_PRIV(x) (((x) >> 20) & 0x1) -#define C_00B028_PRIV 0xFFEFFFFF -#define S_00B028_DX10_CLAMP(x) (((x) & 0x1) << 21) -#define G_00B028_DX10_CLAMP(x) (((x) >> 21) & 0x1) -#define C_00B028_DX10_CLAMP 0xFFDFFFFF -#define S_00B028_DEBUG_MODE(x) (((x) & 0x1) << 22) -#define G_00B028_DEBUG_MODE(x) (((x) >> 22) & 0x1) -#define C_00B028_DEBUG_MODE 0xFFBFFFFF -#define S_00B028_IEEE_MODE(x) (((x) & 0x1) << 23) -#define G_00B028_IEEE_MODE(x) (((x) >> 23) & 0x1) -#define C_00B028_IEEE_MODE 0xFF7FFFFF -#define S_00B028_CU_GROUP_DISABLE(x) (((x) & 0x1) << 24) -#define G_00B028_CU_GROUP_DISABLE(x) (((x) >> 24) & 0x1) -#define C_00B028_CU_GROUP_DISABLE 0xFEFFFFFF -/* CIK */ -#define S_00B028_CACHE_CTL(x) (((x) & 0x07) << 25) -#define G_00B028_CACHE_CTL(x) (((x) >> 25) & 0x07) -#define C_00B028_CACHE_CTL 0xF1FFFFFF -#define S_00B028_CDBG_USER(x) (((x) & 0x1) << 28) -#define G_00B028_CDBG_USER(x) (((x) >> 28) & 0x1) -#define C_00B028_CDBG_USER 0xEFFFFFFF -/* */ -#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C -#define S_00B02C_SCRATCH_EN(x) (((x) & 0x1) << 0) -#define G_00B02C_SCRATCH_EN(x) (((x) >> 0) & 0x1) -#define C_00B02C_SCRATCH_EN 0xFFFFFFFE -#define S_00B02C_USER_SGPR(x) (((x) & 0x1F) << 1) -#define G_00B02C_USER_SGPR(x) (((x) >> 1) & 0x1F) -#define C_00B02C_USER_SGPR 0xFFFFFFC1 -#define S_00B02C_TRAP_PRESENT(x) (((x) & 0x1) << 6) -#define G_00B02C_TRAP_PRESENT(x) (((x) >> 6) & 0x1) -#define C_00B02C_TRAP_PRESENT 0xFFFFFFBF -#define S_00B02C_WAVE_CNT_EN(x) (((x) & 0x1) << 7) -#define G_00B02C_WAVE_CNT_EN(x) (((x) >> 7) & 0x1) -#define C_00B02C_WAVE_CNT_EN 0xFFFFFF7F -#define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8) -#define G_00B02C_EXTRA_LDS_SIZE(x) (((x) >> 8) & 0xFF) -#define C_00B02C_EXTRA_LDS_SIZE 0xFFFF00FF -#define S_00B02C_EXCP_EN(x) (((x) & 0x7F) << 16) /* mask is 0x1FF on CIK */ -#define G_00B02C_EXCP_EN(x) (((x) >> 16) & 0x7F) /* mask is 0x1FF on CIK */ -#define C_00B02C_EXCP_EN 0xFF80FFFF /* mask is 0x1FF on CIK */ -#define S_00B02C_EXCP_EN_CIK(x) (((x) & 0x1FF) << 16) -#define G_00B02C_EXCP_EN_CIK(x) (((x) >> 16) & 0x1FF) -#define C_00B02C_EXCP_EN_CIK 0xFE00FFFF -#define R_00B030_SPI_SHADER_USER_DATA_PS_0 0x00B030 -#define R_00B034_SPI_SHADER_USER_DATA_PS_1 0x00B034 -#define R_00B038_SPI_SHADER_USER_DATA_PS_2 0x00B038 -#define R_00B03C_SPI_SHADER_USER_DATA_PS_3 0x00B03C -#define R_00B040_SPI_SHADER_USER_DATA_PS_4 0x00B040 -#define R_00B044_SPI_SHADER_USER_DATA_PS_5 0x00B044 -#define R_00B048_SPI_SHADER_USER_DATA_PS_6 0x00B048 -#define R_00B04C_SPI_SHADER_USER_DATA_PS_7 0x00B04C -#define R_00B050_SPI_SHADER_USER_DATA_PS_8 0x00B050 -#define R_00B054_SPI_SHADER_USER_DATA_PS_9 0x00B054 -#define R_00B058_SPI_SHADER_USER_DATA_PS_10 0x00B058 -#define R_00B05C_SPI_SHADER_USER_DATA_PS_11 0x00B05C -#define R_00B060_SPI_SHADER_USER_DATA_PS_12 0x00B060 -#define R_00B064_SPI_SHADER_USER_DATA_PS_13 0x00B064 -#define R_00B068_SPI_SHADER_USER_DATA_PS_14 0x00B068 -#define R_00B06C_SPI_SHADER_USER_DATA_PS_15 0x00B06C -#define R_00B100_SPI_SHADER_TBA_LO_VS 0x00B100 -#define R_00B104_SPI_SHADER_TBA_HI_VS 0x00B104 -#define S_00B104_MEM_BASE(x) (((x) & 0xFF) << 0) -#define G_00B104_MEM_BASE(x) (((x) >> 0) & 0xFF) -#define C_00B104_MEM_BASE 0xFFFFFF00 -#define R_00B108_SPI_SHADER_TMA_LO_VS 0x00B108 -#define R_00B10C_SPI_SHADER_TMA_HI_VS 0x00B10C -#define S_00B10C_MEM_BASE(x) (((x) & 0xFF) << 0) -#define G_00B10C_MEM_BASE(x) (((x) >> 0) & 0xFF) -#define C_00B10C_MEM_BASE 0xFFFFFF00 -/* CIK */ -#define R_00B118_SPI_SHADER_PGM_RSRC3_VS 0x00B118 -#define S_00B118_CU_EN(x) (((x) & 0xFFFF) << 0) -#define G_00B118_CU_EN(x) (((x) >> 0) & 0xFFFF) -#define C_00B118_CU_EN 0xFFFF0000 -#define S_00B118_WAVE_LIMIT(x) (((x) & 0x3F) << 16) -#define G_00B118_WAVE_LIMIT(x) (((x) >> 16) & 0x3F) -#define C_00B118_WAVE_LIMIT 0xFFC0FFFF -#define S_00B118_LOCK_LOW_THRESHOLD(x) (((x) & 0x0F) << 22) -#define G_00B118_LOCK_LOW_THRESHOLD(x) (((x) >> 22) & 0x0F) -#define C_00B118_LOCK_LOW_THRESHOLD 0xFC3FFFFF -#define R_00B11C_SPI_SHADER_LATE_ALLOC_VS 0x00B11C -#define S_00B11C_LIMIT(x) (((x) & 0x3F) << 0) -#define G_00B11C_LIMIT(x) (((x) >> 0) & 0x3F) -#define C_00B11C_LIMIT 0xFFFFFFC0 -/* */ -#define R_00B120_SPI_SHADER_PGM_LO_VS 0x00B120 -#define R_00B124_SPI_SHADER_PGM_HI_VS 0x00B124 -#define S_00B124_MEM_BASE(x) (((x) & 0xFF) << 0) -#define G_00B124_MEM_BASE(x) (((x) >> 0) & 0xFF) -#define C_00B124_MEM_BASE 0xFFFFFF00 -#define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128 -#define S_00B128_VGPRS(x) (((x) & 0x3F) << 0) -#define G_00B128_VGPRS(x) (((x) >> 0) & 0x3F) -#define C_00B128_VGPRS 0xFFFFFFC0 -#define S_00B128_SGPRS(x) (((x) & 0x0F) << 6) -#define G_00B128_SGPRS(x) (((x) >> 6) & 0x0F) -#define C_00B128_SGPRS 0xFFFFFC3F -#define S_00B128_PRIORITY(x) (((x) & 0x03) << 10) -#define G_00B128_PRIORITY(x) (((x) >> 10) & 0x03) -#define C_00B128_PRIORITY 0xFFFFF3FF -#define S_00B128_FLOAT_MODE(x) (((x) & 0xFF) << 12) -#define G_00B128_FLOAT_MODE(x) (((x) >> 12) & 0xFF) -#define C_00B128_FLOAT_MODE 0xFFF00FFF -#define S_00B128_PRIV(x) (((x) & 0x1) << 20) -#define G_00B128_PRIV(x) (((x) >> 20) & 0x1) -#define C_00B128_PRIV 0xFFEFFFFF -#define S_00B128_DX10_CLAMP(x) (((x) & 0x1) << 21) -#define G_00B128_DX10_CLAMP(x) (((x) >> 21) & 0x1) -#define C_00B128_DX10_CLAMP 0xFFDFFFFF -#define S_00B128_DEBUG_MODE(x) (((x) & 0x1) << 22) -#define G_00B128_DEBUG_MODE(x) (((x) >> 22) & 0x1) -#define C_00B128_DEBUG_MODE 0xFFBFFFFF -#define S_00B128_IEEE_MODE(x) (((x) & 0x1) << 23) -#define G_00B128_IEEE_MODE(x) (((x) >> 23) & 0x1) -#define C_00B128_IEEE_MODE 0xFF7FFFFF -#define S_00B128_VGPR_COMP_CNT(x) (((x) & 0x03) << 24) -#define G_00B128_VGPR_COMP_CNT(x) (((x) >> 24) & 0x03) -#define C_00B128_VGPR_COMP_CNT 0xFCFFFFFF -#define S_00B128_CU_GROUP_ENABLE(x) (((x) & 0x1) << 26) -#define G_00B128_CU_GROUP_ENABLE(x) (((x) >> 26) & 0x1) -#define C_00B128_CU_GROUP_ENABLE 0xFBFFFFFF -/* CIK */ -#define S_00B128_CACHE_CTL(x) (((x) & 0x07) << 27) -#define G_00B128_CACHE_CTL(x) (((x) >> 27) & 0x07) -#define C_00B128_CACHE_CTL 0xC7FFFFFF -#define S_00B128_CDBG_USER(x) (((x) & 0x1) << 30) -#define G_00B128_CDBG_USER(x) (((x) >> 30) & 0x1) -#define C_00B128_CDBG_USER 0xBFFFFFFF -/* */ -#define R_00B12C_SPI_SHADER_PGM_RSRC2_VS 0x00B12C -#define S_00B12C_SCRATCH_EN(x) (((x) & 0x1) << 0) -#define G_00B12C_SCRATCH_EN(x) (((x) >> 0) & 0x1) -#define C_00B12C_SCRATCH_EN 0xFFFFFFFE -#define S_00B12C_USER_SGPR(x) (((x) & 0x1F) << 1) -#define G_00B12C_USER_SGPR(x) (((x) >> 1) & 0x1F) -#define C_00B12C_USER_SGPR 0xFFFFFFC1 -#define S_00B12C_TRAP_PRESENT(x) (((x) & 0x1) << 6) -#define G_00B12C_TRAP_PRESENT(x) (((x) >> 6) & 0x1) -#define C_00B12C_TRAP_PRESENT 0xFFFFFFBF -#define S_00B12C_OC_LDS_EN(x) (((x) & 0x1) << 7) -#define G_00B12C_OC_LDS_EN(x) (((x) >> 7) & 0x1) -#define C_00B12C_OC_LDS_EN 0xFFFFFF7F -#define S_00B12C_SO_BASE0_EN(x) (((x) & 0x1) << 8) -#define G_00B12C_SO_BASE0_EN(x) (((x) >> 8) & 0x1) -#define C_00B12C_SO_BASE0_EN 0xFFFFFEFF -#define S_00B12C_SO_BASE1_EN(x) (((x) & 0x1) << 9) -#define G_00B12C_SO_BASE1_EN(x) (((x) >> 9) & 0x1) -#define C_00B12C_SO_BASE1_EN 0xFFFFFDFF -#define S_00B12C_SO_BASE2_EN(x) (((x) & 0x1) << 10) -#define G_00B12C_SO_BASE2_EN(x) (((x) >> 10) & 0x1) -#define C_00B12C_SO_BASE2_EN 0xFFFFFBFF -#define S_00B12C_SO_BASE3_EN(x) (((x) & 0x1) << 11) -#define G_00B12C_SO_BASE3_EN(x) (((x) >> 11) & 0x1) -#define C_00B12C_SO_BASE3_EN 0xFFFFF7FF -#define S_00B12C_SO_EN(x) (((x) & 0x1) << 12) -#define G_00B12C_SO_EN(x) (((x) >> 12) & 0x1) -#define C_00B12C_SO_EN 0xFFFFEFFF -#define S_00B12C_EXCP_EN(x) (((x) & 0x7F) << 13) /* mask is 0x1FF on CIK */ -#define G_00B12C_EXCP_EN(x) (((x) >> 13) & 0x7F) /* mask is 0x1FF on CIK */ -#define C_00B12C_EXCP_EN 0xFFF01FFF /* mask is 0x1FF on CIK */ -#define S_00B12C_EXCP_EN_CIK(x) (((x) & 0x1FF) << 13) -#define G_00B12C_EXCP_EN_CIK(x) (((x) >> 13) & 0x1FF) -#define C_00B12C_EXCP_EN_CIK 0xFFC01FFF -/* VI */ -#define S_00B12C_DISPATCH_DRAW_EN(x) (((x) & 0x1) << 24) -#define G_00B12C_DISPATCH_DRAW_EN(x) (((x) >> 24) & 0x1) -#define C_00B12C_DISPATCH_DRAW_EN 0xFEFFFFFF -/* */ -#define R_00B130_SPI_SHADER_USER_DATA_VS_0 0x00B130 -#define R_00B134_SPI_SHADER_USER_DATA_VS_1 0x00B134 -#define R_00B138_SPI_SHADER_USER_DATA_VS_2 0x00B138 -#define R_00B13C_SPI_SHADER_USER_DATA_VS_3 0x00B13C -#define R_00B140_SPI_SHADER_USER_DATA_VS_4 0x00B140 -#define R_00B144_SPI_SHADER_USER_DATA_VS_5 0x00B144 -#define R_00B148_SPI_SHADER_USER_DATA_VS_6 0x00B148 -#define R_00B14C_SPI_SHADER_USER_DATA_VS_7 0x00B14C -#define R_00B150_SPI_SHADER_USER_DATA_VS_8 0x00B150 -#define R_00B154_SPI_SHADER_USER_DATA_VS_9 0x00B154 -#define R_00B158_SPI_SHADER_USER_DATA_VS_10 0x00B158 -#define R_00B15C_SPI_SHADER_USER_DATA_VS_11 0x00B15C -#define R_00B160_SPI_SHADER_USER_DATA_VS_12 0x00B160 -#define R_00B164_SPI_SHADER_USER_DATA_VS_13 0x00B164 -#define R_00B168_SPI_SHADER_USER_DATA_VS_14 0x00B168 -#define R_00B16C_SPI_SHADER_USER_DATA_VS_15 0x00B16C -#define R_00B200_SPI_SHADER_TBA_LO_GS 0x00B200 -#define R_00B204_SPI_SHADER_TBA_HI_GS 0x00B204 -#define S_00B204_MEM_BASE(x) (((x) & 0xFF) << 0) -#define G_00B204_MEM_BASE(x) (((x) >> 0) & 0xFF) -#define C_00B204_MEM_BASE 0xFFFFFF00 -#define R_00B208_SPI_SHADER_TMA_LO_GS 0x00B208 -#define R_00B20C_SPI_SHADER_TMA_HI_GS 0x00B20C -#define S_00B20C_MEM_BASE(x) (((x) & 0xFF) << 0) -#define G_00B20C_MEM_BASE(x) (((x) >> 0) & 0xFF) -#define C_00B20C_MEM_BASE 0xFFFFFF00 -/* CIK */ -#define R_00B21C_SPI_SHADER_PGM_RSRC3_GS 0x00B21C -#define S_00B21C_CU_EN(x) (((x) & 0xFFFF) << 0) -#define G_00B21C_CU_EN(x) (((x) >> 0) & 0xFFFF) -#define C_00B21C_CU_EN 0xFFFF0000 -#define S_00B21C_WAVE_LIMIT(x) (((x) & 0x3F) << 16) -#define G_00B21C_WAVE_LIMIT(x) (((x) >> 16) & 0x3F) -#define C_00B21C_WAVE_LIMIT 0xFFC0FFFF -#define S_00B21C_LOCK_LOW_THRESHOLD(x) (((x) & 0x0F) << 22) -#define G_00B21C_LOCK_LOW_THRESHOLD(x) (((x) >> 22) & 0x0F) -#define C_00B21C_LOCK_LOW_THRESHOLD 0xFC3FFFFF -/* */ -/* VI */ -#define S_00B21C_GROUP_FIFO_DEPTH(x) (((x) & 0x3F) << 26) -#define G_00B21C_GROUP_FIFO_DEPTH(x) (((x) >> 26) & 0x3F) -#define C_00B21C_GROUP_FIFO_DEPTH 0x03FFFFFF -/* */ -#define R_00B220_SPI_SHADER_PGM_LO_GS 0x00B220 -#define R_00B224_SPI_SHADER_PGM_HI_GS 0x00B224 -#define S_00B224_MEM_BASE(x) (((x) & 0xFF) << 0) -#define G_00B224_MEM_BASE(x) (((x) >> 0) & 0xFF) -#define C_00B224_MEM_BASE 0xFFFFFF00 -#define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228 -#define S_00B228_VGPRS(x) (((x) & 0x3F) << 0) -#define G_00B228_VGPRS(x) (((x) >> 0) & 0x3F) -#define C_00B228_VGPRS 0xFFFFFFC0 -#define S_00B228_SGPRS(x) (((x) & 0x0F) << 6) -#define G_00B228_SGPRS(x) (((x) >> 6) & 0x0F) -#define C_00B228_SGPRS 0xFFFFFC3F -#define S_00B228_PRIORITY(x) (((x) & 0x03) << 10) -#define G_00B228_PRIORITY(x) (((x) >> 10) & 0x03) -#define C_00B228_PRIORITY 0xFFFFF3FF -#define S_00B228_FLOAT_MODE(x) (((x) & 0xFF) << 12) -#define G_00B228_FLOAT_MODE(x) (((x) >> 12) & 0xFF) -#define C_00B228_FLOAT_MODE 0xFFF00FFF -#define S_00B228_PRIV(x) (((x) & 0x1) << 20) -#define G_00B228_PRIV(x) (((x) >> 20) & 0x1) -#define C_00B228_PRIV 0xFFEFFFFF -#define S_00B228_DX10_CLAMP(x) (((x) & 0x1) << 21) -#define G_00B228_DX10_CLAMP(x) (((x) >> 21) & 0x1) -#define C_00B228_DX10_CLAMP 0xFFDFFFFF -#define S_00B228_DEBUG_MODE(x) (((x) & 0x1) << 22) -#define G_00B228_DEBUG_MODE(x) (((x) >> 22) & 0x1) -#define C_00B228_DEBUG_MODE 0xFFBFFFFF -#define S_00B228_IEEE_MODE(x) (((x) & 0x1) << 23) -#define G_00B228_IEEE_MODE(x) (((x) >> 23) & 0x1) -#define C_00B228_IEEE_MODE 0xFF7FFFFF -#define S_00B228_CU_GROUP_ENABLE(x) (((x) & 0x1) << 24) -#define G_00B228_CU_GROUP_ENABLE(x) (((x) >> 24) & 0x1) -#define C_00B228_CU_GROUP_ENABLE 0xFEFFFFFF -/* CIK */ -#define S_00B228_CACHE_CTL(x) (((x) & 0x07) << 25) -#define G_00B228_CACHE_CTL(x) (((x) >> 25) & 0x07) -#define C_00B228_CACHE_CTL 0xF1FFFFFF -#define S_00B228_CDBG_USER(x) (((x) & 0x1) << 28) -#define G_00B228_CDBG_USER(x) (((x) >> 28) & 0x1) -#define C_00B228_CDBG_USER 0xEFFFFFFF -/* */ -#define R_00B22C_SPI_SHADER_PGM_RSRC2_GS 0x00B22C -#define S_00B22C_SCRATCH_EN(x) (((x) & 0x1) << 0) -#define G_00B22C_SCRATCH_EN(x) (((x) >> 0) & 0x1) -#define C_00B22C_SCRATCH_EN 0xFFFFFFFE -#define S_00B22C_USER_SGPR(x) (((x) & 0x1F) << 1) -#define G_00B22C_USER_SGPR(x) (((x) >> 1) & 0x1F) -#define C_00B22C_USER_SGPR 0xFFFFFFC1 -#define S_00B22C_TRAP_PRESENT(x) (((x) & 0x1) << 6) -#define G_00B22C_TRAP_PRESENT(x) (((x) >> 6) & 0x1) -#define C_00B22C_TRAP_PRESENT 0xFFFFFFBF -#define S_00B22C_EXCP_EN(x) (((x) & 0x7F) << 7) /* mask is 0x1FF on CIK */ -#define G_00B22C_EXCP_EN(x) (((x) >> 7) & 0x7F) /* mask is 0x1FF on CIK */ -#define C_00B22C_EXCP_EN 0xFFFFC07F /* mask is 0x1FF on CIK */ -#define S_00B22C_EXCP_EN_CIK(x) (((x) & 0x1FF) << 7) -#define G_00B22C_EXCP_EN_CIK(x) (((x) >> 7) & 0x1FF) -#define C_00B22C_EXCP_EN_CIK 0xFFFF007F -#define R_00B230_SPI_SHADER_USER_DATA_GS_0 0x00B230 -#define R_00B234_SPI_SHADER_USER_DATA_GS_1 0x00B234 -#define R_00B238_SPI_SHADER_USER_DATA_GS_2 0x00B238 -#define R_00B23C_SPI_SHADER_USER_DATA_GS_3 0x00B23C -#define R_00B240_SPI_SHADER_USER_DATA_GS_4 0x00B240 -#define R_00B244_SPI_SHADER_USER_DATA_GS_5 0x00B244 -#define R_00B248_SPI_SHADER_USER_DATA_GS_6 0x00B248 -#define R_00B24C_SPI_SHADER_USER_DATA_GS_7 0x00B24C -#define R_00B250_SPI_SHADER_USER_DATA_GS_8 0x00B250 -#define R_00B254_SPI_SHADER_USER_DATA_GS_9 0x00B254 -#define R_00B258_SPI_SHADER_USER_DATA_GS_10 0x00B258 -#define R_00B25C_SPI_SHADER_USER_DATA_GS_11 0x00B25C -#define R_00B260_SPI_SHADER_USER_DATA_GS_12 0x00B260 -#define R_00B264_SPI_SHADER_USER_DATA_GS_13 0x00B264 -#define R_00B268_SPI_SHADER_USER_DATA_GS_14 0x00B268 -#define R_00B26C_SPI_SHADER_USER_DATA_GS_15 0x00B26C -#define R_00B300_SPI_SHADER_TBA_LO_ES 0x00B300 -#define R_00B304_SPI_SHADER_TBA_HI_ES 0x00B304 -#define S_00B304_MEM_BASE(x) (((x) & 0xFF) << 0) -#define G_00B304_MEM_BASE(x) (((x) >> 0) & 0xFF) -#define C_00B304_MEM_BASE 0xFFFFFF00 -#define R_00B308_SPI_SHADER_TMA_LO_ES 0x00B308 -#define R_00B30C_SPI_SHADER_TMA_HI_ES 0x00B30C -#define S_00B30C_MEM_BASE(x) (((x) & 0xFF) << 0) -#define G_00B30C_MEM_BASE(x) (((x) >> 0) & 0xFF) -#define C_00B30C_MEM_BASE 0xFFFFFF00 -/* CIK */ -#define R_00B31C_SPI_SHADER_PGM_RSRC3_ES 0x00B31C -#define S_00B31C_CU_EN(x) (((x) & 0xFFFF) << 0) -#define G_00B31C_CU_EN(x) (((x) >> 0) & 0xFFFF) -#define C_00B31C_CU_EN 0xFFFF0000 -#define S_00B31C_WAVE_LIMIT(x) (((x) & 0x3F) << 16) -#define G_00B31C_WAVE_LIMIT(x) (((x) >> 16) & 0x3F) -#define C_00B31C_WAVE_LIMIT 0xFFC0FFFF -#define S_00B31C_LOCK_LOW_THRESHOLD(x) (((x) & 0x0F) << 22) -#define G_00B31C_LOCK_LOW_THRESHOLD(x) (((x) >> 22) & 0x0F) -#define C_00B31C_LOCK_LOW_THRESHOLD 0xFC3FFFFF -/* */ -/* VI */ -#define S_00B31C_GROUP_FIFO_DEPTH(x) (((x) & 0x3F) << 26) -#define G_00B31C_GROUP_FIFO_DEPTH(x) (((x) >> 26) & 0x3F) -#define C_00B31C_GROUP_FIFO_DEPTH 0x03FFFFFF -/* */ -#define R_00B320_SPI_SHADER_PGM_LO_ES 0x00B320 -#define R_00B324_SPI_SHADER_PGM_HI_ES 0x00B324 -#define S_00B324_MEM_BASE(x) (((x) & 0xFF) << 0) -#define G_00B324_MEM_BASE(x) (((x) >> 0) & 0xFF) -#define C_00B324_MEM_BASE 0xFFFFFF00 -#define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328 -#define S_00B328_VGPRS(x) (((x) & 0x3F) << 0) -#define G_00B328_VGPRS(x) (((x) >> 0) & 0x3F) -#define C_00B328_VGPRS 0xFFFFFFC0 -#define S_00B328_SGPRS(x) (((x) & 0x0F) << 6) -#define G_00B328_SGPRS(x) (((x) >> 6) & 0x0F) -#define C_00B328_SGPRS 0xFFFFFC3F -#define S_00B328_PRIORITY(x) (((x) & 0x03) << 10) -#define G_00B328_PRIORITY(x) (((x) >> 10) & 0x03) -#define C_00B328_PRIORITY 0xFFFFF3FF -#define S_00B328_FLOAT_MODE(x) (((x) & 0xFF) << 12) -#define G_00B328_FLOAT_MODE(x) (((x) >> 12) & 0xFF) -#define C_00B328_FLOAT_MODE 0xFFF00FFF -#define S_00B328_PRIV(x) (((x) & 0x1) << 20) -#define G_00B328_PRIV(x) (((x) >> 20) & 0x1) -#define C_00B328_PRIV 0xFFEFFFFF -#define S_00B328_DX10_CLAMP(x) (((x) & 0x1) << 21) -#define G_00B328_DX10_CLAMP(x) (((x) >> 21) & 0x1) -#define C_00B328_DX10_CLAMP 0xFFDFFFFF -#define S_00B328_DEBUG_MODE(x) (((x) & 0x1) << 22) -#define G_00B328_DEBUG_MODE(x) (((x) >> 22) & 0x1) -#define C_00B328_DEBUG_MODE 0xFFBFFFFF -#define S_00B328_IEEE_MODE(x) (((x) & 0x1) << 23) -#define G_00B328_IEEE_MODE(x) (((x) >> 23) & 0x1) -#define C_00B328_IEEE_MODE 0xFF7FFFFF -#define S_00B328_VGPR_COMP_CNT(x) (((x) & 0x03) << 24) -#define G_00B328_VGPR_COMP_CNT(x) (((x) >> 24) & 0x03) -#define C_00B328_VGPR_COMP_CNT 0xFCFFFFFF -#define S_00B328_CU_GROUP_ENABLE(x) (((x) & 0x1) << 26) -#define G_00B328_CU_GROUP_ENABLE(x) (((x) >> 26) & 0x1) -#define C_00B328_CU_GROUP_ENABLE 0xFBFFFFFF -/* CIK */ -#define S_00B328_CACHE_CTL(x) (((x) & 0x07) << 27) -#define G_00B328_CACHE_CTL(x) (((x) >> 27) & 0x07) -#define C_00B328_CACHE_CTL 0xC7FFFFFF -#define S_00B328_CDBG_USER(x) (((x) & 0x1) << 30) -#define G_00B328_CDBG_USER(x) (((x) >> 30) & 0x1) -#define C_00B328_CDBG_USER 0xBFFFFFFF -/* */ -#define R_00B32C_SPI_SHADER_PGM_RSRC2_ES 0x00B32C -#define S_00B32C_SCRATCH_EN(x) (((x) & 0x1) << 0) -#define G_00B32C_SCRATCH_EN(x) (((x) >> 0) & 0x1) -#define C_00B32C_SCRATCH_EN 0xFFFFFFFE -#define S_00B32C_USER_SGPR(x) (((x) & 0x1F) << 1) -#define G_00B32C_USER_SGPR(x) (((x) >> 1) & 0x1F) -#define C_00B32C_USER_SGPR 0xFFFFFFC1 -#define S_00B32C_TRAP_PRESENT(x) (((x) & 0x1) << 6) -#define G_00B32C_TRAP_PRESENT(x) (((x) >> 6) & 0x1) -#define C_00B32C_TRAP_PRESENT 0xFFFFFFBF -#define S_00B32C_OC_LDS_EN(x) (((x) & 0x1) << 7) -#define G_00B32C_OC_LDS_EN(x) (((x) >> 7) & 0x1) -#define C_00B32C_OC_LDS_EN 0xFFFFFF7F -#define S_00B32C_EXCP_EN(x) (((x) & 0x7F) << 8) /* mask is 0x1FF on CIK */ -#define G_00B32C_EXCP_EN(x) (((x) >> 8) & 0x7F) /* mask is 0x1FF on CIK */ -#define C_00B32C_EXCP_EN 0xFFFF80FF /* mask is 0x1FF on CIK */ -#define S_00B32C_LDS_SIZE(x) (((x) & 0x1FF) << 20) /* CIK, for on-chip GS */ -#define G_00B32C_LDS_SIZE(x) (((x) >> 20) & 0x1FF) /* CIK, for on-chip GS */ -#define C_00B32C_LDS_SIZE 0xE00FFFFF /* CIK, for on-chip GS */ -#define R_00B330_SPI_SHADER_USER_DATA_ES_0 0x00B330 -#define R_00B334_SPI_SHADER_USER_DATA_ES_1 0x00B334 -#define R_00B338_SPI_SHADER_USER_DATA_ES_2 0x00B338 -#define R_00B33C_SPI_SHADER_USER_DATA_ES_3 0x00B33C -#define R_00B340_SPI_SHADER_USER_DATA_ES_4 0x00B340 -#define R_00B344_SPI_SHADER_USER_DATA_ES_5 0x00B344 -#define R_00B348_SPI_SHADER_USER_DATA_ES_6 0x00B348 -#define R_00B34C_SPI_SHADER_USER_DATA_ES_7 0x00B34C -#define R_00B350_SPI_SHADER_USER_DATA_ES_8 0x00B350 -#define R_00B354_SPI_SHADER_USER_DATA_ES_9 0x00B354 -#define R_00B358_SPI_SHADER_USER_DATA_ES_10 0x00B358 -#define R_00B35C_SPI_SHADER_USER_DATA_ES_11 0x00B35C -#define R_00B360_SPI_SHADER_USER_DATA_ES_12 0x00B360 -#define R_00B364_SPI_SHADER_USER_DATA_ES_13 0x00B364 -#define R_00B368_SPI_SHADER_USER_DATA_ES_14 0x00B368 -#define R_00B36C_SPI_SHADER_USER_DATA_ES_15 0x00B36C -#define R_00B400_SPI_SHADER_TBA_LO_HS 0x00B400 -#define R_00B404_SPI_SHADER_TBA_HI_HS 0x00B404 -#define S_00B404_MEM_BASE(x) (((x) & 0xFF) << 0) -#define G_00B404_MEM_BASE(x) (((x) >> 0) & 0xFF) -#define C_00B404_MEM_BASE 0xFFFFFF00 -#define R_00B408_SPI_SHADER_TMA_LO_HS 0x00B408 -#define R_00B40C_SPI_SHADER_TMA_HI_HS 0x00B40C -#define S_00B40C_MEM_BASE(x) (((x) & 0xFF) << 0) -#define G_00B40C_MEM_BASE(x) (((x) >> 0) & 0xFF) -#define C_00B40C_MEM_BASE 0xFFFFFF00 -/* CIK */ -#define R_00B41C_SPI_SHADER_PGM_RSRC3_HS 0x00B41C -#define S_00B41C_WAVE_LIMIT(x) (((x) & 0x3F) << 0) -#define G_00B41C_WAVE_LIMIT(x) (((x) >> 0) & 0x3F) -#define C_00B41C_WAVE_LIMIT 0xFFFFFFC0 -#define S_00B41C_LOCK_LOW_THRESHOLD(x) (((x) & 0x0F) << 6) -#define G_00B41C_LOCK_LOW_THRESHOLD(x) (((x) >> 6) & 0x0F) -#define C_00B41C_LOCK_LOW_THRESHOLD 0xFFFFFC3F -/* */ -/* VI */ -#define S_00B41C_GROUP_FIFO_DEPTH(x) (((x) & 0x3F) << 10) -#define G_00B41C_GROUP_FIFO_DEPTH(x) (((x) >> 10) & 0x3F) -#define C_00B41C_GROUP_FIFO_DEPTH 0xFFFF03FF -/* */ -#define R_00B420_SPI_SHADER_PGM_LO_HS 0x00B420 -#define R_00B424_SPI_SHADER_PGM_HI_HS 0x00B424 -#define S_00B424_MEM_BASE(x) (((x) & 0xFF) << 0) -#define G_00B424_MEM_BASE(x) (((x) >> 0) & 0xFF) -#define C_00B424_MEM_BASE 0xFFFFFF00 -#define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428 -#define S_00B428_VGPRS(x) (((x) & 0x3F) << 0) -#define G_00B428_VGPRS(x) (((x) >> 0) & 0x3F) -#define C_00B428_VGPRS 0xFFFFFFC0 -#define S_00B428_SGPRS(x) (((x) & 0x0F) << 6) -#define G_00B428_SGPRS(x) (((x) >> 6) & 0x0F) -#define C_00B428_SGPRS 0xFFFFFC3F -#define S_00B428_PRIORITY(x) (((x) & 0x03) << 10) -#define G_00B428_PRIORITY(x) (((x) >> 10) & 0x03) -#define C_00B428_PRIORITY 0xFFFFF3FF -#define S_00B428_FLOAT_MODE(x) (((x) & 0xFF) << 12) -#define G_00B428_FLOAT_MODE(x) (((x) >> 12) & 0xFF) -#define C_00B428_FLOAT_MODE 0xFFF00FFF -#define S_00B428_PRIV(x) (((x) & 0x1) << 20) -#define G_00B428_PRIV(x) (((x) >> 20) & 0x1) -#define C_00B428_PRIV 0xFFEFFFFF -#define S_00B428_DX10_CLAMP(x) (((x) & 0x1) << 21) -#define G_00B428_DX10_CLAMP(x) (((x) >> 21) & 0x1) -#define C_00B428_DX10_CLAMP 0xFFDFFFFF -#define S_00B428_DEBUG_MODE(x) (((x) & 0x1) << 22) -#define G_00B428_DEBUG_MODE(x) (((x) >> 22) & 0x1) -#define C_00B428_DEBUG_MODE 0xFFBFFFFF -#define S_00B428_IEEE_MODE(x) (((x) & 0x1) << 23) -#define G_00B428_IEEE_MODE(x) (((x) >> 23) & 0x1) -#define C_00B428_IEEE_MODE 0xFF7FFFFF -/* CIK */ -#define S_00B428_CACHE_CTL(x) (((x) & 0x07) << 24) -#define G_00B428_CACHE_CTL(x) (((x) >> 24) & 0x07) -#define C_00B428_CACHE_CTL 0xF8FFFFFF -#define S_00B428_CDBG_USER(x) (((x) & 0x1) << 27) -#define G_00B428_CDBG_USER(x) (((x) >> 27) & 0x1) -#define C_00B428_CDBG_USER 0xF7FFFFFF -/* */ -#define R_00B42C_SPI_SHADER_PGM_RSRC2_HS 0x00B42C -#define S_00B42C_SCRATCH_EN(x) (((x) & 0x1) << 0) -#define G_00B42C_SCRATCH_EN(x) (((x) >> 0) & 0x1) -#define C_00B42C_SCRATCH_EN 0xFFFFFFFE -#define S_00B42C_USER_SGPR(x) (((x) & 0x1F) << 1) -#define G_00B42C_USER_SGPR(x) (((x) >> 1) & 0x1F) -#define C_00B42C_USER_SGPR 0xFFFFFFC1 -#define S_00B42C_TRAP_PRESENT(x) (((x) & 0x1) << 6) -#define G_00B42C_TRAP_PRESENT(x) (((x) >> 6) & 0x1) -#define C_00B42C_TRAP_PRESENT 0xFFFFFFBF -#define S_00B42C_OC_LDS_EN(x) (((x) & 0x1) << 7) -#define G_00B42C_OC_LDS_EN(x) (((x) >> 7) & 0x1) -#define C_00B42C_OC_LDS_EN 0xFFFFFF7F -#define S_00B42C_TG_SIZE_EN(x) (((x) & 0x1) << 8) -#define G_00B42C_TG_SIZE_EN(x) (((x) >> 8) & 0x1) -#define C_00B42C_TG_SIZE_EN 0xFFFFFEFF -#define S_00B42C_EXCP_EN(x) (((x) & 0x7F) << 9) /* mask is 0x1FF on CIK */ -#define G_00B42C_EXCP_EN(x) (((x) >> 9) & 0x7F) /* mask is 0x1FF on CIK */ -#define C_00B42C_EXCP_EN 0xFFFF01FF /* mask is 0x1FF on CIK */ -#define R_00B430_SPI_SHADER_USER_DATA_HS_0 0x00B430 -#define R_00B434_SPI_SHADER_USER_DATA_HS_1 0x00B434 -#define R_00B438_SPI_SHADER_USER_DATA_HS_2 0x00B438 -#define R_00B43C_SPI_SHADER_USER_DATA_HS_3 0x00B43C -#define R_00B440_SPI_SHADER_USER_DATA_HS_4 0x00B440 -#define R_00B444_SPI_SHADER_USER_DATA_HS_5 0x00B444 -#define R_00B448_SPI_SHADER_USER_DATA_HS_6 0x00B448 -#define R_00B44C_SPI_SHADER_USER_DATA_HS_7 0x00B44C -#define R_00B450_SPI_SHADER_USER_DATA_HS_8 0x00B450 -#define R_00B454_SPI_SHADER_USER_DATA_HS_9 0x00B454 -#define R_00B458_SPI_SHADER_USER_DATA_HS_10 0x00B458 -#define R_00B45C_SPI_SHADER_USER_DATA_HS_11 0x00B45C -#define R_00B460_SPI_SHADER_USER_DATA_HS_12 0x00B460 -#define R_00B464_SPI_SHADER_USER_DATA_HS_13 0x00B464 -#define R_00B468_SPI_SHADER_USER_DATA_HS_14 0x00B468 -#define R_00B46C_SPI_SHADER_USER_DATA_HS_15 0x00B46C -#define R_00B500_SPI_SHADER_TBA_LO_LS 0x00B500 -#define R_00B504_SPI_SHADER_TBA_HI_LS 0x00B504 -#define S_00B504_MEM_BASE(x) (((x) & 0xFF) << 0) -#define G_00B504_MEM_BASE(x) (((x) >> 0) & 0xFF) -#define C_00B504_MEM_BASE 0xFFFFFF00 -#define R_00B508_SPI_SHADER_TMA_LO_LS 0x00B508 -#define R_00B50C_SPI_SHADER_TMA_HI_LS 0x00B50C -#define S_00B50C_MEM_BASE(x) (((x) & 0xFF) << 0) -#define G_00B50C_MEM_BASE(x) (((x) >> 0) & 0xFF) -#define C_00B50C_MEM_BASE 0xFFFFFF00 -/* CIK */ -#define R_00B51C_SPI_SHADER_PGM_RSRC3_LS 0x00B51C -#define S_00B51C_CU_EN(x) (((x) & 0xFFFF) << 0) -#define G_00B51C_CU_EN(x) (((x) >> 0) & 0xFFFF) -#define C_00B51C_CU_EN 0xFFFF0000 -#define S_00B51C_WAVE_LIMIT(x) (((x) & 0x3F) << 16) -#define G_00B51C_WAVE_LIMIT(x) (((x) >> 16) & 0x3F) -#define C_00B51C_WAVE_LIMIT 0xFFC0FFFF -#define S_00B51C_LOCK_LOW_THRESHOLD(x) (((x) & 0x0F) << 22) -#define G_00B51C_LOCK_LOW_THRESHOLD(x) (((x) >> 22) & 0x0F) -#define C_00B51C_LOCK_LOW_THRESHOLD 0xFC3FFFFF -/* */ -/* VI */ -#define S_00B51C_GROUP_FIFO_DEPTH(x) (((x) & 0x3F) << 26) -#define G_00B51C_GROUP_FIFO_DEPTH(x) (((x) >> 26) & 0x3F) -#define C_00B51C_GROUP_FIFO_DEPTH 0x03FFFFFF -/* */ -#define R_00B520_SPI_SHADER_PGM_LO_LS 0x00B520 -#define R_00B524_SPI_SHADER_PGM_HI_LS 0x00B524 -#define S_00B524_MEM_BASE(x) (((x) & 0xFF) << 0) -#define G_00B524_MEM_BASE(x) (((x) >> 0) & 0xFF) -#define C_00B524_MEM_BASE 0xFFFFFF00 -#define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528 -#define S_00B528_VGPRS(x) (((x) & 0x3F) << 0) -#define G_00B528_VGPRS(x) (((x) >> 0) & 0x3F) -#define C_00B528_VGPRS 0xFFFFFFC0 -#define S_00B528_SGPRS(x) (((x) & 0x0F) << 6) -#define G_00B528_SGPRS(x) (((x) >> 6) & 0x0F) -#define C_00B528_SGPRS 0xFFFFFC3F -#define S_00B528_PRIORITY(x) (((x) & 0x03) << 10) -#define G_00B528_PRIORITY(x) (((x) >> 10) & 0x03) -#define C_00B528_PRIORITY 0xFFFFF3FF -#define S_00B528_FLOAT_MODE(x) (((x) & 0xFF) << 12) -#define G_00B528_FLOAT_MODE(x) (((x) >> 12) & 0xFF) -#define C_00B528_FLOAT_MODE 0xFFF00FFF -#define S_00B528_PRIV(x) (((x) & 0x1) << 20) -#define G_00B528_PRIV(x) (((x) >> 20) & 0x1) -#define C_00B528_PRIV 0xFFEFFFFF -#define S_00B528_DX10_CLAMP(x) (((x) & 0x1) << 21) -#define G_00B528_DX10_CLAMP(x) (((x) >> 21) & 0x1) -#define C_00B528_DX10_CLAMP 0xFFDFFFFF -#define S_00B528_DEBUG_MODE(x) (((x) & 0x1) << 22) -#define G_00B528_DEBUG_MODE(x) (((x) >> 22) & 0x1) -#define C_00B528_DEBUG_MODE 0xFFBFFFFF -#define S_00B528_IEEE_MODE(x) (((x) & 0x1) << 23) -#define G_00B528_IEEE_MODE(x) (((x) >> 23) & 0x1) -#define C_00B528_IEEE_MODE 0xFF7FFFFF -#define S_00B528_VGPR_COMP_CNT(x) (((x) & 0x03) << 24) -#define G_00B528_VGPR_COMP_CNT(x) (((x) >> 24) & 0x03) -#define C_00B528_VGPR_COMP_CNT 0xFCFFFFFF -/* CIK */ -#define S_00B528_CACHE_CTL(x) (((x) & 0x07) << 26) -#define G_00B528_CACHE_CTL(x) (((x) >> 26) & 0x07) -#define C_00B528_CACHE_CTL 0xE3FFFFFF -#define S_00B528_CDBG_USER(x) (((x) & 0x1) << 29) -#define G_00B528_CDBG_USER(x) (((x) >> 29) & 0x1) -#define C_00B528_CDBG_USER 0xDFFFFFFF -/* */ -#define R_00B52C_SPI_SHADER_PGM_RSRC2_LS 0x00B52C -#define S_00B52C_SCRATCH_EN(x) (((x) & 0x1) << 0) -#define G_00B52C_SCRATCH_EN(x) (((x) >> 0) & 0x1) -#define C_00B52C_SCRATCH_EN 0xFFFFFFFE -#define S_00B52C_USER_SGPR(x) (((x) & 0x1F) << 1) -#define G_00B52C_USER_SGPR(x) (((x) >> 1) & 0x1F) -#define C_00B52C_USER_SGPR 0xFFFFFFC1 -#define S_00B52C_TRAP_PRESENT(x) (((x) & 0x1) << 6) -#define G_00B52C_TRAP_PRESENT(x) (((x) >> 6) & 0x1) -#define C_00B52C_TRAP_PRESENT 0xFFFFFFBF -#define S_00B52C_LDS_SIZE(x) (((x) & 0x1FF) << 7) -#define G_00B52C_LDS_SIZE(x) (((x) >> 7) & 0x1FF) -#define C_00B52C_LDS_SIZE 0xFFFF007F -#define S_00B52C_EXCP_EN(x) (((x) & 0x7F) << 16) /* mask is 0x1FF on CIK */ -#define G_00B52C_EXCP_EN(x) (((x) >> 16) & 0x7F) /* mask is 0x1FF on CIK */ -#define C_00B52C_EXCP_EN 0xFF80FFFF /* mask is 0x1FF on CIK */ -#define R_00B530_SPI_SHADER_USER_DATA_LS_0 0x00B530 -#define R_00B534_SPI_SHADER_USER_DATA_LS_1 0x00B534 -#define R_00B538_SPI_SHADER_USER_DATA_LS_2 0x00B538 -#define R_00B53C_SPI_SHADER_USER_DATA_LS_3 0x00B53C -#define R_00B540_SPI_SHADER_USER_DATA_LS_4 0x00B540 -#define R_00B544_SPI_SHADER_USER_DATA_LS_5 0x00B544 -#define R_00B548_SPI_SHADER_USER_DATA_LS_6 0x00B548 -#define R_00B54C_SPI_SHADER_USER_DATA_LS_7 0x00B54C -#define R_00B550_SPI_SHADER_USER_DATA_LS_8 0x00B550 -#define R_00B554_SPI_SHADER_USER_DATA_LS_9 0x00B554 -#define R_00B558_SPI_SHADER_USER_DATA_LS_10 0x00B558 -#define R_00B55C_SPI_SHADER_USER_DATA_LS_11 0x00B55C -#define R_00B560_SPI_SHADER_USER_DATA_LS_12 0x00B560 -#define R_00B564_SPI_SHADER_USER_DATA_LS_13 0x00B564 -#define R_00B568_SPI_SHADER_USER_DATA_LS_14 0x00B568 -#define R_00B56C_SPI_SHADER_USER_DATA_LS_15 0x00B56C -#define R_00B800_COMPUTE_DISPATCH_INITIATOR 0x00B800 -#define S_00B800_COMPUTE_SHADER_EN(x) (((x) & 0x1) << 0) -#define G_00B800_COMPUTE_SHADER_EN(x) (((x) >> 0) & 0x1) -#define C_00B800_COMPUTE_SHADER_EN 0xFFFFFFFE -#define S_00B800_PARTIAL_TG_EN(x) (((x) & 0x1) << 1) -#define G_00B800_PARTIAL_TG_EN(x) (((x) >> 1) & 0x1) -#define C_00B800_PARTIAL_TG_EN 0xFFFFFFFD -#define S_00B800_FORCE_START_AT_000(x) (((x) & 0x1) << 2) -#define G_00B800_FORCE_START_AT_000(x) (((x) >> 2) & 0x1) -#define C_00B800_FORCE_START_AT_000 0xFFFFFFFB -#define S_00B800_ORDERED_APPEND_ENBL(x) (((x) & 0x1) << 3) -#define G_00B800_ORDERED_APPEND_ENBL(x) (((x) >> 3) & 0x1) -#define C_00B800_ORDERED_APPEND_ENBL 0xFFFFFFF7 -/* CIK */ -#define S_00B800_ORDERED_APPEND_MODE(x) (((x) & 0x1) << 4) -#define G_00B800_ORDERED_APPEND_MODE(x) (((x) >> 4) & 0x1) -#define C_00B800_ORDERED_APPEND_MODE 0xFFFFFFEF -#define S_00B800_USE_THREAD_DIMENSIONS(x) (((x) & 0x1) << 5) -#define G_00B800_USE_THREAD_DIMENSIONS(x) (((x) >> 5) & 0x1) -#define C_00B800_USE_THREAD_DIMENSIONS 0xFFFFFFDF -#define S_00B800_ORDER_MODE(x) (((x) & 0x1) << 6) -#define G_00B800_ORDER_MODE(x) (((x) >> 6) & 0x1) -#define C_00B800_ORDER_MODE 0xFFFFFFBF -#define S_00B800_DISPATCH_CACHE_CNTL(x) (((x) & 0x07) << 7) -#define G_00B800_DISPATCH_CACHE_CNTL(x) (((x) >> 7) & 0x07) -#define C_00B800_DISPATCH_CACHE_CNTL 0xFFFFFC7F -#define S_00B800_SCALAR_L1_INV_VOL(x) (((x) & 0x1) << 10) -#define G_00B800_SCALAR_L1_INV_VOL(x) (((x) >> 10) & 0x1) -#define C_00B800_SCALAR_L1_INV_VOL 0xFFFFFBFF -#define S_00B800_VECTOR_L1_INV_VOL(x) (((x) & 0x1) << 11) -#define G_00B800_VECTOR_L1_INV_VOL(x) (((x) >> 11) & 0x1) -#define C_00B800_VECTOR_L1_INV_VOL 0xFFFFF7FF -#define S_00B800_DATA_ATC(x) (((x) & 0x1) << 12) -#define G_00B800_DATA_ATC(x) (((x) >> 12) & 0x1) -#define C_00B800_DATA_ATC 0xFFFFEFFF -#define S_00B800_RESTORE(x) (((x) & 0x1) << 14) -#define G_00B800_RESTORE(x) (((x) >> 14) & 0x1) -#define C_00B800_RESTORE 0xFFFFBFFF -/* */ -#define R_00B804_COMPUTE_DIM_X 0x00B804 -#define R_00B808_COMPUTE_DIM_Y 0x00B808 -#define R_00B80C_COMPUTE_DIM_Z 0x00B80C -#define R_00B810_COMPUTE_START_X 0x00B810 -#define R_00B814_COMPUTE_START_Y 0x00B814 -#define R_00B818_COMPUTE_START_Z 0x00B818 -#define R_00B81C_COMPUTE_NUM_THREAD_X 0x00B81C -#define S_00B81C_NUM_THREAD_FULL(x) (((x) & 0xFFFF) << 0) -#define G_00B81C_NUM_THREAD_FULL(x) (((x) >> 0) & 0xFFFF) -#define C_00B81C_NUM_THREAD_FULL 0xFFFF0000 -#define S_00B81C_NUM_THREAD_PARTIAL(x) (((x) & 0xFFFF) << 16) -#define G_00B81C_NUM_THREAD_PARTIAL(x) (((x) >> 16) & 0xFFFF) -#define C_00B81C_NUM_THREAD_PARTIAL 0x0000FFFF -#define R_00B820_COMPUTE_NUM_THREAD_Y 0x00B820 -#define S_00B820_NUM_THREAD_FULL(x) (((x) & 0xFFFF) << 0) -#define G_00B820_NUM_THREAD_FULL(x) (((x) >> 0) & 0xFFFF) -#define C_00B820_NUM_THREAD_FULL 0xFFFF0000 -#define S_00B820_NUM_THREAD_PARTIAL(x) (((x) & 0xFFFF) << 16) -#define G_00B820_NUM_THREAD_PARTIAL(x) (((x) >> 16) & 0xFFFF) -#define C_00B820_NUM_THREAD_PARTIAL 0x0000FFFF -#define R_00B824_COMPUTE_NUM_THREAD_Z 0x00B824 -#define S_00B824_NUM_THREAD_FULL(x) (((x) & 0xFFFF) << 0) -#define G_00B824_NUM_THREAD_FULL(x) (((x) >> 0) & 0xFFFF) -#define C_00B824_NUM_THREAD_FULL 0xFFFF0000 -#define S_00B824_NUM_THREAD_PARTIAL(x) (((x) & 0xFFFF) << 16) -#define G_00B824_NUM_THREAD_PARTIAL(x) (((x) >> 16) & 0xFFFF) -#define C_00B824_NUM_THREAD_PARTIAL 0x0000FFFF -#define R_00B82C_COMPUTE_MAX_WAVE_ID 0x00B82C /* moved to 0xCD20 on CIK */ -#define S_00B82C_MAX_WAVE_ID(x) (((x) & 0xFFF) << 0) -#define G_00B82C_MAX_WAVE_ID(x) (((x) >> 0) & 0xFFF) -#define C_00B82C_MAX_WAVE_ID 0xFFFFF000 -/* CIK */ -#define R_00B828_COMPUTE_PIPELINESTAT_ENABLE 0x00B828 -#define S_00B828_PIPELINESTAT_ENABLE(x) (((x) & 0x1) << 0) -#define G_00B828_PIPELINESTAT_ENABLE(x) (((x) >> 0) & 0x1) -#define C_00B828_PIPELINESTAT_ENABLE 0xFFFFFFFE -#define R_00B82C_COMPUTE_PERFCOUNT_ENABLE 0x00B82C -#define S_00B82C_PERFCOUNT_ENABLE(x) (((x) & 0x1) << 0) -#define G_00B82C_PERFCOUNT_ENABLE(x) (((x) >> 0) & 0x1) -#define C_00B82C_PERFCOUNT_ENABLE 0xFFFFFFFE -/* */ -#define R_00B830_COMPUTE_PGM_LO 0x00B830 -#define R_00B834_COMPUTE_PGM_HI 0x00B834 -#define S_00B834_DATA(x) (((x) & 0xFF) << 0) -#define G_00B834_DATA(x) (((x) >> 0) & 0xFF) -#define C_00B834_DATA 0xFFFFFF00 -/* CIK */ -#define S_00B834_INST_ATC(x) (((x) & 0x1) << 8) -#define G_00B834_INST_ATC(x) (((x) >> 8) & 0x1) -#define C_00B834_INST_ATC 0xFFFFFEFF -/* */ -#define R_00B838_COMPUTE_TBA_LO 0x00B838 -#define R_00B83C_COMPUTE_TBA_HI 0x00B83C -#define S_00B83C_DATA(x) (((x) & 0xFF) << 0) -#define G_00B83C_DATA(x) (((x) >> 0) & 0xFF) -#define C_00B83C_DATA 0xFFFFFF00 -#define R_00B840_COMPUTE_TMA_LO 0x00B840 -#define R_00B844_COMPUTE_TMA_HI 0x00B844 -#define S_00B844_DATA(x) (((x) & 0xFF) << 0) -#define G_00B844_DATA(x) (((x) >> 0) & 0xFF) -#define C_00B844_DATA 0xFFFFFF00 -#define R_00B848_COMPUTE_PGM_RSRC1 0x00B848 -#define S_00B848_VGPRS(x) (((x) & 0x3F) << 0) -#define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F) -#define C_00B848_VGPRS 0xFFFFFFC0 -#define S_00B848_SGPRS(x) (((x) & 0x0F) << 6) -#define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F) -#define C_00B848_SGPRS 0xFFFFFC3F -#define S_00B848_PRIORITY(x) (((x) & 0x03) << 10) -#define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03) -#define C_00B848_PRIORITY 0xFFFFF3FF -#define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12) -#define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF) -#define C_00B848_FLOAT_MODE 0xFFF00FFF -#define S_00B848_PRIV(x) (((x) & 0x1) << 20) -#define G_00B848_PRIV(x) (((x) >> 20) & 0x1) -#define C_00B848_PRIV 0xFFEFFFFF -#define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21) -#define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1) -#define C_00B848_DX10_CLAMP 0xFFDFFFFF -#define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22) -#define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1) -#define C_00B848_DEBUG_MODE 0xFFBFFFFF -#define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23) -#define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1) -#define C_00B848_IEEE_MODE 0xFF7FFFFF -/* CIK */ -#define S_00B848_BULKY(x) (((x) & 0x1) << 24) -#define G_00B848_BULKY(x) (((x) >> 24) & 0x1) -#define C_00B848_BULKY 0xFEFFFFFF -#define S_00B848_CDBG_USER(x) (((x) & 0x1) << 25) -#define G_00B848_CDBG_USER(x) (((x) >> 25) & 0x1) -#define C_00B848_CDBG_USER 0xFDFFFFFF -/* */ -#define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C -#define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0) -#define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1) -#define C_00B84C_SCRATCH_EN 0xFFFFFFFE -#define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1) -#define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F) -#define C_00B84C_USER_SGPR 0xFFFFFFC1 -#define S_00B84C_TRAP_PRESENT(x) (((x) & 0x1) << 6) -#define G_00B84C_TRAP_PRESENT(x) (((x) >> 6) & 0x1) -#define C_00B84C_TRAP_PRESENT 0xFFFFFFBF -#define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7) -#define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1) -#define C_00B84C_TGID_X_EN 0xFFFFFF7F -#define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8) -#define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1) -#define C_00B84C_TGID_Y_EN 0xFFFFFEFF -#define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9) -#define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1) -#define C_00B84C_TGID_Z_EN 0xFFFFFDFF -#define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10) -#define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1) -#define C_00B84C_TG_SIZE_EN 0xFFFFFBFF -#define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11) -#define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03) -#define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF -/* CIK */ -#define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13) -#define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03) -#define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF -/* */ -#define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15) -#define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF) -#define C_00B84C_LDS_SIZE 0xFF007FFF -#define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24) -#define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F) -#define C_00B84C_EXCP_EN 0x80FFFFFF -#define R_00B850_COMPUTE_VMID 0x00B850 -#define S_00B850_DATA(x) (((x) & 0x0F) << 0) -#define G_00B850_DATA(x) (((x) >> 0) & 0x0F) -#define C_00B850_DATA 0xFFFFFFF0 -#define R_00B854_COMPUTE_RESOURCE_LIMITS 0x00B854 -#define S_00B854_WAVES_PER_SH(x) (((x) & 0x3F) << 0) /* mask is 0x3FF on CIK */ -#define G_00B854_WAVES_PER_SH(x) (((x) >> 0) & 0x3F) /* mask is 0x3FF on CIK */ -#define C_00B854_WAVES_PER_SH 0xFFFFFFC0 /* mask is 0x3FF on CIK */ -#define S_00B854_WAVES_PER_SH_CIK(x) (((x) & 0x3FF) << 0) -#define G_00B854_WAVES_PER_SH_CIK(x) (((x) >> 0) & 0x3FF) -#define C_00B854_WAVES_PER_SH_CIK 0xFFFFFC00 -#define S_00B854_TG_PER_CU(x) (((x) & 0x0F) << 12) -#define G_00B854_TG_PER_CU(x) (((x) >> 12) & 0x0F) -#define C_00B854_TG_PER_CU 0xFFFF0FFF -#define S_00B854_LOCK_THRESHOLD(x) (((x) & 0x3F) << 16) -#define G_00B854_LOCK_THRESHOLD(x) (((x) >> 16) & 0x3F) -#define C_00B854_LOCK_THRESHOLD 0xFFC0FFFF -#define S_00B854_SIMD_DEST_CNTL(x) (((x) & 0x1) << 22) -#define G_00B854_SIMD_DEST_CNTL(x) (((x) >> 22) & 0x1) -#define C_00B854_SIMD_DEST_CNTL 0xFFBFFFFF -/* CIK */ -#define S_00B854_FORCE_SIMD_DIST(x) (((x) & 0x1) << 23) -#define G_00B854_FORCE_SIMD_DIST(x) (((x) >> 23) & 0x1) -#define C_00B854_FORCE_SIMD_DIST 0xFF7FFFFF -#define S_00B854_CU_GROUP_COUNT(x) (((x) & 0x07) << 24) -#define G_00B854_CU_GROUP_COUNT(x) (((x) >> 24) & 0x07) -#define C_00B854_CU_GROUP_COUNT 0xF8FFFFFF -/* */ -#define R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 0x00B858 -#define S_00B858_SH0_CU_EN(x) (((x) & 0xFFFF) << 0) -#define G_00B858_SH0_CU_EN(x) (((x) >> 0) & 0xFFFF) -#define C_00B858_SH0_CU_EN 0xFFFF0000 -#define S_00B858_SH1_CU_EN(x) (((x) & 0xFFFF) << 16) -#define G_00B858_SH1_CU_EN(x) (((x) >> 16) & 0xFFFF) -#define C_00B858_SH1_CU_EN 0x0000FFFF -#define R_00B85C_COMPUTE_STATIC_THREAD_MGMT_SE1 0x00B85C -#define S_00B85C_SH0_CU_EN(x) (((x) & 0xFFFF) << 0) -#define G_00B85C_SH0_CU_EN(x) (((x) >> 0) & 0xFFFF) -#define C_00B85C_SH0_CU_EN 0xFFFF0000 -#define S_00B85C_SH1_CU_EN(x) (((x) & 0xFFFF) << 16) -#define G_00B85C_SH1_CU_EN(x) (((x) >> 16) & 0xFFFF) -#define C_00B85C_SH1_CU_EN 0x0000FFFF -#define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860 -#define S_00B860_WAVES(x) (((x) & 0xFFF) << 0) -#define G_00B860_WAVES(x) (((x) >> 0) & 0xFFF) -#define C_00B860_WAVES 0xFFFFF000 -#define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12) -#define G_00B860_WAVESIZE(x) (((x) >> 12) & 0x1FFF) -#define C_00B860_WAVESIZE 0xFE000FFF -/* CIK */ -#define R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2 0x00B864 -#define S_00B864_SH0_CU_EN(x) (((x) & 0xFFFF) << 0) -#define G_00B864_SH0_CU_EN(x) (((x) >> 0) & 0xFFFF) -#define C_00B864_SH0_CU_EN 0xFFFF0000 -#define S_00B864_SH1_CU_EN(x) (((x) & 0xFFFF) << 16) -#define G_00B864_SH1_CU_EN(x) (((x) >> 16) & 0xFFFF) -#define C_00B864_SH1_CU_EN 0x0000FFFF -#define R_00B868_COMPUTE_STATIC_THREAD_MGMT_SE3 0x00B868 -#define S_00B868_SH0_CU_EN(x) (((x) & 0xFFFF) << 0) -#define G_00B868_SH0_CU_EN(x) (((x) >> 0) & 0xFFFF) -#define C_00B868_SH0_CU_EN 0xFFFF0000 -#define S_00B868_SH1_CU_EN(x) (((x) & 0xFFFF) << 16) -#define G_00B868_SH1_CU_EN(x) (((x) >> 16) & 0xFFFF) -#define C_00B868_SH1_CU_EN 0x0000FFFF -#define R_00B86C_COMPUTE_RESTART_X 0x00B86C -#define R_00B870_COMPUTE_RESTART_Y 0x00B870 -#define R_00B874_COMPUTE_RESTART_Z 0x00B874 -#define R_00B87C_COMPUTE_MISC_RESERVED 0x00B87C -#define S_00B87C_SEND_SEID(x) (((x) & 0x03) << 0) -#define G_00B87C_SEND_SEID(x) (((x) >> 0) & 0x03) -#define C_00B87C_SEND_SEID 0xFFFFFFFC -#define S_00B87C_RESERVED2(x) (((x) & 0x1) << 2) -#define G_00B87C_RESERVED2(x) (((x) >> 2) & 0x1) -#define C_00B87C_RESERVED2 0xFFFFFFFB -#define S_00B87C_RESERVED3(x) (((x) & 0x1) << 3) -#define G_00B87C_RESERVED3(x) (((x) >> 3) & 0x1) -#define C_00B87C_RESERVED3 0xFFFFFFF7 -#define S_00B87C_RESERVED4(x) (((x) & 0x1) << 4) -#define G_00B87C_RESERVED4(x) (((x) >> 4) & 0x1) -#define C_00B87C_RESERVED4 0xFFFFFFEF -/* VI */ -#define S_00B87C_WAVE_ID_BASE(x) (((x) & 0xFFF) << 5) -#define G_00B87C_WAVE_ID_BASE(x) (((x) >> 5) & 0xFFF) -#define C_00B87C_WAVE_ID_BASE 0xFFFE001F -#define R_00B880_COMPUTE_DISPATCH_ID 0x00B880 -#define R_00B884_COMPUTE_THREADGROUP_ID 0x00B884 -#define R_00B888_COMPUTE_RELAUNCH 0x00B888 -#define S_00B888_PAYLOAD(x) (((x) & 0x3FFFFFFF) << 0) -#define G_00B888_PAYLOAD(x) (((x) >> 0) & 0x3FFFFFFF) -#define C_00B888_PAYLOAD 0xC0000000 -#define S_00B888_IS_EVENT(x) (((x) & 0x1) << 30) -#define G_00B888_IS_EVENT(x) (((x) >> 30) & 0x1) -#define C_00B888_IS_EVENT 0xBFFFFFFF -#define S_00B888_IS_STATE(x) (((x) & 0x1) << 31) -#define G_00B888_IS_STATE(x) (((x) >> 31) & 0x1) -#define C_00B888_IS_STATE 0x7FFFFFFF -#define R_00B88C_COMPUTE_WAVE_RESTORE_ADDR_LO 0x00B88C -#define R_00B890_COMPUTE_WAVE_RESTORE_ADDR_HI 0x00B890 -#define S_00B890_ADDR(x) (((x) & 0xFFFF) << 0) -#define G_00B890_ADDR(x) (((x) >> 0) & 0xFFFF) -#define C_00B890_ADDR 0xFFFF0000 -#define R_00B894_COMPUTE_WAVE_RESTORE_CONTROL 0x00B894 -#define S_00B894_ATC(x) (((x) & 0x1) << 0) -#define G_00B894_ATC(x) (((x) >> 0) & 0x1) -#define C_00B894_ATC 0xFFFFFFFE -#define S_00B894_MTYPE(x) (((x) & 0x03) << 1) -#define G_00B894_MTYPE(x) (((x) >> 1) & 0x03) -#define C_00B894_MTYPE 0xFFFFFFF9 -/* */ -/* */ -#define R_00B900_COMPUTE_USER_DATA_0 0x00B900 -#define R_00B904_COMPUTE_USER_DATA_1 0x00B904 -#define R_00B908_COMPUTE_USER_DATA_2 0x00B908 -#define R_00B90C_COMPUTE_USER_DATA_3 0x00B90C -#define R_00B910_COMPUTE_USER_DATA_4 0x00B910 -#define R_00B914_COMPUTE_USER_DATA_5 0x00B914 -#define R_00B918_COMPUTE_USER_DATA_6 0x00B918 -#define R_00B91C_COMPUTE_USER_DATA_7 0x00B91C -#define R_00B920_COMPUTE_USER_DATA_8 0x00B920 -#define R_00B924_COMPUTE_USER_DATA_9 0x00B924 -#define R_00B928_COMPUTE_USER_DATA_10 0x00B928 -#define R_00B92C_COMPUTE_USER_DATA_11 0x00B92C -#define R_00B930_COMPUTE_USER_DATA_12 0x00B930 -#define R_00B934_COMPUTE_USER_DATA_13 0x00B934 -#define R_00B938_COMPUTE_USER_DATA_14 0x00B938 -#define R_00B93C_COMPUTE_USER_DATA_15 0x00B93C -#define R_00B9FC_COMPUTE_NOWHERE 0x00B9FC -#define R_028000_DB_RENDER_CONTROL 0x028000 -#define S_028000_DEPTH_CLEAR_ENABLE(x) (((x) & 0x1) << 0) -#define G_028000_DEPTH_CLEAR_ENABLE(x) (((x) >> 0) & 0x1) -#define C_028000_DEPTH_CLEAR_ENABLE 0xFFFFFFFE -#define S_028000_STENCIL_CLEAR_ENABLE(x) (((x) & 0x1) << 1) -#define G_028000_STENCIL_CLEAR_ENABLE(x) (((x) >> 1) & 0x1) -#define C_028000_STENCIL_CLEAR_ENABLE 0xFFFFFFFD -#define S_028000_DEPTH_COPY(x) (((x) & 0x1) << 2) -#define G_028000_DEPTH_COPY(x) (((x) >> 2) & 0x1) -#define C_028000_DEPTH_COPY 0xFFFFFFFB -#define S_028000_STENCIL_COPY(x) (((x) & 0x1) << 3) -#define G_028000_STENCIL_COPY(x) (((x) >> 3) & 0x1) -#define C_028000_STENCIL_COPY 0xFFFFFFF7 -#define S_028000_RESUMMARIZE_ENABLE(x) (((x) & 0x1) << 4) -#define G_028000_RESUMMARIZE_ENABLE(x) (((x) >> 4) & 0x1) -#define C_028000_RESUMMARIZE_ENABLE 0xFFFFFFEF -#define S_028000_STENCIL_COMPRESS_DISABLE(x) (((x) & 0x1) << 5) -#define G_028000_STENCIL_COMPRESS_DISABLE(x) (((x) >> 5) & 0x1) -#define C_028000_STENCIL_COMPRESS_DISABLE 0xFFFFFFDF -#define S_028000_DEPTH_COMPRESS_DISABLE(x) (((x) & 0x1) << 6) -#define G_028000_DEPTH_COMPRESS_DISABLE(x) (((x) >> 6) & 0x1) -#define C_028000_DEPTH_COMPRESS_DISABLE 0xFFFFFFBF -#define S_028000_COPY_CENTROID(x) (((x) & 0x1) << 7) -#define G_028000_COPY_CENTROID(x) (((x) >> 7) & 0x1) -#define C_028000_COPY_CENTROID 0xFFFFFF7F -#define S_028000_COPY_SAMPLE(x) (((x) & 0x0F) << 8) -#define G_028000_COPY_SAMPLE(x) (((x) >> 8) & 0x0F) -#define C_028000_COPY_SAMPLE 0xFFFFF0FF -/* VI */ -#define S_028000_DECOMPRESS_ENABLE(x) (((x) & 0x1) << 12) -#define G_028000_DECOMPRESS_ENABLE(x) (((x) >> 12) & 0x1) -#define C_028000_DECOMPRESS_ENABLE 0xFFFFEFFF -/* */ -#define R_028004_DB_COUNT_CONTROL 0x028004 -#define S_028004_ZPASS_INCREMENT_DISABLE(x) (((x) & 0x1) << 0) -#define G_028004_ZPASS_INCREMENT_DISABLE(x) (((x) >> 0) & 0x1) -#define C_028004_ZPASS_INCREMENT_DISABLE 0xFFFFFFFE -#define S_028004_PERFECT_ZPASS_COUNTS(x) (((x) & 0x1) << 1) -#define G_028004_PERFECT_ZPASS_COUNTS(x) (((x) >> 1) & 0x1) -#define C_028004_PERFECT_ZPASS_COUNTS 0xFFFFFFFD -#define S_028004_SAMPLE_RATE(x) (((x) & 0x07) << 4) -#define G_028004_SAMPLE_RATE(x) (((x) >> 4) & 0x07) -#define C_028004_SAMPLE_RATE 0xFFFFFF8F -/* CIK */ -#define S_028004_ZPASS_ENABLE(x) (((x) & 0x0F) << 8) -#define G_028004_ZPASS_ENABLE(x) (((x) >> 8) & 0x0F) -#define C_028004_ZPASS_ENABLE 0xFFFFF0FF -#define S_028004_ZFAIL_ENABLE(x) (((x) & 0x0F) << 12) -#define G_028004_ZFAIL_ENABLE(x) (((x) >> 12) & 0x0F) -#define C_028004_ZFAIL_ENABLE 0xFFFF0FFF -#define S_028004_SFAIL_ENABLE(x) (((x) & 0x0F) << 16) -#define G_028004_SFAIL_ENABLE(x) (((x) >> 16) & 0x0F) -#define C_028004_SFAIL_ENABLE 0xFFF0FFFF -#define S_028004_DBFAIL_ENABLE(x) (((x) & 0x0F) << 20) -#define G_028004_DBFAIL_ENABLE(x) (((x) >> 20) & 0x0F) -#define C_028004_DBFAIL_ENABLE 0xFF0FFFFF -#define S_028004_SLICE_EVEN_ENABLE(x) (((x) & 0x0F) << 24) -#define G_028004_SLICE_EVEN_ENABLE(x) (((x) >> 24) & 0x0F) -#define C_028004_SLICE_EVEN_ENABLE 0xF0FFFFFF -#define S_028004_SLICE_ODD_ENABLE(x) (((x) & 0x0F) << 28) -#define G_028004_SLICE_ODD_ENABLE(x) (((x) >> 28) & 0x0F) -#define C_028004_SLICE_ODD_ENABLE 0x0FFFFFFF -/* */ -#define R_028008_DB_DEPTH_VIEW 0x028008 -#define S_028008_SLICE_START(x) (((x) & 0x7FF) << 0) -#define G_028008_SLICE_START(x) (((x) >> 0) & 0x7FF) -#define C_028008_SLICE_START 0xFFFFF800 -#define S_028008_SLICE_MAX(x) (((x) & 0x7FF) << 13) -#define G_028008_SLICE_MAX(x) (((x) >> 13) & 0x7FF) -#define C_028008_SLICE_MAX 0xFF001FFF -#define S_028008_Z_READ_ONLY(x) (((x) & 0x1) << 24) -#define G_028008_Z_READ_ONLY(x) (((x) >> 24) & 0x1) -#define C_028008_Z_READ_ONLY 0xFEFFFFFF -#define S_028008_STENCIL_READ_ONLY(x) (((x) & 0x1) << 25) -#define G_028008_STENCIL_READ_ONLY(x) (((x) >> 25) & 0x1) -#define C_028008_STENCIL_READ_ONLY 0xFDFFFFFF -#define R_02800C_DB_RENDER_OVERRIDE 0x02800C -#define S_02800C_FORCE_HIZ_ENABLE(x) (((x) & 0x03) << 0) -#define G_02800C_FORCE_HIZ_ENABLE(x) (((x) >> 0) & 0x03) -#define C_02800C_FORCE_HIZ_ENABLE 0xFFFFFFFC -#define V_02800C_FORCE_OFF 0x00 -#define V_02800C_FORCE_ENABLE 0x01 -#define V_02800C_FORCE_DISABLE 0x02 -#define V_02800C_FORCE_RESERVED 0x03 -#define S_02800C_FORCE_HIS_ENABLE0(x) (((x) & 0x03) << 2) -#define G_02800C_FORCE_HIS_ENABLE0(x) (((x) >> 2) & 0x03) -#define C_02800C_FORCE_HIS_ENABLE0 0xFFFFFFF3 -#define V_02800C_FORCE_OFF 0x00 -#define V_02800C_FORCE_ENABLE 0x01 -#define V_02800C_FORCE_DISABLE 0x02 -#define V_02800C_FORCE_RESERVED 0x03 -#define S_02800C_FORCE_HIS_ENABLE1(x) (((x) & 0x03) << 4) -#define G_02800C_FORCE_HIS_ENABLE1(x) (((x) >> 4) & 0x03) -#define C_02800C_FORCE_HIS_ENABLE1 0xFFFFFFCF -#define V_02800C_FORCE_OFF 0x00 -#define V_02800C_FORCE_ENABLE 0x01 -#define V_02800C_FORCE_DISABLE 0x02 -#define V_02800C_FORCE_RESERVED 0x03 -#define S_02800C_FORCE_SHADER_Z_ORDER(x) (((x) & 0x1) << 6) -#define G_02800C_FORCE_SHADER_Z_ORDER(x) (((x) >> 6) & 0x1) -#define C_02800C_FORCE_SHADER_Z_ORDER 0xFFFFFFBF -#define S_02800C_FAST_Z_DISABLE(x) (((x) & 0x1) << 7) -#define G_02800C_FAST_Z_DISABLE(x) (((x) >> 7) & 0x1) -#define C_02800C_FAST_Z_DISABLE 0xFFFFFF7F -#define S_02800C_FAST_STENCIL_DISABLE(x) (((x) & 0x1) << 8) -#define G_02800C_FAST_STENCIL_DISABLE(x) (((x) >> 8) & 0x1) -#define C_02800C_FAST_STENCIL_DISABLE 0xFFFFFEFF -#define S_02800C_NOOP_CULL_DISABLE(x) (((x) & 0x1) << 9) -#define G_02800C_NOOP_CULL_DISABLE(x) (((x) >> 9) & 0x1) -#define C_02800C_NOOP_CULL_DISABLE 0xFFFFFDFF -#define S_02800C_FORCE_COLOR_KILL(x) (((x) & 0x1) << 10) -#define G_02800C_FORCE_COLOR_KILL(x) (((x) >> 10) & 0x1) -#define C_02800C_FORCE_COLOR_KILL 0xFFFFFBFF -#define S_02800C_FORCE_Z_READ(x) (((x) & 0x1) << 11) -#define G_02800C_FORCE_Z_READ(x) (((x) >> 11) & 0x1) -#define C_02800C_FORCE_Z_READ 0xFFFFF7FF -#define S_02800C_FORCE_STENCIL_READ(x) (((x) & 0x1) << 12) -#define G_02800C_FORCE_STENCIL_READ(x) (((x) >> 12) & 0x1) -#define C_02800C_FORCE_STENCIL_READ 0xFFFFEFFF -#define S_02800C_FORCE_FULL_Z_RANGE(x) (((x) & 0x03) << 13) -#define G_02800C_FORCE_FULL_Z_RANGE(x) (((x) >> 13) & 0x03) -#define C_02800C_FORCE_FULL_Z_RANGE 0xFFFF9FFF -#define V_02800C_FORCE_OFF 0x00 -#define V_02800C_FORCE_ENABLE 0x01 -#define V_02800C_FORCE_DISABLE 0x02 -#define V_02800C_FORCE_RESERVED 0x03 -#define S_02800C_FORCE_QC_SMASK_CONFLICT(x) (((x) & 0x1) << 15) -#define G_02800C_FORCE_QC_SMASK_CONFLICT(x) (((x) >> 15) & 0x1) -#define C_02800C_FORCE_QC_SMASK_CONFLICT 0xFFFF7FFF -#define S_02800C_DISABLE_VIEWPORT_CLAMP(x) (((x) & 0x1) << 16) -#define G_02800C_DISABLE_VIEWPORT_CLAMP(x) (((x) >> 16) & 0x1) -#define C_02800C_DISABLE_VIEWPORT_CLAMP 0xFFFEFFFF -#define S_02800C_IGNORE_SC_ZRANGE(x) (((x) & 0x1) << 17) -#define G_02800C_IGNORE_SC_ZRANGE(x) (((x) >> 17) & 0x1) -#define C_02800C_IGNORE_SC_ZRANGE 0xFFFDFFFF -#define S_02800C_DISABLE_FULLY_COVERED(x) (((x) & 0x1) << 18) -#define G_02800C_DISABLE_FULLY_COVERED(x) (((x) >> 18) & 0x1) -#define C_02800C_DISABLE_FULLY_COVERED 0xFFFBFFFF -#define S_02800C_FORCE_Z_LIMIT_SUMM(x) (((x) & 0x03) << 19) -#define G_02800C_FORCE_Z_LIMIT_SUMM(x) (((x) >> 19) & 0x03) -#define C_02800C_FORCE_Z_LIMIT_SUMM 0xFFE7FFFF -#define V_02800C_FORCE_SUMM_OFF 0x00 -#define V_02800C_FORCE_SUMM_MINZ 0x01 -#define V_02800C_FORCE_SUMM_MAXZ 0x02 -#define V_02800C_FORCE_SUMM_BOTH 0x03 -#define S_02800C_MAX_TILES_IN_DTT(x) (((x) & 0x1F) << 21) -#define G_02800C_MAX_TILES_IN_DTT(x) (((x) >> 21) & 0x1F) -#define C_02800C_MAX_TILES_IN_DTT 0xFC1FFFFF -#define S_02800C_DISABLE_TILE_RATE_TILES(x) (((x) & 0x1) << 26) -#define G_02800C_DISABLE_TILE_RATE_TILES(x) (((x) >> 26) & 0x1) -#define C_02800C_DISABLE_TILE_RATE_TILES 0xFBFFFFFF -#define S_02800C_FORCE_Z_DIRTY(x) (((x) & 0x1) << 27) -#define G_02800C_FORCE_Z_DIRTY(x) (((x) >> 27) & 0x1) -#define C_02800C_FORCE_Z_DIRTY 0xF7FFFFFF -#define S_02800C_FORCE_STENCIL_DIRTY(x) (((x) & 0x1) << 28) -#define G_02800C_FORCE_STENCIL_DIRTY(x) (((x) >> 28) & 0x1) -#define C_02800C_FORCE_STENCIL_DIRTY 0xEFFFFFFF -#define S_02800C_FORCE_Z_VALID(x) (((x) & 0x1) << 29) -#define G_02800C_FORCE_Z_VALID(x) (((x) >> 29) & 0x1) -#define C_02800C_FORCE_Z_VALID 0xDFFFFFFF -#define S_02800C_FORCE_STENCIL_VALID(x) (((x) & 0x1) << 30) -#define G_02800C_FORCE_STENCIL_VALID(x) (((x) >> 30) & 0x1) -#define C_02800C_FORCE_STENCIL_VALID 0xBFFFFFFF -#define S_02800C_PRESERVE_COMPRESSION(x) (((x) & 0x1) << 31) -#define G_02800C_PRESERVE_COMPRESSION(x) (((x) >> 31) & 0x1) -#define C_02800C_PRESERVE_COMPRESSION 0x7FFFFFFF -#define R_028010_DB_RENDER_OVERRIDE2 0x028010 -#define S_028010_PARTIAL_SQUAD_LAUNCH_CONTROL(x) (((x) & 0x03) << 0) -#define G_028010_PARTIAL_SQUAD_LAUNCH_CONTROL(x) (((x) >> 0) & 0x03) -#define C_028010_PARTIAL_SQUAD_LAUNCH_CONTROL 0xFFFFFFFC -#define V_028010_PSLC_AUTO 0x00 -#define V_028010_PSLC_ON_HANG_ONLY 0x01 -#define V_028010_PSLC_ASAP 0x02 -#define V_028010_PSLC_COUNTDOWN 0x03 -#define S_028010_PARTIAL_SQUAD_LAUNCH_COUNTDOWN(x) (((x) & 0x07) << 2) -#define G_028010_PARTIAL_SQUAD_LAUNCH_COUNTDOWN(x) (((x) >> 2) & 0x07) -#define C_028010_PARTIAL_SQUAD_LAUNCH_COUNTDOWN 0xFFFFFFE3 -#define S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(x) (((x) & 0x1) << 5) -#define G_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(x) (((x) >> 5) & 0x1) -#define C_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION 0xFFFFFFDF -#define S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(x) (((x) & 0x1) << 6) -#define G_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(x) (((x) >> 6) & 0x1) -#define C_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION 0xFFFFFFBF -#define S_028010_DISABLE_COLOR_ON_VALIDATION(x) (((x) & 0x1) << 7) -#define G_028010_DISABLE_COLOR_ON_VALIDATION(x) (((x) >> 7) & 0x1) -#define C_028010_DISABLE_COLOR_ON_VALIDATION 0xFFFFFF7F -#define S_028010_DECOMPRESS_Z_ON_FLUSH(x) (((x) & 0x1) << 8) -#define G_028010_DECOMPRESS_Z_ON_FLUSH(x) (((x) >> 8) & 0x1) -#define C_028010_DECOMPRESS_Z_ON_FLUSH 0xFFFFFEFF -#define S_028010_DISABLE_REG_SNOOP(x) (((x) & 0x1) << 9) -#define G_028010_DISABLE_REG_SNOOP(x) (((x) >> 9) & 0x1) -#define C_028010_DISABLE_REG_SNOOP 0xFFFFFDFF -#define S_028010_DEPTH_BOUNDS_HIER_DEPTH_DISABLE(x) (((x) & 0x1) << 10) -#define G_028010_DEPTH_BOUNDS_HIER_DEPTH_DISABLE(x) (((x) >> 10) & 0x1) -#define C_028010_DEPTH_BOUNDS_HIER_DEPTH_DISABLE 0xFFFFFBFF -/* CIK */ -#define S_028010_SEPARATE_HIZS_FUNC_ENABLE(x) (((x) & 0x1) << 11) -#define G_028010_SEPARATE_HIZS_FUNC_ENABLE(x) (((x) >> 11) & 0x1) -#define C_028010_SEPARATE_HIZS_FUNC_ENABLE 0xFFFFF7FF -#define S_028010_HIZ_ZFUNC(x) (((x) & 0x07) << 12) -#define G_028010_HIZ_ZFUNC(x) (((x) >> 12) & 0x07) -#define C_028010_HIZ_ZFUNC 0xFFFF8FFF -#define S_028010_HIS_SFUNC_FF(x) (((x) & 0x07) << 15) -#define G_028010_HIS_SFUNC_FF(x) (((x) >> 15) & 0x07) -#define C_028010_HIS_SFUNC_FF 0xFFFC7FFF -#define S_028010_HIS_SFUNC_BF(x) (((x) & 0x07) << 18) -#define G_028010_HIS_SFUNC_BF(x) (((x) >> 18) & 0x07) -#define C_028010_HIS_SFUNC_BF 0xFFE3FFFF -#define S_028010_PRESERVE_ZRANGE(x) (((x) & 0x1) << 21) -#define G_028010_PRESERVE_ZRANGE(x) (((x) >> 21) & 0x1) -#define C_028010_PRESERVE_ZRANGE 0xFFDFFFFF -#define S_028010_PRESERVE_SRESULTS(x) (((x) & 0x1) << 22) -#define G_028010_PRESERVE_SRESULTS(x) (((x) >> 22) & 0x1) -#define C_028010_PRESERVE_SRESULTS 0xFFBFFFFF -#define S_028010_DISABLE_FAST_PASS(x) (((x) & 0x1) << 23) -#define G_028010_DISABLE_FAST_PASS(x) (((x) >> 23) & 0x1) -#define C_028010_DISABLE_FAST_PASS 0xFF7FFFFF -/* */ -#define R_028014_DB_HTILE_DATA_BASE 0x028014 -#define R_028020_DB_DEPTH_BOUNDS_MIN 0x028020 -#define R_028024_DB_DEPTH_BOUNDS_MAX 0x028024 -#define R_028028_DB_STENCIL_CLEAR 0x028028 -#define S_028028_CLEAR(x) (((x) & 0xFF) << 0) -#define G_028028_CLEAR(x) (((x) >> 0) & 0xFF) -#define C_028028_CLEAR 0xFFFFFF00 -#define R_02802C_DB_DEPTH_CLEAR 0x02802C -#define R_028030_PA_SC_SCREEN_SCISSOR_TL 0x028030 -#define S_028030_TL_X(x) (((x) & 0xFFFF) << 0) -#define G_028030_TL_X(x) (((x) >> 0) & 0xFFFF) -#define C_028030_TL_X 0xFFFF0000 -#define S_028030_TL_Y(x) (((x) & 0xFFFF) << 16) -#define G_028030_TL_Y(x) (((x) >> 16) & 0xFFFF) -#define C_028030_TL_Y 0x0000FFFF -#define R_028034_PA_SC_SCREEN_SCISSOR_BR 0x028034 -#define S_028034_BR_X(x) (((x) & 0xFFFF) << 0) -#define G_028034_BR_X(x) (((x) >> 0) & 0xFFFF) -#define C_028034_BR_X 0xFFFF0000 -#define S_028034_BR_Y(x) (((x) & 0xFFFF) << 16) -#define G_028034_BR_Y(x) (((x) >> 16) & 0xFFFF) -#define C_028034_BR_Y 0x0000FFFF -#define R_02803C_DB_DEPTH_INFO 0x02803C -#define S_02803C_ADDR5_SWIZZLE_MASK(x) (((x) & 0x0F) << 0) -#define G_02803C_ADDR5_SWIZZLE_MASK(x) (((x) >> 0) & 0x0F) -#define C_02803C_ADDR5_SWIZZLE_MASK 0xFFFFFFF0 -/* CIK */ -#define S_02803C_ARRAY_MODE(x) (((x) & 0x0F) << 4) -#define G_02803C_ARRAY_MODE(x) (((x) >> 4) & 0x0F) -#define C_02803C_ARRAY_MODE 0xFFFFFF0F -#define V_02803C_ARRAY_LINEAR_GENERAL 0x00 -#define V_02803C_ARRAY_LINEAR_ALIGNED 0x01 -#define V_02803C_ARRAY_1D_TILED_THIN1 0x02 -#define V_02803C_ARRAY_2D_TILED_THIN1 0x04 -#define V_02803C_ARRAY_PRT_TILED_THIN1 0x05 -#define V_02803C_ARRAY_PRT_2D_TILED_THIN1 0x06 -#define S_02803C_PIPE_CONFIG(x) (((x) & 0x1F) << 8) -#define G_02803C_PIPE_CONFIG(x) (((x) >> 8) & 0x1F) -#define C_02803C_PIPE_CONFIG 0xFFFFE0FF -#define V_02803C_ADDR_SURF_P2 0x00 -#define V_02803C_X_ADDR_SURF_P4_8X16 0x04 -#define V_02803C_X_ADDR_SURF_P4_16X16 0x05 -#define V_02803C_X_ADDR_SURF_P4_16X32 0x06 -#define V_02803C_X_ADDR_SURF_P4_32X32 0x07 -#define V_02803C_X_ADDR_SURF_P8_16X16_8X16 0x08 -#define V_02803C_X_ADDR_SURF_P8_16X32_8X16 0x09 -#define V_02803C_X_ADDR_SURF_P8_32X32_8X16 0x0A -#define V_02803C_X_ADDR_SURF_P8_16X32_16X16 0x0B -#define V_02803C_X_ADDR_SURF_P8_32X32_16X16 0x0C -#define V_02803C_X_ADDR_SURF_P8_32X32_16X32 0x0D -#define V_02803C_X_ADDR_SURF_P8_32X64_32X32 0x0E -#define V_02803C_X_ADDR_SURF_P16_32X32_8X16 0x10 -#define V_02803C_X_ADDR_SURF_P16_32X32_16X16 0x11 -#define S_02803C_BANK_WIDTH(x) (((x) & 0x03) << 13) -#define G_02803C_BANK_WIDTH(x) (((x) >> 13) & 0x03) -#define C_02803C_BANK_WIDTH 0xFFFF9FFF -#define V_02803C_ADDR_SURF_BANK_WIDTH_1 0x00 -#define V_02803C_ADDR_SURF_BANK_WIDTH_2 0x01 -#define V_02803C_ADDR_SURF_BANK_WIDTH_4 0x02 -#define V_02803C_ADDR_SURF_BANK_WIDTH_8 0x03 -#define S_02803C_BANK_HEIGHT(x) (((x) & 0x03) << 15) -#define G_02803C_BANK_HEIGHT(x) (((x) >> 15) & 0x03) -#define C_02803C_BANK_HEIGHT 0xFFFE7FFF -#define V_02803C_ADDR_SURF_BANK_HEIGHT_1 0x00 -#define V_02803C_ADDR_SURF_BANK_HEIGHT_2 0x01 -#define V_02803C_ADDR_SURF_BANK_HEIGHT_4 0x02 -#define V_02803C_ADDR_SURF_BANK_HEIGHT_8 0x03 -#define S_02803C_MACRO_TILE_ASPECT(x) (((x) & 0x03) << 17) -#define G_02803C_MACRO_TILE_ASPECT(x) (((x) >> 17) & 0x03) -#define C_02803C_MACRO_TILE_ASPECT 0xFFF9FFFF -#define V_02803C_ADDR_SURF_MACRO_ASPECT_1 0x00 -#define V_02803C_ADDR_SURF_MACRO_ASPECT_2 0x01 -#define V_02803C_ADDR_SURF_MACRO_ASPECT_4 0x02 -#define V_02803C_ADDR_SURF_MACRO_ASPECT_8 0x03 -#define S_02803C_NUM_BANKS(x) (((x) & 0x03) << 19) -#define G_02803C_NUM_BANKS(x) (((x) >> 19) & 0x03) -#define C_02803C_NUM_BANKS 0xFFE7FFFF -#define V_02803C_ADDR_SURF_2_BANK 0x00 -#define V_02803C_ADDR_SURF_4_BANK 0x01 -#define V_02803C_ADDR_SURF_8_BANK 0x02 -#define V_02803C_ADDR_SURF_16_BANK 0x03 -/* */ -#define R_028040_DB_Z_INFO 0x028040 -#define S_028040_FORMAT(x) (((x) & 0x03) << 0) -#define G_028040_FORMAT(x) (((x) >> 0) & 0x03) -#define C_028040_FORMAT 0xFFFFFFFC -#define V_028040_Z_INVALID 0x00 -#define V_028040_Z_16 0x01 -#define V_028040_Z_24 0x02 /* deprecated */ -#define V_028040_Z_32_FLOAT 0x03 -#define S_028040_NUM_SAMPLES(x) (((x) & 0x03) << 2) -#define G_028040_NUM_SAMPLES(x) (((x) >> 2) & 0x03) -#define C_028040_NUM_SAMPLES 0xFFFFFFF3 -/* CIK */ -#define S_028040_TILE_SPLIT(x) (((x) & 0x07) << 13) -#define G_028040_TILE_SPLIT(x) (((x) >> 13) & 0x07) -#define C_028040_TILE_SPLIT 0xFFFF1FFF -#define V_028040_ADDR_SURF_TILE_SPLIT_64B 0x00 -#define V_028040_ADDR_SURF_TILE_SPLIT_128B 0x01 -#define V_028040_ADDR_SURF_TILE_SPLIT_256B 0x02 -#define V_028040_ADDR_SURF_TILE_SPLIT_512B 0x03 -#define V_028040_ADDR_SURF_TILE_SPLIT_1KB 0x04 -#define V_028040_ADDR_SURF_TILE_SPLIT_2KB 0x05 -#define V_028040_ADDR_SURF_TILE_SPLIT_4KB 0x06 -/* */ -#define S_028040_TILE_MODE_INDEX(x) (((x) & 0x07) << 20) /* not on CIK */ -#define G_028040_TILE_MODE_INDEX(x) (((x) >> 20) & 0x07) /* not on CIK */ -#define C_028040_TILE_MODE_INDEX 0xFF8FFFFF /* not on CIK */ -/* VI */ -#define S_028040_DECOMPRESS_ON_N_ZPLANES(x) (((x) & 0x0F) << 23) -#define G_028040_DECOMPRESS_ON_N_ZPLANES(x) (((x) >> 23) & 0x0F) -#define C_028040_DECOMPRESS_ON_N_ZPLANES 0xF87FFFFF -/* */ -#define S_028040_ALLOW_EXPCLEAR(x) (((x) & 0x1) << 27) -#define G_028040_ALLOW_EXPCLEAR(x) (((x) >> 27) & 0x1) -#define C_028040_ALLOW_EXPCLEAR 0xF7FFFFFF -#define S_028040_READ_SIZE(x) (((x) & 0x1) << 28) -#define G_028040_READ_SIZE(x) (((x) >> 28) & 0x1) -#define C_028040_READ_SIZE 0xEFFFFFFF -#define S_028040_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 29) -#define G_028040_TILE_SURFACE_ENABLE(x) (((x) >> 29) & 0x1) -#define C_028040_TILE_SURFACE_ENABLE 0xDFFFFFFF -/* VI */ -#define S_028040_CLEAR_DISALLOWED(x) (((x) & 0x1) << 30) -#define G_028040_CLEAR_DISALLOWED(x) (((x) >> 30) & 0x1) -#define C_028040_CLEAR_DISALLOWED 0xBFFFFFFF -/* */ -#define S_028040_ZRANGE_PRECISION(x) (((x) & 0x1) << 31) -#define G_028040_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1) -#define C_028040_ZRANGE_PRECISION 0x7FFFFFFF -#define R_028044_DB_STENCIL_INFO 0x028044 -#define S_028044_FORMAT(x) (((x) & 0x1) << 0) -#define G_028044_FORMAT(x) (((x) >> 0) & 0x1) -#define C_028044_FORMAT 0xFFFFFFFE -#define V_028044_STENCIL_INVALID 0x00 -#define V_028044_STENCIL_8 0x01 -/* CIK */ -#define S_028044_TILE_SPLIT(x) (((x) & 0x07) << 13) -#define G_028044_TILE_SPLIT(x) (((x) >> 13) & 0x07) -#define C_028044_TILE_SPLIT 0xFFFF1FFF -#define V_028044_ADDR_SURF_TILE_SPLIT_64B 0x00 -#define V_028044_ADDR_SURF_TILE_SPLIT_128B 0x01 -#define V_028044_ADDR_SURF_TILE_SPLIT_256B 0x02 -#define V_028044_ADDR_SURF_TILE_SPLIT_512B 0x03 -#define V_028044_ADDR_SURF_TILE_SPLIT_1KB 0x04 -#define V_028044_ADDR_SURF_TILE_SPLIT_2KB 0x05 -#define V_028044_ADDR_SURF_TILE_SPLIT_4KB 0x06 -/* */ -#define S_028044_TILE_MODE_INDEX(x) (((x) & 0x07) << 20) /* not on CIK */ -#define G_028044_TILE_MODE_INDEX(x) (((x) >> 20) & 0x07) /* not on CIK */ -#define C_028044_TILE_MODE_INDEX 0xFF8FFFFF /* not on CIK */ -#define S_028044_ALLOW_EXPCLEAR(x) (((x) & 0x1) << 27) -#define G_028044_ALLOW_EXPCLEAR(x) (((x) >> 27) & 0x1) -#define C_028044_ALLOW_EXPCLEAR 0xF7FFFFFF -#define S_028044_TILE_STENCIL_DISABLE(x) (((x) & 0x1) << 29) -#define G_028044_TILE_STENCIL_DISABLE(x) (((x) >> 29) & 0x1) -#define C_028044_TILE_STENCIL_DISABLE 0xDFFFFFFF -/* VI */ -#define S_028044_CLEAR_DISALLOWED(x) (((x) & 0x1) << 30) -#define G_028044_CLEAR_DISALLOWED(x) (((x) >> 30) & 0x1) -#define C_028044_CLEAR_DISALLOWED 0xBFFFFFFF -/* */ -#define R_028048_DB_Z_READ_BASE 0x028048 -#define R_02804C_DB_STENCIL_READ_BASE 0x02804C -#define R_028050_DB_Z_WRITE_BASE 0x028050 -#define R_028054_DB_STENCIL_WRITE_BASE 0x028054 -#define R_028058_DB_DEPTH_SIZE 0x028058 -#define S_028058_PITCH_TILE_MAX(x) (((x) & 0x7FF) << 0) -#define G_028058_PITCH_TILE_MAX(x) (((x) >> 0) & 0x7FF) -#define C_028058_PITCH_TILE_MAX 0xFFFFF800 -#define S_028058_HEIGHT_TILE_MAX(x) (((x) & 0x7FF) << 11) -#define G_028058_HEIGHT_TILE_MAX(x) (((x) >> 11) & 0x7FF) -#define C_028058_HEIGHT_TILE_MAX 0xFFC007FF -#define R_02805C_DB_DEPTH_SLICE 0x02805C -#define S_02805C_SLICE_TILE_MAX(x) (((x) & 0x3FFFFF) << 0) -#define G_02805C_SLICE_TILE_MAX(x) (((x) >> 0) & 0x3FFFFF) -#define C_02805C_SLICE_TILE_MAX 0xFFC00000 -#define R_028080_TA_BC_BASE_ADDR 0x028080 -/* CIK */ -#define R_028084_TA_BC_BASE_ADDR_HI 0x028084 -#define S_028084_ADDRESS(x) (((x) & 0xFF) << 0) -#define G_028084_ADDRESS(x) (((x) >> 0) & 0xFF) -#define C_028084_ADDRESS 0xFFFFFF00 -#define R_0281E8_COHER_DEST_BASE_HI_0 0x0281E8 -#define R_0281EC_COHER_DEST_BASE_HI_1 0x0281EC -#define R_0281F0_COHER_DEST_BASE_HI_2 0x0281F0 -#define R_0281F4_COHER_DEST_BASE_HI_3 0x0281F4 -/* */ -#define R_0281F8_COHER_DEST_BASE_2 0x0281F8 -#define R_0281FC_COHER_DEST_BASE_3 0x0281FC -#define R_028200_PA_SC_WINDOW_OFFSET 0x028200 -#define S_028200_WINDOW_X_OFFSET(x) (((x) & 0xFFFF) << 0) -#define G_028200_WINDOW_X_OFFSET(x) (((x) >> 0) & 0xFFFF) -#define C_028200_WINDOW_X_OFFSET 0xFFFF0000 -#define S_028200_WINDOW_Y_OFFSET(x) (((x) & 0xFFFF) << 16) -#define G_028200_WINDOW_Y_OFFSET(x) (((x) >> 16) & 0xFFFF) -#define C_028200_WINDOW_Y_OFFSET 0x0000FFFF -#define R_028204_PA_SC_WINDOW_SCISSOR_TL 0x028204 -#define S_028204_TL_X(x) (((x) & 0x7FFF) << 0) -#define G_028204_TL_X(x) (((x) >> 0) & 0x7FFF) -#define C_028204_TL_X 0xFFFF8000 -#define S_028204_TL_Y(x) (((x) & 0x7FFF) << 16) -#define G_028204_TL_Y(x) (((x) >> 16) & 0x7FFF) -#define C_028204_TL_Y 0x8000FFFF -#define S_028204_WINDOW_OFFSET_DISABLE(x) (((x) & 0x1) << 31) -#define G_028204_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1) -#define C_028204_WINDOW_OFFSET_DISABLE 0x7FFFFFFF -#define R_028208_PA_SC_WINDOW_SCISSOR_BR 0x028208 -#define S_028208_BR_X(x) (((x) & 0x7FFF) << 0) -#define G_028208_BR_X(x) (((x) >> 0) & 0x7FFF) -#define C_028208_BR_X 0xFFFF8000 -#define S_028208_BR_Y(x) (((x) & 0x7FFF) << 16) -#define G_028208_BR_Y(x) (((x) >> 16) & 0x7FFF) -#define C_028208_BR_Y 0x8000FFFF -#define R_02820C_PA_SC_CLIPRECT_RULE 0x02820C -#define S_02820C_CLIP_RULE(x) (((x) & 0xFFFF) << 0) -#define G_02820C_CLIP_RULE(x) (((x) >> 0) & 0xFFFF) -#define C_02820C_CLIP_RULE 0xFFFF0000 -#define R_028210_PA_SC_CLIPRECT_0_TL 0x028210 -#define S_028210_TL_X(x) (((x) & 0x7FFF) << 0) -#define G_028210_TL_X(x) (((x) >> 0) & 0x7FFF) -#define C_028210_TL_X 0xFFFF8000 -#define S_028210_TL_Y(x) (((x) & 0x7FFF) << 16) -#define G_028210_TL_Y(x) (((x) >> 16) & 0x7FFF) -#define C_028210_TL_Y 0x8000FFFF -#define R_028214_PA_SC_CLIPRECT_0_BR 0x028214 -#define S_028214_BR_X(x) (((x) & 0x7FFF) << 0) -#define G_028214_BR_X(x) (((x) >> 0) & 0x7FFF) -#define C_028214_BR_X 0xFFFF8000 -#define S_028214_BR_Y(x) (((x) & 0x7FFF) << 16) -#define G_028214_BR_Y(x) (((x) >> 16) & 0x7FFF) -#define C_028214_BR_Y 0x8000FFFF -#define R_028218_PA_SC_CLIPRECT_1_TL 0x028218 -#define R_02821C_PA_SC_CLIPRECT_1_BR 0x02821C -#define R_028220_PA_SC_CLIPRECT_2_TL 0x028220 -#define R_028224_PA_SC_CLIPRECT_2_BR 0x028224 -#define R_028228_PA_SC_CLIPRECT_3_TL 0x028228 -#define R_02822C_PA_SC_CLIPRECT_3_BR 0x02822C -#define R_028230_PA_SC_EDGERULE 0x028230 -#define S_028230_ER_TRI(x) (((x) & 0x0F) << 0) -#define G_028230_ER_TRI(x) (((x) >> 0) & 0x0F) -#define C_028230_ER_TRI 0xFFFFFFF0 -#define S_028230_ER_POINT(x) (((x) & 0x0F) << 4) -#define G_028230_ER_POINT(x) (((x) >> 4) & 0x0F) -#define C_028230_ER_POINT 0xFFFFFF0F -#define S_028230_ER_RECT(x) (((x) & 0x0F) << 8) -#define G_028230_ER_RECT(x) (((x) >> 8) & 0x0F) -#define C_028230_ER_RECT 0xFFFFF0FF -#define S_028230_ER_LINE_LR(x) (((x) & 0x3F) << 12) -#define G_028230_ER_LINE_LR(x) (((x) >> 12) & 0x3F) -#define C_028230_ER_LINE_LR 0xFFFC0FFF -#define S_028230_ER_LINE_RL(x) (((x) & 0x3F) << 18) -#define G_028230_ER_LINE_RL(x) (((x) >> 18) & 0x3F) -#define C_028230_ER_LINE_RL 0xFF03FFFF -#define S_028230_ER_LINE_TB(x) (((x) & 0x0F) << 24) -#define G_028230_ER_LINE_TB(x) (((x) >> 24) & 0x0F) -#define C_028230_ER_LINE_TB 0xF0FFFFFF -#define S_028230_ER_LINE_BT(x) (((x) & 0x0F) << 28) -#define G_028230_ER_LINE_BT(x) (((x) >> 28) & 0x0F) -#define C_028230_ER_LINE_BT 0x0FFFFFFF -#define R_028234_PA_SU_HARDWARE_SCREEN_OFFSET 0x028234 -#define S_028234_HW_SCREEN_OFFSET_X(x) (((x) & 0x1FF) << 0) -#define G_028234_HW_SCREEN_OFFSET_X(x) (((x) >> 0) & 0x1FF) -#define C_028234_HW_SCREEN_OFFSET_X 0xFFFFFE00 -#define S_028234_HW_SCREEN_OFFSET_Y(x) (((x) & 0x1FF) << 16) -#define G_028234_HW_SCREEN_OFFSET_Y(x) (((x) >> 16) & 0x1FF) -#define C_028234_HW_SCREEN_OFFSET_Y 0xFE00FFFF -#define R_028238_CB_TARGET_MASK 0x028238 -#define S_028238_TARGET0_ENABLE(x) (((x) & 0x0F) << 0) -#define G_028238_TARGET0_ENABLE(x) (((x) >> 0) & 0x0F) -#define C_028238_TARGET0_ENABLE 0xFFFFFFF0 -#define S_028238_TARGET1_ENABLE(x) (((x) & 0x0F) << 4) -#define G_028238_TARGET1_ENABLE(x) (((x) >> 4) & 0x0F) -#define C_028238_TARGET1_ENABLE 0xFFFFFF0F -#define S_028238_TARGET2_ENABLE(x) (((x) & 0x0F) << 8) -#define G_028238_TARGET2_ENABLE(x) (((x) >> 8) & 0x0F) -#define C_028238_TARGET2_ENABLE 0xFFFFF0FF -#define S_028238_TARGET3_ENABLE(x) (((x) & 0x0F) << 12) -#define G_028238_TARGET3_ENABLE(x) (((x) >> 12) & 0x0F) -#define C_028238_TARGET3_ENABLE 0xFFFF0FFF -#define S_028238_TARGET4_ENABLE(x) (((x) & 0x0F) << 16) -#define G_028238_TARGET4_ENABLE(x) (((x) >> 16) & 0x0F) -#define C_028238_TARGET4_ENABLE 0xFFF0FFFF -#define S_028238_TARGET5_ENABLE(x) (((x) & 0x0F) << 20) -#define G_028238_TARGET5_ENABLE(x) (((x) >> 20) & 0x0F) -#define C_028238_TARGET5_ENABLE 0xFF0FFFFF -#define S_028238_TARGET6_ENABLE(x) (((x) & 0x0F) << 24) -#define G_028238_TARGET6_ENABLE(x) (((x) >> 24) & 0x0F) -#define C_028238_TARGET6_ENABLE 0xF0FFFFFF -#define S_028238_TARGET7_ENABLE(x) (((x) & 0x0F) << 28) -#define G_028238_TARGET7_ENABLE(x) (((x) >> 28) & 0x0F) -#define C_028238_TARGET7_ENABLE 0x0FFFFFFF -#define R_02823C_CB_SHADER_MASK 0x02823C -#define S_02823C_OUTPUT0_ENABLE(x) (((x) & 0x0F) << 0) -#define G_02823C_OUTPUT0_ENABLE(x) (((x) >> 0) & 0x0F) -#define C_02823C_OUTPUT0_ENABLE 0xFFFFFFF0 -#define S_02823C_OUTPUT1_ENABLE(x) (((x) & 0x0F) << 4) -#define G_02823C_OUTPUT1_ENABLE(x) (((x) >> 4) & 0x0F) -#define C_02823C_OUTPUT1_ENABLE 0xFFFFFF0F -#define S_02823C_OUTPUT2_ENABLE(x) (((x) & 0x0F) << 8) -#define G_02823C_OUTPUT2_ENABLE(x) (((x) >> 8) & 0x0F) -#define C_02823C_OUTPUT2_ENABLE 0xFFFFF0FF -#define S_02823C_OUTPUT3_ENABLE(x) (((x) & 0x0F) << 12) -#define G_02823C_OUTPUT3_ENABLE(x) (((x) >> 12) & 0x0F) -#define C_02823C_OUTPUT3_ENABLE 0xFFFF0FFF -#define S_02823C_OUTPUT4_ENABLE(x) (((x) & 0x0F) << 16) -#define G_02823C_OUTPUT4_ENABLE(x) (((x) >> 16) & 0x0F) -#define C_02823C_OUTPUT4_ENABLE 0xFFF0FFFF -#define S_02823C_OUTPUT5_ENABLE(x) (((x) & 0x0F) << 20) -#define G_02823C_OUTPUT5_ENABLE(x) (((x) >> 20) & 0x0F) -#define C_02823C_OUTPUT5_ENABLE 0xFF0FFFFF -#define S_02823C_OUTPUT6_ENABLE(x) (((x) & 0x0F) << 24) -#define G_02823C_OUTPUT6_ENABLE(x) (((x) >> 24) & 0x0F) -#define C_02823C_OUTPUT6_ENABLE 0xF0FFFFFF -#define S_02823C_OUTPUT7_ENABLE(x) (((x) & 0x0F) << 28) -#define G_02823C_OUTPUT7_ENABLE(x) (((x) >> 28) & 0x0F) -#define C_02823C_OUTPUT7_ENABLE 0x0FFFFFFF -#define R_028240_PA_SC_GENERIC_SCISSOR_TL 0x028240 -#define S_028240_TL_X(x) (((x) & 0x7FFF) << 0) -#define G_028240_TL_X(x) (((x) >> 0) & 0x7FFF) -#define C_028240_TL_X 0xFFFF8000 -#define S_028240_TL_Y(x) (((x) & 0x7FFF) << 16) -#define G_028240_TL_Y(x) (((x) >> 16) & 0x7FFF) -#define C_028240_TL_Y 0x8000FFFF -#define S_028240_WINDOW_OFFSET_DISABLE(x) (((x) & 0x1) << 31) -#define G_028240_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1) -#define C_028240_WINDOW_OFFSET_DISABLE 0x7FFFFFFF -#define R_028244_PA_SC_GENERIC_SCISSOR_BR 0x028244 -#define S_028244_BR_X(x) (((x) & 0x7FFF) << 0) -#define G_028244_BR_X(x) (((x) >> 0) & 0x7FFF) -#define C_028244_BR_X 0xFFFF8000 -#define S_028244_BR_Y(x) (((x) & 0x7FFF) << 16) -#define G_028244_BR_Y(x) (((x) >> 16) & 0x7FFF) -#define C_028244_BR_Y 0x8000FFFF -#define R_028248_COHER_DEST_BASE_0 0x028248 -#define R_02824C_COHER_DEST_BASE_1 0x02824C -#define R_028250_PA_SC_VPORT_SCISSOR_0_TL 0x028250 -#define S_028250_TL_X(x) (((x) & 0x7FFF) << 0) -#define G_028250_TL_X(x) (((x) >> 0) & 0x7FFF) -#define C_028250_TL_X 0xFFFF8000 -#define S_028250_TL_Y(x) (((x) & 0x7FFF) << 16) -#define G_028250_TL_Y(x) (((x) >> 16) & 0x7FFF) -#define C_028250_TL_Y 0x8000FFFF -#define S_028250_WINDOW_OFFSET_DISABLE(x) (((x) & 0x1) << 31) -#define G_028250_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1) -#define C_028250_WINDOW_OFFSET_DISABLE 0x7FFFFFFF -#define R_028254_PA_SC_VPORT_SCISSOR_0_BR 0x028254 -#define S_028254_BR_X(x) (((x) & 0x7FFF) << 0) -#define G_028254_BR_X(x) (((x) >> 0) & 0x7FFF) -#define C_028254_BR_X 0xFFFF8000 -#define S_028254_BR_Y(x) (((x) & 0x7FFF) << 16) -#define G_028254_BR_Y(x) (((x) >> 16) & 0x7FFF) -#define C_028254_BR_Y 0x8000FFFF -#define R_028258_PA_SC_VPORT_SCISSOR_1_TL 0x028258 -#define R_02825C_PA_SC_VPORT_SCISSOR_1_BR 0x02825C -#define R_028260_PA_SC_VPORT_SCISSOR_2_TL 0x028260 -#define R_028264_PA_SC_VPORT_SCISSOR_2_BR 0x028264 -#define R_028268_PA_SC_VPORT_SCISSOR_3_TL 0x028268 -#define R_02826C_PA_SC_VPORT_SCISSOR_3_BR 0x02826C -#define R_028270_PA_SC_VPORT_SCISSOR_4_TL 0x028270 -#define R_028274_PA_SC_VPORT_SCISSOR_4_BR 0x028274 -#define R_028278_PA_SC_VPORT_SCISSOR_5_TL 0x028278 -#define R_02827C_PA_SC_VPORT_SCISSOR_5_BR 0x02827C -#define R_028280_PA_SC_VPORT_SCISSOR_6_TL 0x028280 -#define R_028284_PA_SC_VPORT_SCISSOR_6_BR 0x028284 -#define R_028288_PA_SC_VPORT_SCISSOR_7_TL 0x028288 -#define R_02828C_PA_SC_VPORT_SCISSOR_7_BR 0x02828C -#define R_028290_PA_SC_VPORT_SCISSOR_8_TL 0x028290 -#define R_028294_PA_SC_VPORT_SCISSOR_8_BR 0x028294 -#define R_028298_PA_SC_VPORT_SCISSOR_9_TL 0x028298 -#define R_02829C_PA_SC_VPORT_SCISSOR_9_BR 0x02829C -#define R_0282A0_PA_SC_VPORT_SCISSOR_10_TL 0x0282A0 -#define R_0282A4_PA_SC_VPORT_SCISSOR_10_BR 0x0282A4 -#define R_0282A8_PA_SC_VPORT_SCISSOR_11_TL 0x0282A8 -#define R_0282AC_PA_SC_VPORT_SCISSOR_11_BR 0x0282AC -#define R_0282B0_PA_SC_VPORT_SCISSOR_12_TL 0x0282B0 -#define R_0282B4_PA_SC_VPORT_SCISSOR_12_BR 0x0282B4 -#define R_0282B8_PA_SC_VPORT_SCISSOR_13_TL 0x0282B8 -#define R_0282BC_PA_SC_VPORT_SCISSOR_13_BR 0x0282BC -#define R_0282C0_PA_SC_VPORT_SCISSOR_14_TL 0x0282C0 -#define R_0282C4_PA_SC_VPORT_SCISSOR_14_BR 0x0282C4 -#define R_0282C8_PA_SC_VPORT_SCISSOR_15_TL 0x0282C8 -#define R_0282CC_PA_SC_VPORT_SCISSOR_15_BR 0x0282CC -#define R_0282D0_PA_SC_VPORT_ZMIN_0 0x0282D0 -#define R_0282D4_PA_SC_VPORT_ZMAX_0 0x0282D4 -#define R_0282D8_PA_SC_VPORT_ZMIN_1 0x0282D8 -#define R_0282DC_PA_SC_VPORT_ZMAX_1 0x0282DC -#define R_0282E0_PA_SC_VPORT_ZMIN_2 0x0282E0 -#define R_0282E4_PA_SC_VPORT_ZMAX_2 0x0282E4 -#define R_0282E8_PA_SC_VPORT_ZMIN_3 0x0282E8 -#define R_0282EC_PA_SC_VPORT_ZMAX_3 0x0282EC -#define R_0282F0_PA_SC_VPORT_ZMIN_4 0x0282F0 -#define R_0282F4_PA_SC_VPORT_ZMAX_4 0x0282F4 -#define R_0282F8_PA_SC_VPORT_ZMIN_5 0x0282F8 -#define R_0282FC_PA_SC_VPORT_ZMAX_5 0x0282FC -#define R_028300_PA_SC_VPORT_ZMIN_6 0x028300 -#define R_028304_PA_SC_VPORT_ZMAX_6 0x028304 -#define R_028308_PA_SC_VPORT_ZMIN_7 0x028308 -#define R_02830C_PA_SC_VPORT_ZMAX_7 0x02830C -#define R_028310_PA_SC_VPORT_ZMIN_8 0x028310 -#define R_028314_PA_SC_VPORT_ZMAX_8 0x028314 -#define R_028318_PA_SC_VPORT_ZMIN_9 0x028318 -#define R_02831C_PA_SC_VPORT_ZMAX_9 0x02831C -#define R_028320_PA_SC_VPORT_ZMIN_10 0x028320 -#define R_028324_PA_SC_VPORT_ZMAX_10 0x028324 -#define R_028328_PA_SC_VPORT_ZMIN_11 0x028328 -#define R_02832C_PA_SC_VPORT_ZMAX_11 0x02832C -#define R_028330_PA_SC_VPORT_ZMIN_12 0x028330 -#define R_028334_PA_SC_VPORT_ZMAX_12 0x028334 -#define R_028338_PA_SC_VPORT_ZMIN_13 0x028338 -#define R_02833C_PA_SC_VPORT_ZMAX_13 0x02833C -#define R_028340_PA_SC_VPORT_ZMIN_14 0x028340 -#define R_028344_PA_SC_VPORT_ZMAX_14 0x028344 -#define R_028348_PA_SC_VPORT_ZMIN_15 0x028348 -#define R_02834C_PA_SC_VPORT_ZMAX_15 0x02834C -#define R_028350_PA_SC_RASTER_CONFIG 0x028350 -#define S_028350_RB_MAP_PKR0(x) (((x) & 0x03) << 0) -#define G_028350_RB_MAP_PKR0(x) (((x) >> 0) & 0x03) -#define C_028350_RB_MAP_PKR0 0xFFFFFFFC -#define V_028350_RASTER_CONFIG_RB_MAP_0 0x00 -#define V_028350_RASTER_CONFIG_RB_MAP_1 0x01 -#define V_028350_RASTER_CONFIG_RB_MAP_2 0x02 -#define V_028350_RASTER_CONFIG_RB_MAP_3 0x03 -#define S_028350_RB_MAP_PKR1(x) (((x) & 0x03) << 2) -#define G_028350_RB_MAP_PKR1(x) (((x) >> 2) & 0x03) -#define C_028350_RB_MAP_PKR1 0xFFFFFFF3 -#define V_028350_RASTER_CONFIG_RB_MAP_0 0x00 -#define V_028350_RASTER_CONFIG_RB_MAP_1 0x01 -#define V_028350_RASTER_CONFIG_RB_MAP_2 0x02 -#define V_028350_RASTER_CONFIG_RB_MAP_3 0x03 -#define S_028350_RB_XSEL2(x) (((x) & 0x03) << 4) -#define G_028350_RB_XSEL2(x) (((x) >> 4) & 0x03) -#define C_028350_RB_XSEL2 0xFFFFFFCF -#define V_028350_RASTER_CONFIG_RB_XSEL2_0 0x00 -#define V_028350_RASTER_CONFIG_RB_XSEL2_1 0x01 -#define V_028350_RASTER_CONFIG_RB_XSEL2_2 0x02 -#define V_028350_RASTER_CONFIG_RB_XSEL2_3 0x03 -#define S_028350_RB_XSEL(x) (((x) & 0x1) << 6) -#define G_028350_RB_XSEL(x) (((x) >> 6) & 0x1) -#define C_028350_RB_XSEL 0xFFFFFFBF -#define S_028350_RB_YSEL(x) (((x) & 0x1) << 7) -#define G_028350_RB_YSEL(x) (((x) >> 7) & 0x1) -#define C_028350_RB_YSEL 0xFFFFFF7F -#define S_028350_PKR_MAP(x) (((x) & 0x03) << 8) -#define G_028350_PKR_MAP(x) (((x) >> 8) & 0x03) -#define C_028350_PKR_MAP 0xFFFFFCFF -#define V_028350_RASTER_CONFIG_PKR_MAP_0 0x00 -#define V_028350_RASTER_CONFIG_PKR_MAP_1 0x01 -#define V_028350_RASTER_CONFIG_PKR_MAP_2 0x02 -#define V_028350_RASTER_CONFIG_PKR_MAP_3 0x03 -#define S_028350_PKR_XSEL(x) (((x) & 0x03) << 10) -#define G_028350_PKR_XSEL(x) (((x) >> 10) & 0x03) -#define C_028350_PKR_XSEL 0xFFFFF3FF -#define V_028350_RASTER_CONFIG_PKR_XSEL_0 0x00 -#define V_028350_RASTER_CONFIG_PKR_XSEL_1 0x01 -#define V_028350_RASTER_CONFIG_PKR_XSEL_2 0x02 -#define V_028350_RASTER_CONFIG_PKR_XSEL_3 0x03 -#define S_028350_PKR_YSEL(x) (((x) & 0x03) << 12) -#define G_028350_PKR_YSEL(x) (((x) >> 12) & 0x03) -#define C_028350_PKR_YSEL 0xFFFFCFFF -#define V_028350_RASTER_CONFIG_PKR_YSEL_0 0x00 -#define V_028350_RASTER_CONFIG_PKR_YSEL_1 0x01 -#define V_028350_RASTER_CONFIG_PKR_YSEL_2 0x02 -#define V_028350_RASTER_CONFIG_PKR_YSEL_3 0x03 -#define S_028350_PKR_XSEL2(x) (((x) & 0x03) << 14) -#define G_028350_PKR_XSEL2(x) (((x) >> 14) & 0x03) -#define C_028350_PKR_XSEL2 0xFFFF3FFF -#define V_028350_RASTER_CONFIG_PKR_XSEL2_0 0x00 -#define V_028350_RASTER_CONFIG_PKR_XSEL2_1 0x01 -#define V_028350_RASTER_CONFIG_PKR_XSEL2_2 0x02 -#define V_028350_RASTER_CONFIG_PKR_XSEL2_3 0x03 -#define S_028350_SC_MAP(x) (((x) & 0x03) << 16) -#define G_028350_SC_MAP(x) (((x) >> 16) & 0x03) -#define C_028350_SC_MAP 0xFFFCFFFF -#define V_028350_RASTER_CONFIG_SC_MAP_0 0x00 -#define V_028350_RASTER_CONFIG_SC_MAP_1 0x01 -#define V_028350_RASTER_CONFIG_SC_MAP_2 0x02 -#define V_028350_RASTER_CONFIG_SC_MAP_3 0x03 -#define S_028350_SC_XSEL(x) (((x) & 0x03) << 18) -#define G_028350_SC_XSEL(x) (((x) >> 18) & 0x03) -#define C_028350_SC_XSEL 0xFFF3FFFF -#define V_028350_RASTER_CONFIG_SC_XSEL_8_WIDE_TILE 0x00 -#define V_028350_RASTER_CONFIG_SC_XSEL_16_WIDE_TILE 0x01 -#define V_028350_RASTER_CONFIG_SC_XSEL_32_WIDE_TILE 0x02 -#define V_028350_RASTER_CONFIG_SC_XSEL_64_WIDE_TILE 0x03 -#define S_028350_SC_YSEL(x) (((x) & 0x03) << 20) -#define G_028350_SC_YSEL(x) (((x) >> 20) & 0x03) -#define C_028350_SC_YSEL 0xFFCFFFFF -#define V_028350_RASTER_CONFIG_SC_YSEL_8_WIDE_TILE 0x00 -#define V_028350_RASTER_CONFIG_SC_YSEL_16_WIDE_TILE 0x01 -#define V_028350_RASTER_CONFIG_SC_YSEL_32_WIDE_TILE 0x02 -#define V_028350_RASTER_CONFIG_SC_YSEL_64_WIDE_TILE 0x03 -#define S_028350_SE_MAP(x) (((x) & 0x03) << 24) -#define G_028350_SE_MAP(x) (((x) >> 24) & 0x03) -#define C_028350_SE_MAP 0xFCFFFFFF -#define V_028350_RASTER_CONFIG_SE_MAP_0 0x00 -#define V_028350_RASTER_CONFIG_SE_MAP_1 0x01 -#define V_028350_RASTER_CONFIG_SE_MAP_2 0x02 -#define V_028350_RASTER_CONFIG_SE_MAP_3 0x03 -#define S_028350_SE_XSEL(x) (((x) & 0x03) << 26) -#define G_028350_SE_XSEL(x) (((x) >> 26) & 0x03) -#define C_028350_SE_XSEL 0xF3FFFFFF -#define V_028350_RASTER_CONFIG_SE_XSEL_8_WIDE_TILE 0x00 -#define V_028350_RASTER_CONFIG_SE_XSEL_16_WIDE_TILE 0x01 -#define V_028350_RASTER_CONFIG_SE_XSEL_32_WIDE_TILE 0x02 -#define V_028350_RASTER_CONFIG_SE_XSEL_64_WIDE_TILE 0x03 -#define S_028350_SE_YSEL(x) (((x) & 0x03) << 28) -#define G_028350_SE_YSEL(x) (((x) >> 28) & 0x03) -#define C_028350_SE_YSEL 0xCFFFFFFF -#define V_028350_RASTER_CONFIG_SE_YSEL_8_WIDE_TILE 0x00 -#define V_028350_RASTER_CONFIG_SE_YSEL_16_WIDE_TILE 0x01 -#define V_028350_RASTER_CONFIG_SE_YSEL_32_WIDE_TILE 0x02 -#define V_028350_RASTER_CONFIG_SE_YSEL_64_WIDE_TILE 0x03 -/* CIK */ -#define R_028354_PA_SC_RASTER_CONFIG_1 0x028354 -#define S_028354_SE_PAIR_MAP(x) (((x) & 0x03) << 0) -#define G_028354_SE_PAIR_MAP(x) (((x) >> 0) & 0x03) -#define C_028354_SE_PAIR_MAP 0xFFFFFFFC -#define V_028354_RASTER_CONFIG_SE_PAIR_MAP_0 0x00 -#define V_028354_RASTER_CONFIG_SE_PAIR_MAP_1 0x01 -#define V_028354_RASTER_CONFIG_SE_PAIR_MAP_2 0x02 -#define V_028354_RASTER_CONFIG_SE_PAIR_MAP_3 0x03 -#define S_028354_SE_PAIR_XSEL(x) (((x) & 0x03) << 2) -#define G_028354_SE_PAIR_XSEL(x) (((x) >> 2) & 0x03) -#define C_028354_SE_PAIR_XSEL 0xFFFFFFF3 -#define V_028354_RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE 0x00 -#define V_028354_RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE 0x01 -#define V_028354_RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE 0x02 -#define V_028354_RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE 0x03 -#define S_028354_SE_PAIR_YSEL(x) (((x) & 0x03) << 4) -#define G_028354_SE_PAIR_YSEL(x) (((x) >> 4) & 0x03) -#define C_028354_SE_PAIR_YSEL 0xFFFFFFCF -#define V_028354_RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE 0x00 -#define V_028354_RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE 0x01 -#define V_028354_RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE 0x02 -#define V_028354_RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE 0x03 -#define R_028358_PA_SC_SCREEN_EXTENT_CONTROL 0x028358 -#define S_028358_SLICE_EVEN_ENABLE(x) (((x) & 0x03) << 0) -#define G_028358_SLICE_EVEN_ENABLE(x) (((x) >> 0) & 0x03) -#define C_028358_SLICE_EVEN_ENABLE 0xFFFFFFFC -#define S_028358_SLICE_ODD_ENABLE(x) (((x) & 0x03) << 2) -#define G_028358_SLICE_ODD_ENABLE(x) (((x) >> 2) & 0x03) -#define C_028358_SLICE_ODD_ENABLE 0xFFFFFFF3 -/* */ -#define R_028400_VGT_MAX_VTX_INDX 0x028400 -#define R_028404_VGT_MIN_VTX_INDX 0x028404 -#define R_028408_VGT_INDX_OFFSET 0x028408 -#define R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX 0x02840C -#define R_028414_CB_BLEND_RED 0x028414 -#define R_028418_CB_BLEND_GREEN 0x028418 -#define R_02841C_CB_BLEND_BLUE 0x02841C -#define R_028420_CB_BLEND_ALPHA 0x028420 -/* VI */ -#define R_028424_CB_DCC_CONTROL 0x028424 -#define S_028424_OVERWRITE_COMBINER_DISABLE(x) (((x) & 0x1) << 0) -#define G_028424_OVERWRITE_COMBINER_DISABLE(x) (((x) >> 0) & 0x1) -#define C_028424_OVERWRITE_COMBINER_DISABLE 0xFFFFFFFE -#define S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(x) (((x) & 0x1) << 1) -#define G_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(x) (((x) >> 1) & 0x1) -#define C_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE 0xFFFFFFFD -#define S_028424_OVERWRITE_COMBINER_WATERMARK(x) (((x) & 0x1F) << 2) -#define G_028424_OVERWRITE_COMBINER_WATERMARK(x) (((x) >> 2) & 0x1F) -#define C_028424_OVERWRITE_COMBINER_WATERMARK 0xFFFFFF83 -/* */ -#define R_02842C_DB_STENCIL_CONTROL 0x02842C -#define S_02842C_STENCILFAIL(x) (((x) & 0x0F) << 0) -#define G_02842C_STENCILFAIL(x) (((x) >> 0) & 0x0F) -#define C_02842C_STENCILFAIL 0xFFFFFFF0 -#define V_02842C_STENCIL_KEEP 0x00 -#define V_02842C_STENCIL_ZERO 0x01 -#define V_02842C_STENCIL_ONES 0x02 -#define V_02842C_STENCIL_REPLACE_TEST 0x03 -#define V_02842C_STENCIL_REPLACE_OP 0x04 -#define V_02842C_STENCIL_ADD_CLAMP 0x05 -#define V_02842C_STENCIL_SUB_CLAMP 0x06 -#define V_02842C_STENCIL_INVERT 0x07 -#define V_02842C_STENCIL_ADD_WRAP 0x08 -#define V_02842C_STENCIL_SUB_WRAP 0x09 -#define V_02842C_STENCIL_AND 0x0A -#define V_02842C_STENCIL_OR 0x0B -#define V_02842C_STENCIL_XOR 0x0C -#define V_02842C_STENCIL_NAND 0x0D -#define V_02842C_STENCIL_NOR 0x0E -#define V_02842C_STENCIL_XNOR 0x0F -#define S_02842C_STENCILZPASS(x) (((x) & 0x0F) << 4) -#define G_02842C_STENCILZPASS(x) (((x) >> 4) & 0x0F) -#define C_02842C_STENCILZPASS 0xFFFFFF0F -#define V_02842C_STENCIL_KEEP 0x00 -#define V_02842C_STENCIL_ZERO 0x01 -#define V_02842C_STENCIL_ONES 0x02 -#define V_02842C_STENCIL_REPLACE_TEST 0x03 -#define V_02842C_STENCIL_REPLACE_OP 0x04 -#define V_02842C_STENCIL_ADD_CLAMP 0x05 -#define V_02842C_STENCIL_SUB_CLAMP 0x06 -#define V_02842C_STENCIL_INVERT 0x07 -#define V_02842C_STENCIL_ADD_WRAP 0x08 -#define V_02842C_STENCIL_SUB_WRAP 0x09 -#define V_02842C_STENCIL_AND 0x0A -#define V_02842C_STENCIL_OR 0x0B -#define V_02842C_STENCIL_XOR 0x0C -#define V_02842C_STENCIL_NAND 0x0D -#define V_02842C_STENCIL_NOR 0x0E -#define V_02842C_STENCIL_XNOR 0x0F -#define S_02842C_STENCILZFAIL(x) (((x) & 0x0F) << 8) -#define G_02842C_STENCILZFAIL(x) (((x) >> 8) & 0x0F) -#define C_02842C_STENCILZFAIL 0xFFFFF0FF -#define V_02842C_STENCIL_KEEP 0x00 -#define V_02842C_STENCIL_ZERO 0x01 -#define V_02842C_STENCIL_ONES 0x02 -#define V_02842C_STENCIL_REPLACE_TEST 0x03 -#define V_02842C_STENCIL_REPLACE_OP 0x04 -#define V_02842C_STENCIL_ADD_CLAMP 0x05 -#define V_02842C_STENCIL_SUB_CLAMP 0x06 -#define V_02842C_STENCIL_INVERT 0x07 -#define V_02842C_STENCIL_ADD_WRAP 0x08 -#define V_02842C_STENCIL_SUB_WRAP 0x09 -#define V_02842C_STENCIL_AND 0x0A -#define V_02842C_STENCIL_OR 0x0B -#define V_02842C_STENCIL_XOR 0x0C -#define V_02842C_STENCIL_NAND 0x0D -#define V_02842C_STENCIL_NOR 0x0E -#define V_02842C_STENCIL_XNOR 0x0F -#define S_02842C_STENCILFAIL_BF(x) (((x) & 0x0F) << 12) -#define G_02842C_STENCILFAIL_BF(x) (((x) >> 12) & 0x0F) -#define C_02842C_STENCILFAIL_BF 0xFFFF0FFF -#define V_02842C_STENCIL_KEEP 0x00 -#define V_02842C_STENCIL_ZERO 0x01 -#define V_02842C_STENCIL_ONES 0x02 -#define V_02842C_STENCIL_REPLACE_TEST 0x03 -#define V_02842C_STENCIL_REPLACE_OP 0x04 -#define V_02842C_STENCIL_ADD_CLAMP 0x05 -#define V_02842C_STENCIL_SUB_CLAMP 0x06 -#define V_02842C_STENCIL_INVERT 0x07 -#define V_02842C_STENCIL_ADD_WRAP 0x08 -#define V_02842C_STENCIL_SUB_WRAP 0x09 -#define V_02842C_STENCIL_AND 0x0A -#define V_02842C_STENCIL_OR 0x0B -#define V_02842C_STENCIL_XOR 0x0C -#define V_02842C_STENCIL_NAND 0x0D -#define V_02842C_STENCIL_NOR 0x0E -#define V_02842C_STENCIL_XNOR 0x0F -#define S_02842C_STENCILZPASS_BF(x) (((x) & 0x0F) << 16) -#define G_02842C_STENCILZPASS_BF(x) (((x) >> 16) & 0x0F) -#define C_02842C_STENCILZPASS_BF 0xFFF0FFFF -#define V_02842C_STENCIL_KEEP 0x00 -#define V_02842C_STENCIL_ZERO 0x01 -#define V_02842C_STENCIL_ONES 0x02 -#define V_02842C_STENCIL_REPLACE_TEST 0x03 -#define V_02842C_STENCIL_REPLACE_OP 0x04 -#define V_02842C_STENCIL_ADD_CLAMP 0x05 -#define V_02842C_STENCIL_SUB_CLAMP 0x06 -#define V_02842C_STENCIL_INVERT 0x07 -#define V_02842C_STENCIL_ADD_WRAP 0x08 -#define V_02842C_STENCIL_SUB_WRAP 0x09 -#define V_02842C_STENCIL_AND 0x0A -#define V_02842C_STENCIL_OR 0x0B -#define V_02842C_STENCIL_XOR 0x0C -#define V_02842C_STENCIL_NAND 0x0D -#define V_02842C_STENCIL_NOR 0x0E -#define V_02842C_STENCIL_XNOR 0x0F -#define S_02842C_STENCILZFAIL_BF(x) (((x) & 0x0F) << 20) -#define G_02842C_STENCILZFAIL_BF(x) (((x) >> 20) & 0x0F) -#define C_02842C_STENCILZFAIL_BF 0xFF0FFFFF -#define V_02842C_STENCIL_KEEP 0x00 -#define V_02842C_STENCIL_ZERO 0x01 -#define V_02842C_STENCIL_ONES 0x02 -#define V_02842C_STENCIL_REPLACE_TEST 0x03 -#define V_02842C_STENCIL_REPLACE_OP 0x04 -#define V_02842C_STENCIL_ADD_CLAMP 0x05 -#define V_02842C_STENCIL_SUB_CLAMP 0x06 -#define V_02842C_STENCIL_INVERT 0x07 -#define V_02842C_STENCIL_ADD_WRAP 0x08 -#define V_02842C_STENCIL_SUB_WRAP 0x09 -#define V_02842C_STENCIL_AND 0x0A -#define V_02842C_STENCIL_OR 0x0B -#define V_02842C_STENCIL_XOR 0x0C -#define V_02842C_STENCIL_NAND 0x0D -#define V_02842C_STENCIL_NOR 0x0E -#define V_02842C_STENCIL_XNOR 0x0F -#define R_028430_DB_STENCILREFMASK 0x028430 -#define S_028430_STENCILTESTVAL(x) (((x) & 0xFF) << 0) -#define G_028430_STENCILTESTVAL(x) (((x) >> 0) & 0xFF) -#define C_028430_STENCILTESTVAL 0xFFFFFF00 -#define S_028430_STENCILMASK(x) (((x) & 0xFF) << 8) -#define G_028430_STENCILMASK(x) (((x) >> 8) & 0xFF) -#define C_028430_STENCILMASK 0xFFFF00FF -#define S_028430_STENCILWRITEMASK(x) (((x) & 0xFF) << 16) -#define G_028430_STENCILWRITEMASK(x) (((x) >> 16) & 0xFF) -#define C_028430_STENCILWRITEMASK 0xFF00FFFF -#define S_028430_STENCILOPVAL(x) (((x) & 0xFF) << 24) -#define G_028430_STENCILOPVAL(x) (((x) >> 24) & 0xFF) -#define C_028430_STENCILOPVAL 0x00FFFFFF -#define R_028434_DB_STENCILREFMASK_BF 0x028434 -#define S_028434_STENCILTESTVAL_BF(x) (((x) & 0xFF) << 0) -#define G_028434_STENCILTESTVAL_BF(x) (((x) >> 0) & 0xFF) -#define C_028434_STENCILTESTVAL_BF 0xFFFFFF00 -#define S_028434_STENCILMASK_BF(x) (((x) & 0xFF) << 8) -#define G_028434_STENCILMASK_BF(x) (((x) >> 8) & 0xFF) -#define C_028434_STENCILMASK_BF 0xFFFF00FF -#define S_028434_STENCILWRITEMASK_BF(x) (((x) & 0xFF) << 16) -#define G_028434_STENCILWRITEMASK_BF(x) (((x) >> 16) & 0xFF) -#define C_028434_STENCILWRITEMASK_BF 0xFF00FFFF -#define S_028434_STENCILOPVAL_BF(x) (((x) & 0xFF) << 24) -#define G_028434_STENCILOPVAL_BF(x) (((x) >> 24) & 0xFF) -#define C_028434_STENCILOPVAL_BF 0x00FFFFFF -#define R_02843C_PA_CL_VPORT_XSCALE 0x02843C -#define R_028440_PA_CL_VPORT_XOFFSET 0x028440 -#define R_028444_PA_CL_VPORT_YSCALE 0x028444 -#define R_028448_PA_CL_VPORT_YOFFSET 0x028448 -#define R_02844C_PA_CL_VPORT_ZSCALE 0x02844C -#define R_028450_PA_CL_VPORT_ZOFFSET 0x028450 -#define R_028454_PA_CL_VPORT_XSCALE_1 0x028454 -#define R_028458_PA_CL_VPORT_XOFFSET_1 0x028458 -#define R_02845C_PA_CL_VPORT_YSCALE_1 0x02845C -#define R_028460_PA_CL_VPORT_YOFFSET_1 0x028460 -#define R_028464_PA_CL_VPORT_ZSCALE_1 0x028464 -#define R_028468_PA_CL_VPORT_ZOFFSET_1 0x028468 -#define R_02846C_PA_CL_VPORT_XSCALE_2 0x02846C -#define R_028470_PA_CL_VPORT_XOFFSET_2 0x028470 -#define R_028474_PA_CL_VPORT_YSCALE_2 0x028474 -#define R_028478_PA_CL_VPORT_YOFFSET_2 0x028478 -#define R_02847C_PA_CL_VPORT_ZSCALE_2 0x02847C -#define R_028480_PA_CL_VPORT_ZOFFSET_2 0x028480 -#define R_028484_PA_CL_VPORT_XSCALE_3 0x028484 -#define R_028488_PA_CL_VPORT_XOFFSET_3 0x028488 -#define R_02848C_PA_CL_VPORT_YSCALE_3 0x02848C -#define R_028490_PA_CL_VPORT_YOFFSET_3 0x028490 -#define R_028494_PA_CL_VPORT_ZSCALE_3 0x028494 -#define R_028498_PA_CL_VPORT_ZOFFSET_3 0x028498 -#define R_02849C_PA_CL_VPORT_XSCALE_4 0x02849C -#define R_0284A0_PA_CL_VPORT_XOFFSET_4 0x0284A0 -#define R_0284A4_PA_CL_VPORT_YSCALE_4 0x0284A4 -#define R_0284A8_PA_CL_VPORT_YOFFSET_4 0x0284A8 -#define R_0284AC_PA_CL_VPORT_ZSCALE_4 0x0284AC -#define R_0284B0_PA_CL_VPORT_ZOFFSET_4 0x0284B0 -#define R_0284B4_PA_CL_VPORT_XSCALE_5 0x0284B4 -#define R_0284B8_PA_CL_VPORT_XOFFSET_5 0x0284B8 -#define R_0284BC_PA_CL_VPORT_YSCALE_5 0x0284BC -#define R_0284C0_PA_CL_VPORT_YOFFSET_5 0x0284C0 -#define R_0284C4_PA_CL_VPORT_ZSCALE_5 0x0284C4 -#define R_0284C8_PA_CL_VPORT_ZOFFSET_5 0x0284C8 -#define R_0284CC_PA_CL_VPORT_XSCALE_6 0x0284CC -#define R_0284D0_PA_CL_VPORT_XOFFSET_6 0x0284D0 -#define R_0284D4_PA_CL_VPORT_YSCALE_6 0x0284D4 -#define R_0284D8_PA_CL_VPORT_YOFFSET_6 0x0284D8 -#define R_0284DC_PA_CL_VPORT_ZSCALE_6 0x0284DC -#define R_0284E0_PA_CL_VPORT_ZOFFSET_6 0x0284E0 -#define R_0284E4_PA_CL_VPORT_XSCALE_7 0x0284E4 -#define R_0284E8_PA_CL_VPORT_XOFFSET_7 0x0284E8 -#define R_0284EC_PA_CL_VPORT_YSCALE_7 0x0284EC -#define R_0284F0_PA_CL_VPORT_YOFFSET_7 0x0284F0 -#define R_0284F4_PA_CL_VPORT_ZSCALE_7 0x0284F4 -#define R_0284F8_PA_CL_VPORT_ZOFFSET_7 0x0284F8 -#define R_0284FC_PA_CL_VPORT_XSCALE_8 0x0284FC -#define R_028500_PA_CL_VPORT_XOFFSET_8 0x028500 -#define R_028504_PA_CL_VPORT_YSCALE_8 0x028504 -#define R_028508_PA_CL_VPORT_YOFFSET_8 0x028508 -#define R_02850C_PA_CL_VPORT_ZSCALE_8 0x02850C -#define R_028510_PA_CL_VPORT_ZOFFSET_8 0x028510 -#define R_028514_PA_CL_VPORT_XSCALE_9 0x028514 -#define R_028518_PA_CL_VPORT_XOFFSET_9 0x028518 -#define R_02851C_PA_CL_VPORT_YSCALE_9 0x02851C -#define R_028520_PA_CL_VPORT_YOFFSET_9 0x028520 -#define R_028524_PA_CL_VPORT_ZSCALE_9 0x028524 -#define R_028528_PA_CL_VPORT_ZOFFSET_9 0x028528 -#define R_02852C_PA_CL_VPORT_XSCALE_10 0x02852C -#define R_028530_PA_CL_VPORT_XOFFSET_10 0x028530 -#define R_028534_PA_CL_VPORT_YSCALE_10 0x028534 -#define R_028538_PA_CL_VPORT_YOFFSET_10 0x028538 -#define R_02853C_PA_CL_VPORT_ZSCALE_10 0x02853C -#define R_028540_PA_CL_VPORT_ZOFFSET_10 0x028540 -#define R_028544_PA_CL_VPORT_XSCALE_11 0x028544 -#define R_028548_PA_CL_VPORT_XOFFSET_11 0x028548 -#define R_02854C_PA_CL_VPORT_YSCALE_11 0x02854C -#define R_028550_PA_CL_VPORT_YOFFSET_11 0x028550 -#define R_028554_PA_CL_VPORT_ZSCALE_11 0x028554 -#define R_028558_PA_CL_VPORT_ZOFFSET_11 0x028558 -#define R_02855C_PA_CL_VPORT_XSCALE_12 0x02855C -#define R_028560_PA_CL_VPORT_XOFFSET_12 0x028560 -#define R_028564_PA_CL_VPORT_YSCALE_12 0x028564 -#define R_028568_PA_CL_VPORT_YOFFSET_12 0x028568 -#define R_02856C_PA_CL_VPORT_ZSCALE_12 0x02856C -#define R_028570_PA_CL_VPORT_ZOFFSET_12 0x028570 -#define R_028574_PA_CL_VPORT_XSCALE_13 0x028574 -#define R_028578_PA_CL_VPORT_XOFFSET_13 0x028578 -#define R_02857C_PA_CL_VPORT_YSCALE_13 0x02857C -#define R_028580_PA_CL_VPORT_YOFFSET_13 0x028580 -#define R_028584_PA_CL_VPORT_ZSCALE_13 0x028584 -#define R_028588_PA_CL_VPORT_ZOFFSET_13 0x028588 -#define R_02858C_PA_CL_VPORT_XSCALE_14 0x02858C -#define R_028590_PA_CL_VPORT_XOFFSET_14 0x028590 -#define R_028594_PA_CL_VPORT_YSCALE_14 0x028594 -#define R_028598_PA_CL_VPORT_YOFFSET_14 0x028598 -#define R_02859C_PA_CL_VPORT_ZSCALE_14 0x02859C -#define R_0285A0_PA_CL_VPORT_ZOFFSET_14 0x0285A0 -#define R_0285A4_PA_CL_VPORT_XSCALE_15 0x0285A4 -#define R_0285A8_PA_CL_VPORT_XOFFSET_15 0x0285A8 -#define R_0285AC_PA_CL_VPORT_YSCALE_15 0x0285AC -#define R_0285B0_PA_CL_VPORT_YOFFSET_15 0x0285B0 -#define R_0285B4_PA_CL_VPORT_ZSCALE_15 0x0285B4 -#define R_0285B8_PA_CL_VPORT_ZOFFSET_15 0x0285B8 -#define R_0285BC_PA_CL_UCP_0_X 0x0285BC -#define R_0285C0_PA_CL_UCP_0_Y 0x0285C0 -#define R_0285C4_PA_CL_UCP_0_Z 0x0285C4 -#define R_0285C8_PA_CL_UCP_0_W 0x0285C8 -#define R_0285CC_PA_CL_UCP_1_X 0x0285CC -#define R_0285D0_PA_CL_UCP_1_Y 0x0285D0 -#define R_0285D4_PA_CL_UCP_1_Z 0x0285D4 -#define R_0285D8_PA_CL_UCP_1_W 0x0285D8 -#define R_0285DC_PA_CL_UCP_2_X 0x0285DC -#define R_0285E0_PA_CL_UCP_2_Y 0x0285E0 -#define R_0285E4_PA_CL_UCP_2_Z 0x0285E4 -#define R_0285E8_PA_CL_UCP_2_W 0x0285E8 -#define R_0285EC_PA_CL_UCP_3_X 0x0285EC -#define R_0285F0_PA_CL_UCP_3_Y 0x0285F0 -#define R_0285F4_PA_CL_UCP_3_Z 0x0285F4 -#define R_0285F8_PA_CL_UCP_3_W 0x0285F8 -#define R_0285FC_PA_CL_UCP_4_X 0x0285FC -#define R_028600_PA_CL_UCP_4_Y 0x028600 -#define R_028604_PA_CL_UCP_4_Z 0x028604 -#define R_028608_PA_CL_UCP_4_W 0x028608 -#define R_02860C_PA_CL_UCP_5_X 0x02860C -#define R_028610_PA_CL_UCP_5_Y 0x028610 -#define R_028614_PA_CL_UCP_5_Z 0x028614 -#define R_028618_PA_CL_UCP_5_W 0x028618 -#define R_028644_SPI_PS_INPUT_CNTL_0 0x028644 -#define S_028644_OFFSET(x) (((x) & 0x3F) << 0) -#define G_028644_OFFSET(x) (((x) >> 0) & 0x3F) -#define C_028644_OFFSET 0xFFFFFFC0 -#define S_028644_DEFAULT_VAL(x) (((x) & 0x03) << 8) -#define G_028644_DEFAULT_VAL(x) (((x) >> 8) & 0x03) -#define C_028644_DEFAULT_VAL 0xFFFFFCFF -#define V_028644_X_0_0F 0x00 -#define S_028644_FLAT_SHADE(x) (((x) & 0x1) << 10) -#define G_028644_FLAT_SHADE(x) (((x) >> 10) & 0x1) -#define C_028644_FLAT_SHADE 0xFFFFFBFF -#define S_028644_CYL_WRAP(x) (((x) & 0x0F) << 13) -#define G_028644_CYL_WRAP(x) (((x) >> 13) & 0x0F) -#define C_028644_CYL_WRAP 0xFFFE1FFF -#define S_028644_PT_SPRITE_TEX(x) (((x) & 0x1) << 17) -#define G_028644_PT_SPRITE_TEX(x) (((x) >> 17) & 0x1) -#define C_028644_PT_SPRITE_TEX 0xFFFDFFFF -/* CIK */ -#define S_028644_DUP(x) (((x) & 0x1) << 18) -#define G_028644_DUP(x) (((x) >> 18) & 0x1) -#define C_028644_DUP 0xFFFBFFFF -/* */ -/* VI */ -#define S_028644_FP16_INTERP_MODE(x) (((x) & 0x1) << 19) -#define G_028644_FP16_INTERP_MODE(x) (((x) >> 19) & 0x1) -#define C_028644_FP16_INTERP_MODE 0xFFF7FFFF -#define S_028644_USE_DEFAULT_ATTR1(x) (((x) & 0x1) << 20) -#define G_028644_USE_DEFAULT_ATTR1(x) (((x) >> 20) & 0x1) -#define C_028644_USE_DEFAULT_ATTR1 0xFFEFFFFF -#define S_028644_DEFAULT_VAL_ATTR1(x) (((x) & 0x03) << 21) -#define G_028644_DEFAULT_VAL_ATTR1(x) (((x) >> 21) & 0x03) -#define C_028644_DEFAULT_VAL_ATTR1 0xFF9FFFFF -#define S_028644_PT_SPRITE_TEX_ATTR1(x) (((x) & 0x1) << 23) -#define G_028644_PT_SPRITE_TEX_ATTR1(x) (((x) >> 23) & 0x1) -#define C_028644_PT_SPRITE_TEX_ATTR1 0xFF7FFFFF -#define S_028644_ATTR0_VALID(x) (((x) & 0x1) << 24) -#define G_028644_ATTR0_VALID(x) (((x) >> 24) & 0x1) -#define C_028644_ATTR0_VALID 0xFEFFFFFF -#define S_028644_ATTR1_VALID(x) (((x) & 0x1) << 25) -#define G_028644_ATTR1_VALID(x) (((x) >> 25) & 0x1) -#define C_028644_ATTR1_VALID 0xFDFFFFFF -/* */ -#define R_028648_SPI_PS_INPUT_CNTL_1 0x028648 -#define R_02864C_SPI_PS_INPUT_CNTL_2 0x02864C -#define R_028650_SPI_PS_INPUT_CNTL_3 0x028650 -#define R_028654_SPI_PS_INPUT_CNTL_4 0x028654 -#define R_028658_SPI_PS_INPUT_CNTL_5 0x028658 -#define R_02865C_SPI_PS_INPUT_CNTL_6 0x02865C -#define R_028660_SPI_PS_INPUT_CNTL_7 0x028660 -#define R_028664_SPI_PS_INPUT_CNTL_8 0x028664 -#define R_028668_SPI_PS_INPUT_CNTL_9 0x028668 -#define R_02866C_SPI_PS_INPUT_CNTL_10 0x02866C -#define R_028670_SPI_PS_INPUT_CNTL_11 0x028670 -#define R_028674_SPI_PS_INPUT_CNTL_12 0x028674 -#define R_028678_SPI_PS_INPUT_CNTL_13 0x028678 -#define R_02867C_SPI_PS_INPUT_CNTL_14 0x02867C -#define R_028680_SPI_PS_INPUT_CNTL_15 0x028680 -#define R_028684_SPI_PS_INPUT_CNTL_16 0x028684 -#define R_028688_SPI_PS_INPUT_CNTL_17 0x028688 -#define R_02868C_SPI_PS_INPUT_CNTL_18 0x02868C -#define R_028690_SPI_PS_INPUT_CNTL_19 0x028690 -#define R_028694_SPI_PS_INPUT_CNTL_20 0x028694 -#define R_028698_SPI_PS_INPUT_CNTL_21 0x028698 -#define R_02869C_SPI_PS_INPUT_CNTL_22 0x02869C -#define R_0286A0_SPI_PS_INPUT_CNTL_23 0x0286A0 -#define R_0286A4_SPI_PS_INPUT_CNTL_24 0x0286A4 -#define R_0286A8_SPI_PS_INPUT_CNTL_25 0x0286A8 -#define R_0286AC_SPI_PS_INPUT_CNTL_26 0x0286AC -#define R_0286B0_SPI_PS_INPUT_CNTL_27 0x0286B0 -#define R_0286B4_SPI_PS_INPUT_CNTL_28 0x0286B4 -#define R_0286B8_SPI_PS_INPUT_CNTL_29 0x0286B8 -#define R_0286BC_SPI_PS_INPUT_CNTL_30 0x0286BC -#define R_0286C0_SPI_PS_INPUT_CNTL_31 0x0286C0 -#define R_0286C4_SPI_VS_OUT_CONFIG 0x0286C4 -#define S_0286C4_VS_EXPORT_COUNT(x) (((x) & 0x1F) << 1) -#define G_0286C4_VS_EXPORT_COUNT(x) (((x) >> 1) & 0x1F) -#define C_0286C4_VS_EXPORT_COUNT 0xFFFFFFC1 -#define S_0286C4_VS_HALF_PACK(x) (((x) & 0x1) << 6) -#define G_0286C4_VS_HALF_PACK(x) (((x) >> 6) & 0x1) -#define C_0286C4_VS_HALF_PACK 0xFFFFFFBF -#define S_0286C4_VS_EXPORTS_FOG(x) (((x) & 0x1) << 7) /* not on CIK */ -#define G_0286C4_VS_EXPORTS_FOG(x) (((x) >> 7) & 0x1) /* not on CIK */ -#define C_0286C4_VS_EXPORTS_FOG 0xFFFFFF7F /* not on CIK */ -#define S_0286C4_VS_OUT_FOG_VEC_ADDR(x) (((x) & 0x1F) << 8) /* not on CIK */ -#define G_0286C4_VS_OUT_FOG_VEC_ADDR(x) (((x) >> 8) & 0x1F) /* not on CIK */ -#define C_0286C4_VS_OUT_FOG_VEC_ADDR 0xFFFFE0FF /* not on CIK */ -#define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC -#define S_0286CC_PERSP_SAMPLE_ENA(x) (((x) & 0x1) << 0) -#define G_0286CC_PERSP_SAMPLE_ENA(x) (((x) >> 0) & 0x1) -#define C_0286CC_PERSP_SAMPLE_ENA 0xFFFFFFFE -#define S_0286CC_PERSP_CENTER_ENA(x) (((x) & 0x1) << 1) -#define G_0286CC_PERSP_CENTER_ENA(x) (((x) >> 1) & 0x1) -#define C_0286CC_PERSP_CENTER_ENA 0xFFFFFFFD -#define S_0286CC_PERSP_CENTROID_ENA(x) (((x) & 0x1) << 2) -#define G_0286CC_PERSP_CENTROID_ENA(x) (((x) >> 2) & 0x1) -#define C_0286CC_PERSP_CENTROID_ENA 0xFFFFFFFB -#define S_0286CC_PERSP_PULL_MODEL_ENA(x) (((x) & 0x1) << 3) -#define G_0286CC_PERSP_PULL_MODEL_ENA(x) (((x) >> 3) & 0x1) -#define C_0286CC_PERSP_PULL_MODEL_ENA 0xFFFFFFF7 -#define S_0286CC_LINEAR_SAMPLE_ENA(x) (((x) & 0x1) << 4) -#define G_0286CC_LINEAR_SAMPLE_ENA(x) (((x) >> 4) & 0x1) -#define C_0286CC_LINEAR_SAMPLE_ENA 0xFFFFFFEF -#define S_0286CC_LINEAR_CENTER_ENA(x) (((x) & 0x1) << 5) -#define G_0286CC_LINEAR_CENTER_ENA(x) (((x) >> 5) & 0x1) -#define C_0286CC_LINEAR_CENTER_ENA 0xFFFFFFDF -#define S_0286CC_LINEAR_CENTROID_ENA(x) (((x) & 0x1) << 6) -#define G_0286CC_LINEAR_CENTROID_ENA(x) (((x) >> 6) & 0x1) -#define C_0286CC_LINEAR_CENTROID_ENA 0xFFFFFFBF -#define S_0286CC_LINE_STIPPLE_TEX_ENA(x) (((x) & 0x1) << 7) -#define G_0286CC_LINE_STIPPLE_TEX_ENA(x) (((x) >> 7) & 0x1) -#define C_0286CC_LINE_STIPPLE_TEX_ENA 0xFFFFFF7F -#define S_0286CC_POS_X_FLOAT_ENA(x) (((x) & 0x1) << 8) -#define G_0286CC_POS_X_FLOAT_ENA(x) (((x) >> 8) & 0x1) -#define C_0286CC_POS_X_FLOAT_ENA 0xFFFFFEFF -#define S_0286CC_POS_Y_FLOAT_ENA(x) (((x) & 0x1) << 9) -#define G_0286CC_POS_Y_FLOAT_ENA(x) (((x) >> 9) & 0x1) -#define C_0286CC_POS_Y_FLOAT_ENA 0xFFFFFDFF -#define S_0286CC_POS_Z_FLOAT_ENA(x) (((x) & 0x1) << 10) -#define G_0286CC_POS_Z_FLOAT_ENA(x) (((x) >> 10) & 0x1) -#define C_0286CC_POS_Z_FLOAT_ENA 0xFFFFFBFF -#define S_0286CC_POS_W_FLOAT_ENA(x) (((x) & 0x1) << 11) -#define G_0286CC_POS_W_FLOAT_ENA(x) (((x) >> 11) & 0x1) -#define C_0286CC_POS_W_FLOAT_ENA 0xFFFFF7FF -#define S_0286CC_FRONT_FACE_ENA(x) (((x) & 0x1) << 12) -#define G_0286CC_FRONT_FACE_ENA(x) (((x) >> 12) & 0x1) -#define C_0286CC_FRONT_FACE_ENA 0xFFFFEFFF -#define S_0286CC_ANCILLARY_ENA(x) (((x) & 0x1) << 13) -#define G_0286CC_ANCILLARY_ENA(x) (((x) >> 13) & 0x1) -#define C_0286CC_ANCILLARY_ENA 0xFFFFDFFF -#define S_0286CC_SAMPLE_COVERAGE_ENA(x) (((x) & 0x1) << 14) -#define G_0286CC_SAMPLE_COVERAGE_ENA(x) (((x) >> 14) & 0x1) -#define C_0286CC_SAMPLE_COVERAGE_ENA 0xFFFFBFFF -#define S_0286CC_POS_FIXED_PT_ENA(x) (((x) & 0x1) << 15) -#define G_0286CC_POS_FIXED_PT_ENA(x) (((x) >> 15) & 0x1) -#define C_0286CC_POS_FIXED_PT_ENA 0xFFFF7FFF -#define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0 -#define S_0286D0_PERSP_SAMPLE_ENA(x) (((x) & 0x1) << 0) -#define G_0286D0_PERSP_SAMPLE_ENA(x) (((x) >> 0) & 0x1) -#define C_0286D0_PERSP_SAMPLE_ENA 0xFFFFFFFE -#define S_0286D0_PERSP_CENTER_ENA(x) (((x) & 0x1) << 1) -#define G_0286D0_PERSP_CENTER_ENA(x) (((x) >> 1) & 0x1) -#define C_0286D0_PERSP_CENTER_ENA 0xFFFFFFFD -#define S_0286D0_PERSP_CENTROID_ENA(x) (((x) & 0x1) << 2) -#define G_0286D0_PERSP_CENTROID_ENA(x) (((x) >> 2) & 0x1) -#define C_0286D0_PERSP_CENTROID_ENA 0xFFFFFFFB -#define S_0286D0_PERSP_PULL_MODEL_ENA(x) (((x) & 0x1) << 3) -#define G_0286D0_PERSP_PULL_MODEL_ENA(x) (((x) >> 3) & 0x1) -#define C_0286D0_PERSP_PULL_MODEL_ENA 0xFFFFFFF7 -#define S_0286D0_LINEAR_SAMPLE_ENA(x) (((x) & 0x1) << 4) -#define G_0286D0_LINEAR_SAMPLE_ENA(x) (((x) >> 4) & 0x1) -#define C_0286D0_LINEAR_SAMPLE_ENA 0xFFFFFFEF -#define S_0286D0_LINEAR_CENTER_ENA(x) (((x) & 0x1) << 5) -#define G_0286D0_LINEAR_CENTER_ENA(x) (((x) >> 5) & 0x1) -#define C_0286D0_LINEAR_CENTER_ENA 0xFFFFFFDF -#define S_0286D0_LINEAR_CENTROID_ENA(x) (((x) & 0x1) << 6) -#define G_0286D0_LINEAR_CENTROID_ENA(x) (((x) >> 6) & 0x1) -#define C_0286D0_LINEAR_CENTROID_ENA 0xFFFFFFBF -#define S_0286D0_LINE_STIPPLE_TEX_ENA(x) (((x) & 0x1) << 7) -#define G_0286D0_LINE_STIPPLE_TEX_ENA(x) (((x) >> 7) & 0x1) -#define C_0286D0_LINE_STIPPLE_TEX_ENA 0xFFFFFF7F -#define S_0286D0_POS_X_FLOAT_ENA(x) (((x) & 0x1) << 8) -#define G_0286D0_POS_X_FLOAT_ENA(x) (((x) >> 8) & 0x1) -#define C_0286D0_POS_X_FLOAT_ENA 0xFFFFFEFF -#define S_0286D0_POS_Y_FLOAT_ENA(x) (((x) & 0x1) << 9) -#define G_0286D0_POS_Y_FLOAT_ENA(x) (((x) >> 9) & 0x1) -#define C_0286D0_POS_Y_FLOAT_ENA 0xFFFFFDFF -#define S_0286D0_POS_Z_FLOAT_ENA(x) (((x) & 0x1) << 10) -#define G_0286D0_POS_Z_FLOAT_ENA(x) (((x) >> 10) & 0x1) -#define C_0286D0_POS_Z_FLOAT_ENA 0xFFFFFBFF -#define S_0286D0_POS_W_FLOAT_ENA(x) (((x) & 0x1) << 11) -#define G_0286D0_POS_W_FLOAT_ENA(x) (((x) >> 11) & 0x1) -#define C_0286D0_POS_W_FLOAT_ENA 0xFFFFF7FF -#define S_0286D0_FRONT_FACE_ENA(x) (((x) & 0x1) << 12) -#define G_0286D0_FRONT_FACE_ENA(x) (((x) >> 12) & 0x1) -#define C_0286D0_FRONT_FACE_ENA 0xFFFFEFFF -#define S_0286D0_ANCILLARY_ENA(x) (((x) & 0x1) << 13) -#define G_0286D0_ANCILLARY_ENA(x) (((x) >> 13) & 0x1) -#define C_0286D0_ANCILLARY_ENA 0xFFFFDFFF -#define S_0286D0_SAMPLE_COVERAGE_ENA(x) (((x) & 0x1) << 14) -#define G_0286D0_SAMPLE_COVERAGE_ENA(x) (((x) >> 14) & 0x1) -#define C_0286D0_SAMPLE_COVERAGE_ENA 0xFFFFBFFF -#define S_0286D0_POS_FIXED_PT_ENA(x) (((x) & 0x1) << 15) -#define G_0286D0_POS_FIXED_PT_ENA(x) (((x) >> 15) & 0x1) -#define C_0286D0_POS_FIXED_PT_ENA 0xFFFF7FFF -#define R_0286D4_SPI_INTERP_CONTROL_0 0x0286D4 -#define S_0286D4_FLAT_SHADE_ENA(x) (((x) & 0x1) << 0) -#define G_0286D4_FLAT_SHADE_ENA(x) (((x) >> 0) & 0x1) -#define C_0286D4_FLAT_SHADE_ENA 0xFFFFFFFE -#define S_0286D4_PNT_SPRITE_ENA(x) (((x) & 0x1) << 1) -#define G_0286D4_PNT_SPRITE_ENA(x) (((x) >> 1) & 0x1) -#define C_0286D4_PNT_SPRITE_ENA 0xFFFFFFFD -#define S_0286D4_PNT_SPRITE_OVRD_X(x) (((x) & 0x07) << 2) -#define G_0286D4_PNT_SPRITE_OVRD_X(x) (((x) >> 2) & 0x07) -#define C_0286D4_PNT_SPRITE_OVRD_X 0xFFFFFFE3 -#define V_0286D4_SPI_PNT_SPRITE_SEL_0 0x00 -#define V_0286D4_SPI_PNT_SPRITE_SEL_1 0x01 -#define V_0286D4_SPI_PNT_SPRITE_SEL_S 0x02 -#define V_0286D4_SPI_PNT_SPRITE_SEL_T 0x03 -#define V_0286D4_SPI_PNT_SPRITE_SEL_NONE 0x04 -#define S_0286D4_PNT_SPRITE_OVRD_Y(x) (((x) & 0x07) << 5) -#define G_0286D4_PNT_SPRITE_OVRD_Y(x) (((x) >> 5) & 0x07) -#define C_0286D4_PNT_SPRITE_OVRD_Y 0xFFFFFF1F -#define V_0286D4_SPI_PNT_SPRITE_SEL_0 0x00 -#define V_0286D4_SPI_PNT_SPRITE_SEL_1 0x01 -#define V_0286D4_SPI_PNT_SPRITE_SEL_S 0x02 -#define V_0286D4_SPI_PNT_SPRITE_SEL_T 0x03 -#define V_0286D4_SPI_PNT_SPRITE_SEL_NONE 0x04 -#define S_0286D4_PNT_SPRITE_OVRD_Z(x) (((x) & 0x07) << 8) -#define G_0286D4_PNT_SPRITE_OVRD_Z(x) (((x) >> 8) & 0x07) -#define C_0286D4_PNT_SPRITE_OVRD_Z 0xFFFFF8FF -#define V_0286D4_SPI_PNT_SPRITE_SEL_0 0x00 -#define V_0286D4_SPI_PNT_SPRITE_SEL_1 0x01 -#define V_0286D4_SPI_PNT_SPRITE_SEL_S 0x02 -#define V_0286D4_SPI_PNT_SPRITE_SEL_T 0x03 -#define V_0286D4_SPI_PNT_SPRITE_SEL_NONE 0x04 -#define S_0286D4_PNT_SPRITE_OVRD_W(x) (((x) & 0x07) << 11) -#define G_0286D4_PNT_SPRITE_OVRD_W(x) (((x) >> 11) & 0x07) -#define C_0286D4_PNT_SPRITE_OVRD_W 0xFFFFC7FF -#define V_0286D4_SPI_PNT_SPRITE_SEL_0 0x00 -#define V_0286D4_SPI_PNT_SPRITE_SEL_1 0x01 -#define V_0286D4_SPI_PNT_SPRITE_SEL_S 0x02 -#define V_0286D4_SPI_PNT_SPRITE_SEL_T 0x03 -#define V_0286D4_SPI_PNT_SPRITE_SEL_NONE 0x04 -#define S_0286D4_PNT_SPRITE_TOP_1(x) (((x) & 0x1) << 14) -#define G_0286D4_PNT_SPRITE_TOP_1(x) (((x) >> 14) & 0x1) -#define C_0286D4_PNT_SPRITE_TOP_1 0xFFFFBFFF -#define R_0286D8_SPI_PS_IN_CONTROL 0x0286D8 -#define S_0286D8_NUM_INTERP(x) (((x) & 0x3F) << 0) -#define G_0286D8_NUM_INTERP(x) (((x) >> 0) & 0x3F) -#define C_0286D8_NUM_INTERP 0xFFFFFFC0 -#define S_0286D8_PARAM_GEN(x) (((x) & 0x1) << 6) -#define G_0286D8_PARAM_GEN(x) (((x) >> 6) & 0x1) -#define C_0286D8_PARAM_GEN 0xFFFFFFBF -#define S_0286D8_FOG_ADDR(x) (((x) & 0x7F) << 7) /* not on CIK */ -#define G_0286D8_FOG_ADDR(x) (((x) >> 7) & 0x7F) /* not on CIK */ -#define C_0286D8_FOG_ADDR 0xFFFFC07F /* not on CIK */ -#define S_0286D8_BC_OPTIMIZE_DISABLE(x) (((x) & 0x1) << 14) -#define G_0286D8_BC_OPTIMIZE_DISABLE(x) (((x) >> 14) & 0x1) -#define C_0286D8_BC_OPTIMIZE_DISABLE 0xFFFFBFFF -#define S_0286D8_PASS_FOG_THROUGH_PS(x) (((x) & 0x1) << 15) /* not on CIK */ -#define G_0286D8_PASS_FOG_THROUGH_PS(x) (((x) >> 15) & 0x1) /* not on CIK */ -#define C_0286D8_PASS_FOG_THROUGH_PS 0xFFFF7FFF /* not on CIK */ -#define R_0286E0_SPI_BARYC_CNTL 0x0286E0 -#define S_0286E0_PERSP_CENTER_CNTL(x) (((x) & 0x1) << 0) -#define G_0286E0_PERSP_CENTER_CNTL(x) (((x) >> 0) & 0x1) -#define C_0286E0_PERSP_CENTER_CNTL 0xFFFFFFFE -#define S_0286E0_PERSP_CENTROID_CNTL(x) (((x) & 0x1) << 4) -#define G_0286E0_PERSP_CENTROID_CNTL(x) (((x) >> 4) & 0x1) -#define C_0286E0_PERSP_CENTROID_CNTL 0xFFFFFFEF -#define S_0286E0_LINEAR_CENTER_CNTL(x) (((x) & 0x1) << 8) -#define G_0286E0_LINEAR_CENTER_CNTL(x) (((x) >> 8) & 0x1) -#define C_0286E0_LINEAR_CENTER_CNTL 0xFFFFFEFF -#define S_0286E0_LINEAR_CENTROID_CNTL(x) (((x) & 0x1) << 12) -#define G_0286E0_LINEAR_CENTROID_CNTL(x) (((x) >> 12) & 0x1) -#define C_0286E0_LINEAR_CENTROID_CNTL 0xFFFFEFFF -#define S_0286E0_POS_FLOAT_LOCATION(x) (((x) & 0x03) << 16) -#define G_0286E0_POS_FLOAT_LOCATION(x) (((x) >> 16) & 0x03) -#define C_0286E0_POS_FLOAT_LOCATION 0xFFFCFFFF -#define V_0286E0_X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT 0x00 -#define S_0286E0_POS_FLOAT_ULC(x) (((x) & 0x1) << 20) -#define G_0286E0_POS_FLOAT_ULC(x) (((x) >> 20) & 0x1) -#define C_0286E0_POS_FLOAT_ULC 0xFFEFFFFF -#define S_0286E0_FRONT_FACE_ALL_BITS(x) (((x) & 0x1) << 24) -#define G_0286E0_FRONT_FACE_ALL_BITS(x) (((x) >> 24) & 0x1) -#define C_0286E0_FRONT_FACE_ALL_BITS 0xFEFFFFFF -#define R_0286E8_SPI_TMPRING_SIZE 0x0286E8 -#define S_0286E8_WAVES(x) (((x) & 0xFFF) << 0) -#define G_0286E8_WAVES(x) (((x) >> 0) & 0xFFF) -#define C_0286E8_WAVES 0xFFFFF000 -#define S_0286E8_WAVESIZE(x) (((x) & 0x1FFF) << 12) -#define G_0286E8_WAVESIZE(x) (((x) >> 12) & 0x1FFF) -#define C_0286E8_WAVESIZE 0xFE000FFF -#define R_028704_SPI_WAVE_MGMT_1 0x028704 /* not on CIK */ -#define S_028704_NUM_PS_WAVES(x) (((x) & 0x3F) << 0) -#define G_028704_NUM_PS_WAVES(x) (((x) >> 0) & 0x3F) -#define C_028704_NUM_PS_WAVES 0xFFFFFFC0 -#define S_028704_NUM_VS_WAVES(x) (((x) & 0x3F) << 6) -#define G_028704_NUM_VS_WAVES(x) (((x) >> 6) & 0x3F) -#define C_028704_NUM_VS_WAVES 0xFFFFF03F -#define S_028704_NUM_GS_WAVES(x) (((x) & 0x3F) << 12) -#define G_028704_NUM_GS_WAVES(x) (((x) >> 12) & 0x3F) -#define C_028704_NUM_GS_WAVES 0xFFFC0FFF -#define S_028704_NUM_ES_WAVES(x) (((x) & 0x3F) << 18) -#define G_028704_NUM_ES_WAVES(x) (((x) >> 18) & 0x3F) -#define C_028704_NUM_ES_WAVES 0xFF03FFFF -#define S_028704_NUM_HS_WAVES(x) (((x) & 0x3F) << 24) -#define G_028704_NUM_HS_WAVES(x) (((x) >> 24) & 0x3F) -#define C_028704_NUM_HS_WAVES 0xC0FFFFFF -#define R_028708_SPI_WAVE_MGMT_2 0x028708 /* not on CIK */ -#define S_028708_NUM_LS_WAVES(x) (((x) & 0x3F) << 0) -#define G_028708_NUM_LS_WAVES(x) (((x) >> 0) & 0x3F) -#define C_028708_NUM_LS_WAVES 0xFFFFFFC0 -#define R_02870C_SPI_SHADER_POS_FORMAT 0x02870C -#define S_02870C_POS0_EXPORT_FORMAT(x) (((x) & 0x0F) << 0) -#define G_02870C_POS0_EXPORT_FORMAT(x) (((x) >> 0) & 0x0F) -#define C_02870C_POS0_EXPORT_FORMAT 0xFFFFFFF0 -#define V_02870C_SPI_SHADER_NONE 0x00 -#define V_02870C_SPI_SHADER_1COMP 0x01 -#define V_02870C_SPI_SHADER_2COMP 0x02 -#define V_02870C_SPI_SHADER_4COMPRESS 0x03 -#define V_02870C_SPI_SHADER_4COMP 0x04 -#define S_02870C_POS1_EXPORT_FORMAT(x) (((x) & 0x0F) << 4) -#define G_02870C_POS1_EXPORT_FORMAT(x) (((x) >> 4) & 0x0F) -#define C_02870C_POS1_EXPORT_FORMAT 0xFFFFFF0F -#define V_02870C_SPI_SHADER_NONE 0x00 -#define V_02870C_SPI_SHADER_1COMP 0x01 -#define V_02870C_SPI_SHADER_2COMP 0x02 -#define V_02870C_SPI_SHADER_4COMPRESS 0x03 -#define V_02870C_SPI_SHADER_4COMP 0x04 -#define S_02870C_POS2_EXPORT_FORMAT(x) (((x) & 0x0F) << 8) -#define G_02870C_POS2_EXPORT_FORMAT(x) (((x) >> 8) & 0x0F) -#define C_02870C_POS2_EXPORT_FORMAT 0xFFFFF0FF -#define V_02870C_SPI_SHADER_NONE 0x00 -#define V_02870C_SPI_SHADER_1COMP 0x01 -#define V_02870C_SPI_SHADER_2COMP 0x02 -#define V_02870C_SPI_SHADER_4COMPRESS 0x03 -#define V_02870C_SPI_SHADER_4COMP 0x04 -#define S_02870C_POS3_EXPORT_FORMAT(x) (((x) & 0x0F) << 12) -#define G_02870C_POS3_EXPORT_FORMAT(x) (((x) >> 12) & 0x0F) -#define C_02870C_POS3_EXPORT_FORMAT 0xFFFF0FFF -#define V_02870C_SPI_SHADER_NONE 0x00 -#define V_02870C_SPI_SHADER_1COMP 0x01 -#define V_02870C_SPI_SHADER_2COMP 0x02 -#define V_02870C_SPI_SHADER_4COMPRESS 0x03 -#define V_02870C_SPI_SHADER_4COMP 0x04 -#define R_028710_SPI_SHADER_Z_FORMAT 0x028710 -#define S_028710_Z_EXPORT_FORMAT(x) (((x) & 0x0F) << 0) -#define G_028710_Z_EXPORT_FORMAT(x) (((x) >> 0) & 0x0F) -#define C_028710_Z_EXPORT_FORMAT 0xFFFFFFF0 -#define V_028710_SPI_SHADER_ZERO 0x00 -#define V_028710_SPI_SHADER_32_R 0x01 -#define V_028710_SPI_SHADER_32_GR 0x02 -#define V_028710_SPI_SHADER_32_AR 0x03 -#define V_028710_SPI_SHADER_FP16_ABGR 0x04 -#define V_028710_SPI_SHADER_UNORM16_ABGR 0x05 -#define V_028710_SPI_SHADER_SNORM16_ABGR 0x06 -#define V_028710_SPI_SHADER_UINT16_ABGR 0x07 -#define V_028710_SPI_SHADER_SINT16_ABGR 0x08 -#define V_028710_SPI_SHADER_32_ABGR 0x09 -#define R_028714_SPI_SHADER_COL_FORMAT 0x028714 -#define S_028714_COL0_EXPORT_FORMAT(x) (((x) & 0x0F) << 0) -#define G_028714_COL0_EXPORT_FORMAT(x) (((x) >> 0) & 0x0F) -#define C_028714_COL0_EXPORT_FORMAT 0xFFFFFFF0 -#define V_028714_SPI_SHADER_ZERO 0x00 -#define V_028714_SPI_SHADER_32_R 0x01 -#define V_028714_SPI_SHADER_32_GR 0x02 -#define V_028714_SPI_SHADER_32_AR 0x03 -#define V_028714_SPI_SHADER_FP16_ABGR 0x04 -#define V_028714_SPI_SHADER_UNORM16_ABGR 0x05 -#define V_028714_SPI_SHADER_SNORM16_ABGR 0x06 -#define V_028714_SPI_SHADER_UINT16_ABGR 0x07 -#define V_028714_SPI_SHADER_SINT16_ABGR 0x08 -#define V_028714_SPI_SHADER_32_ABGR 0x09 -#define S_028714_COL1_EXPORT_FORMAT(x) (((x) & 0x0F) << 4) -#define G_028714_COL1_EXPORT_FORMAT(x) (((x) >> 4) & 0x0F) -#define C_028714_COL1_EXPORT_FORMAT 0xFFFFFF0F -#define V_028714_SPI_SHADER_ZERO 0x00 -#define V_028714_SPI_SHADER_32_R 0x01 -#define V_028714_SPI_SHADER_32_GR 0x02 -#define V_028714_SPI_SHADER_32_AR 0x03 -#define V_028714_SPI_SHADER_FP16_ABGR 0x04 -#define V_028714_SPI_SHADER_UNORM16_ABGR 0x05 -#define V_028714_SPI_SHADER_SNORM16_ABGR 0x06 -#define V_028714_SPI_SHADER_UINT16_ABGR 0x07 -#define V_028714_SPI_SHADER_SINT16_ABGR 0x08 -#define V_028714_SPI_SHADER_32_ABGR 0x09 -#define S_028714_COL2_EXPORT_FORMAT(x) (((x) & 0x0F) << 8) -#define G_028714_COL2_EXPORT_FORMAT(x) (((x) >> 8) & 0x0F) -#define C_028714_COL2_EXPORT_FORMAT 0xFFFFF0FF -#define V_028714_SPI_SHADER_ZERO 0x00 -#define V_028714_SPI_SHADER_32_R 0x01 -#define V_028714_SPI_SHADER_32_GR 0x02 -#define V_028714_SPI_SHADER_32_AR 0x03 -#define V_028714_SPI_SHADER_FP16_ABGR 0x04 -#define V_028714_SPI_SHADER_UNORM16_ABGR 0x05 -#define V_028714_SPI_SHADER_SNORM16_ABGR 0x06 -#define V_028714_SPI_SHADER_UINT16_ABGR 0x07 -#define V_028714_SPI_SHADER_SINT16_ABGR 0x08 -#define V_028714_SPI_SHADER_32_ABGR 0x09 -#define S_028714_COL3_EXPORT_FORMAT(x) (((x) & 0x0F) << 12) -#define G_028714_COL3_EXPORT_FORMAT(x) (((x) >> 12) & 0x0F) -#define C_028714_COL3_EXPORT_FORMAT 0xFFFF0FFF -#define V_028714_SPI_SHADER_ZERO 0x00 -#define V_028714_SPI_SHADER_32_R 0x01 -#define V_028714_SPI_SHADER_32_GR 0x02 -#define V_028714_SPI_SHADER_32_AR 0x03 -#define V_028714_SPI_SHADER_FP16_ABGR 0x04 -#define V_028714_SPI_SHADER_UNORM16_ABGR 0x05 -#define V_028714_SPI_SHADER_SNORM16_ABGR 0x06 -#define V_028714_SPI_SHADER_UINT16_ABGR 0x07 -#define V_028714_SPI_SHADER_SINT16_ABGR 0x08 -#define V_028714_SPI_SHADER_32_ABGR 0x09 -#define S_028714_COL4_EXPORT_FORMAT(x) (((x) & 0x0F) << 16) -#define G_028714_COL4_EXPORT_FORMAT(x) (((x) >> 16) & 0x0F) -#define C_028714_COL4_EXPORT_FORMAT 0xFFF0FFFF -#define V_028714_SPI_SHADER_ZERO 0x00 -#define V_028714_SPI_SHADER_32_R 0x01 -#define V_028714_SPI_SHADER_32_GR 0x02 -#define V_028714_SPI_SHADER_32_AR 0x03 -#define V_028714_SPI_SHADER_FP16_ABGR 0x04 -#define V_028714_SPI_SHADER_UNORM16_ABGR 0x05 -#define V_028714_SPI_SHADER_SNORM16_ABGR 0x06 -#define V_028714_SPI_SHADER_UINT16_ABGR 0x07 -#define V_028714_SPI_SHADER_SINT16_ABGR 0x08 -#define V_028714_SPI_SHADER_32_ABGR 0x09 -#define S_028714_COL5_EXPORT_FORMAT(x) (((x) & 0x0F) << 20) -#define G_028714_COL5_EXPORT_FORMAT(x) (((x) >> 20) & 0x0F) -#define C_028714_COL5_EXPORT_FORMAT 0xFF0FFFFF -#define V_028714_SPI_SHADER_ZERO 0x00 -#define V_028714_SPI_SHADER_32_R 0x01 -#define V_028714_SPI_SHADER_32_GR 0x02 -#define V_028714_SPI_SHADER_32_AR 0x03 -#define V_028714_SPI_SHADER_FP16_ABGR 0x04 -#define V_028714_SPI_SHADER_UNORM16_ABGR 0x05 -#define V_028714_SPI_SHADER_SNORM16_ABGR 0x06 -#define V_028714_SPI_SHADER_UINT16_ABGR 0x07 -#define V_028714_SPI_SHADER_SINT16_ABGR 0x08 -#define V_028714_SPI_SHADER_32_ABGR 0x09 -#define S_028714_COL6_EXPORT_FORMAT(x) (((x) & 0x0F) << 24) -#define G_028714_COL6_EXPORT_FORMAT(x) (((x) >> 24) & 0x0F) -#define C_028714_COL6_EXPORT_FORMAT 0xF0FFFFFF -#define V_028714_SPI_SHADER_ZERO 0x00 -#define V_028714_SPI_SHADER_32_R 0x01 -#define V_028714_SPI_SHADER_32_GR 0x02 -#define V_028714_SPI_SHADER_32_AR 0x03 -#define V_028714_SPI_SHADER_FP16_ABGR 0x04 -#define V_028714_SPI_SHADER_UNORM16_ABGR 0x05 -#define V_028714_SPI_SHADER_SNORM16_ABGR 0x06 -#define V_028714_SPI_SHADER_UINT16_ABGR 0x07 -#define V_028714_SPI_SHADER_SINT16_ABGR 0x08 -#define V_028714_SPI_SHADER_32_ABGR 0x09 -#define S_028714_COL7_EXPORT_FORMAT(x) (((x) & 0x0F) << 28) -#define G_028714_COL7_EXPORT_FORMAT(x) (((x) >> 28) & 0x0F) -#define C_028714_COL7_EXPORT_FORMAT 0x0FFFFFFF -#define V_028714_SPI_SHADER_ZERO 0x00 -#define V_028714_SPI_SHADER_32_R 0x01 -#define V_028714_SPI_SHADER_32_GR 0x02 -#define V_028714_SPI_SHADER_32_AR 0x03 -#define V_028714_SPI_SHADER_FP16_ABGR 0x04 -#define V_028714_SPI_SHADER_UNORM16_ABGR 0x05 -#define V_028714_SPI_SHADER_SNORM16_ABGR 0x06 -#define V_028714_SPI_SHADER_UINT16_ABGR 0x07 -#define V_028714_SPI_SHADER_SINT16_ABGR 0x08 -#define V_028714_SPI_SHADER_32_ABGR 0x09 -/* Stoney */ -#define R_028754_SX_PS_DOWNCONVERT 0x028754 -#define S_028754_MRT0(x) (((x) & 0x0F) << 0) -#define G_028754_MRT0(x) (((x) >> 0) & 0x0F) -#define C_028754_MRT0 0xFFFFFFF0 -#define V_028754_SX_RT_EXPORT_NO_CONVERSION 0 -#define V_028754_SX_RT_EXPORT_32_R 1 -#define V_028754_SX_RT_EXPORT_32_A 2 -#define V_028754_SX_RT_EXPORT_10_11_11 3 -#define V_028754_SX_RT_EXPORT_2_10_10_10 4 -#define V_028754_SX_RT_EXPORT_8_8_8_8 5 -#define V_028754_SX_RT_EXPORT_5_6_5 6 -#define V_028754_SX_RT_EXPORT_1_5_5_5 7 -#define V_028754_SX_RT_EXPORT_4_4_4_4 8 -#define V_028754_SX_RT_EXPORT_16_16_GR 9 -#define V_028754_SX_RT_EXPORT_16_16_AR 10 -#define S_028754_MRT1(x) (((x) & 0x0F) << 4) -#define G_028754_MRT1(x) (((x) >> 4) & 0x0F) -#define C_028754_MRT1 0xFFFFFF0F -#define S_028754_MRT2(x) (((x) & 0x0F) << 8) -#define G_028754_MRT2(x) (((x) >> 8) & 0x0F) -#define C_028754_MRT2 0xFFFFF0FF -#define S_028754_MRT3(x) (((x) & 0x0F) << 12) -#define G_028754_MRT3(x) (((x) >> 12) & 0x0F) -#define C_028754_MRT3 0xFFFF0FFF -#define S_028754_MRT4(x) (((x) & 0x0F) << 16) -#define G_028754_MRT4(x) (((x) >> 16) & 0x0F) -#define C_028754_MRT4 0xFFF0FFFF -#define S_028754_MRT5(x) (((x) & 0x0F) << 20) -#define G_028754_MRT5(x) (((x) >> 20) & 0x0F) -#define C_028754_MRT5 0xFF0FFFFF -#define S_028754_MRT6(x) (((x) & 0x0F) << 24) -#define G_028754_MRT6(x) (((x) >> 24) & 0x0F) -#define C_028754_MRT6 0xF0FFFFFF -#define S_028754_MRT7(x) (((x) & 0x0F) << 28) -#define G_028754_MRT7(x) (((x) >> 28) & 0x0F) -#define C_028754_MRT7 0x0FFFFFFF -#define R_028758_SX_BLEND_OPT_EPSILON 0x028758 -#define S_028758_MRT0_EPSILON(x) (((x) & 0x0F) << 0) -#define G_028758_MRT0_EPSILON(x) (((x) >> 0) & 0x0F) -#define C_028758_MRT0_EPSILON 0xFFFFFFF0 -#define V_028758_EXACT 0 -#define V_028758_11BIT_FORMAT 1 -#define V_028758_10BIT_FORMAT 3 -#define V_028758_8BIT_FORMAT 7 -#define V_028758_6BIT_FORMAT 11 -#define V_028758_5BIT_FORMAT 13 -#define V_028758_4BIT_FORMAT 15 -#define S_028758_MRT1_EPSILON(x) (((x) & 0x0F) << 4) -#define G_028758_MRT1_EPSILON(x) (((x) >> 4) & 0x0F) -#define C_028758_MRT1_EPSILON 0xFFFFFF0F -#define S_028758_MRT2_EPSILON(x) (((x) & 0x0F) << 8) -#define G_028758_MRT2_EPSILON(x) (((x) >> 8) & 0x0F) -#define C_028758_MRT2_EPSILON 0xFFFFF0FF -#define S_028758_MRT3_EPSILON(x) (((x) & 0x0F) << 12) -#define G_028758_MRT3_EPSILON(x) (((x) >> 12) & 0x0F) -#define C_028758_MRT3_EPSILON 0xFFFF0FFF -#define S_028758_MRT4_EPSILON(x) (((x) & 0x0F) << 16) -#define G_028758_MRT4_EPSILON(x) (((x) >> 16) & 0x0F) -#define C_028758_MRT4_EPSILON 0xFFF0FFFF -#define S_028758_MRT5_EPSILON(x) (((x) & 0x0F) << 20) -#define G_028758_MRT5_EPSILON(x) (((x) >> 20) & 0x0F) -#define C_028758_MRT5_EPSILON 0xFF0FFFFF -#define S_028758_MRT6_EPSILON(x) (((x) & 0x0F) << 24) -#define G_028758_MRT6_EPSILON(x) (((x) >> 24) & 0x0F) -#define C_028758_MRT6_EPSILON 0xF0FFFFFF -#define S_028758_MRT7_EPSILON(x) (((x) & 0x0F) << 28) -#define G_028758_MRT7_EPSILON(x) (((x) >> 28) & 0x0F) -#define C_028758_MRT7_EPSILON 0x0FFFFFFF -#define R_02875C_SX_BLEND_OPT_CONTROL 0x02875C -#define S_02875C_MRT0_COLOR_OPT_DISABLE(x) (((x) & 0x1) << 0) -#define G_02875C_MRT0_COLOR_OPT_DISABLE(x) (((x) >> 0) & 0x1) -#define C_02875C_MRT0_COLOR_OPT_DISABLE 0xFFFFFFFE -#define S_02875C_MRT0_ALPHA_OPT_DISABLE(x) (((x) & 0x1) << 1) -#define G_02875C_MRT0_ALPHA_OPT_DISABLE(x) (((x) >> 1) & 0x1) -#define C_02875C_MRT0_ALPHA_OPT_DISABLE 0xFFFFFFFD -#define S_02875C_MRT1_COLOR_OPT_DISABLE(x) (((x) & 0x1) << 4) -#define G_02875C_MRT1_COLOR_OPT_DISABLE(x) (((x) >> 4) & 0x1) -#define C_02875C_MRT1_COLOR_OPT_DISABLE 0xFFFFFFEF -#define S_02875C_MRT1_ALPHA_OPT_DISABLE(x) (((x) & 0x1) << 5) -#define G_02875C_MRT1_ALPHA_OPT_DISABLE(x) (((x) >> 5) & 0x1) -#define C_02875C_MRT1_ALPHA_OPT_DISABLE 0xFFFFFFDF -#define S_02875C_MRT2_COLOR_OPT_DISABLE(x) (((x) & 0x1) << 8) -#define G_02875C_MRT2_COLOR_OPT_DISABLE(x) (((x) >> 8) & 0x1) -#define C_02875C_MRT2_COLOR_OPT_DISABLE 0xFFFFFEFF -#define S_02875C_MRT2_ALPHA_OPT_DISABLE(x) (((x) & 0x1) << 9) -#define G_02875C_MRT2_ALPHA_OPT_DISABLE(x) (((x) >> 9) & 0x1) -#define C_02875C_MRT2_ALPHA_OPT_DISABLE 0xFFFFFDFF -#define S_02875C_MRT3_COLOR_OPT_DISABLE(x) (((x) & 0x1) << 12) -#define G_02875C_MRT3_COLOR_OPT_DISABLE(x) (((x) >> 12) & 0x1) -#define C_02875C_MRT3_COLOR_OPT_DISABLE 0xFFFFEFFF -#define S_02875C_MRT3_ALPHA_OPT_DISABLE(x) (((x) & 0x1) << 13) -#define G_02875C_MRT3_ALPHA_OPT_DISABLE(x) (((x) >> 13) & 0x1) -#define C_02875C_MRT3_ALPHA_OPT_DISABLE 0xFFFFDFFF -#define S_02875C_MRT4_COLOR_OPT_DISABLE(x) (((x) & 0x1) << 16) -#define G_02875C_MRT4_COLOR_OPT_DISABLE(x) (((x) >> 16) & 0x1) -#define C_02875C_MRT4_COLOR_OPT_DISABLE 0xFFFEFFFF -#define S_02875C_MRT4_ALPHA_OPT_DISABLE(x) (((x) & 0x1) << 17) -#define G_02875C_MRT4_ALPHA_OPT_DISABLE(x) (((x) >> 17) & 0x1) -#define C_02875C_MRT4_ALPHA_OPT_DISABLE 0xFFFDFFFF -#define S_02875C_MRT5_COLOR_OPT_DISABLE(x) (((x) & 0x1) << 20) -#define G_02875C_MRT5_COLOR_OPT_DISABLE(x) (((x) >> 20) & 0x1) -#define C_02875C_MRT5_COLOR_OPT_DISABLE 0xFFEFFFFF -#define S_02875C_MRT5_ALPHA_OPT_DISABLE(x) (((x) & 0x1) << 21) -#define G_02875C_MRT5_ALPHA_OPT_DISABLE(x) (((x) >> 21) & 0x1) -#define C_02875C_MRT5_ALPHA_OPT_DISABLE 0xFFDFFFFF -#define S_02875C_MRT6_COLOR_OPT_DISABLE(x) (((x) & 0x1) << 24) -#define G_02875C_MRT6_COLOR_OPT_DISABLE(x) (((x) >> 24) & 0x1) -#define C_02875C_MRT6_COLOR_OPT_DISABLE 0xFEFFFFFF -#define S_02875C_MRT6_ALPHA_OPT_DISABLE(x) (((x) & 0x1) << 25) -#define G_02875C_MRT6_ALPHA_OPT_DISABLE(x) (((x) >> 25) & 0x1) -#define C_02875C_MRT6_ALPHA_OPT_DISABLE 0xFDFFFFFF -#define S_02875C_MRT7_COLOR_OPT_DISABLE(x) (((x) & 0x1) << 28) -#define G_02875C_MRT7_COLOR_OPT_DISABLE(x) (((x) >> 28) & 0x1) -#define C_02875C_MRT7_COLOR_OPT_DISABLE 0xEFFFFFFF -#define S_02875C_MRT7_ALPHA_OPT_DISABLE(x) (((x) & 0x1) << 29) -#define G_02875C_MRT7_ALPHA_OPT_DISABLE(x) (((x) >> 29) & 0x1) -#define C_02875C_MRT7_ALPHA_OPT_DISABLE 0xDFFFFFFF -#define S_02875C_PIXEN_ZERO_OPT_DISABLE(x) (((x) & 0x1) << 31) -#define G_02875C_PIXEN_ZERO_OPT_DISABLE(x) (((x) >> 31) & 0x1) -#define C_02875C_PIXEN_ZERO_OPT_DISABLE 0x7FFFFFFF -#define R_028760_SX_MRT0_BLEND_OPT 0x028760 -#define S_028760_COLOR_SRC_OPT(x) (((x) & 0x07) << 0) -#define G_028760_COLOR_SRC_OPT(x) (((x) >> 0) & 0x07) -#define C_028760_COLOR_SRC_OPT 0xFFFFFFF8 -#define V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL 0 -#define V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE 1 -#define V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0 2 -#define V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1 3 -#define V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0 4 -#define V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1 5 -#define V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0 6 -#define V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE 7 -#define S_028760_COLOR_DST_OPT(x) (((x) & 0x07) << 4) -#define G_028760_COLOR_DST_OPT(x) (((x) >> 4) & 0x07) -#define C_028760_COLOR_DST_OPT 0xFFFFFF8F -#define S_028760_COLOR_COMB_FCN(x) (((x) & 0x07) << 8) -#define G_028760_COLOR_COMB_FCN(x) (((x) >> 8) & 0x07) -#define C_028760_COLOR_COMB_FCN 0xFFFFF8FF -#define V_028760_OPT_COMB_NONE 0 -#define V_028760_OPT_COMB_ADD 1 -#define V_028760_OPT_COMB_SUBTRACT 2 -#define V_028760_OPT_COMB_MIN 3 -#define V_028760_OPT_COMB_MAX 4 -#define V_028760_OPT_COMB_REVSUBTRACT 5 -#define V_028760_OPT_COMB_BLEND_DISABLED 6 -#define V_028760_OPT_COMB_SAFE_ADD 7 -#define S_028760_ALPHA_SRC_OPT(x) (((x) & 0x07) << 16) -#define G_028760_ALPHA_SRC_OPT(x) (((x) >> 16) & 0x07) -#define C_028760_ALPHA_SRC_OPT 0xFFF8FFFF -#define S_028760_ALPHA_DST_OPT(x) (((x) & 0x07) << 20) -#define G_028760_ALPHA_DST_OPT(x) (((x) >> 20) & 0x07) -#define C_028760_ALPHA_DST_OPT 0xFF8FFFFF -#define S_028760_ALPHA_COMB_FCN(x) (((x) & 0x07) << 24) -#define G_028760_ALPHA_COMB_FCN(x) (((x) >> 24) & 0x07) -#define C_028760_ALPHA_COMB_FCN 0xF8FFFFFF -#define R_028764_SX_MRT1_BLEND_OPT 0x028764 -#define S_028764_COLOR_SRC_OPT(x) (((x) & 0x07) << 0) -#define G_028764_COLOR_SRC_OPT(x) (((x) >> 0) & 0x07) -#define C_028764_COLOR_SRC_OPT 0xFFFFFFF8 -#define S_028764_COLOR_DST_OPT(x) (((x) & 0x07) << 4) -#define G_028764_COLOR_DST_OPT(x) (((x) >> 4) & 0x07) -#define C_028764_COLOR_DST_OPT 0xFFFFFF8F -#define S_028764_COLOR_COMB_FCN(x) (((x) & 0x07) << 8) -#define G_028764_COLOR_COMB_FCN(x) (((x) >> 8) & 0x07) -#define C_028764_COLOR_COMB_FCN 0xFFFFF8FF -#define S_028764_ALPHA_SRC_OPT(x) (((x) & 0x07) << 16) -#define G_028764_ALPHA_SRC_OPT(x) (((x) >> 16) & 0x07) -#define C_028764_ALPHA_SRC_OPT 0xFFF8FFFF -#define S_028764_ALPHA_DST_OPT(x) (((x) & 0x07) << 20) -#define G_028764_ALPHA_DST_OPT(x) (((x) >> 20) & 0x07) -#define C_028764_ALPHA_DST_OPT 0xFF8FFFFF -#define S_028764_ALPHA_COMB_FCN(x) (((x) & 0x07) << 24) -#define G_028764_ALPHA_COMB_FCN(x) (((x) >> 24) & 0x07) -#define C_028764_ALPHA_COMB_FCN 0xF8FFFFFF -#define R_028768_SX_MRT2_BLEND_OPT 0x028768 -#define S_028768_COLOR_SRC_OPT(x) (((x) & 0x07) << 0) -#define G_028768_COLOR_SRC_OPT(x) (((x) >> 0) & 0x07) -#define C_028768_COLOR_SRC_OPT 0xFFFFFFF8 -#define S_028768_COLOR_DST_OPT(x) (((x) & 0x07) << 4) -#define G_028768_COLOR_DST_OPT(x) (((x) >> 4) & 0x07) -#define C_028768_COLOR_DST_OPT 0xFFFFFF8F -#define S_028768_COLOR_COMB_FCN(x) (((x) & 0x07) << 8) -#define G_028768_COLOR_COMB_FCN(x) (((x) >> 8) & 0x07) -#define C_028768_COLOR_COMB_FCN 0xFFFFF8FF -#define S_028768_ALPHA_SRC_OPT(x) (((x) & 0x07) << 16) -#define G_028768_ALPHA_SRC_OPT(x) (((x) >> 16) & 0x07) -#define C_028768_ALPHA_SRC_OPT 0xFFF8FFFF -#define S_028768_ALPHA_DST_OPT(x) (((x) & 0x07) << 20) -#define G_028768_ALPHA_DST_OPT(x) (((x) >> 20) & 0x07) -#define C_028768_ALPHA_DST_OPT 0xFF8FFFFF -#define S_028768_ALPHA_COMB_FCN(x) (((x) & 0x07) << 24) -#define G_028768_ALPHA_COMB_FCN(x) (((x) >> 24) & 0x07) -#define C_028768_ALPHA_COMB_FCN 0xF8FFFFFF -#define R_02876C_SX_MRT3_BLEND_OPT 0x02876C -#define S_02876C_COLOR_SRC_OPT(x) (((x) & 0x07) << 0) -#define G_02876C_COLOR_SRC_OPT(x) (((x) >> 0) & 0x07) -#define C_02876C_COLOR_SRC_OPT 0xFFFFFFF8 -#define S_02876C_COLOR_DST_OPT(x) (((x) & 0x07) << 4) -#define G_02876C_COLOR_DST_OPT(x) (((x) >> 4) & 0x07) -#define C_02876C_COLOR_DST_OPT 0xFFFFFF8F -#define S_02876C_COLOR_COMB_FCN(x) (((x) & 0x07) << 8) -#define G_02876C_COLOR_COMB_FCN(x) (((x) >> 8) & 0x07) -#define C_02876C_COLOR_COMB_FCN 0xFFFFF8FF -#define S_02876C_ALPHA_SRC_OPT(x) (((x) & 0x07) << 16) -#define G_02876C_ALPHA_SRC_OPT(x) (((x) >> 16) & 0x07) -#define C_02876C_ALPHA_SRC_OPT 0xFFF8FFFF -#define S_02876C_ALPHA_DST_OPT(x) (((x) & 0x07) << 20) -#define G_02876C_ALPHA_DST_OPT(x) (((x) >> 20) & 0x07) -#define C_02876C_ALPHA_DST_OPT 0xFF8FFFFF -#define S_02876C_ALPHA_COMB_FCN(x) (((x) & 0x07) << 24) -#define G_02876C_ALPHA_COMB_FCN(x) (((x) >> 24) & 0x07) -#define C_02876C_ALPHA_COMB_FCN 0xF8FFFFFF -#define R_028770_SX_MRT4_BLEND_OPT 0x028770 -#define S_028770_COLOR_SRC_OPT(x) (((x) & 0x07) << 0) -#define G_028770_COLOR_SRC_OPT(x) (((x) >> 0) & 0x07) -#define C_028770_COLOR_SRC_OPT 0xFFFFFFF8 -#define S_028770_COLOR_DST_OPT(x) (((x) & 0x07) << 4) -#define G_028770_COLOR_DST_OPT(x) (((x) >> 4) & 0x07) -#define C_028770_COLOR_DST_OPT 0xFFFFFF8F -#define S_028770_COLOR_COMB_FCN(x) (((x) & 0x07) << 8) -#define G_028770_COLOR_COMB_FCN(x) (((x) >> 8) & 0x07) -#define C_028770_COLOR_COMB_FCN 0xFFFFF8FF -#define S_028770_ALPHA_SRC_OPT(x) (((x) & 0x07) << 16) -#define G_028770_ALPHA_SRC_OPT(x) (((x) >> 16) & 0x07) -#define C_028770_ALPHA_SRC_OPT 0xFFF8FFFF -#define S_028770_ALPHA_DST_OPT(x) (((x) & 0x07) << 20) -#define G_028770_ALPHA_DST_OPT(x) (((x) >> 20) & 0x07) -#define C_028770_ALPHA_DST_OPT 0xFF8FFFFF -#define S_028770_ALPHA_COMB_FCN(x) (((x) & 0x07) << 24) -#define G_028770_ALPHA_COMB_FCN(x) (((x) >> 24) & 0x07) -#define C_028770_ALPHA_COMB_FCN 0xF8FFFFFF -#define R_028774_SX_MRT5_BLEND_OPT 0x028774 -#define S_028774_COLOR_SRC_OPT(x) (((x) & 0x07) << 0) -#define G_028774_COLOR_SRC_OPT(x) (((x) >> 0) & 0x07) -#define C_028774_COLOR_SRC_OPT 0xFFFFFFF8 -#define S_028774_COLOR_DST_OPT(x) (((x) & 0x07) << 4) -#define G_028774_COLOR_DST_OPT(x) (((x) >> 4) & 0x07) -#define C_028774_COLOR_DST_OPT 0xFFFFFF8F -#define S_028774_COLOR_COMB_FCN(x) (((x) & 0x07) << 8) -#define G_028774_COLOR_COMB_FCN(x) (((x) >> 8) & 0x07) -#define C_028774_COLOR_COMB_FCN 0xFFFFF8FF -#define S_028774_ALPHA_SRC_OPT(x) (((x) & 0x07) << 16) -#define G_028774_ALPHA_SRC_OPT(x) (((x) >> 16) & 0x07) -#define C_028774_ALPHA_SRC_OPT 0xFFF8FFFF -#define S_028774_ALPHA_DST_OPT(x) (((x) & 0x07) << 20) -#define G_028774_ALPHA_DST_OPT(x) (((x) >> 20) & 0x07) -#define C_028774_ALPHA_DST_OPT 0xFF8FFFFF -#define S_028774_ALPHA_COMB_FCN(x) (((x) & 0x07) << 24) -#define G_028774_ALPHA_COMB_FCN(x) (((x) >> 24) & 0x07) -#define C_028774_ALPHA_COMB_FCN 0xF8FFFFFF -#define R_028778_SX_MRT6_BLEND_OPT 0x028778 -#define S_028778_COLOR_SRC_OPT(x) (((x) & 0x07) << 0) -#define G_028778_COLOR_SRC_OPT(x) (((x) >> 0) & 0x07) -#define C_028778_COLOR_SRC_OPT 0xFFFFFFF8 -#define S_028778_COLOR_DST_OPT(x) (((x) & 0x07) << 4) -#define G_028778_COLOR_DST_OPT(x) (((x) >> 4) & 0x07) -#define C_028778_COLOR_DST_OPT 0xFFFFFF8F -#define S_028778_COLOR_COMB_FCN(x) (((x) & 0x07) << 8) -#define G_028778_COLOR_COMB_FCN(x) (((x) >> 8) & 0x07) -#define C_028778_COLOR_COMB_FCN 0xFFFFF8FF -#define S_028778_ALPHA_SRC_OPT(x) (((x) & 0x07) << 16) -#define G_028778_ALPHA_SRC_OPT(x) (((x) >> 16) & 0x07) -#define C_028778_ALPHA_SRC_OPT 0xFFF8FFFF -#define S_028778_ALPHA_DST_OPT(x) (((x) & 0x07) << 20) -#define G_028778_ALPHA_DST_OPT(x) (((x) >> 20) & 0x07) -#define C_028778_ALPHA_DST_OPT 0xFF8FFFFF -#define S_028778_ALPHA_COMB_FCN(x) (((x) & 0x07) << 24) -#define G_028778_ALPHA_COMB_FCN(x) (((x) >> 24) & 0x07) -#define C_028778_ALPHA_COMB_FCN 0xF8FFFFFF -#define R_02877C_SX_MRT7_BLEND_OPT 0x02877C -#define S_02877C_COLOR_SRC_OPT(x) (((x) & 0x07) << 0) -#define G_02877C_COLOR_SRC_OPT(x) (((x) >> 0) & 0x07) -#define C_02877C_COLOR_SRC_OPT 0xFFFFFFF8 -#define S_02877C_COLOR_DST_OPT(x) (((x) & 0x07) << 4) -#define G_02877C_COLOR_DST_OPT(x) (((x) >> 4) & 0x07) -#define C_02877C_COLOR_DST_OPT 0xFFFFFF8F -#define S_02877C_COLOR_COMB_FCN(x) (((x) & 0x07) << 8) -#define G_02877C_COLOR_COMB_FCN(x) (((x) >> 8) & 0x07) -#define C_02877C_COLOR_COMB_FCN 0xFFFFF8FF -#define S_02877C_ALPHA_SRC_OPT(x) (((x) & 0x07) << 16) -#define G_02877C_ALPHA_SRC_OPT(x) (((x) >> 16) & 0x07) -#define C_02877C_ALPHA_SRC_OPT 0xFFF8FFFF -#define S_02877C_ALPHA_DST_OPT(x) (((x) & 0x07) << 20) -#define G_02877C_ALPHA_DST_OPT(x) (((x) >> 20) & 0x07) -#define C_02877C_ALPHA_DST_OPT 0xFF8FFFFF -#define S_02877C_ALPHA_COMB_FCN(x) (((x) & 0x07) << 24) -#define G_02877C_ALPHA_COMB_FCN(x) (((x) >> 24) & 0x07) -#define C_02877C_ALPHA_COMB_FCN 0xF8FFFFFF -/* */ -#define R_028780_CB_BLEND0_CONTROL 0x028780 -#define S_028780_COLOR_SRCBLEND(x) (((x) & 0x1F) << 0) -#define G_028780_COLOR_SRCBLEND(x) (((x) >> 0) & 0x1F) -#define C_028780_COLOR_SRCBLEND 0xFFFFFFE0 -#define V_028780_BLEND_ZERO 0x00 -#define V_028780_BLEND_ONE 0x01 -#define V_028780_BLEND_SRC_COLOR 0x02 -#define V_028780_BLEND_ONE_MINUS_SRC_COLOR 0x03 -#define V_028780_BLEND_SRC_ALPHA 0x04 -#define V_028780_BLEND_ONE_MINUS_SRC_ALPHA 0x05 -#define V_028780_BLEND_DST_ALPHA 0x06 -#define V_028780_BLEND_ONE_MINUS_DST_ALPHA 0x07 -#define V_028780_BLEND_DST_COLOR 0x08 -#define V_028780_BLEND_ONE_MINUS_DST_COLOR 0x09 -#define V_028780_BLEND_SRC_ALPHA_SATURATE 0x0A -#define V_028780_BLEND_CONSTANT_COLOR 0x0D -#define V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0E -#define V_028780_BLEND_SRC1_COLOR 0x0F -#define V_028780_BLEND_INV_SRC1_COLOR 0x10 -#define V_028780_BLEND_SRC1_ALPHA 0x11 -#define V_028780_BLEND_INV_SRC1_ALPHA 0x12 -#define V_028780_BLEND_CONSTANT_ALPHA 0x13 -#define V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14 -#define S_028780_COLOR_COMB_FCN(x) (((x) & 0x07) << 5) -#define G_028780_COLOR_COMB_FCN(x) (((x) >> 5) & 0x07) -#define C_028780_COLOR_COMB_FCN 0xFFFFFF1F -#define V_028780_COMB_DST_PLUS_SRC 0x00 -#define V_028780_COMB_SRC_MINUS_DST 0x01 -#define V_028780_COMB_MIN_DST_SRC 0x02 -#define V_028780_COMB_MAX_DST_SRC 0x03 -#define V_028780_COMB_DST_MINUS_SRC 0x04 -#define S_028780_COLOR_DESTBLEND(x) (((x) & 0x1F) << 8) -#define G_028780_COLOR_DESTBLEND(x) (((x) >> 8) & 0x1F) -#define C_028780_COLOR_DESTBLEND 0xFFFFE0FF -#define V_028780_BLEND_ZERO 0x00 -#define V_028780_BLEND_ONE 0x01 -#define V_028780_BLEND_SRC_COLOR 0x02 -#define V_028780_BLEND_ONE_MINUS_SRC_COLOR 0x03 -#define V_028780_BLEND_SRC_ALPHA 0x04 -#define V_028780_BLEND_ONE_MINUS_SRC_ALPHA 0x05 -#define V_028780_BLEND_DST_ALPHA 0x06 -#define V_028780_BLEND_ONE_MINUS_DST_ALPHA 0x07 -#define V_028780_BLEND_DST_COLOR 0x08 -#define V_028780_BLEND_ONE_MINUS_DST_COLOR 0x09 -#define V_028780_BLEND_SRC_ALPHA_SATURATE 0x0A -#define V_028780_BLEND_CONSTANT_COLOR 0x0D -#define V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0E -#define V_028780_BLEND_SRC1_COLOR 0x0F -#define V_028780_BLEND_INV_SRC1_COLOR 0x10 -#define V_028780_BLEND_SRC1_ALPHA 0x11 -#define V_028780_BLEND_INV_SRC1_ALPHA 0x12 -#define V_028780_BLEND_CONSTANT_ALPHA 0x13 -#define V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14 -#define S_028780_ALPHA_SRCBLEND(x) (((x) & 0x1F) << 16) -#define G_028780_ALPHA_SRCBLEND(x) (((x) >> 16) & 0x1F) -#define C_028780_ALPHA_SRCBLEND 0xFFE0FFFF -#define V_028780_BLEND_ZERO 0x00 -#define V_028780_BLEND_ONE 0x01 -#define V_028780_BLEND_SRC_COLOR 0x02 -#define V_028780_BLEND_ONE_MINUS_SRC_COLOR 0x03 -#define V_028780_BLEND_SRC_ALPHA 0x04 -#define V_028780_BLEND_ONE_MINUS_SRC_ALPHA 0x05 -#define V_028780_BLEND_DST_ALPHA 0x06 -#define V_028780_BLEND_ONE_MINUS_DST_ALPHA 0x07 -#define V_028780_BLEND_DST_COLOR 0x08 -#define V_028780_BLEND_ONE_MINUS_DST_COLOR 0x09 -#define V_028780_BLEND_SRC_ALPHA_SATURATE 0x0A -#define V_028780_BLEND_CONSTANT_COLOR 0x0D -#define V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0E -#define V_028780_BLEND_SRC1_COLOR 0x0F -#define V_028780_BLEND_INV_SRC1_COLOR 0x10 -#define V_028780_BLEND_SRC1_ALPHA 0x11 -#define V_028780_BLEND_INV_SRC1_ALPHA 0x12 -#define V_028780_BLEND_CONSTANT_ALPHA 0x13 -#define V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14 -#define S_028780_ALPHA_COMB_FCN(x) (((x) & 0x07) << 21) -#define G_028780_ALPHA_COMB_FCN(x) (((x) >> 21) & 0x07) -#define C_028780_ALPHA_COMB_FCN 0xFF1FFFFF -#define V_028780_COMB_DST_PLUS_SRC 0x00 -#define V_028780_COMB_SRC_MINUS_DST 0x01 -#define V_028780_COMB_MIN_DST_SRC 0x02 -#define V_028780_COMB_MAX_DST_SRC 0x03 -#define V_028780_COMB_DST_MINUS_SRC 0x04 -#define S_028780_ALPHA_DESTBLEND(x) (((x) & 0x1F) << 24) -#define G_028780_ALPHA_DESTBLEND(x) (((x) >> 24) & 0x1F) -#define C_028780_ALPHA_DESTBLEND 0xE0FFFFFF -#define V_028780_BLEND_ZERO 0x00 -#define V_028780_BLEND_ONE 0x01 -#define V_028780_BLEND_SRC_COLOR 0x02 -#define V_028780_BLEND_ONE_MINUS_SRC_COLOR 0x03 -#define V_028780_BLEND_SRC_ALPHA 0x04 -#define V_028780_BLEND_ONE_MINUS_SRC_ALPHA 0x05 -#define V_028780_BLEND_DST_ALPHA 0x06 -#define V_028780_BLEND_ONE_MINUS_DST_ALPHA 0x07 -#define V_028780_BLEND_DST_COLOR 0x08 -#define V_028780_BLEND_ONE_MINUS_DST_COLOR 0x09 -#define V_028780_BLEND_SRC_ALPHA_SATURATE 0x0A -#define V_028780_BLEND_CONSTANT_COLOR 0x0D -#define V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR 0x0E -#define V_028780_BLEND_SRC1_COLOR 0x0F -#define V_028780_BLEND_INV_SRC1_COLOR 0x10 -#define V_028780_BLEND_SRC1_ALPHA 0x11 -#define V_028780_BLEND_INV_SRC1_ALPHA 0x12 -#define V_028780_BLEND_CONSTANT_ALPHA 0x13 -#define V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA 0x14 -#define S_028780_SEPARATE_ALPHA_BLEND(x) (((x) & 0x1) << 29) -#define G_028780_SEPARATE_ALPHA_BLEND(x) (((x) >> 29) & 0x1) -#define C_028780_SEPARATE_ALPHA_BLEND 0xDFFFFFFF -#define S_028780_ENABLE(x) (((x) & 0x1) << 30) -#define G_028780_ENABLE(x) (((x) >> 30) & 0x1) -#define C_028780_ENABLE 0xBFFFFFFF -#define S_028780_DISABLE_ROP3(x) (((x) & 0x1) << 31) -#define G_028780_DISABLE_ROP3(x) (((x) >> 31) & 0x1) -#define C_028780_DISABLE_ROP3 0x7FFFFFFF -#define R_028784_CB_BLEND1_CONTROL 0x028784 -#define R_028788_CB_BLEND2_CONTROL 0x028788 -#define R_02878C_CB_BLEND3_CONTROL 0x02878C -#define R_028790_CB_BLEND4_CONTROL 0x028790 -#define R_028794_CB_BLEND5_CONTROL 0x028794 -#define R_028798_CB_BLEND6_CONTROL 0x028798 -#define R_02879C_CB_BLEND7_CONTROL 0x02879C -#define R_0287CC_CS_COPY_STATE 0x0287CC -#define S_0287CC_SRC_STATE_ID(x) (((x) & 0x07) << 0) -#define G_0287CC_SRC_STATE_ID(x) (((x) >> 0) & 0x07) -#define C_0287CC_SRC_STATE_ID 0xFFFFFFF8 -#define R_0287D4_PA_CL_POINT_X_RAD 0x0287D4 -#define R_0287D8_PA_CL_POINT_Y_RAD 0x0287D8 -#define R_0287DC_PA_CL_POINT_SIZE 0x0287DC -#define R_0287E0_PA_CL_POINT_CULL_RAD 0x0287E0 -#define R_0287E4_VGT_DMA_BASE_HI 0x0287E4 -#define S_0287E4_BASE_ADDR(x) (((x) & 0xFF) << 0) -#define G_0287E4_BASE_ADDR(x) (((x) >> 0) & 0xFF) -#define C_0287E4_BASE_ADDR 0xFFFFFF00 -#define R_0287E8_VGT_DMA_BASE 0x0287E8 -#define R_0287F0_VGT_DRAW_INITIATOR 0x0287F0 -#define S_0287F0_SOURCE_SELECT(x) (((x) & 0x03) << 0) -#define G_0287F0_SOURCE_SELECT(x) (((x) >> 0) & 0x03) -#define C_0287F0_SOURCE_SELECT 0xFFFFFFFC -#define V_0287F0_DI_SRC_SEL_DMA 0x00 -#define V_0287F0_DI_SRC_SEL_IMMEDIATE 0x01 /* not on CIK */ -#define V_0287F0_DI_SRC_SEL_AUTO_INDEX 0x02 -#define V_0287F0_DI_SRC_SEL_RESERVED 0x03 -#define S_0287F0_MAJOR_MODE(x) (((x) & 0x03) << 2) -#define G_0287F0_MAJOR_MODE(x) (((x) >> 2) & 0x03) -#define C_0287F0_MAJOR_MODE 0xFFFFFFF3 -#define V_0287F0_DI_MAJOR_MODE_0 0x00 -#define V_0287F0_DI_MAJOR_MODE_1 0x01 -#define S_0287F0_NOT_EOP(x) (((x) & 0x1) << 5) -#define G_0287F0_NOT_EOP(x) (((x) >> 5) & 0x1) -#define C_0287F0_NOT_EOP 0xFFFFFFDF -#define S_0287F0_USE_OPAQUE(x) (((x) & 0x1) << 6) -#define G_0287F0_USE_OPAQUE(x) (((x) >> 6) & 0x1) -#define C_0287F0_USE_OPAQUE 0xFFFFFFBF -#define R_0287F4_VGT_IMMED_DATA 0x0287F4 /* not on CIK */ -#define R_0287F8_VGT_EVENT_ADDRESS_REG 0x0287F8 -#define S_0287F8_ADDRESS_LOW(x) (((x) & 0xFFFFFFF) << 0) -#define G_0287F8_ADDRESS_LOW(x) (((x) >> 0) & 0xFFFFFFF) -#define C_0287F8_ADDRESS_LOW 0xF0000000 -#define R_028800_DB_DEPTH_CONTROL 0x028800 -#define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0) -#define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1) -#define C_028800_STENCIL_ENABLE 0xFFFFFFFE -#define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1) -#define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1) -#define C_028800_Z_ENABLE 0xFFFFFFFD -#define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2) -#define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1) -#define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB -#define S_028800_DEPTH_BOUNDS_ENABLE(x) (((x) & 0x1) << 3) -#define G_028800_DEPTH_BOUNDS_ENABLE(x) (((x) >> 3) & 0x1) -#define C_028800_DEPTH_BOUNDS_ENABLE 0xFFFFFFF7 -#define S_028800_ZFUNC(x) (((x) & 0x07) << 4) -#define G_028800_ZFUNC(x) (((x) >> 4) & 0x07) -#define C_028800_ZFUNC 0xFFFFFF8F -#define V_028800_FRAG_NEVER 0x00 -#define V_028800_FRAG_LESS 0x01 -#define V_028800_FRAG_EQUAL 0x02 -#define V_028800_FRAG_LEQUAL 0x03 -#define V_028800_FRAG_GREATER 0x04 -#define V_028800_FRAG_NOTEQUAL 0x05 -#define V_028800_FRAG_GEQUAL 0x06 -#define V_028800_FRAG_ALWAYS 0x07 -#define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7) -#define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1) -#define C_028800_BACKFACE_ENABLE 0xFFFFFF7F -#define S_028800_STENCILFUNC(x) (((x) & 0x07) << 8) -#define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x07) -#define C_028800_STENCILFUNC 0xFFFFF8FF -#define V_028800_REF_NEVER 0x00 -#define V_028800_REF_LESS 0x01 -#define V_028800_REF_EQUAL 0x02 -#define V_028800_REF_LEQUAL 0x03 -#define V_028800_REF_GREATER 0x04 -#define V_028800_REF_NOTEQUAL 0x05 -#define V_028800_REF_GEQUAL 0x06 -#define V_028800_REF_ALWAYS 0x07 -#define S_028800_STENCILFUNC_BF(x) (((x) & 0x07) << 20) -#define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x07) -#define C_028800_STENCILFUNC_BF 0xFF8FFFFF -#define V_028800_REF_NEVER 0x00 -#define V_028800_REF_LESS 0x01 -#define V_028800_REF_EQUAL 0x02 -#define V_028800_REF_LEQUAL 0x03 -#define V_028800_REF_GREATER 0x04 -#define V_028800_REF_NOTEQUAL 0x05 -#define V_028800_REF_GEQUAL 0x06 -#define V_028800_REF_ALWAYS 0x07 -#define S_028800_ENABLE_COLOR_WRITES_ON_DEPTH_FAIL(x) (((x) & 0x1) << 30) -#define G_028800_ENABLE_COLOR_WRITES_ON_DEPTH_FAIL(x) (((x) >> 30) & 0x1) -#define C_028800_ENABLE_COLOR_WRITES_ON_DEPTH_FAIL 0xBFFFFFFF -#define S_028800_DISABLE_COLOR_WRITES_ON_DEPTH_PASS(x) (((x) & 0x1) << 31) -#define G_028800_DISABLE_COLOR_WRITES_ON_DEPTH_PASS(x) (((x) >> 31) & 0x1) -#define C_028800_DISABLE_COLOR_WRITES_ON_DEPTH_PASS 0x7FFFFFFF -#define R_028804_DB_EQAA 0x028804 -#define S_028804_MAX_ANCHOR_SAMPLES(x) (((x) & 0x7) << 0) -#define G_028804_MAX_ANCHOR_SAMPLES(x) (((x) >> 0) & 0x07) -#define C_028804_MAX_ANCHOR_SAMPLES 0xFFFFFFF8 -#define S_028804_PS_ITER_SAMPLES(x) (((x) & 0x7) << 4) -#define G_028804_PS_ITER_SAMPLES(x) (((x) >> 4) & 0x07) -#define C_028804_PS_ITER_SAMPLES 0xFFFFFF8F -#define S_028804_MASK_EXPORT_NUM_SAMPLES(x) (((x) & 0x7) << 8) -#define G_028804_MASK_EXPORT_NUM_SAMPLES(x) (((x) >> 8) & 0x07) -#define C_028804_MASK_EXPORT_NUM_SAMPLES 0xFFFFF8FF -#define S_028804_ALPHA_TO_MASK_NUM_SAMPLES(x) (((x) & 0x7) << 12) -#define G_028804_ALPHA_TO_MASK_NUM_SAMPLES(x) (((x) >> 12) & 0x07) -#define C_028804_ALPHA_TO_MASK_NUM_SAMPLES 0xFFFF8FFF -#define S_028804_HIGH_QUALITY_INTERSECTIONS(x) (((x) & 0x1) << 16) -#define G_028804_HIGH_QUALITY_INTERSECTIONS(x) (((x) >> 16) & 0x1) -#define C_028804_HIGH_QUALITY_INTERSECTIONS 0xFFFEFFFF -#define S_028804_INCOHERENT_EQAA_READS(x) (((x) & 0x1) << 17) -#define G_028804_INCOHERENT_EQAA_READS(x) (((x) >> 17) & 0x1) -#define C_028804_INCOHERENT_EQAA_READS 0xFFFDFFFF -#define S_028804_INTERPOLATE_COMP_Z(x) (((x) & 0x1) << 18) -#define G_028804_INTERPOLATE_COMP_Z(x) (((x) >> 18) & 0x1) -#define C_028804_INTERPOLATE_COMP_Z 0xFFFBFFFF -#define S_028804_INTERPOLATE_SRC_Z(x) (((x) & 0x1) << 19) -#define G_028804_INTERPOLATE_SRC_Z(x) (((x) >> 19) & 0x1) -#define C_028804_INTERPOLATE_SRC_Z 0xFFF7FFFF -#define S_028804_STATIC_ANCHOR_ASSOCIATIONS(x) (((x) & 0x1) << 20) -#define G_028804_STATIC_ANCHOR_ASSOCIATIONS(x) (((x) >> 20) & 0x1) -#define C_028804_STATIC_ANCHOR_ASSOCIATIONS 0xFFEFFFFF -#define S_028804_ALPHA_TO_MASK_EQAA_DISABLE(x) (((x) & 0x1) << 21) -#define G_028804_ALPHA_TO_MASK_EQAA_DISABLE(x) (((x) >> 21) & 0x1) -#define C_028804_ALPHA_TO_MASK_EQAA_DISABLE 0xFFDFFFFF -#define S_028804_OVERRASTERIZATION_AMOUNT(x) (((x) & 0x07) << 24) -#define G_028804_OVERRASTERIZATION_AMOUNT(x) (((x) >> 24) & 0x07) -#define C_028804_OVERRASTERIZATION_AMOUNT 0xF8FFFFFF -#define S_028804_ENABLE_POSTZ_OVERRASTERIZATION(x) (((x) & 0x1) << 27) -#define G_028804_ENABLE_POSTZ_OVERRASTERIZATION(x) (((x) >> 27) & 0x1) -#define C_028804_ENABLE_POSTZ_OVERRASTERIZATION 0xF7FFFFFF -#define R_028808_CB_COLOR_CONTROL 0x028808 -#define S_028808_DEGAMMA_ENABLE(x) (((x) & 0x1) << 3) -#define G_028808_DEGAMMA_ENABLE(x) (((x) >> 3) & 0x1) -#define C_028808_DEGAMMA_ENABLE 0xFFFFFFF7 -#define S_028808_MODE(x) (((x) & 0x07) << 4) -#define G_028808_MODE(x) (((x) >> 4) & 0x07) -#define C_028808_MODE 0xFFFFFF8F -#define V_028808_CB_DISABLE 0x00 -#define V_028808_CB_NORMAL 0x01 -#define V_028808_CB_ELIMINATE_FAST_CLEAR 0x02 -#define V_028808_CB_RESOLVE 0x03 -#define V_028808_CB_FMASK_DECOMPRESS 0x05 -#define V_028808_CB_DCC_DECOMPRESS 0x06 -#define S_028808_ROP3(x) (((x) & 0xFF) << 16) -#define G_028808_ROP3(x) (((x) >> 16) & 0xFF) -#define C_028808_ROP3 0xFF00FFFF -#define V_028808_X_0X00 0x00 -#define V_028808_X_0X05 0x05 -#define V_028808_X_0X0A 0x0A -#define V_028808_X_0X0F 0x0F -#define V_028808_X_0X11 0x11 -#define V_028808_X_0X22 0x22 -#define V_028808_X_0X33 0x33 -#define V_028808_X_0X44 0x44 -#define V_028808_X_0X50 0x50 -#define V_028808_X_0X55 0x55 -#define V_028808_X_0X5A 0x5A -#define V_028808_X_0X5F 0x5F -#define V_028808_X_0X66 0x66 -#define V_028808_X_0X77 0x77 -#define V_028808_X_0X88 0x88 -#define V_028808_X_0X99 0x99 -#define V_028808_X_0XA0 0xA0 -#define V_028808_X_0XA5 0xA5 -#define V_028808_X_0XAA 0xAA -#define V_028808_X_0XAF 0xAF -#define V_028808_X_0XBB 0xBB -#define V_028808_X_0XCC 0xCC -#define V_028808_X_0XDD 0xDD -#define V_028808_X_0XEE 0xEE -#define V_028808_X_0XF0 0xF0 -#define V_028808_X_0XF5 0xF5 -#define V_028808_X_0XFA 0xFA -#define V_028808_X_0XFF 0xFF -#define R_02880C_DB_SHADER_CONTROL 0x02880C -#define S_02880C_Z_EXPORT_ENABLE(x) (((x) & 0x1) << 0) -#define G_02880C_Z_EXPORT_ENABLE(x) (((x) >> 0) & 0x1) -#define C_02880C_Z_EXPORT_ENABLE 0xFFFFFFFE -#define S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(x) (((x) & 0x1) << 1) -#define G_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(x) (((x) >> 1) & 0x1) -#define C_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE 0xFFFFFFFD -#define S_02880C_STENCIL_OP_VAL_EXPORT_ENABLE(x) (((x) & 0x1) << 2) -#define G_02880C_STENCIL_OP_VAL_EXPORT_ENABLE(x) (((x) >> 2) & 0x1) -#define C_02880C_STENCIL_OP_VAL_EXPORT_ENABLE 0xFFFFFFFB -#define S_02880C_Z_ORDER(x) (((x) & 0x03) << 4) -#define G_02880C_Z_ORDER(x) (((x) >> 4) & 0x03) -#define C_02880C_Z_ORDER 0xFFFFFFCF -#define V_02880C_LATE_Z 0x00 -#define V_02880C_EARLY_Z_THEN_LATE_Z 0x01 -#define V_02880C_RE_Z 0x02 -#define V_02880C_EARLY_Z_THEN_RE_Z 0x03 -#define S_02880C_KILL_ENABLE(x) (((x) & 0x1) << 6) -#define G_02880C_KILL_ENABLE(x) (((x) >> 6) & 0x1) -#define C_02880C_KILL_ENABLE 0xFFFFFFBF -#define S_02880C_COVERAGE_TO_MASK_ENABLE(x) (((x) & 0x1) << 7) -#define G_02880C_COVERAGE_TO_MASK_ENABLE(x) (((x) >> 7) & 0x1) -#define C_02880C_COVERAGE_TO_MASK_ENABLE 0xFFFFFF7F -#define S_02880C_MASK_EXPORT_ENABLE(x) (((x) & 0x1) << 8) -#define G_02880C_MASK_EXPORT_ENABLE(x) (((x) >> 8) & 0x1) -#define C_02880C_MASK_EXPORT_ENABLE 0xFFFFFEFF -#define S_02880C_EXEC_ON_HIER_FAIL(x) (((x) & 0x1) << 9) -#define G_02880C_EXEC_ON_HIER_FAIL(x) (((x) >> 9) & 0x1) -#define C_02880C_EXEC_ON_HIER_FAIL 0xFFFFFDFF -#define S_02880C_EXEC_ON_NOOP(x) (((x) & 0x1) << 10) -#define G_02880C_EXEC_ON_NOOP(x) (((x) >> 10) & 0x1) -#define C_02880C_EXEC_ON_NOOP 0xFFFFFBFF -#define S_02880C_ALPHA_TO_MASK_DISABLE(x) (((x) & 0x1) << 11) -#define G_02880C_ALPHA_TO_MASK_DISABLE(x) (((x) >> 11) & 0x1) -#define C_02880C_ALPHA_TO_MASK_DISABLE 0xFFFFF7FF -#define S_02880C_DEPTH_BEFORE_SHADER(x) (((x) & 0x1) << 12) -#define G_02880C_DEPTH_BEFORE_SHADER(x) (((x) >> 12) & 0x1) -#define C_02880C_DEPTH_BEFORE_SHADER 0xFFFFEFFF -/* CIK */ -#define S_02880C_CONSERVATIVE_Z_EXPORT(x) (((x) & 0x03) << 13) -#define G_02880C_CONSERVATIVE_Z_EXPORT(x) (((x) >> 13) & 0x03) -#define C_02880C_CONSERVATIVE_Z_EXPORT 0xFFFF9FFF -#define V_02880C_EXPORT_ANY_Z 0 -#define V_02880C_EXPORT_LESS_THAN_Z 1 -#define V_02880C_EXPORT_GREATER_THAN_Z 2 -#define V_02880C_EXPORT_RESERVED 3 -/* */ -/* Stoney */ -#define S_02880C_DUAL_QUAD_DISABLE(x) (((x) & 0x1) << 15) -#define G_02880C_DUAL_QUAD_DISABLE(x) (((x) >> 15) & 0x1) -#define C_02880C_DUAL_QUAD_DISABLE 0xFFFF7FFF -/* */ -#define R_028810_PA_CL_CLIP_CNTL 0x028810 -#define S_028810_UCP_ENA_0(x) (((x) & 0x1) << 0) -#define G_028810_UCP_ENA_0(x) (((x) >> 0) & 0x1) -#define C_028810_UCP_ENA_0 0xFFFFFFFE -#define S_028810_UCP_ENA_1(x) (((x) & 0x1) << 1) -#define G_028810_UCP_ENA_1(x) (((x) >> 1) & 0x1) -#define C_028810_UCP_ENA_1 0xFFFFFFFD -#define S_028810_UCP_ENA_2(x) (((x) & 0x1) << 2) -#define G_028810_UCP_ENA_2(x) (((x) >> 2) & 0x1) -#define C_028810_UCP_ENA_2 0xFFFFFFFB -#define S_028810_UCP_ENA_3(x) (((x) & 0x1) << 3) -#define G_028810_UCP_ENA_3(x) (((x) >> 3) & 0x1) -#define C_028810_UCP_ENA_3 0xFFFFFFF7 -#define S_028810_UCP_ENA_4(x) (((x) & 0x1) << 4) -#define G_028810_UCP_ENA_4(x) (((x) >> 4) & 0x1) -#define C_028810_UCP_ENA_4 0xFFFFFFEF -#define S_028810_UCP_ENA_5(x) (((x) & 0x1) << 5) -#define G_028810_UCP_ENA_5(x) (((x) >> 5) & 0x1) -#define C_028810_UCP_ENA_5 0xFFFFFFDF -#define S_028810_PS_UCP_Y_SCALE_NEG(x) (((x) & 0x1) << 13) -#define G_028810_PS_UCP_Y_SCALE_NEG(x) (((x) >> 13) & 0x1) -#define C_028810_PS_UCP_Y_SCALE_NEG 0xFFFFDFFF -#define S_028810_PS_UCP_MODE(x) (((x) & 0x03) << 14) -#define G_028810_PS_UCP_MODE(x) (((x) >> 14) & 0x03) -#define C_028810_PS_UCP_MODE 0xFFFF3FFF -#define S_028810_CLIP_DISABLE(x) (((x) & 0x1) << 16) -#define G_028810_CLIP_DISABLE(x) (((x) >> 16) & 0x1) -#define C_028810_CLIP_DISABLE 0xFFFEFFFF -#define S_028810_UCP_CULL_ONLY_ENA(x) (((x) & 0x1) << 17) -#define G_028810_UCP_CULL_ONLY_ENA(x) (((x) >> 17) & 0x1) -#define C_028810_UCP_CULL_ONLY_ENA 0xFFFDFFFF -#define S_028810_BOUNDARY_EDGE_FLAG_ENA(x) (((x) & 0x1) << 18) -#define G_028810_BOUNDARY_EDGE_FLAG_ENA(x) (((x) >> 18) & 0x1) -#define C_028810_BOUNDARY_EDGE_FLAG_ENA 0xFFFBFFFF -#define S_028810_DX_CLIP_SPACE_DEF(x) (((x) & 0x1) << 19) -#define G_028810_DX_CLIP_SPACE_DEF(x) (((x) >> 19) & 0x1) -#define C_028810_DX_CLIP_SPACE_DEF 0xFFF7FFFF -#define S_028810_DIS_CLIP_ERR_DETECT(x) (((x) & 0x1) << 20) -#define G_028810_DIS_CLIP_ERR_DETECT(x) (((x) >> 20) & 0x1) -#define C_028810_DIS_CLIP_ERR_DETECT 0xFFEFFFFF -#define S_028810_VTX_KILL_OR(x) (((x) & 0x1) << 21) -#define G_028810_VTX_KILL_OR(x) (((x) >> 21) & 0x1) -#define C_028810_VTX_KILL_OR 0xFFDFFFFF -#define S_028810_DX_RASTERIZATION_KILL(x) (((x) & 0x1) << 22) -#define G_028810_DX_RASTERIZATION_KILL(x) (((x) >> 22) & 0x1) -#define C_028810_DX_RASTERIZATION_KILL 0xFFBFFFFF -#define S_028810_DX_LINEAR_ATTR_CLIP_ENA(x) (((x) & 0x1) << 24) -#define G_028810_DX_LINEAR_ATTR_CLIP_ENA(x) (((x) >> 24) & 0x1) -#define C_028810_DX_LINEAR_ATTR_CLIP_ENA 0xFEFFFFFF -#define S_028810_VTE_VPORT_PROVOKE_DISABLE(x) (((x) & 0x1) << 25) -#define G_028810_VTE_VPORT_PROVOKE_DISABLE(x) (((x) >> 25) & 0x1) -#define C_028810_VTE_VPORT_PROVOKE_DISABLE 0xFDFFFFFF -#define S_028810_ZCLIP_NEAR_DISABLE(x) (((x) & 0x1) << 26) -#define G_028810_ZCLIP_NEAR_DISABLE(x) (((x) >> 26) & 0x1) -#define C_028810_ZCLIP_NEAR_DISABLE 0xFBFFFFFF -#define S_028810_ZCLIP_FAR_DISABLE(x) (((x) & 0x1) << 27) -#define G_028810_ZCLIP_FAR_DISABLE(x) (((x) >> 27) & 0x1) -#define C_028810_ZCLIP_FAR_DISABLE 0xF7FFFFFF -#define R_028814_PA_SU_SC_MODE_CNTL 0x028814 -#define S_028814_CULL_FRONT(x) (((x) & 0x1) << 0) -#define G_028814_CULL_FRONT(x) (((x) >> 0) & 0x1) -#define C_028814_CULL_FRONT 0xFFFFFFFE -#define S_028814_CULL_BACK(x) (((x) & 0x1) << 1) -#define G_028814_CULL_BACK(x) (((x) >> 1) & 0x1) -#define C_028814_CULL_BACK 0xFFFFFFFD -#define S_028814_FACE(x) (((x) & 0x1) << 2) -#define G_028814_FACE(x) (((x) >> 2) & 0x1) -#define C_028814_FACE 0xFFFFFFFB -#define S_028814_POLY_MODE(x) (((x) & 0x03) << 3) -#define G_028814_POLY_MODE(x) (((x) >> 3) & 0x03) -#define C_028814_POLY_MODE 0xFFFFFFE7 -#define V_028814_X_DISABLE_POLY_MODE 0x00 -#define V_028814_X_DUAL_MODE 0x01 -#define S_028814_POLYMODE_FRONT_PTYPE(x) (((x) & 0x07) << 5) -#define G_028814_POLYMODE_FRONT_PTYPE(x) (((x) >> 5) & 0x07) -#define C_028814_POLYMODE_FRONT_PTYPE 0xFFFFFF1F -#define V_028814_X_DRAW_POINTS 0x00 -#define V_028814_X_DRAW_LINES 0x01 -#define V_028814_X_DRAW_TRIANGLES 0x02 -#define S_028814_POLYMODE_BACK_PTYPE(x) (((x) & 0x07) << 8) -#define G_028814_POLYMODE_BACK_PTYPE(x) (((x) >> 8) & 0x07) -#define C_028814_POLYMODE_BACK_PTYPE 0xFFFFF8FF -#define V_028814_X_DRAW_POINTS 0x00 -#define V_028814_X_DRAW_LINES 0x01 -#define V_028814_X_DRAW_TRIANGLES 0x02 -#define S_028814_POLY_OFFSET_FRONT_ENABLE(x) (((x) & 0x1) << 11) -#define G_028814_POLY_OFFSET_FRONT_ENABLE(x) (((x) >> 11) & 0x1) -#define C_028814_POLY_OFFSET_FRONT_ENABLE 0xFFFFF7FF -#define S_028814_POLY_OFFSET_BACK_ENABLE(x) (((x) & 0x1) << 12) -#define G_028814_POLY_OFFSET_BACK_ENABLE(x) (((x) >> 12) & 0x1) -#define C_028814_POLY_OFFSET_BACK_ENABLE 0xFFFFEFFF -#define S_028814_POLY_OFFSET_PARA_ENABLE(x) (((x) & 0x1) << 13) -#define G_028814_POLY_OFFSET_PARA_ENABLE(x) (((x) >> 13) & 0x1) -#define C_028814_POLY_OFFSET_PARA_ENABLE 0xFFFFDFFF -#define S_028814_VTX_WINDOW_OFFSET_ENABLE(x) (((x) & 0x1) << 16) -#define G_028814_VTX_WINDOW_OFFSET_ENABLE(x) (((x) >> 16) & 0x1) -#define C_028814_VTX_WINDOW_OFFSET_ENABLE 0xFFFEFFFF -#define S_028814_PROVOKING_VTX_LAST(x) (((x) & 0x1) << 19) -#define G_028814_PROVOKING_VTX_LAST(x) (((x) >> 19) & 0x1) -#define C_028814_PROVOKING_VTX_LAST 0xFFF7FFFF -#define S_028814_PERSP_CORR_DIS(x) (((x) & 0x1) << 20) -#define G_028814_PERSP_CORR_DIS(x) (((x) >> 20) & 0x1) -#define C_028814_PERSP_CORR_DIS 0xFFEFFFFF -#define S_028814_MULTI_PRIM_IB_ENA(x) (((x) & 0x1) << 21) -#define G_028814_MULTI_PRIM_IB_ENA(x) (((x) >> 21) & 0x1) -#define C_028814_MULTI_PRIM_IB_ENA 0xFFDFFFFF -#define R_028818_PA_CL_VTE_CNTL 0x028818 -#define S_028818_VPORT_X_SCALE_ENA(x) (((x) & 0x1) << 0) -#define G_028818_VPORT_X_SCALE_ENA(x) (((x) >> 0) & 0x1) -#define C_028818_VPORT_X_SCALE_ENA 0xFFFFFFFE -#define S_028818_VPORT_X_OFFSET_ENA(x) (((x) & 0x1) << 1) -#define G_028818_VPORT_X_OFFSET_ENA(x) (((x) >> 1) & 0x1) -#define C_028818_VPORT_X_OFFSET_ENA 0xFFFFFFFD -#define S_028818_VPORT_Y_SCALE_ENA(x) (((x) & 0x1) << 2) -#define G_028818_VPORT_Y_SCALE_ENA(x) (((x) >> 2) & 0x1) -#define C_028818_VPORT_Y_SCALE_ENA 0xFFFFFFFB -#define S_028818_VPORT_Y_OFFSET_ENA(x) (((x) & 0x1) << 3) -#define G_028818_VPORT_Y_OFFSET_ENA(x) (((x) >> 3) & 0x1) -#define C_028818_VPORT_Y_OFFSET_ENA 0xFFFFFFF7 -#define S_028818_VPORT_Z_SCALE_ENA(x) (((x) & 0x1) << 4) -#define G_028818_VPORT_Z_SCALE_ENA(x) (((x) >> 4) & 0x1) -#define C_028818_VPORT_Z_SCALE_ENA 0xFFFFFFEF -#define S_028818_VPORT_Z_OFFSET_ENA(x) (((x) & 0x1) << 5) -#define G_028818_VPORT_Z_OFFSET_ENA(x) (((x) >> 5) & 0x1) -#define C_028818_VPORT_Z_OFFSET_ENA 0xFFFFFFDF -#define S_028818_VTX_XY_FMT(x) (((x) & 0x1) << 8) -#define G_028818_VTX_XY_FMT(x) (((x) >> 8) & 0x1) -#define C_028818_VTX_XY_FMT 0xFFFFFEFF -#define S_028818_VTX_Z_FMT(x) (((x) & 0x1) << 9) -#define G_028818_VTX_Z_FMT(x) (((x) >> 9) & 0x1) -#define C_028818_VTX_Z_FMT 0xFFFFFDFF -#define S_028818_VTX_W0_FMT(x) (((x) & 0x1) << 10) -#define G_028818_VTX_W0_FMT(x) (((x) >> 10) & 0x1) -#define C_028818_VTX_W0_FMT 0xFFFFFBFF -#define R_02881C_PA_CL_VS_OUT_CNTL 0x02881C -#define S_02881C_CLIP_DIST_ENA_0(x) (((x) & 0x1) << 0) -#define G_02881C_CLIP_DIST_ENA_0(x) (((x) >> 0) & 0x1) -#define C_02881C_CLIP_DIST_ENA_0 0xFFFFFFFE -#define S_02881C_CLIP_DIST_ENA_1(x) (((x) & 0x1) << 1) -#define G_02881C_CLIP_DIST_ENA_1(x) (((x) >> 1) & 0x1) -#define C_02881C_CLIP_DIST_ENA_1 0xFFFFFFFD -#define S_02881C_CLIP_DIST_ENA_2(x) (((x) & 0x1) << 2) -#define G_02881C_CLIP_DIST_ENA_2(x) (((x) >> 2) & 0x1) -#define C_02881C_CLIP_DIST_ENA_2 0xFFFFFFFB -#define S_02881C_CLIP_DIST_ENA_3(x) (((x) & 0x1) << 3) -#define G_02881C_CLIP_DIST_ENA_3(x) (((x) >> 3) & 0x1) -#define C_02881C_CLIP_DIST_ENA_3 0xFFFFFFF7 -#define S_02881C_CLIP_DIST_ENA_4(x) (((x) & 0x1) << 4) -#define G_02881C_CLIP_DIST_ENA_4(x) (((x) >> 4) & 0x1) -#define C_02881C_CLIP_DIST_ENA_4 0xFFFFFFEF -#define S_02881C_CLIP_DIST_ENA_5(x) (((x) & 0x1) << 5) -#define G_02881C_CLIP_DIST_ENA_5(x) (((x) >> 5) & 0x1) -#define C_02881C_CLIP_DIST_ENA_5 0xFFFFFFDF -#define S_02881C_CLIP_DIST_ENA_6(x) (((x) & 0x1) << 6) -#define G_02881C_CLIP_DIST_ENA_6(x) (((x) >> 6) & 0x1) -#define C_02881C_CLIP_DIST_ENA_6 0xFFFFFFBF -#define S_02881C_CLIP_DIST_ENA_7(x) (((x) & 0x1) << 7) -#define G_02881C_CLIP_DIST_ENA_7(x) (((x) >> 7) & 0x1) -#define C_02881C_CLIP_DIST_ENA_7 0xFFFFFF7F -#define S_02881C_CULL_DIST_ENA_0(x) (((x) & 0x1) << 8) -#define G_02881C_CULL_DIST_ENA_0(x) (((x) >> 8) & 0x1) -#define C_02881C_CULL_DIST_ENA_0 0xFFFFFEFF -#define S_02881C_CULL_DIST_ENA_1(x) (((x) & 0x1) << 9) -#define G_02881C_CULL_DIST_ENA_1(x) (((x) >> 9) & 0x1) -#define C_02881C_CULL_DIST_ENA_1 0xFFFFFDFF -#define S_02881C_CULL_DIST_ENA_2(x) (((x) & 0x1) << 10) -#define G_02881C_CULL_DIST_ENA_2(x) (((x) >> 10) & 0x1) -#define C_02881C_CULL_DIST_ENA_2 0xFFFFFBFF -#define S_02881C_CULL_DIST_ENA_3(x) (((x) & 0x1) << 11) -#define G_02881C_CULL_DIST_ENA_3(x) (((x) >> 11) & 0x1) -#define C_02881C_CULL_DIST_ENA_3 0xFFFFF7FF -#define S_02881C_CULL_DIST_ENA_4(x) (((x) & 0x1) << 12) -#define G_02881C_CULL_DIST_ENA_4(x) (((x) >> 12) & 0x1) -#define C_02881C_CULL_DIST_ENA_4 0xFFFFEFFF -#define S_02881C_CULL_DIST_ENA_5(x) (((x) & 0x1) << 13) -#define G_02881C_CULL_DIST_ENA_5(x) (((x) >> 13) & 0x1) -#define C_02881C_CULL_DIST_ENA_5 0xFFFFDFFF -#define S_02881C_CULL_DIST_ENA_6(x) (((x) & 0x1) << 14) -#define G_02881C_CULL_DIST_ENA_6(x) (((x) >> 14) & 0x1) -#define C_02881C_CULL_DIST_ENA_6 0xFFFFBFFF -#define S_02881C_CULL_DIST_ENA_7(x) (((x) & 0x1) << 15) -#define G_02881C_CULL_DIST_ENA_7(x) (((x) >> 15) & 0x1) -#define C_02881C_CULL_DIST_ENA_7 0xFFFF7FFF -#define S_02881C_USE_VTX_POINT_SIZE(x) (((x) & 0x1) << 16) -#define G_02881C_USE_VTX_POINT_SIZE(x) (((x) >> 16) & 0x1) -#define C_02881C_USE_VTX_POINT_SIZE 0xFFFEFFFF -#define S_02881C_USE_VTX_EDGE_FLAG(x) (((x) & 0x1) << 17) -#define G_02881C_USE_VTX_EDGE_FLAG(x) (((x) >> 17) & 0x1) -#define C_02881C_USE_VTX_EDGE_FLAG 0xFFFDFFFF -#define S_02881C_USE_VTX_RENDER_TARGET_INDX(x) (((x) & 0x1) << 18) -#define G_02881C_USE_VTX_RENDER_TARGET_INDX(x) (((x) >> 18) & 0x1) -#define C_02881C_USE_VTX_RENDER_TARGET_INDX 0xFFFBFFFF -#define S_02881C_USE_VTX_VIEWPORT_INDX(x) (((x) & 0x1) << 19) -#define G_02881C_USE_VTX_VIEWPORT_INDX(x) (((x) >> 19) & 0x1) -#define C_02881C_USE_VTX_VIEWPORT_INDX 0xFFF7FFFF -#define S_02881C_USE_VTX_KILL_FLAG(x) (((x) & 0x1) << 20) -#define G_02881C_USE_VTX_KILL_FLAG(x) (((x) >> 20) & 0x1) -#define C_02881C_USE_VTX_KILL_FLAG 0xFFEFFFFF -#define S_02881C_VS_OUT_MISC_VEC_ENA(x) (((x) & 0x1) << 21) -#define G_02881C_VS_OUT_MISC_VEC_ENA(x) (((x) >> 21) & 0x1) -#define C_02881C_VS_OUT_MISC_VEC_ENA 0xFFDFFFFF -#define S_02881C_VS_OUT_CCDIST0_VEC_ENA(x) (((x) & 0x1) << 22) -#define G_02881C_VS_OUT_CCDIST0_VEC_ENA(x) (((x) >> 22) & 0x1) -#define C_02881C_VS_OUT_CCDIST0_VEC_ENA 0xFFBFFFFF -#define S_02881C_VS_OUT_CCDIST1_VEC_ENA(x) (((x) & 0x1) << 23) -#define G_02881C_VS_OUT_CCDIST1_VEC_ENA(x) (((x) >> 23) & 0x1) -#define C_02881C_VS_OUT_CCDIST1_VEC_ENA 0xFF7FFFFF -#define S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(x) (((x) & 0x1) << 24) -#define G_02881C_VS_OUT_MISC_SIDE_BUS_ENA(x) (((x) >> 24) & 0x1) -#define C_02881C_VS_OUT_MISC_SIDE_BUS_ENA 0xFEFFFFFF -#define S_02881C_USE_VTX_GS_CUT_FLAG(x) (((x) & 0x1) << 25) -#define G_02881C_USE_VTX_GS_CUT_FLAG(x) (((x) >> 25) & 0x1) -#define C_02881C_USE_VTX_GS_CUT_FLAG 0xFDFFFFFF -/* VI */ -#define S_02881C_USE_VTX_LINE_WIDTH(x) (((x) & 0x1) << 26) -#define G_02881C_USE_VTX_LINE_WIDTH(x) (((x) >> 26) & 0x1) -#define C_02881C_USE_VTX_LINE_WIDTH 0xFBFFFFFF -/* */ -#define R_028820_PA_CL_NANINF_CNTL 0x028820 -#define S_028820_VTE_XY_INF_DISCARD(x) (((x) & 0x1) << 0) -#define G_028820_VTE_XY_INF_DISCARD(x) (((x) >> 0) & 0x1) -#define C_028820_VTE_XY_INF_DISCARD 0xFFFFFFFE -#define S_028820_VTE_Z_INF_DISCARD(x) (((x) & 0x1) << 1) -#define G_028820_VTE_Z_INF_DISCARD(x) (((x) >> 1) & 0x1) -#define C_028820_VTE_Z_INF_DISCARD 0xFFFFFFFD -#define S_028820_VTE_W_INF_DISCARD(x) (((x) & 0x1) << 2) -#define G_028820_VTE_W_INF_DISCARD(x) (((x) >> 2) & 0x1) -#define C_028820_VTE_W_INF_DISCARD 0xFFFFFFFB -#define S_028820_VTE_0XNANINF_IS_0(x) (((x) & 0x1) << 3) -#define G_028820_VTE_0XNANINF_IS_0(x) (((x) >> 3) & 0x1) -#define C_028820_VTE_0XNANINF_IS_0 0xFFFFFFF7 -#define S_028820_VTE_XY_NAN_RETAIN(x) (((x) & 0x1) << 4) -#define G_028820_VTE_XY_NAN_RETAIN(x) (((x) >> 4) & 0x1) -#define C_028820_VTE_XY_NAN_RETAIN 0xFFFFFFEF -#define S_028820_VTE_Z_NAN_RETAIN(x) (((x) & 0x1) << 5) -#define G_028820_VTE_Z_NAN_RETAIN(x) (((x) >> 5) & 0x1) -#define C_028820_VTE_Z_NAN_RETAIN 0xFFFFFFDF -#define S_028820_VTE_W_NAN_RETAIN(x) (((x) & 0x1) << 6) -#define G_028820_VTE_W_NAN_RETAIN(x) (((x) >> 6) & 0x1) -#define C_028820_VTE_W_NAN_RETAIN 0xFFFFFFBF -#define S_028820_VTE_W_RECIP_NAN_IS_0(x) (((x) & 0x1) << 7) -#define G_028820_VTE_W_RECIP_NAN_IS_0(x) (((x) >> 7) & 0x1) -#define C_028820_VTE_W_RECIP_NAN_IS_0 0xFFFFFF7F -#define S_028820_VS_XY_NAN_TO_INF(x) (((x) & 0x1) << 8) -#define G_028820_VS_XY_NAN_TO_INF(x) (((x) >> 8) & 0x1) -#define C_028820_VS_XY_NAN_TO_INF 0xFFFFFEFF -#define S_028820_VS_XY_INF_RETAIN(x) (((x) & 0x1) << 9) -#define G_028820_VS_XY_INF_RETAIN(x) (((x) >> 9) & 0x1) -#define C_028820_VS_XY_INF_RETAIN 0xFFFFFDFF -#define S_028820_VS_Z_NAN_TO_INF(x) (((x) & 0x1) << 10) -#define G_028820_VS_Z_NAN_TO_INF(x) (((x) >> 10) & 0x1) -#define C_028820_VS_Z_NAN_TO_INF 0xFFFFFBFF -#define S_028820_VS_Z_INF_RETAIN(x) (((x) & 0x1) << 11) -#define G_028820_VS_Z_INF_RETAIN(x) (((x) >> 11) & 0x1) -#define C_028820_VS_Z_INF_RETAIN 0xFFFFF7FF -#define S_028820_VS_W_NAN_TO_INF(x) (((x) & 0x1) << 12) -#define G_028820_VS_W_NAN_TO_INF(x) (((x) >> 12) & 0x1) -#define C_028820_VS_W_NAN_TO_INF 0xFFFFEFFF -#define S_028820_VS_W_INF_RETAIN(x) (((x) & 0x1) << 13) -#define G_028820_VS_W_INF_RETAIN(x) (((x) >> 13) & 0x1) -#define C_028820_VS_W_INF_RETAIN 0xFFFFDFFF -#define S_028820_VS_CLIP_DIST_INF_DISCARD(x) (((x) & 0x1) << 14) -#define G_028820_VS_CLIP_DIST_INF_DISCARD(x) (((x) >> 14) & 0x1) -#define C_028820_VS_CLIP_DIST_INF_DISCARD 0xFFFFBFFF -#define S_028820_VTE_NO_OUTPUT_NEG_0(x) (((x) & 0x1) << 20) -#define G_028820_VTE_NO_OUTPUT_NEG_0(x) (((x) >> 20) & 0x1) -#define C_028820_VTE_NO_OUTPUT_NEG_0 0xFFEFFFFF -#define R_028824_PA_SU_LINE_STIPPLE_CNTL 0x028824 -#define S_028824_LINE_STIPPLE_RESET(x) (((x) & 0x03) << 0) -#define G_028824_LINE_STIPPLE_RESET(x) (((x) >> 0) & 0x03) -#define C_028824_LINE_STIPPLE_RESET 0xFFFFFFFC -#define S_028824_EXPAND_FULL_LENGTH(x) (((x) & 0x1) << 2) -#define G_028824_EXPAND_FULL_LENGTH(x) (((x) >> 2) & 0x1) -#define C_028824_EXPAND_FULL_LENGTH 0xFFFFFFFB -#define S_028824_FRACTIONAL_ACCUM(x) (((x) & 0x1) << 3) -#define G_028824_FRACTIONAL_ACCUM(x) (((x) >> 3) & 0x1) -#define C_028824_FRACTIONAL_ACCUM 0xFFFFFFF7 -#define S_028824_DIAMOND_ADJUST(x) (((x) & 0x1) << 4) -#define G_028824_DIAMOND_ADJUST(x) (((x) >> 4) & 0x1) -#define C_028824_DIAMOND_ADJUST 0xFFFFFFEF -#define R_028828_PA_SU_LINE_STIPPLE_SCALE 0x028828 -#define R_02882C_PA_SU_PRIM_FILTER_CNTL 0x02882C -#define S_02882C_TRIANGLE_FILTER_DISABLE(x) (((x) & 0x1) << 0) -#define G_02882C_TRIANGLE_FILTER_DISABLE(x) (((x) >> 0) & 0x1) -#define C_02882C_TRIANGLE_FILTER_DISABLE 0xFFFFFFFE -#define S_02882C_LINE_FILTER_DISABLE(x) (((x) & 0x1) << 1) -#define G_02882C_LINE_FILTER_DISABLE(x) (((x) >> 1) & 0x1) -#define C_02882C_LINE_FILTER_DISABLE 0xFFFFFFFD -#define S_02882C_POINT_FILTER_DISABLE(x) (((x) & 0x1) << 2) -#define G_02882C_POINT_FILTER_DISABLE(x) (((x) >> 2) & 0x1) -#define C_02882C_POINT_FILTER_DISABLE 0xFFFFFFFB -#define S_02882C_RECTANGLE_FILTER_DISABLE(x) (((x) & 0x1) << 3) -#define G_02882C_RECTANGLE_FILTER_DISABLE(x) (((x) >> 3) & 0x1) -#define C_02882C_RECTANGLE_FILTER_DISABLE 0xFFFFFFF7 -#define S_02882C_TRIANGLE_EXPAND_ENA(x) (((x) & 0x1) << 4) -#define G_02882C_TRIANGLE_EXPAND_ENA(x) (((x) >> 4) & 0x1) -#define C_02882C_TRIANGLE_EXPAND_ENA 0xFFFFFFEF -#define S_02882C_LINE_EXPAND_ENA(x) (((x) & 0x1) << 5) -#define G_02882C_LINE_EXPAND_ENA(x) (((x) >> 5) & 0x1) -#define C_02882C_LINE_EXPAND_ENA 0xFFFFFFDF -#define S_02882C_POINT_EXPAND_ENA(x) (((x) & 0x1) << 6) -#define G_02882C_POINT_EXPAND_ENA(x) (((x) >> 6) & 0x1) -#define C_02882C_POINT_EXPAND_ENA 0xFFFFFFBF -#define S_02882C_RECTANGLE_EXPAND_ENA(x) (((x) & 0x1) << 7) -#define G_02882C_RECTANGLE_EXPAND_ENA(x) (((x) >> 7) & 0x1) -#define C_02882C_RECTANGLE_EXPAND_ENA 0xFFFFFF7F -#define S_02882C_PRIM_EXPAND_CONSTANT(x) (((x) & 0xFF) << 8) -#define G_02882C_PRIM_EXPAND_CONSTANT(x) (((x) >> 8) & 0xFF) -#define C_02882C_PRIM_EXPAND_CONSTANT 0xFFFF00FF -/* CIK */ -#define S_02882C_XMAX_RIGHT_EXCLUSION(x) (((x) & 0x1) << 30) -#define G_02882C_XMAX_RIGHT_EXCLUSION(x) (((x) >> 30) & 0x1) -#define C_02882C_XMAX_RIGHT_EXCLUSION 0xBFFFFFFF -#define S_02882C_YMAX_BOTTOM_EXCLUSION(x) (((x) & 0x1) << 31) -#define G_02882C_YMAX_BOTTOM_EXCLUSION(x) (((x) >> 31) & 0x1) -#define C_02882C_YMAX_BOTTOM_EXCLUSION 0x7FFFFFFF -/* */ -#define R_028A00_PA_SU_POINT_SIZE 0x028A00 -#define S_028A00_HEIGHT(x) (((x) & 0xFFFF) << 0) -#define G_028A00_HEIGHT(x) (((x) >> 0) & 0xFFFF) -#define C_028A00_HEIGHT 0xFFFF0000 -#define S_028A00_WIDTH(x) (((x) & 0xFFFF) << 16) -#define G_028A00_WIDTH(x) (((x) >> 16) & 0xFFFF) -#define C_028A00_WIDTH 0x0000FFFF -#define R_028A04_PA_SU_POINT_MINMAX 0x028A04 -#define S_028A04_MIN_SIZE(x) (((x) & 0xFFFF) << 0) -#define G_028A04_MIN_SIZE(x) (((x) >> 0) & 0xFFFF) -#define C_028A04_MIN_SIZE 0xFFFF0000 -#define S_028A04_MAX_SIZE(x) (((x) & 0xFFFF) << 16) -#define G_028A04_MAX_SIZE(x) (((x) >> 16) & 0xFFFF) -#define C_028A04_MAX_SIZE 0x0000FFFF -#define R_028A08_PA_SU_LINE_CNTL 0x028A08 -#define S_028A08_WIDTH(x) (((x) & 0xFFFF) << 0) -#define G_028A08_WIDTH(x) (((x) >> 0) & 0xFFFF) -#define C_028A08_WIDTH 0xFFFF0000 -#define R_028A0C_PA_SC_LINE_STIPPLE 0x028A0C -#define S_028A0C_LINE_PATTERN(x) (((x) & 0xFFFF) << 0) -#define G_028A0C_LINE_PATTERN(x) (((x) >> 0) & 0xFFFF) -#define C_028A0C_LINE_PATTERN 0xFFFF0000 -#define S_028A0C_REPEAT_COUNT(x) (((x) & 0xFF) << 16) -#define G_028A0C_REPEAT_COUNT(x) (((x) >> 16) & 0xFF) -#define C_028A0C_REPEAT_COUNT 0xFF00FFFF -#define S_028A0C_PATTERN_BIT_ORDER(x) (((x) & 0x1) << 28) -#define G_028A0C_PATTERN_BIT_ORDER(x) (((x) >> 28) & 0x1) -#define C_028A0C_PATTERN_BIT_ORDER 0xEFFFFFFF -#define S_028A0C_AUTO_RESET_CNTL(x) (((x) & 0x03) << 29) -#define G_028A0C_AUTO_RESET_CNTL(x) (((x) >> 29) & 0x03) -#define C_028A0C_AUTO_RESET_CNTL 0x9FFFFFFF -#define R_028A10_VGT_OUTPUT_PATH_CNTL 0x028A10 -#define S_028A10_PATH_SELECT(x) (((x) & 0x07) << 0) -#define G_028A10_PATH_SELECT(x) (((x) >> 0) & 0x07) -#define C_028A10_PATH_SELECT 0xFFFFFFF8 -#define V_028A10_VGT_OUTPATH_VTX_REUSE 0x00 -#define V_028A10_VGT_OUTPATH_TESS_EN 0x01 -#define V_028A10_VGT_OUTPATH_PASSTHRU 0x02 -#define V_028A10_VGT_OUTPATH_GS_BLOCK 0x03 -#define V_028A10_VGT_OUTPATH_HS_BLOCK 0x04 -#define R_028A14_VGT_HOS_CNTL 0x028A14 -#define S_028A14_TESS_MODE(x) (((x) & 0x03) << 0) -#define G_028A14_TESS_MODE(x) (((x) >> 0) & 0x03) -#define C_028A14_TESS_MODE 0xFFFFFFFC -#define R_028A18_VGT_HOS_MAX_TESS_LEVEL 0x028A18 -#define R_028A1C_VGT_HOS_MIN_TESS_LEVEL 0x028A1C -#define R_028A20_VGT_HOS_REUSE_DEPTH 0x028A20 -#define S_028A20_REUSE_DEPTH(x) (((x) & 0xFF) << 0) -#define G_028A20_REUSE_DEPTH(x) (((x) >> 0) & 0xFF) -#define C_028A20_REUSE_DEPTH 0xFFFFFF00 -#define R_028A24_VGT_GROUP_PRIM_TYPE 0x028A24 -#define S_028A24_PRIM_TYPE(x) (((x) & 0x1F) << 0) -#define G_028A24_PRIM_TYPE(x) (((x) >> 0) & 0x1F) -#define C_028A24_PRIM_TYPE 0xFFFFFFE0 -#define V_028A24_VGT_GRP_3D_POINT 0x00 -#define V_028A24_VGT_GRP_3D_LINE 0x01 -#define V_028A24_VGT_GRP_3D_TRI 0x02 -#define V_028A24_VGT_GRP_3D_RECT 0x03 -#define V_028A24_VGT_GRP_3D_QUAD 0x04 -#define V_028A24_VGT_GRP_2D_COPY_RECT_V0 0x05 -#define V_028A24_VGT_GRP_2D_COPY_RECT_V1 0x06 -#define V_028A24_VGT_GRP_2D_COPY_RECT_V2 0x07 -#define V_028A24_VGT_GRP_2D_COPY_RECT_V3 0x08 -#define V_028A24_VGT_GRP_2D_FILL_RECT 0x09 -#define V_028A24_VGT_GRP_2D_LINE 0x0A -#define V_028A24_VGT_GRP_2D_TRI 0x0B -#define V_028A24_VGT_GRP_PRIM_INDEX_LINE 0x0C -#define V_028A24_VGT_GRP_PRIM_INDEX_TRI 0x0D -#define V_028A24_VGT_GRP_PRIM_INDEX_QUAD 0x0E -#define V_028A24_VGT_GRP_3D_LINE_ADJ 0x0F -#define V_028A24_VGT_GRP_3D_TRI_ADJ 0x10 -#define V_028A24_VGT_GRP_3D_PATCH 0x11 -#define S_028A24_RETAIN_ORDER(x) (((x) & 0x1) << 14) -#define G_028A24_RETAIN_ORDER(x) (((x) >> 14) & 0x1) -#define C_028A24_RETAIN_ORDER 0xFFFFBFFF -#define S_028A24_RETAIN_QUADS(x) (((x) & 0x1) << 15) -#define G_028A24_RETAIN_QUADS(x) (((x) >> 15) & 0x1) -#define C_028A24_RETAIN_QUADS 0xFFFF7FFF -#define S_028A24_PRIM_ORDER(x) (((x) & 0x07) << 16) -#define G_028A24_PRIM_ORDER(x) (((x) >> 16) & 0x07) -#define C_028A24_PRIM_ORDER 0xFFF8FFFF -#define V_028A24_VGT_GRP_LIST 0x00 -#define V_028A24_VGT_GRP_STRIP 0x01 -#define V_028A24_VGT_GRP_FAN 0x02 -#define V_028A24_VGT_GRP_LOOP 0x03 -#define V_028A24_VGT_GRP_POLYGON 0x04 -#define R_028A28_VGT_GROUP_FIRST_DECR 0x028A28 -#define S_028A28_FIRST_DECR(x) (((x) & 0x0F) << 0) -#define G_028A28_FIRST_DECR(x) (((x) >> 0) & 0x0F) -#define C_028A28_FIRST_DECR 0xFFFFFFF0 -#define R_028A2C_VGT_GROUP_DECR 0x028A2C -#define S_028A2C_DECR(x) (((x) & 0x0F) << 0) -#define G_028A2C_DECR(x) (((x) >> 0) & 0x0F) -#define C_028A2C_DECR 0xFFFFFFF0 -#define R_028A30_VGT_GROUP_VECT_0_CNTL 0x028A30 -#define S_028A30_COMP_X_EN(x) (((x) & 0x1) << 0) -#define G_028A30_COMP_X_EN(x) (((x) >> 0) & 0x1) -#define C_028A30_COMP_X_EN 0xFFFFFFFE -#define S_028A30_COMP_Y_EN(x) (((x) & 0x1) << 1) -#define G_028A30_COMP_Y_EN(x) (((x) >> 1) & 0x1) -#define C_028A30_COMP_Y_EN 0xFFFFFFFD -#define S_028A30_COMP_Z_EN(x) (((x) & 0x1) << 2) -#define G_028A30_COMP_Z_EN(x) (((x) >> 2) & 0x1) -#define C_028A30_COMP_Z_EN 0xFFFFFFFB -#define S_028A30_COMP_W_EN(x) (((x) & 0x1) << 3) -#define G_028A30_COMP_W_EN(x) (((x) >> 3) & 0x1) -#define C_028A30_COMP_W_EN 0xFFFFFFF7 -#define S_028A30_STRIDE(x) (((x) & 0xFF) << 8) -#define G_028A30_STRIDE(x) (((x) >> 8) & 0xFF) -#define C_028A30_STRIDE 0xFFFF00FF -#define S_028A30_SHIFT(x) (((x) & 0xFF) << 16) -#define G_028A30_SHIFT(x) (((x) >> 16) & 0xFF) -#define C_028A30_SHIFT 0xFF00FFFF -#define R_028A34_VGT_GROUP_VECT_1_CNTL 0x028A34 -#define S_028A34_COMP_X_EN(x) (((x) & 0x1) << 0) -#define G_028A34_COMP_X_EN(x) (((x) >> 0) & 0x1) -#define C_028A34_COMP_X_EN 0xFFFFFFFE -#define S_028A34_COMP_Y_EN(x) (((x) & 0x1) << 1) -#define G_028A34_COMP_Y_EN(x) (((x) >> 1) & 0x1) -#define C_028A34_COMP_Y_EN 0xFFFFFFFD -#define S_028A34_COMP_Z_EN(x) (((x) & 0x1) << 2) -#define G_028A34_COMP_Z_EN(x) (((x) >> 2) & 0x1) -#define C_028A34_COMP_Z_EN 0xFFFFFFFB -#define S_028A34_COMP_W_EN(x) (((x) & 0x1) << 3) -#define G_028A34_COMP_W_EN(x) (((x) >> 3) & 0x1) -#define C_028A34_COMP_W_EN 0xFFFFFFF7 -#define S_028A34_STRIDE(x) (((x) & 0xFF) << 8) -#define G_028A34_STRIDE(x) (((x) >> 8) & 0xFF) -#define C_028A34_STRIDE 0xFFFF00FF -#define S_028A34_SHIFT(x) (((x) & 0xFF) << 16) -#define G_028A34_SHIFT(x) (((x) >> 16) & 0xFF) -#define C_028A34_SHIFT 0xFF00FFFF -#define R_028A38_VGT_GROUP_VECT_0_FMT_CNTL 0x028A38 -#define S_028A38_X_CONV(x) (((x) & 0x0F) << 0) -#define G_028A38_X_CONV(x) (((x) >> 0) & 0x0F) -#define C_028A38_X_CONV 0xFFFFFFF0 -#define V_028A38_VGT_GRP_INDEX_16 0x00 -#define V_028A38_VGT_GRP_INDEX_32 0x01 -#define V_028A38_VGT_GRP_UINT_16 0x02 -#define V_028A38_VGT_GRP_UINT_32 0x03 -#define V_028A38_VGT_GRP_SINT_16 0x04 -#define V_028A38_VGT_GRP_SINT_32 0x05 -#define V_028A38_VGT_GRP_FLOAT_32 0x06 -#define V_028A38_VGT_GRP_AUTO_PRIM 0x07 -#define V_028A38_VGT_GRP_FIX_1_23_TO_FLOAT 0x08 -#define S_028A38_X_OFFSET(x) (((x) & 0x0F) << 4) -#define G_028A38_X_OFFSET(x) (((x) >> 4) & 0x0F) -#define C_028A38_X_OFFSET 0xFFFFFF0F -#define S_028A38_Y_CONV(x) (((x) & 0x0F) << 8) -#define G_028A38_Y_CONV(x) (((x) >> 8) & 0x0F) -#define C_028A38_Y_CONV 0xFFFFF0FF -#define V_028A38_VGT_GRP_INDEX_16 0x00 -#define V_028A38_VGT_GRP_INDEX_32 0x01 -#define V_028A38_VGT_GRP_UINT_16 0x02 -#define V_028A38_VGT_GRP_UINT_32 0x03 -#define V_028A38_VGT_GRP_SINT_16 0x04 -#define V_028A38_VGT_GRP_SINT_32 0x05 -#define V_028A38_VGT_GRP_FLOAT_32 0x06 -#define V_028A38_VGT_GRP_AUTO_PRIM 0x07 -#define V_028A38_VGT_GRP_FIX_1_23_TO_FLOAT 0x08 -#define S_028A38_Y_OFFSET(x) (((x) & 0x0F) << 12) -#define G_028A38_Y_OFFSET(x) (((x) >> 12) & 0x0F) -#define C_028A38_Y_OFFSET 0xFFFF0FFF -#define S_028A38_Z_CONV(x) (((x) & 0x0F) << 16) -#define G_028A38_Z_CONV(x) (((x) >> 16) & 0x0F) -#define C_028A38_Z_CONV 0xFFF0FFFF -#define V_028A38_VGT_GRP_INDEX_16 0x00 -#define V_028A38_VGT_GRP_INDEX_32 0x01 -#define V_028A38_VGT_GRP_UINT_16 0x02 -#define V_028A38_VGT_GRP_UINT_32 0x03 -#define V_028A38_VGT_GRP_SINT_16 0x04 -#define V_028A38_VGT_GRP_SINT_32 0x05 -#define V_028A38_VGT_GRP_FLOAT_32 0x06 -#define V_028A38_VGT_GRP_AUTO_PRIM 0x07 -#define V_028A38_VGT_GRP_FIX_1_23_TO_FLOAT 0x08 -#define S_028A38_Z_OFFSET(x) (((x) & 0x0F) << 20) -#define G_028A38_Z_OFFSET(x) (((x) >> 20) & 0x0F) -#define C_028A38_Z_OFFSET 0xFF0FFFFF -#define S_028A38_W_CONV(x) (((x) & 0x0F) << 24) -#define G_028A38_W_CONV(x) (((x) >> 24) & 0x0F) -#define C_028A38_W_CONV 0xF0FFFFFF -#define V_028A38_VGT_GRP_INDEX_16 0x00 -#define V_028A38_VGT_GRP_INDEX_32 0x01 -#define V_028A38_VGT_GRP_UINT_16 0x02 -#define V_028A38_VGT_GRP_UINT_32 0x03 -#define V_028A38_VGT_GRP_SINT_16 0x04 -#define V_028A38_VGT_GRP_SINT_32 0x05 -#define V_028A38_VGT_GRP_FLOAT_32 0x06 -#define V_028A38_VGT_GRP_AUTO_PRIM 0x07 -#define V_028A38_VGT_GRP_FIX_1_23_TO_FLOAT 0x08 -#define S_028A38_W_OFFSET(x) (((x) & 0x0F) << 28) -#define G_028A38_W_OFFSET(x) (((x) >> 28) & 0x0F) -#define C_028A38_W_OFFSET 0x0FFFFFFF -#define R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL 0x028A3C -#define S_028A3C_X_CONV(x) (((x) & 0x0F) << 0) -#define G_028A3C_X_CONV(x) (((x) >> 0) & 0x0F) -#define C_028A3C_X_CONV 0xFFFFFFF0 -#define V_028A3C_VGT_GRP_INDEX_16 0x00 -#define V_028A3C_VGT_GRP_INDEX_32 0x01 -#define V_028A3C_VGT_GRP_UINT_16 0x02 -#define V_028A3C_VGT_GRP_UINT_32 0x03 -#define V_028A3C_VGT_GRP_SINT_16 0x04 -#define V_028A3C_VGT_GRP_SINT_32 0x05 -#define V_028A3C_VGT_GRP_FLOAT_32 0x06 -#define V_028A3C_VGT_GRP_AUTO_PRIM 0x07 -#define V_028A3C_VGT_GRP_FIX_1_23_TO_FLOAT 0x08 -#define S_028A3C_X_OFFSET(x) (((x) & 0x0F) << 4) -#define G_028A3C_X_OFFSET(x) (((x) >> 4) & 0x0F) -#define C_028A3C_X_OFFSET 0xFFFFFF0F -#define S_028A3C_Y_CONV(x) (((x) & 0x0F) << 8) -#define G_028A3C_Y_CONV(x) (((x) >> 8) & 0x0F) -#define C_028A3C_Y_CONV 0xFFFFF0FF -#define V_028A3C_VGT_GRP_INDEX_16 0x00 -#define V_028A3C_VGT_GRP_INDEX_32 0x01 -#define V_028A3C_VGT_GRP_UINT_16 0x02 -#define V_028A3C_VGT_GRP_UINT_32 0x03 -#define V_028A3C_VGT_GRP_SINT_16 0x04 -#define V_028A3C_VGT_GRP_SINT_32 0x05 -#define V_028A3C_VGT_GRP_FLOAT_32 0x06 -#define V_028A3C_VGT_GRP_AUTO_PRIM 0x07 -#define V_028A3C_VGT_GRP_FIX_1_23_TO_FLOAT 0x08 -#define S_028A3C_Y_OFFSET(x) (((x) & 0x0F) << 12) -#define G_028A3C_Y_OFFSET(x) (((x) >> 12) & 0x0F) -#define C_028A3C_Y_OFFSET 0xFFFF0FFF -#define S_028A3C_Z_CONV(x) (((x) & 0x0F) << 16) -#define G_028A3C_Z_CONV(x) (((x) >> 16) & 0x0F) -#define C_028A3C_Z_CONV 0xFFF0FFFF -#define V_028A3C_VGT_GRP_INDEX_16 0x00 -#define V_028A3C_VGT_GRP_INDEX_32 0x01 -#define V_028A3C_VGT_GRP_UINT_16 0x02 -#define V_028A3C_VGT_GRP_UINT_32 0x03 -#define V_028A3C_VGT_GRP_SINT_16 0x04 -#define V_028A3C_VGT_GRP_SINT_32 0x05 -#define V_028A3C_VGT_GRP_FLOAT_32 0x06 -#define V_028A3C_VGT_GRP_AUTO_PRIM 0x07 -#define V_028A3C_VGT_GRP_FIX_1_23_TO_FLOAT 0x08 -#define S_028A3C_Z_OFFSET(x) (((x) & 0x0F) << 20) -#define G_028A3C_Z_OFFSET(x) (((x) >> 20) & 0x0F) -#define C_028A3C_Z_OFFSET 0xFF0FFFFF -#define S_028A3C_W_CONV(x) (((x) & 0x0F) << 24) -#define G_028A3C_W_CONV(x) (((x) >> 24) & 0x0F) -#define C_028A3C_W_CONV 0xF0FFFFFF -#define V_028A3C_VGT_GRP_INDEX_16 0x00 -#define V_028A3C_VGT_GRP_INDEX_32 0x01 -#define V_028A3C_VGT_GRP_UINT_16 0x02 -#define V_028A3C_VGT_GRP_UINT_32 0x03 -#define V_028A3C_VGT_GRP_SINT_16 0x04 -#define V_028A3C_VGT_GRP_SINT_32 0x05 -#define V_028A3C_VGT_GRP_FLOAT_32 0x06 -#define V_028A3C_VGT_GRP_AUTO_PRIM 0x07 -#define V_028A3C_VGT_GRP_FIX_1_23_TO_FLOAT 0x08 -#define S_028A3C_W_OFFSET(x) (((x) & 0x0F) << 28) -#define G_028A3C_W_OFFSET(x) (((x) >> 28) & 0x0F) -#define C_028A3C_W_OFFSET 0x0FFFFFFF -#define R_028A40_VGT_GS_MODE 0x028A40 -#define S_028A40_MODE(x) (((x) & 0x07) << 0) -#define G_028A40_MODE(x) (((x) >> 0) & 0x07) -#define C_028A40_MODE 0xFFFFFFF8 -#define V_028A40_GS_OFF 0x00 -#define V_028A40_GS_SCENARIO_A 0x01 -#define V_028A40_GS_SCENARIO_B 0x02 -#define V_028A40_GS_SCENARIO_G 0x03 -#define V_028A40_GS_SCENARIO_C 0x04 -#define V_028A40_SPRITE_EN 0x05 -#define S_028A40_RESERVED_0(x) (((x) & 0x1) << 3) -#define G_028A40_RESERVED_0(x) (((x) >> 3) & 0x1) -#define C_028A40_RESERVED_0 0xFFFFFFF7 -#define S_028A40_CUT_MODE(x) (((x) & 0x03) << 4) -#define G_028A40_CUT_MODE(x) (((x) >> 4) & 0x03) -#define C_028A40_CUT_MODE 0xFFFFFFCF -#define V_028A40_GS_CUT_1024 0x00 -#define V_028A40_GS_CUT_512 0x01 -#define V_028A40_GS_CUT_256 0x02 -#define V_028A40_GS_CUT_128 0x03 -#define S_028A40_RESERVED_1(x) (((x) & 0x1F) << 6) -#define G_028A40_RESERVED_1(x) (((x) >> 6) & 0x1F) -#define C_028A40_RESERVED_1 0xFFFFF83F -#define S_028A40_GS_C_PACK_EN(x) (((x) & 0x1) << 11) -#define G_028A40_GS_C_PACK_EN(x) (((x) >> 11) & 0x1) -#define C_028A40_GS_C_PACK_EN 0xFFFFF7FF -#define S_028A40_RESERVED_2(x) (((x) & 0x1) << 12) -#define G_028A40_RESERVED_2(x) (((x) >> 12) & 0x1) -#define C_028A40_RESERVED_2 0xFFFFEFFF -#define S_028A40_ES_PASSTHRU(x) (((x) & 0x1) << 13) -#define G_028A40_ES_PASSTHRU(x) (((x) >> 13) & 0x1) -#define C_028A40_ES_PASSTHRU 0xFFFFDFFF -/* SI-CIK */ -#define S_028A40_COMPUTE_MODE(x) (((x) & 0x1) << 14) -#define G_028A40_COMPUTE_MODE(x) (((x) >> 14) & 0x1) -#define C_028A40_COMPUTE_MODE 0xFFFFBFFF -#define S_028A40_FAST_COMPUTE_MODE(x) (((x) & 0x1) << 15) -#define G_028A40_FAST_COMPUTE_MODE(x) (((x) >> 15) & 0x1) -#define C_028A40_FAST_COMPUTE_MODE 0xFFFF7FFF -#define S_028A40_ELEMENT_INFO_EN(x) (((x) & 0x1) << 16) -#define G_028A40_ELEMENT_INFO_EN(x) (((x) >> 16) & 0x1) -#define C_028A40_ELEMENT_INFO_EN 0xFFFEFFFF -/* */ -#define S_028A40_PARTIAL_THD_AT_EOI(x) (((x) & 0x1) << 17) -#define G_028A40_PARTIAL_THD_AT_EOI(x) (((x) >> 17) & 0x1) -#define C_028A40_PARTIAL_THD_AT_EOI 0xFFFDFFFF -#define S_028A40_SUPPRESS_CUTS(x) (((x) & 0x1) << 18) -#define G_028A40_SUPPRESS_CUTS(x) (((x) >> 18) & 0x1) -#define C_028A40_SUPPRESS_CUTS 0xFFFBFFFF -#define S_028A40_ES_WRITE_OPTIMIZE(x) (((x) & 0x1) << 19) -#define G_028A40_ES_WRITE_OPTIMIZE(x) (((x) >> 19) & 0x1) -#define C_028A40_ES_WRITE_OPTIMIZE 0xFFF7FFFF -#define S_028A40_GS_WRITE_OPTIMIZE(x) (((x) & 0x1) << 20) -#define G_028A40_GS_WRITE_OPTIMIZE(x) (((x) >> 20) & 0x1) -#define C_028A40_GS_WRITE_OPTIMIZE 0xFFEFFFFF -/* CIK */ -#define S_028A40_ONCHIP(x) (((x) & 0x03) << 21) -#define G_028A40_ONCHIP(x) (((x) >> 21) & 0x03) -#define C_028A40_ONCHIP 0xFF9FFFFF -#define V_028A40_X_0_OFFCHIP_GS 0x00 -#define V_028A40_X_3_ES_AND_GS_ARE_ONCHIP 0x03 -#define R_028A44_VGT_GS_ONCHIP_CNTL 0x028A44 -#define S_028A44_ES_VERTS_PER_SUBGRP(x) (((x) & 0x7FF) << 0) -#define G_028A44_ES_VERTS_PER_SUBGRP(x) (((x) >> 0) & 0x7FF) -#define C_028A44_ES_VERTS_PER_SUBGRP 0xFFFFF800 -#define S_028A44_GS_PRIMS_PER_SUBGRP(x) (((x) & 0x7FF) << 11) -#define G_028A44_GS_PRIMS_PER_SUBGRP(x) (((x) >> 11) & 0x7FF) -#define C_028A44_GS_PRIMS_PER_SUBGRP 0xFFC007FF -/* */ -#define R_028A48_PA_SC_MODE_CNTL_0 0x028A48 -#define S_028A48_MSAA_ENABLE(x) (((x) & 0x1) << 0) -#define G_028A48_MSAA_ENABLE(x) (((x) >> 0) & 0x1) -#define C_028A48_MSAA_ENABLE 0xFFFFFFFE -#define S_028A48_VPORT_SCISSOR_ENABLE(x) (((x) & 0x1) << 1) -#define G_028A48_VPORT_SCISSOR_ENABLE(x) (((x) >> 1) & 0x1) -#define C_028A48_VPORT_SCISSOR_ENABLE 0xFFFFFFFD -#define S_028A48_LINE_STIPPLE_ENABLE(x) (((x) & 0x1) << 2) -#define G_028A48_LINE_STIPPLE_ENABLE(x) (((x) >> 2) & 0x1) -#define C_028A48_LINE_STIPPLE_ENABLE 0xFFFFFFFB -#define S_028A48_SEND_UNLIT_STILES_TO_PKR(x) (((x) & 0x1) << 3) -#define G_028A48_SEND_UNLIT_STILES_TO_PKR(x) (((x) >> 3) & 0x1) -#define C_028A48_SEND_UNLIT_STILES_TO_PKR 0xFFFFFFF7 -#define R_028A4C_PA_SC_MODE_CNTL_1 0x028A4C -#define S_028A4C_WALK_SIZE(x) (((x) & 0x1) << 0) -#define G_028A4C_WALK_SIZE(x) (((x) >> 0) & 0x1) -#define C_028A4C_WALK_SIZE 0xFFFFFFFE -#define S_028A4C_WALK_ALIGNMENT(x) (((x) & 0x1) << 1) -#define G_028A4C_WALK_ALIGNMENT(x) (((x) >> 1) & 0x1) -#define C_028A4C_WALK_ALIGNMENT 0xFFFFFFFD -#define S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(x) (((x) & 0x1) << 2) -#define G_028A4C_WALK_ALIGN8_PRIM_FITS_ST(x) (((x) >> 2) & 0x1) -#define C_028A4C_WALK_ALIGN8_PRIM_FITS_ST 0xFFFFFFFB -#define S_028A4C_WALK_FENCE_ENABLE(x) (((x) & 0x1) << 3) -#define G_028A4C_WALK_FENCE_ENABLE(x) (((x) >> 3) & 0x1) -#define C_028A4C_WALK_FENCE_ENABLE 0xFFFFFFF7 -#define S_028A4C_WALK_FENCE_SIZE(x) (((x) & 0x07) << 4) -#define G_028A4C_WALK_FENCE_SIZE(x) (((x) >> 4) & 0x07) -#define C_028A4C_WALK_FENCE_SIZE 0xFFFFFF8F -#define S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(x) (((x) & 0x1) << 7) -#define G_028A4C_SUPERTILE_WALK_ORDER_ENABLE(x) (((x) >> 7) & 0x1) -#define C_028A4C_SUPERTILE_WALK_ORDER_ENABLE 0xFFFFFF7F -#define S_028A4C_TILE_WALK_ORDER_ENABLE(x) (((x) & 0x1) << 8) -#define G_028A4C_TILE_WALK_ORDER_ENABLE(x) (((x) >> 8) & 0x1) -#define C_028A4C_TILE_WALK_ORDER_ENABLE 0xFFFFFEFF -#define S_028A4C_TILE_COVER_DISABLE(x) (((x) & 0x1) << 9) -#define G_028A4C_TILE_COVER_DISABLE(x) (((x) >> 9) & 0x1) -#define C_028A4C_TILE_COVER_DISABLE 0xFFFFFDFF -#define S_028A4C_TILE_COVER_NO_SCISSOR(x) (((x) & 0x1) << 10) -#define G_028A4C_TILE_COVER_NO_SCISSOR(x) (((x) >> 10) & 0x1) -#define C_028A4C_TILE_COVER_NO_SCISSOR 0xFFFFFBFF -#define S_028A4C_ZMM_LINE_EXTENT(x) (((x) & 0x1) << 11) -#define G_028A4C_ZMM_LINE_EXTENT(x) (((x) >> 11) & 0x1) -#define C_028A4C_ZMM_LINE_EXTENT 0xFFFFF7FF -#define S_028A4C_ZMM_LINE_OFFSET(x) (((x) & 0x1) << 12) -#define G_028A4C_ZMM_LINE_OFFSET(x) (((x) >> 12) & 0x1) -#define C_028A4C_ZMM_LINE_OFFSET 0xFFFFEFFF -#define S_028A4C_ZMM_RECT_EXTENT(x) (((x) & 0x1) << 13) -#define G_028A4C_ZMM_RECT_EXTENT(x) (((x) >> 13) & 0x1) -#define C_028A4C_ZMM_RECT_EXTENT 0xFFFFDFFF -#define S_028A4C_KILL_PIX_POST_HI_Z(x) (((x) & 0x1) << 14) -#define G_028A4C_KILL_PIX_POST_HI_Z(x) (((x) >> 14) & 0x1) -#define C_028A4C_KILL_PIX_POST_HI_Z 0xFFFFBFFF -#define S_028A4C_KILL_PIX_POST_DETAIL_MASK(x) (((x) & 0x1) << 15) -#define G_028A4C_KILL_PIX_POST_DETAIL_MASK(x) (((x) >> 15) & 0x1) -#define C_028A4C_KILL_PIX_POST_DETAIL_MASK 0xFFFF7FFF -#define S_028A4C_PS_ITER_SAMPLE(x) (((x) & 0x1) << 16) -#define G_028A4C_PS_ITER_SAMPLE(x) (((x) >> 16) & 0x1) -#define C_028A4C_PS_ITER_SAMPLE 0xFFFEFFFF -#define S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(x) (((x) & 0x1) << 17) -#define G_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(x) (((x) >> 17) & 0x1) -#define C_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE 0xFFFDFFFF -#define S_028A4C_MULTI_GPU_SUPERTILE_ENABLE(x) (((x) & 0x1) << 18) -#define G_028A4C_MULTI_GPU_SUPERTILE_ENABLE(x) (((x) >> 18) & 0x1) -#define C_028A4C_MULTI_GPU_SUPERTILE_ENABLE 0xFFFBFFFF -#define S_028A4C_GPU_ID_OVERRIDE_ENABLE(x) (((x) & 0x1) << 19) -#define G_028A4C_GPU_ID_OVERRIDE_ENABLE(x) (((x) >> 19) & 0x1) -#define C_028A4C_GPU_ID_OVERRIDE_ENABLE 0xFFF7FFFF -#define S_028A4C_GPU_ID_OVERRIDE(x) (((x) & 0x0F) << 20) -#define G_028A4C_GPU_ID_OVERRIDE(x) (((x) >> 20) & 0x0F) -#define C_028A4C_GPU_ID_OVERRIDE 0xFF0FFFFF -#define S_028A4C_MULTI_GPU_PRIM_DISCARD_ENABLE(x) (((x) & 0x1) << 24) -#define G_028A4C_MULTI_GPU_PRIM_DISCARD_ENABLE(x) (((x) >> 24) & 0x1) -#define C_028A4C_MULTI_GPU_PRIM_DISCARD_ENABLE 0xFEFFFFFF -#define S_028A4C_FORCE_EOV_CNTDWN_ENABLE(x) (((x) & 0x1) << 25) -#define G_028A4C_FORCE_EOV_CNTDWN_ENABLE(x) (((x) >> 25) & 0x1) -#define C_028A4C_FORCE_EOV_CNTDWN_ENABLE 0xFDFFFFFF -#define S_028A4C_FORCE_EOV_REZ_ENABLE(x) (((x) & 0x1) << 26) -#define G_028A4C_FORCE_EOV_REZ_ENABLE(x) (((x) >> 26) & 0x1) -#define C_028A4C_FORCE_EOV_REZ_ENABLE 0xFBFFFFFF -#define S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(x) (((x) & 0x1) << 27) -#define G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(x) (((x) >> 27) & 0x1) -#define C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE 0xF7FFFFFF -#define S_028A4C_OUT_OF_ORDER_WATER_MARK(x) (((x) & 0x07) << 28) -#define G_028A4C_OUT_OF_ORDER_WATER_MARK(x) (((x) >> 28) & 0x07) -#define C_028A4C_OUT_OF_ORDER_WATER_MARK 0x8FFFFFFF -#define R_028A50_VGT_ENHANCE 0x028A50 -#define R_028A54_VGT_GS_PER_ES 0x028A54 -#define S_028A54_GS_PER_ES(x) (((x) & 0x7FF) << 0) -#define G_028A54_GS_PER_ES(x) (((x) >> 0) & 0x7FF) -#define C_028A54_GS_PER_ES 0xFFFFF800 -#define R_028A58_VGT_ES_PER_GS 0x028A58 -#define S_028A58_ES_PER_GS(x) (((x) & 0x7FF) << 0) -#define G_028A58_ES_PER_GS(x) (((x) >> 0) & 0x7FF) -#define C_028A58_ES_PER_GS 0xFFFFF800 -#define R_028A5C_VGT_GS_PER_VS 0x028A5C -#define S_028A5C_GS_PER_VS(x) (((x) & 0x0F) << 0) -#define G_028A5C_GS_PER_VS(x) (((x) >> 0) & 0x0F) -#define C_028A5C_GS_PER_VS 0xFFFFFFF0 -#define R_028A60_VGT_GSVS_RING_OFFSET_1 0x028A60 -#define S_028A60_OFFSET(x) (((x) & 0x7FFF) << 0) -#define G_028A60_OFFSET(x) (((x) >> 0) & 0x7FFF) -#define C_028A60_OFFSET 0xFFFF8000 -#define R_028A64_VGT_GSVS_RING_OFFSET_2 0x028A64 -#define S_028A64_OFFSET(x) (((x) & 0x7FFF) << 0) -#define G_028A64_OFFSET(x) (((x) >> 0) & 0x7FFF) -#define C_028A64_OFFSET 0xFFFF8000 -#define R_028A68_VGT_GSVS_RING_OFFSET_3 0x028A68 -#define S_028A68_OFFSET(x) (((x) & 0x7FFF) << 0) -#define G_028A68_OFFSET(x) (((x) >> 0) & 0x7FFF) -#define C_028A68_OFFSET 0xFFFF8000 -#define R_028A6C_VGT_GS_OUT_PRIM_TYPE 0x028A6C -#define S_028A6C_OUTPRIM_TYPE(x) (((x) & 0x3F) << 0) -#define G_028A6C_OUTPRIM_TYPE(x) (((x) >> 0) & 0x3F) -#define C_028A6C_OUTPRIM_TYPE 0xFFFFFFC0 -#define V_028A6C_OUTPRIM_TYPE_POINTLIST 0 -#define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1 -#define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2 -#define S_028A6C_OUTPRIM_TYPE_1(x) (((x) & 0x3F) << 8) -#define G_028A6C_OUTPRIM_TYPE_1(x) (((x) >> 8) & 0x3F) -#define C_028A6C_OUTPRIM_TYPE_1 0xFFFFC0FF -#define S_028A6C_OUTPRIM_TYPE_2(x) (((x) & 0x3F) << 16) -#define G_028A6C_OUTPRIM_TYPE_2(x) (((x) >> 16) & 0x3F) -#define C_028A6C_OUTPRIM_TYPE_2 0xFFC0FFFF -#define S_028A6C_OUTPRIM_TYPE_3(x) (((x) & 0x3F) << 22) -#define G_028A6C_OUTPRIM_TYPE_3(x) (((x) >> 22) & 0x3F) -#define C_028A6C_OUTPRIM_TYPE_3 0xF03FFFFF -#define S_028A6C_UNIQUE_TYPE_PER_STREAM(x) (((x) & 0x1) << 31) -#define G_028A6C_UNIQUE_TYPE_PER_STREAM(x) (((x) >> 31) & 0x1) -#define C_028A6C_UNIQUE_TYPE_PER_STREAM 0x7FFFFFFF -#define R_028A70_IA_ENHANCE 0x028A70 -#define R_028A74_VGT_DMA_SIZE 0x028A74 -#define R_028A78_VGT_DMA_MAX_SIZE 0x028A78 -#define R_028A7C_VGT_DMA_INDEX_TYPE 0x028A7C -#define S_028A7C_INDEX_TYPE(x) (((x) & 0x03) << 0) -#define G_028A7C_INDEX_TYPE(x) (((x) >> 0) & 0x03) -#define C_028A7C_INDEX_TYPE 0xFFFFFFFC -#define V_028A7C_VGT_INDEX_16 0x00 -#define V_028A7C_VGT_INDEX_32 0x01 -#define V_028A7C_VGT_INDEX_8 0x02 /* VI */ -#define S_028A7C_SWAP_MODE(x) (((x) & 0x03) << 2) -#define G_028A7C_SWAP_MODE(x) (((x) >> 2) & 0x03) -#define C_028A7C_SWAP_MODE 0xFFFFFFF3 -#define V_028A7C_VGT_DMA_SWAP_NONE 0x00 -#define V_028A7C_VGT_DMA_SWAP_16_BIT 0x01 -#define V_028A7C_VGT_DMA_SWAP_32_BIT 0x02 -#define V_028A7C_VGT_DMA_SWAP_WORD 0x03 -/* CIK */ -#define S_028A7C_BUF_TYPE(x) (((x) & 0x03) << 4) -#define G_028A7C_BUF_TYPE(x) (((x) >> 4) & 0x03) -#define C_028A7C_BUF_TYPE 0xFFFFFFCF -#define V_028A7C_VGT_DMA_BUF_MEM 0x00 -#define V_028A7C_VGT_DMA_BUF_RING 0x01 -#define V_028A7C_VGT_DMA_BUF_SETUP 0x02 -#define S_028A7C_RDREQ_POLICY(x) (((x) & 0x03) << 6) -#define G_028A7C_RDREQ_POLICY(x) (((x) >> 6) & 0x03) -#define C_028A7C_RDREQ_POLICY 0xFFFFFF3F -#define V_028A7C_VGT_POLICY_LRU 0x00 -#define V_028A7C_VGT_POLICY_STREAM 0x01 -#define S_028A7C_RDREQ_POLICY_VI(x) (((x) & 0x1) << 6) -#define G_028A7C_RDREQ_POLICY_VI(x) (((x) >> 6) & 0x1) -#define C_028A7C_RDREQ_POLICY_VI 0xFFFFFFBF -#define S_028A7C_ATC(x) (((x) & 0x1) << 8) -#define G_028A7C_ATC(x) (((x) >> 8) & 0x1) -#define C_028A7C_ATC 0xFFFFFEFF -#define S_028A7C_NOT_EOP(x) (((x) & 0x1) << 9) -#define G_028A7C_NOT_EOP(x) (((x) >> 9) & 0x1) -#define C_028A7C_NOT_EOP 0xFFFFFDFF -#define S_028A7C_REQ_PATH(x) (((x) & 0x1) << 10) -#define G_028A7C_REQ_PATH(x) (((x) >> 10) & 0x1) -#define C_028A7C_REQ_PATH 0xFFFFFBFF -/* */ -/* VI */ -#define S_028A7C_MTYPE(x) (((x) & 0x03) << 11) -#define G_028A7C_MTYPE(x) (((x) >> 11) & 0x03) -#define C_028A7C_MTYPE 0xFFFFE7FF -/* */ -#define R_028A80_WD_ENHANCE 0x028A80 -#define R_028A84_VGT_PRIMITIVEID_EN 0x028A84 -#define S_028A84_PRIMITIVEID_EN(x) (((x) & 0x1) << 0) -#define G_028A84_PRIMITIVEID_EN(x) (((x) >> 0) & 0x1) -#define C_028A84_PRIMITIVEID_EN 0xFFFFFFFE -#define S_028A84_DISABLE_RESET_ON_EOI(x) (((x) & 0x1) << 1) /* not on CIK */ -#define G_028A84_DISABLE_RESET_ON_EOI(x) (((x) >> 1) & 0x1) /* not on CIK */ -#define C_028A84_DISABLE_RESET_ON_EOI 0xFFFFFFFD /* not on CIK */ -#define R_028A88_VGT_DMA_NUM_INSTANCES 0x028A88 -#define R_028A8C_VGT_PRIMITIVEID_RESET 0x028A8C -#define R_028A90_VGT_EVENT_INITIATOR 0x028A90 -#define S_028A90_EVENT_TYPE(x) (((x) & 0x3F) << 0) -#define G_028A90_EVENT_TYPE(x) (((x) >> 0) & 0x3F) -#define C_028A90_EVENT_TYPE 0xFFFFFFC0 -#define V_028A90_SAMPLE_STREAMOUTSTATS1 0x01 -#define V_028A90_SAMPLE_STREAMOUTSTATS2 0x02 -#define V_028A90_SAMPLE_STREAMOUTSTATS3 0x03 -#define V_028A90_CACHE_FLUSH_TS 0x04 -#define V_028A90_CONTEXT_DONE 0x05 -#define V_028A90_CACHE_FLUSH 0x06 -#define V_028A90_CS_PARTIAL_FLUSH 0x07 -#define V_028A90_VGT_STREAMOUT_SYNC 0x08 -#define V_028A90_VGT_STREAMOUT_RESET 0x0A -#define V_028A90_END_OF_PIPE_INCR_DE 0x0B -#define V_028A90_END_OF_PIPE_IB_END 0x0C -#define V_028A90_RST_PIX_CNT 0x0D -#define V_028A90_VS_PARTIAL_FLUSH 0x0F -#define V_028A90_PS_PARTIAL_FLUSH 0x10 -#define V_028A90_FLUSH_HS_OUTPUT 0x11 -#define V_028A90_FLUSH_LS_OUTPUT 0x12 -#define V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT 0x14 -#define V_028A90_ZPASS_DONE 0x15 /* not on CIK */ -#define V_028A90_CACHE_FLUSH_AND_INV_EVENT 0x16 -#define V_028A90_PERFCOUNTER_START 0x17 -#define V_028A90_PERFCOUNTER_STOP 0x18 -#define V_028A90_PIPELINESTAT_START 0x19 -#define V_028A90_PIPELINESTAT_STOP 0x1A -#define V_028A90_PERFCOUNTER_SAMPLE 0x1B -#define V_028A90_FLUSH_ES_OUTPUT 0x1C -#define V_028A90_FLUSH_GS_OUTPUT 0x1D -#define V_028A90_SAMPLE_PIPELINESTAT 0x1E -#define V_028A90_SO_VGTSTREAMOUT_FLUSH 0x1F -#define V_028A90_SAMPLE_STREAMOUTSTATS 0x20 -#define V_028A90_RESET_VTX_CNT 0x21 -#define V_028A90_BLOCK_CONTEXT_DONE 0x22 -#define V_028A90_CS_CONTEXT_DONE 0x23 -#define V_028A90_VGT_FLUSH 0x24 -#define V_028A90_SC_SEND_DB_VPZ 0x27 -#define V_028A90_BOTTOM_OF_PIPE_TS 0x28 -#define V_028A90_DB_CACHE_FLUSH_AND_INV 0x2A -#define V_028A90_FLUSH_AND_INV_DB_DATA_TS 0x2B -#define V_028A90_FLUSH_AND_INV_DB_META 0x2C -#define V_028A90_FLUSH_AND_INV_CB_DATA_TS 0x2D -#define V_028A90_FLUSH_AND_INV_CB_META 0x2E -#define V_028A90_CS_DONE 0x2F -#define V_028A90_PS_DONE 0x30 -#define V_028A90_FLUSH_AND_INV_CB_PIXEL_DATA 0x31 -#define V_028A90_THREAD_TRACE_START 0x33 -#define V_028A90_THREAD_TRACE_STOP 0x34 -#define V_028A90_THREAD_TRACE_MARKER 0x35 -#define V_028A90_THREAD_TRACE_FLUSH 0x36 -#define V_028A90_THREAD_TRACE_FINISH 0x37 -/* CIK */ -#define V_028A90_PIXEL_PIPE_STAT_CONTROL 0x38 -#define V_028A90_PIXEL_PIPE_STAT_DUMP 0x39 -#define V_028A90_PIXEL_PIPE_STAT_RESET 0x40 -/* */ -#define S_028A90_ADDRESS_HI(x) (((x) & 0x1FF) << 18) -#define G_028A90_ADDRESS_HI(x) (((x) >> 18) & 0x1FF) -#define C_028A90_ADDRESS_HI 0xF803FFFF -#define S_028A90_EXTENDED_EVENT(x) (((x) & 0x1) << 27) -#define G_028A90_EXTENDED_EVENT(x) (((x) >> 27) & 0x1) -#define C_028A90_EXTENDED_EVENT 0xF7FFFFFF -#define R_028A94_VGT_MULTI_PRIM_IB_RESET_EN 0x028A94 -#define S_028A94_RESET_EN(x) (((x) & 0x1) << 0) -#define G_028A94_RESET_EN(x) (((x) >> 0) & 0x1) -#define C_028A94_RESET_EN 0xFFFFFFFE -#define R_028AA0_VGT_INSTANCE_STEP_RATE_0 0x028AA0 -#define R_028AA4_VGT_INSTANCE_STEP_RATE_1 0x028AA4 -#define R_028AA8_IA_MULTI_VGT_PARAM 0x028AA8 -#define S_028AA8_PRIMGROUP_SIZE(x) (((x) & 0xFFFF) << 0) -#define G_028AA8_PRIMGROUP_SIZE(x) (((x) >> 0) & 0xFFFF) -#define C_028AA8_PRIMGROUP_SIZE 0xFFFF0000 -#define S_028AA8_PARTIAL_VS_WAVE_ON(x) (((x) & 0x1) << 16) -#define G_028AA8_PARTIAL_VS_WAVE_ON(x) (((x) >> 16) & 0x1) -#define C_028AA8_PARTIAL_VS_WAVE_ON 0xFFFEFFFF -#define S_028AA8_SWITCH_ON_EOP(x) (((x) & 0x1) << 17) -#define G_028AA8_SWITCH_ON_EOP(x) (((x) >> 17) & 0x1) -#define C_028AA8_SWITCH_ON_EOP 0xFFFDFFFF -#define S_028AA8_PARTIAL_ES_WAVE_ON(x) (((x) & 0x1) << 18) -#define G_028AA8_PARTIAL_ES_WAVE_ON(x) (((x) >> 18) & 0x1) -#define C_028AA8_PARTIAL_ES_WAVE_ON 0xFFFBFFFF -#define S_028AA8_SWITCH_ON_EOI(x) (((x) & 0x1) << 19) -#define G_028AA8_SWITCH_ON_EOI(x) (((x) >> 19) & 0x1) -#define C_028AA8_SWITCH_ON_EOI 0xFFF7FFFF -/* CIK */ -#define S_028AA8_WD_SWITCH_ON_EOP(x) (((x) & 0x1) << 20) -#define G_028AA8_WD_SWITCH_ON_EOP(x) (((x) >> 20) & 0x1) -#define C_028AA8_WD_SWITCH_ON_EOP 0xFFEFFFFF -/* VI */ -#define S_028AA8_MAX_PRIMGRP_IN_WAVE(x) (((x) & 0x0F) << 28) -#define G_028AA8_MAX_PRIMGRP_IN_WAVE(x) (((x) >> 28) & 0x0F) -#define C_028AA8_MAX_PRIMGRP_IN_WAVE 0x0FFFFFFF -/* */ -#define R_028AAC_VGT_ESGS_RING_ITEMSIZE 0x028AAC -#define S_028AAC_ITEMSIZE(x) (((x) & 0x7FFF) << 0) -#define G_028AAC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) -#define C_028AAC_ITEMSIZE 0xFFFF8000 -#define R_028AB0_VGT_GSVS_RING_ITEMSIZE 0x028AB0 -#define S_028AB0_ITEMSIZE(x) (((x) & 0x7FFF) << 0) -#define G_028AB0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) -#define C_028AB0_ITEMSIZE 0xFFFF8000 -#define R_028AB4_VGT_REUSE_OFF 0x028AB4 -#define S_028AB4_REUSE_OFF(x) (((x) & 0x1) << 0) -#define G_028AB4_REUSE_OFF(x) (((x) >> 0) & 0x1) -#define C_028AB4_REUSE_OFF 0xFFFFFFFE -#define R_028AB8_VGT_VTX_CNT_EN 0x028AB8 -#define S_028AB8_VTX_CNT_EN(x) (((x) & 0x1) << 0) -#define G_028AB8_VTX_CNT_EN(x) (((x) >> 0) & 0x1) -#define C_028AB8_VTX_CNT_EN 0xFFFFFFFE -#define R_028ABC_DB_HTILE_SURFACE 0x028ABC -#define S_028ABC_LINEAR(x) (((x) & 0x1) << 0) -#define G_028ABC_LINEAR(x) (((x) >> 0) & 0x1) -#define C_028ABC_LINEAR 0xFFFFFFFE -#define S_028ABC_FULL_CACHE(x) (((x) & 0x1) << 1) -#define G_028ABC_FULL_CACHE(x) (((x) >> 1) & 0x1) -#define C_028ABC_FULL_CACHE 0xFFFFFFFD -#define S_028ABC_HTILE_USES_PRELOAD_WIN(x) (((x) & 0x1) << 2) -#define G_028ABC_HTILE_USES_PRELOAD_WIN(x) (((x) >> 2) & 0x1) -#define C_028ABC_HTILE_USES_PRELOAD_WIN 0xFFFFFFFB -#define S_028ABC_PRELOAD(x) (((x) & 0x1) << 3) -#define G_028ABC_PRELOAD(x) (((x) >> 3) & 0x1) -#define C_028ABC_PRELOAD 0xFFFFFFF7 -#define S_028ABC_PREFETCH_WIDTH(x) (((x) & 0x3F) << 4) -#define G_028ABC_PREFETCH_WIDTH(x) (((x) >> 4) & 0x3F) -#define C_028ABC_PREFETCH_WIDTH 0xFFFFFC0F -#define S_028ABC_PREFETCH_HEIGHT(x) (((x) & 0x3F) << 10) -#define G_028ABC_PREFETCH_HEIGHT(x) (((x) >> 10) & 0x3F) -#define C_028ABC_PREFETCH_HEIGHT 0xFFFF03FF -#define S_028ABC_DST_OUTSIDE_ZERO_TO_ONE(x) (((x) & 0x1) << 16) -#define G_028ABC_DST_OUTSIDE_ZERO_TO_ONE(x) (((x) >> 16) & 0x1) -#define C_028ABC_DST_OUTSIDE_ZERO_TO_ONE 0xFFFEFFFF -/* VI */ -#define S_028ABC_TC_COMPATIBLE(x) (((x) & 0x1) << 17) -#define G_028ABC_TC_COMPATIBLE(x) (((x) >> 17) & 0x1) -#define C_028ABC_TC_COMPATIBLE 0xFFFDFFFF -/* */ -#define R_028AC0_DB_SRESULTS_COMPARE_STATE0 0x028AC0 -#define S_028AC0_COMPAREFUNC0(x) (((x) & 0x07) << 0) -#define G_028AC0_COMPAREFUNC0(x) (((x) >> 0) & 0x07) -#define C_028AC0_COMPAREFUNC0 0xFFFFFFF8 -#define V_028AC0_REF_NEVER 0x00 -#define V_028AC0_REF_LESS 0x01 -#define V_028AC0_REF_EQUAL 0x02 -#define V_028AC0_REF_LEQUAL 0x03 -#define V_028AC0_REF_GREATER 0x04 -#define V_028AC0_REF_NOTEQUAL 0x05 -#define V_028AC0_REF_GEQUAL 0x06 -#define V_028AC0_REF_ALWAYS 0x07 -#define S_028AC0_COMPAREVALUE0(x) (((x) & 0xFF) << 4) -#define G_028AC0_COMPAREVALUE0(x) (((x) >> 4) & 0xFF) -#define C_028AC0_COMPAREVALUE0 0xFFFFF00F -#define S_028AC0_COMPAREMASK0(x) (((x) & 0xFF) << 12) -#define G_028AC0_COMPAREMASK0(x) (((x) >> 12) & 0xFF) -#define C_028AC0_COMPAREMASK0 0xFFF00FFF -#define S_028AC0_ENABLE0(x) (((x) & 0x1) << 24) -#define G_028AC0_ENABLE0(x) (((x) >> 24) & 0x1) -#define C_028AC0_ENABLE0 0xFEFFFFFF -#define R_028AC4_DB_SRESULTS_COMPARE_STATE1 0x028AC4 -#define S_028AC4_COMPAREFUNC1(x) (((x) & 0x07) << 0) -#define G_028AC4_COMPAREFUNC1(x) (((x) >> 0) & 0x07) -#define C_028AC4_COMPAREFUNC1 0xFFFFFFF8 -#define V_028AC4_REF_NEVER 0x00 -#define V_028AC4_REF_LESS 0x01 -#define V_028AC4_REF_EQUAL 0x02 -#define V_028AC4_REF_LEQUAL 0x03 -#define V_028AC4_REF_GREATER 0x04 -#define V_028AC4_REF_NOTEQUAL 0x05 -#define V_028AC4_REF_GEQUAL 0x06 -#define V_028AC4_REF_ALWAYS 0x07 -#define S_028AC4_COMPAREVALUE1(x) (((x) & 0xFF) << 4) -#define G_028AC4_COMPAREVALUE1(x) (((x) >> 4) & 0xFF) -#define C_028AC4_COMPAREVALUE1 0xFFFFF00F -#define S_028AC4_COMPAREMASK1(x) (((x) & 0xFF) << 12) -#define G_028AC4_COMPAREMASK1(x) (((x) >> 12) & 0xFF) -#define C_028AC4_COMPAREMASK1 0xFFF00FFF -#define S_028AC4_ENABLE1(x) (((x) & 0x1) << 24) -#define G_028AC4_ENABLE1(x) (((x) >> 24) & 0x1) -#define C_028AC4_ENABLE1 0xFEFFFFFF -#define R_028AC8_DB_PRELOAD_CONTROL 0x028AC8 -#define S_028AC8_START_X(x) (((x) & 0xFF) << 0) -#define G_028AC8_START_X(x) (((x) >> 0) & 0xFF) -#define C_028AC8_START_X 0xFFFFFF00 -#define S_028AC8_START_Y(x) (((x) & 0xFF) << 8) -#define G_028AC8_START_Y(x) (((x) >> 8) & 0xFF) -#define C_028AC8_START_Y 0xFFFF00FF -#define S_028AC8_MAX_X(x) (((x) & 0xFF) << 16) -#define G_028AC8_MAX_X(x) (((x) >> 16) & 0xFF) -#define C_028AC8_MAX_X 0xFF00FFFF -#define S_028AC8_MAX_Y(x) (((x) & 0xFF) << 24) -#define G_028AC8_MAX_Y(x) (((x) >> 24) & 0xFF) -#define C_028AC8_MAX_Y 0x00FFFFFF -#define R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 0x028AD0 -#define R_028AD4_VGT_STRMOUT_VTX_STRIDE_0 0x028AD4 -#define S_028AD4_STRIDE(x) (((x) & 0x3FF) << 0) -#define G_028AD4_STRIDE(x) (((x) >> 0) & 0x3FF) -#define C_028AD4_STRIDE 0xFFFFFC00 -#define R_028ADC_VGT_STRMOUT_BUFFER_OFFSET_0 0x028ADC -#define R_028AE0_VGT_STRMOUT_BUFFER_SIZE_1 0x028AE0 -#define R_028AE4_VGT_STRMOUT_VTX_STRIDE_1 0x028AE4 -#define S_028AE4_STRIDE(x) (((x) & 0x3FF) << 0) -#define G_028AE4_STRIDE(x) (((x) >> 0) & 0x3FF) -#define C_028AE4_STRIDE 0xFFFFFC00 -#define R_028AEC_VGT_STRMOUT_BUFFER_OFFSET_1 0x028AEC -#define R_028AF0_VGT_STRMOUT_BUFFER_SIZE_2 0x028AF0 -#define R_028AF4_VGT_STRMOUT_VTX_STRIDE_2 0x028AF4 -#define S_028AF4_STRIDE(x) (((x) & 0x3FF) << 0) -#define G_028AF4_STRIDE(x) (((x) >> 0) & 0x3FF) -#define C_028AF4_STRIDE 0xFFFFFC00 -#define R_028AFC_VGT_STRMOUT_BUFFER_OFFSET_2 0x028AFC -#define R_028B00_VGT_STRMOUT_BUFFER_SIZE_3 0x028B00 -#define R_028B04_VGT_STRMOUT_VTX_STRIDE_3 0x028B04 -#define S_028B04_STRIDE(x) (((x) & 0x3FF) << 0) -#define G_028B04_STRIDE(x) (((x) >> 0) & 0x3FF) -#define C_028B04_STRIDE 0xFFFFFC00 -#define R_028B0C_VGT_STRMOUT_BUFFER_OFFSET_3 0x028B0C -#define R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET 0x028B28 -#define R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0x028B2C -#define R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0x028B30 -#define S_028B30_VERTEX_STRIDE(x) (((x) & 0x1FF) << 0) -#define G_028B30_VERTEX_STRIDE(x) (((x) >> 0) & 0x1FF) -#define C_028B30_VERTEX_STRIDE 0xFFFFFE00 -#define R_028B38_VGT_GS_MAX_VERT_OUT 0x028B38 -#define S_028B38_MAX_VERT_OUT(x) (((x) & 0x7FF) << 0) -#define G_028B38_MAX_VERT_OUT(x) (((x) >> 0) & 0x7FF) -#define C_028B38_MAX_VERT_OUT 0xFFFFF800 -/* VI */ -#define R_028B50_VGT_TESS_DISTRIBUTION 0x028B50 -#define S_028B50_ACCUM_ISOLINE(x) (((x) & 0xFF) << 0) -#define G_028B50_ACCUM_ISOLINE(x) (((x) >> 0) & 0xFF) -#define C_028B50_ACCUM_ISOLINE 0xFFFFFF00 -#define S_028B50_ACCUM_TRI(x) (((x) & 0xFF) << 8) -#define G_028B50_ACCUM_TRI(x) (((x) >> 8) & 0xFF) -#define C_028B50_ACCUM_TRI 0xFFFF00FF -#define S_028B50_ACCUM_QUAD(x) (((x) & 0xFF) << 16) -#define G_028B50_ACCUM_QUAD(x) (((x) >> 16) & 0xFF) -#define C_028B50_ACCUM_QUAD 0xFF00FFFF -#define S_028B50_DONUT_SPLIT(x) (((x) & 0xFF) << 24) -#define G_028B50_DONUT_SPLIT(x) (((x) >> 24) & 0xFF) -#define C_028B50_DONUT_SPLIT 0x00FFFFFF -/* */ -#define R_028B54_VGT_SHADER_STAGES_EN 0x028B54 -#define S_028B54_LS_EN(x) (((x) & 0x03) << 0) -#define G_028B54_LS_EN(x) (((x) >> 0) & 0x03) -#define C_028B54_LS_EN 0xFFFFFFFC -#define V_028B54_LS_STAGE_OFF 0x00 -#define V_028B54_LS_STAGE_ON 0x01 -#define V_028B54_CS_STAGE_ON 0x02 -#define S_028B54_HS_EN(x) (((x) & 0x1) << 2) -#define G_028B54_HS_EN(x) (((x) >> 2) & 0x1) -#define C_028B54_HS_EN 0xFFFFFFFB -#define S_028B54_ES_EN(x) (((x) & 0x03) << 3) -#define G_028B54_ES_EN(x) (((x) >> 3) & 0x03) -#define C_028B54_ES_EN 0xFFFFFFE7 -#define V_028B54_ES_STAGE_OFF 0x00 -#define V_028B54_ES_STAGE_DS 0x01 -#define V_028B54_ES_STAGE_REAL 0x02 -#define S_028B54_GS_EN(x) (((x) & 0x1) << 5) -#define G_028B54_GS_EN(x) (((x) >> 5) & 0x1) -#define C_028B54_GS_EN 0xFFFFFFDF -#define S_028B54_VS_EN(x) (((x) & 0x03) << 6) -#define G_028B54_VS_EN(x) (((x) >> 6) & 0x03) -#define C_028B54_VS_EN 0xFFFFFF3F -#define V_028B54_VS_STAGE_REAL 0x00 -#define V_028B54_VS_STAGE_DS 0x01 -#define V_028B54_VS_STAGE_COPY_SHADER 0x02 -#define S_028B54_DYNAMIC_HS(x) (((x) & 0x1) << 8) -#define G_028B54_DYNAMIC_HS(x) (((x) >> 8) & 0x1) -#define C_028B54_DYNAMIC_HS 0xFFFFFEFF -/* VI */ -#define S_028B54_DISPATCH_DRAW_EN(x) (((x) & 0x1) << 9) -#define G_028B54_DISPATCH_DRAW_EN(x) (((x) >> 9) & 0x1) -#define C_028B54_DISPATCH_DRAW_EN 0xFFFFFDFF -#define S_028B54_DIS_DEALLOC_ACCUM_0(x) (((x) & 0x1) << 10) -#define G_028B54_DIS_DEALLOC_ACCUM_0(x) (((x) >> 10) & 0x1) -#define C_028B54_DIS_DEALLOC_ACCUM_0 0xFFFFFBFF -#define S_028B54_DIS_DEALLOC_ACCUM_1(x) (((x) & 0x1) << 11) -#define G_028B54_DIS_DEALLOC_ACCUM_1(x) (((x) >> 11) & 0x1) -#define C_028B54_DIS_DEALLOC_ACCUM_1 0xFFFFF7FF -#define S_028B54_VS_WAVE_ID_EN(x) (((x) & 0x1) << 12) -#define G_028B54_VS_WAVE_ID_EN(x) (((x) >> 12) & 0x1) -#define C_028B54_VS_WAVE_ID_EN 0xFFFFEFFF -/* */ -#define R_028B58_VGT_LS_HS_CONFIG 0x028B58 -#define S_028B58_NUM_PATCHES(x) (((x) & 0xFF) << 0) -#define G_028B58_NUM_PATCHES(x) (((x) >> 0) & 0xFF) -#define C_028B58_NUM_PATCHES 0xFFFFFF00 -#define S_028B58_HS_NUM_INPUT_CP(x) (((x) & 0x3F) << 8) -#define G_028B58_HS_NUM_INPUT_CP(x) (((x) >> 8) & 0x3F) -#define C_028B58_HS_NUM_INPUT_CP 0xFFFFC0FF -#define S_028B58_HS_NUM_OUTPUT_CP(x) (((x) & 0x3F) << 14) -#define G_028B58_HS_NUM_OUTPUT_CP(x) (((x) >> 14) & 0x3F) -#define C_028B58_HS_NUM_OUTPUT_CP 0xFFF03FFF -#define R_028B5C_VGT_GS_VERT_ITEMSIZE 0x028B5C -#define S_028B5C_ITEMSIZE(x) (((x) & 0x7FFF) << 0) -#define G_028B5C_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) -#define C_028B5C_ITEMSIZE 0xFFFF8000 -#define R_028B60_VGT_GS_VERT_ITEMSIZE_1 0x028B60 -#define S_028B60_ITEMSIZE(x) (((x) & 0x7FFF) << 0) -#define G_028B60_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) -#define C_028B60_ITEMSIZE 0xFFFF8000 -#define R_028B64_VGT_GS_VERT_ITEMSIZE_2 0x028B64 -#define S_028B64_ITEMSIZE(x) (((x) & 0x7FFF) << 0) -#define G_028B64_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) -#define C_028B64_ITEMSIZE 0xFFFF8000 -#define R_028B68_VGT_GS_VERT_ITEMSIZE_3 0x028B68 -#define S_028B68_ITEMSIZE(x) (((x) & 0x7FFF) << 0) -#define G_028B68_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) -#define C_028B68_ITEMSIZE 0xFFFF8000 -#define R_028B6C_VGT_TF_PARAM 0x028B6C -#define S_028B6C_TYPE(x) (((x) & 0x03) << 0) -#define G_028B6C_TYPE(x) (((x) >> 0) & 0x03) -#define C_028B6C_TYPE 0xFFFFFFFC -#define V_028B6C_TESS_ISOLINE 0x00 -#define V_028B6C_TESS_TRIANGLE 0x01 -#define V_028B6C_TESS_QUAD 0x02 -#define S_028B6C_PARTITIONING(x) (((x) & 0x07) << 2) -#define G_028B6C_PARTITIONING(x) (((x) >> 2) & 0x07) -#define C_028B6C_PARTITIONING 0xFFFFFFE3 -#define V_028B6C_PART_INTEGER 0x00 -#define V_028B6C_PART_POW2 0x01 -#define V_028B6C_PART_FRAC_ODD 0x02 -#define V_028B6C_PART_FRAC_EVEN 0x03 -#define S_028B6C_TOPOLOGY(x) (((x) & 0x07) << 5) -#define G_028B6C_TOPOLOGY(x) (((x) >> 5) & 0x07) -#define C_028B6C_TOPOLOGY 0xFFFFFF1F -#define V_028B6C_OUTPUT_POINT 0x00 -#define V_028B6C_OUTPUT_LINE 0x01 -#define V_028B6C_OUTPUT_TRIANGLE_CW 0x02 -#define V_028B6C_OUTPUT_TRIANGLE_CCW 0x03 -#define S_028B6C_RESERVED_REDUC_AXIS(x) (((x) & 0x1) << 8) /* not on CIK */ -#define G_028B6C_RESERVED_REDUC_AXIS(x) (((x) >> 8) & 0x1) /* not on CIK */ -#define C_028B6C_RESERVED_REDUC_AXIS 0xFFFFFEFF /* not on CIK */ -#define S_028B6C_DEPRECATED(x) (((x) & 0x1) << 9) -#define G_028B6C_DEPRECATED(x) (((x) >> 9) & 0x1) -#define C_028B6C_DEPRECATED 0xFFFFFDFF -#define S_028B6C_NUM_DS_WAVES_PER_SIMD(x) (((x) & 0x0F) << 10) -#define G_028B6C_NUM_DS_WAVES_PER_SIMD(x) (((x) >> 10) & 0x0F) -#define C_028B6C_NUM_DS_WAVES_PER_SIMD 0xFFFFC3FF -#define S_028B6C_DISABLE_DONUTS(x) (((x) & 0x1) << 14) -#define G_028B6C_DISABLE_DONUTS(x) (((x) >> 14) & 0x1) -#define C_028B6C_DISABLE_DONUTS 0xFFFFBFFF -/* CIK */ -#define S_028B6C_RDREQ_POLICY(x) (((x) & 0x03) << 15) -#define G_028B6C_RDREQ_POLICY(x) (((x) >> 15) & 0x03) -#define C_028B6C_RDREQ_POLICY 0xFFFE7FFF -#define V_028B6C_VGT_POLICY_LRU 0x00 -#define V_028B6C_VGT_POLICY_STREAM 0x01 -#define V_028B6C_VGT_POLICY_BYPASS 0x02 -/* */ -/* VI */ -#define S_028B6C_RDREQ_POLICY_VI(x) (((x) & 0x1) << 15) -#define G_028B6C_RDREQ_POLICY_VI(x) (((x) >> 15) & 0x1) -#define C_028B6C_RDREQ_POLICY_VI 0xFFFF7FFF -#define S_028B6C_DISTRIBUTION_MODE(x) (((x) & 0x03) << 17) -#define G_028B6C_DISTRIBUTION_MODE(x) (((x) >> 17) & 0x03) -#define C_028B6C_DISTRIBUTION_MODE 0xFFF9FFFF -#define S_028B6C_MTYPE(x) (((x) & 0x03) << 19) -#define G_028B6C_MTYPE(x) (((x) >> 19) & 0x03) -#define C_028B6C_MTYPE 0xFFE7FFFF -/* */ -#define R_028B70_DB_ALPHA_TO_MASK 0x028B70 -#define S_028B70_ALPHA_TO_MASK_ENABLE(x) (((x) & 0x1) << 0) -#define G_028B70_ALPHA_TO_MASK_ENABLE(x) (((x) >> 0) & 0x1) -#define C_028B70_ALPHA_TO_MASK_ENABLE 0xFFFFFFFE -#define S_028B70_ALPHA_TO_MASK_OFFSET0(x) (((x) & 0x03) << 8) -#define G_028B70_ALPHA_TO_MASK_OFFSET0(x) (((x) >> 8) & 0x03) -#define C_028B70_ALPHA_TO_MASK_OFFSET0 0xFFFFFCFF -#define S_028B70_ALPHA_TO_MASK_OFFSET1(x) (((x) & 0x03) << 10) -#define G_028B70_ALPHA_TO_MASK_OFFSET1(x) (((x) >> 10) & 0x03) -#define C_028B70_ALPHA_TO_MASK_OFFSET1 0xFFFFF3FF -#define S_028B70_ALPHA_TO_MASK_OFFSET2(x) (((x) & 0x03) << 12) -#define G_028B70_ALPHA_TO_MASK_OFFSET2(x) (((x) >> 12) & 0x03) -#define C_028B70_ALPHA_TO_MASK_OFFSET2 0xFFFFCFFF -#define S_028B70_ALPHA_TO_MASK_OFFSET3(x) (((x) & 0x03) << 14) -#define G_028B70_ALPHA_TO_MASK_OFFSET3(x) (((x) >> 14) & 0x03) -#define C_028B70_ALPHA_TO_MASK_OFFSET3 0xFFFF3FFF -#define S_028B70_OFFSET_ROUND(x) (((x) & 0x1) << 16) -#define G_028B70_OFFSET_ROUND(x) (((x) >> 16) & 0x1) -#define C_028B70_OFFSET_ROUND 0xFFFEFFFF -/* CIK */ -#define R_028B74_VGT_DISPATCH_DRAW_INDEX 0x028B74 -/* */ -#define R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL 0x028B78 -#define S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(x) (((x) & 0xFF) << 0) -#define G_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(x) (((x) >> 0) & 0xFF) -#define C_028B78_POLY_OFFSET_NEG_NUM_DB_BITS 0xFFFFFF00 -#define S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(x) (((x) & 0x1) << 8) -#define G_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(x) (((x) >> 8) & 0x1) -#define C_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT 0xFFFFFEFF -#define R_028B7C_PA_SU_POLY_OFFSET_CLAMP 0x028B7C -#define R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE 0x028B80 -#define R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET 0x028B84 -#define R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE 0x028B88 -#define R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET 0x028B8C -#define R_028B90_VGT_GS_INSTANCE_CNT 0x028B90 -#define S_028B90_ENABLE(x) (((x) & 0x1) << 0) -#define G_028B90_ENABLE(x) (((x) >> 0) & 0x1) -#define C_028B90_ENABLE 0xFFFFFFFE -#define S_028B90_CNT(x) (((x) & 0x7F) << 2) -#define G_028B90_CNT(x) (((x) >> 2) & 0x7F) -#define C_028B90_CNT 0xFFFFFE03 -#define R_028B94_VGT_STRMOUT_CONFIG 0x028B94 -#define S_028B94_STREAMOUT_0_EN(x) (((x) & 0x1) << 0) -#define G_028B94_STREAMOUT_0_EN(x) (((x) >> 0) & 0x1) -#define C_028B94_STREAMOUT_0_EN 0xFFFFFFFE -#define S_028B94_STREAMOUT_1_EN(x) (((x) & 0x1) << 1) -#define G_028B94_STREAMOUT_1_EN(x) (((x) >> 1) & 0x1) -#define C_028B94_STREAMOUT_1_EN 0xFFFFFFFD -#define S_028B94_STREAMOUT_2_EN(x) (((x) & 0x1) << 2) -#define G_028B94_STREAMOUT_2_EN(x) (((x) >> 2) & 0x1) -#define C_028B94_STREAMOUT_2_EN 0xFFFFFFFB -#define S_028B94_STREAMOUT_3_EN(x) (((x) & 0x1) << 3) -#define G_028B94_STREAMOUT_3_EN(x) (((x) >> 3) & 0x1) -#define C_028B94_STREAMOUT_3_EN 0xFFFFFFF7 -#define S_028B94_RAST_STREAM(x) (((x) & 0x07) << 4) -#define G_028B94_RAST_STREAM(x) (((x) >> 4) & 0x07) -#define C_028B94_RAST_STREAM 0xFFFFFF8F -#define S_028B94_RAST_STREAM_MASK(x) (((x) & 0x0F) << 8) -#define G_028B94_RAST_STREAM_MASK(x) (((x) >> 8) & 0x0F) -#define C_028B94_RAST_STREAM_MASK 0xFFFFF0FF -#define S_028B94_USE_RAST_STREAM_MASK(x) (((x) & 0x1) << 31) -#define G_028B94_USE_RAST_STREAM_MASK(x) (((x) >> 31) & 0x1) -#define C_028B94_USE_RAST_STREAM_MASK 0x7FFFFFFF -#define R_028B98_VGT_STRMOUT_BUFFER_CONFIG 0x028B98 -#define S_028B98_STREAM_0_BUFFER_EN(x) (((x) & 0x0F) << 0) -#define G_028B98_STREAM_0_BUFFER_EN(x) (((x) >> 0) & 0x0F) -#define C_028B98_STREAM_0_BUFFER_EN 0xFFFFFFF0 -#define S_028B98_STREAM_1_BUFFER_EN(x) (((x) & 0x0F) << 4) -#define G_028B98_STREAM_1_BUFFER_EN(x) (((x) >> 4) & 0x0F) -#define C_028B98_STREAM_1_BUFFER_EN 0xFFFFFF0F -#define S_028B98_STREAM_2_BUFFER_EN(x) (((x) & 0x0F) << 8) -#define G_028B98_STREAM_2_BUFFER_EN(x) (((x) >> 8) & 0x0F) -#define C_028B98_STREAM_2_BUFFER_EN 0xFFFFF0FF -#define S_028B98_STREAM_3_BUFFER_EN(x) (((x) & 0x0F) << 12) -#define G_028B98_STREAM_3_BUFFER_EN(x) (((x) >> 12) & 0x0F) -#define C_028B98_STREAM_3_BUFFER_EN 0xFFFF0FFF -#define R_028BD4_PA_SC_CENTROID_PRIORITY_0 0x028BD4 -#define S_028BD4_DISTANCE_0(x) (((x) & 0x0F) << 0) -#define G_028BD4_DISTANCE_0(x) (((x) >> 0) & 0x0F) -#define C_028BD4_DISTANCE_0 0xFFFFFFF0 -#define S_028BD4_DISTANCE_1(x) (((x) & 0x0F) << 4) -#define G_028BD4_DISTANCE_1(x) (((x) >> 4) & 0x0F) -#define C_028BD4_DISTANCE_1 0xFFFFFF0F -#define S_028BD4_DISTANCE_2(x) (((x) & 0x0F) << 8) -#define G_028BD4_DISTANCE_2(x) (((x) >> 8) & 0x0F) -#define C_028BD4_DISTANCE_2 0xFFFFF0FF -#define S_028BD4_DISTANCE_3(x) (((x) & 0x0F) << 12) -#define G_028BD4_DISTANCE_3(x) (((x) >> 12) & 0x0F) -#define C_028BD4_DISTANCE_3 0xFFFF0FFF -#define S_028BD4_DISTANCE_4(x) (((x) & 0x0F) << 16) -#define G_028BD4_DISTANCE_4(x) (((x) >> 16) & 0x0F) -#define C_028BD4_DISTANCE_4 0xFFF0FFFF -#define S_028BD4_DISTANCE_5(x) (((x) & 0x0F) << 20) -#define G_028BD4_DISTANCE_5(x) (((x) >> 20) & 0x0F) -#define C_028BD4_DISTANCE_5 0xFF0FFFFF -#define S_028BD4_DISTANCE_6(x) (((x) & 0x0F) << 24) -#define G_028BD4_DISTANCE_6(x) (((x) >> 24) & 0x0F) -#define C_028BD4_DISTANCE_6 0xF0FFFFFF -#define S_028BD4_DISTANCE_7(x) (((x) & 0x0F) << 28) -#define G_028BD4_DISTANCE_7(x) (((x) >> 28) & 0x0F) -#define C_028BD4_DISTANCE_7 0x0FFFFFFF -#define R_028BD8_PA_SC_CENTROID_PRIORITY_1 0x028BD8 -#define S_028BD8_DISTANCE_8(x) (((x) & 0x0F) << 0) -#define G_028BD8_DISTANCE_8(x) (((x) >> 0) & 0x0F) -#define C_028BD8_DISTANCE_8 0xFFFFFFF0 -#define S_028BD8_DISTANCE_9(x) (((x) & 0x0F) << 4) -#define G_028BD8_DISTANCE_9(x) (((x) >> 4) & 0x0F) -#define C_028BD8_DISTANCE_9 0xFFFFFF0F -#define S_028BD8_DISTANCE_10(x) (((x) & 0x0F) << 8) -#define G_028BD8_DISTANCE_10(x) (((x) >> 8) & 0x0F) -#define C_028BD8_DISTANCE_10 0xFFFFF0FF -#define S_028BD8_DISTANCE_11(x) (((x) & 0x0F) << 12) -#define G_028BD8_DISTANCE_11(x) (((x) >> 12) & 0x0F) -#define C_028BD8_DISTANCE_11 0xFFFF0FFF -#define S_028BD8_DISTANCE_12(x) (((x) & 0x0F) << 16) -#define G_028BD8_DISTANCE_12(x) (((x) >> 16) & 0x0F) -#define C_028BD8_DISTANCE_12 0xFFF0FFFF -#define S_028BD8_DISTANCE_13(x) (((x) & 0x0F) << 20) -#define G_028BD8_DISTANCE_13(x) (((x) >> 20) & 0x0F) -#define C_028BD8_DISTANCE_13 0xFF0FFFFF -#define S_028BD8_DISTANCE_14(x) (((x) & 0x0F) << 24) -#define G_028BD8_DISTANCE_14(x) (((x) >> 24) & 0x0F) -#define C_028BD8_DISTANCE_14 0xF0FFFFFF -#define S_028BD8_DISTANCE_15(x) (((x) & 0x0F) << 28) -#define G_028BD8_DISTANCE_15(x) (((x) >> 28) & 0x0F) -#define C_028BD8_DISTANCE_15 0x0FFFFFFF -#define R_028BDC_PA_SC_LINE_CNTL 0x028BDC -#define S_028BDC_EXPAND_LINE_WIDTH(x) (((x) & 0x1) << 9) -#define G_028BDC_EXPAND_LINE_WIDTH(x) (((x) >> 9) & 0x1) -#define C_028BDC_EXPAND_LINE_WIDTH 0xFFFFFDFF -#define S_028BDC_LAST_PIXEL(x) (((x) & 0x1) << 10) -#define G_028BDC_LAST_PIXEL(x) (((x) >> 10) & 0x1) -#define C_028BDC_LAST_PIXEL 0xFFFFFBFF -#define S_028BDC_PERPENDICULAR_ENDCAP_ENA(x) (((x) & 0x1) << 11) -#define G_028BDC_PERPENDICULAR_ENDCAP_ENA(x) (((x) >> 11) & 0x1) -#define C_028BDC_PERPENDICULAR_ENDCAP_ENA 0xFFFFF7FF -#define S_028BDC_DX10_DIAMOND_TEST_ENA(x) (((x) & 0x1) << 12) -#define G_028BDC_DX10_DIAMOND_TEST_ENA(x) (((x) >> 12) & 0x1) -#define C_028BDC_DX10_DIAMOND_TEST_ENA 0xFFFFEFFF -#define R_028BE0_PA_SC_AA_CONFIG 0x028BE0 -#define S_028BE0_MSAA_NUM_SAMPLES(x) (((x) & 0x7) << 0) -#define G_028BE0_MSAA_NUM_SAMPLES(x) (((x) >> 0) & 0x07) -#define C_028BE0_MSAA_NUM_SAMPLES 0xFFFFFFF8 -#define S_028BE0_AA_MASK_CENTROID_DTMN(x) (((x) & 0x1) << 4) -#define G_028BE0_AA_MASK_CENTROID_DTMN(x) (((x) >> 4) & 0x1) -#define C_028BE0_AA_MASK_CENTROID_DTMN 0xFFFFFFEF -#define S_028BE0_MAX_SAMPLE_DIST(x) (((x) & 0xf) << 13) -#define G_028BE0_MAX_SAMPLE_DIST(x) (((x) >> 13) & 0x0F) -#define C_028BE0_MAX_SAMPLE_DIST 0xFFFE1FFF -#define S_028BE0_MSAA_EXPOSED_SAMPLES(x) (((x) & 0x7) << 20) -#define G_028BE0_MSAA_EXPOSED_SAMPLES(x) (((x) >> 20) & 0x07) -#define C_028BE0_MSAA_EXPOSED_SAMPLES 0xFF8FFFFF -#define S_028BE0_DETAIL_TO_EXPOSED_MODE(x) (((x) & 0x3) << 24) -#define G_028BE0_DETAIL_TO_EXPOSED_MODE(x) (((x) >> 24) & 0x03) -#define C_028BE0_DETAIL_TO_EXPOSED_MODE 0xFCFFFFFF -#define R_028BE4_PA_SU_VTX_CNTL 0x028BE4 -#define S_028BE4_PIX_CENTER(x) (((x) & 0x1) << 0) -#define G_028BE4_PIX_CENTER(x) (((x) >> 0) & 0x1) -#define C_028BE4_PIX_CENTER 0xFFFFFFFE -#define S_028BE4_ROUND_MODE(x) (((x) & 0x03) << 1) -#define G_028BE4_ROUND_MODE(x) (((x) >> 1) & 0x03) -#define C_028BE4_ROUND_MODE 0xFFFFFFF9 -#define V_028BE4_X_TRUNCATE 0x00 -#define V_028BE4_X_ROUND 0x01 -#define V_028BE4_X_ROUND_TO_EVEN 0x02 -#define V_028BE4_X_ROUND_TO_ODD 0x03 -#define S_028BE4_QUANT_MODE(x) (((x) & 0x07) << 3) -#define G_028BE4_QUANT_MODE(x) (((x) >> 3) & 0x07) -#define C_028BE4_QUANT_MODE 0xFFFFFFC7 -#define V_028BE4_X_16_8_FIXED_POINT_1_16TH 0x00 -#define V_028BE4_X_16_8_FIXED_POINT_1_8TH 0x01 -#define V_028BE4_X_16_8_FIXED_POINT_1_4TH 0x02 -#define V_028BE4_X_16_8_FIXED_POINT_1_2 0x03 -#define V_028BE4_X_16_8_FIXED_POINT_1 0x04 -#define V_028BE4_X_16_8_FIXED_POINT_1_256TH 0x05 -#define V_028BE4_X_14_10_FIXED_POINT_1_1024TH 0x06 -#define V_028BE4_X_12_12_FIXED_POINT_1_4096TH 0x07 -#define R_028BE8_PA_CL_GB_VERT_CLIP_ADJ 0x028BE8 -#define R_028BEC_PA_CL_GB_VERT_DISC_ADJ 0x028BEC -#define R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ 0x028BF0 -#define R_028BF4_PA_CL_GB_HORZ_DISC_ADJ 0x028BF4 -#define R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0x028BF8 -#define S_028BF8_S0_X(x) (((x) & 0x0F) << 0) -#define G_028BF8_S0_X(x) (((x) >> 0) & 0x0F) -#define C_028BF8_S0_X 0xFFFFFFF0 -#define S_028BF8_S0_Y(x) (((x) & 0x0F) << 4) -#define G_028BF8_S0_Y(x) (((x) >> 4) & 0x0F) -#define C_028BF8_S0_Y 0xFFFFFF0F -#define S_028BF8_S1_X(x) (((x) & 0x0F) << 8) -#define G_028BF8_S1_X(x) (((x) >> 8) & 0x0F) -#define C_028BF8_S1_X 0xFFFFF0FF -#define S_028BF8_S1_Y(x) (((x) & 0x0F) << 12) -#define G_028BF8_S1_Y(x) (((x) >> 12) & 0x0F) -#define C_028BF8_S1_Y 0xFFFF0FFF -#define S_028BF8_S2_X(x) (((x) & 0x0F) << 16) -#define G_028BF8_S2_X(x) (((x) >> 16) & 0x0F) -#define C_028BF8_S2_X 0xFFF0FFFF -#define S_028BF8_S2_Y(x) (((x) & 0x0F) << 20) -#define G_028BF8_S2_Y(x) (((x) >> 20) & 0x0F) -#define C_028BF8_S2_Y 0xFF0FFFFF -#define S_028BF8_S3_X(x) (((x) & 0x0F) << 24) -#define G_028BF8_S3_X(x) (((x) >> 24) & 0x0F) -#define C_028BF8_S3_X 0xF0FFFFFF -#define S_028BF8_S3_Y(x) (((x) & 0x0F) << 28) -#define G_028BF8_S3_Y(x) (((x) >> 28) & 0x0F) -#define C_028BF8_S3_Y 0x0FFFFFFF -#define R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0x028BFC -#define S_028BFC_S4_X(x) (((x) & 0x0F) << 0) -#define G_028BFC_S4_X(x) (((x) >> 0) & 0x0F) -#define C_028BFC_S4_X 0xFFFFFFF0 -#define S_028BFC_S4_Y(x) (((x) & 0x0F) << 4) -#define G_028BFC_S4_Y(x) (((x) >> 4) & 0x0F) -#define C_028BFC_S4_Y 0xFFFFFF0F -#define S_028BFC_S5_X(x) (((x) & 0x0F) << 8) -#define G_028BFC_S5_X(x) (((x) >> 8) & 0x0F) -#define C_028BFC_S5_X 0xFFFFF0FF -#define S_028BFC_S5_Y(x) (((x) & 0x0F) << 12) -#define G_028BFC_S5_Y(x) (((x) >> 12) & 0x0F) -#define C_028BFC_S5_Y 0xFFFF0FFF -#define S_028BFC_S6_X(x) (((x) & 0x0F) << 16) -#define G_028BFC_S6_X(x) (((x) >> 16) & 0x0F) -#define C_028BFC_S6_X 0xFFF0FFFF -#define S_028BFC_S6_Y(x) (((x) & 0x0F) << 20) -#define G_028BFC_S6_Y(x) (((x) >> 20) & 0x0F) -#define C_028BFC_S6_Y 0xFF0FFFFF -#define S_028BFC_S7_X(x) (((x) & 0x0F) << 24) -#define G_028BFC_S7_X(x) (((x) >> 24) & 0x0F) -#define C_028BFC_S7_X 0xF0FFFFFF -#define S_028BFC_S7_Y(x) (((x) & 0x0F) << 28) -#define G_028BFC_S7_Y(x) (((x) >> 28) & 0x0F) -#define C_028BFC_S7_Y 0x0FFFFFFF -#define R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0x028C00 -#define S_028C00_S8_X(x) (((x) & 0x0F) << 0) -#define G_028C00_S8_X(x) (((x) >> 0) & 0x0F) -#define C_028C00_S8_X 0xFFFFFFF0 -#define S_028C00_S8_Y(x) (((x) & 0x0F) << 4) -#define G_028C00_S8_Y(x) (((x) >> 4) & 0x0F) -#define C_028C00_S8_Y 0xFFFFFF0F -#define S_028C00_S9_X(x) (((x) & 0x0F) << 8) -#define G_028C00_S9_X(x) (((x) >> 8) & 0x0F) -#define C_028C00_S9_X 0xFFFFF0FF -#define S_028C00_S9_Y(x) (((x) & 0x0F) << 12) -#define G_028C00_S9_Y(x) (((x) >> 12) & 0x0F) -#define C_028C00_S9_Y 0xFFFF0FFF -#define S_028C00_S10_X(x) (((x) & 0x0F) << 16) -#define G_028C00_S10_X(x) (((x) >> 16) & 0x0F) -#define C_028C00_S10_X 0xFFF0FFFF -#define S_028C00_S10_Y(x) (((x) & 0x0F) << 20) -#define G_028C00_S10_Y(x) (((x) >> 20) & 0x0F) -#define C_028C00_S10_Y 0xFF0FFFFF -#define S_028C00_S11_X(x) (((x) & 0x0F) << 24) -#define G_028C00_S11_X(x) (((x) >> 24) & 0x0F) -#define C_028C00_S11_X 0xF0FFFFFF -#define S_028C00_S11_Y(x) (((x) & 0x0F) << 28) -#define G_028C00_S11_Y(x) (((x) >> 28) & 0x0F) -#define C_028C00_S11_Y 0x0FFFFFFF -#define R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0x028C04 -#define S_028C04_S12_X(x) (((x) & 0x0F) << 0) -#define G_028C04_S12_X(x) (((x) >> 0) & 0x0F) -#define C_028C04_S12_X 0xFFFFFFF0 -#define S_028C04_S12_Y(x) (((x) & 0x0F) << 4) -#define G_028C04_S12_Y(x) (((x) >> 4) & 0x0F) -#define C_028C04_S12_Y 0xFFFFFF0F -#define S_028C04_S13_X(x) (((x) & 0x0F) << 8) -#define G_028C04_S13_X(x) (((x) >> 8) & 0x0F) -#define C_028C04_S13_X 0xFFFFF0FF -#define S_028C04_S13_Y(x) (((x) & 0x0F) << 12) -#define G_028C04_S13_Y(x) (((x) >> 12) & 0x0F) -#define C_028C04_S13_Y 0xFFFF0FFF -#define S_028C04_S14_X(x) (((x) & 0x0F) << 16) -#define G_028C04_S14_X(x) (((x) >> 16) & 0x0F) -#define C_028C04_S14_X 0xFFF0FFFF -#define S_028C04_S14_Y(x) (((x) & 0x0F) << 20) -#define G_028C04_S14_Y(x) (((x) >> 20) & 0x0F) -#define C_028C04_S14_Y 0xFF0FFFFF -#define S_028C04_S15_X(x) (((x) & 0x0F) << 24) -#define G_028C04_S15_X(x) (((x) >> 24) & 0x0F) -#define C_028C04_S15_X 0xF0FFFFFF -#define S_028C04_S15_Y(x) (((x) & 0x0F) << 28) -#define G_028C04_S15_Y(x) (((x) >> 28) & 0x0F) -#define C_028C04_S15_Y 0x0FFFFFFF -#define R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0x028C08 -#define S_028C08_S0_X(x) (((x) & 0x0F) << 0) -#define G_028C08_S0_X(x) (((x) >> 0) & 0x0F) -#define C_028C08_S0_X 0xFFFFFFF0 -#define S_028C08_S0_Y(x) (((x) & 0x0F) << 4) -#define G_028C08_S0_Y(x) (((x) >> 4) & 0x0F) -#define C_028C08_S0_Y 0xFFFFFF0F -#define S_028C08_S1_X(x) (((x) & 0x0F) << 8) -#define G_028C08_S1_X(x) (((x) >> 8) & 0x0F) -#define C_028C08_S1_X 0xFFFFF0FF -#define S_028C08_S1_Y(x) (((x) & 0x0F) << 12) -#define G_028C08_S1_Y(x) (((x) >> 12) & 0x0F) -#define C_028C08_S1_Y 0xFFFF0FFF -#define S_028C08_S2_X(x) (((x) & 0x0F) << 16) -#define G_028C08_S2_X(x) (((x) >> 16) & 0x0F) -#define C_028C08_S2_X 0xFFF0FFFF -#define S_028C08_S2_Y(x) (((x) & 0x0F) << 20) -#define G_028C08_S2_Y(x) (((x) >> 20) & 0x0F) -#define C_028C08_S2_Y 0xFF0FFFFF -#define S_028C08_S3_X(x) (((x) & 0x0F) << 24) -#define G_028C08_S3_X(x) (((x) >> 24) & 0x0F) -#define C_028C08_S3_X 0xF0FFFFFF -#define S_028C08_S3_Y(x) (((x) & 0x0F) << 28) -#define G_028C08_S3_Y(x) (((x) >> 28) & 0x0F) -#define C_028C08_S3_Y 0x0FFFFFFF -#define R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0x028C0C -#define S_028C0C_S4_X(x) (((x) & 0x0F) << 0) -#define G_028C0C_S4_X(x) (((x) >> 0) & 0x0F) -#define C_028C0C_S4_X 0xFFFFFFF0 -#define S_028C0C_S4_Y(x) (((x) & 0x0F) << 4) -#define G_028C0C_S4_Y(x) (((x) >> 4) & 0x0F) -#define C_028C0C_S4_Y 0xFFFFFF0F -#define S_028C0C_S5_X(x) (((x) & 0x0F) << 8) -#define G_028C0C_S5_X(x) (((x) >> 8) & 0x0F) -#define C_028C0C_S5_X 0xFFFFF0FF -#define S_028C0C_S5_Y(x) (((x) & 0x0F) << 12) -#define G_028C0C_S5_Y(x) (((x) >> 12) & 0x0F) -#define C_028C0C_S5_Y 0xFFFF0FFF -#define S_028C0C_S6_X(x) (((x) & 0x0F) << 16) -#define G_028C0C_S6_X(x) (((x) >> 16) & 0x0F) -#define C_028C0C_S6_X 0xFFF0FFFF -#define S_028C0C_S6_Y(x) (((x) & 0x0F) << 20) -#define G_028C0C_S6_Y(x) (((x) >> 20) & 0x0F) -#define C_028C0C_S6_Y 0xFF0FFFFF -#define S_028C0C_S7_X(x) (((x) & 0x0F) << 24) -#define G_028C0C_S7_X(x) (((x) >> 24) & 0x0F) -#define C_028C0C_S7_X 0xF0FFFFFF -#define S_028C0C_S7_Y(x) (((x) & 0x0F) << 28) -#define G_028C0C_S7_Y(x) (((x) >> 28) & 0x0F) -#define C_028C0C_S7_Y 0x0FFFFFFF -#define R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0x028C10 -#define S_028C10_S8_X(x) (((x) & 0x0F) << 0) -#define G_028C10_S8_X(x) (((x) >> 0) & 0x0F) -#define C_028C10_S8_X 0xFFFFFFF0 -#define S_028C10_S8_Y(x) (((x) & 0x0F) << 4) -#define G_028C10_S8_Y(x) (((x) >> 4) & 0x0F) -#define C_028C10_S8_Y 0xFFFFFF0F -#define S_028C10_S9_X(x) (((x) & 0x0F) << 8) -#define G_028C10_S9_X(x) (((x) >> 8) & 0x0F) -#define C_028C10_S9_X 0xFFFFF0FF -#define S_028C10_S9_Y(x) (((x) & 0x0F) << 12) -#define G_028C10_S9_Y(x) (((x) >> 12) & 0x0F) -#define C_028C10_S9_Y 0xFFFF0FFF -#define S_028C10_S10_X(x) (((x) & 0x0F) << 16) -#define G_028C10_S10_X(x) (((x) >> 16) & 0x0F) -#define C_028C10_S10_X 0xFFF0FFFF -#define S_028C10_S10_Y(x) (((x) & 0x0F) << 20) -#define G_028C10_S10_Y(x) (((x) >> 20) & 0x0F) -#define C_028C10_S10_Y 0xFF0FFFFF -#define S_028C10_S11_X(x) (((x) & 0x0F) << 24) -#define G_028C10_S11_X(x) (((x) >> 24) & 0x0F) -#define C_028C10_S11_X 0xF0FFFFFF -#define S_028C10_S11_Y(x) (((x) & 0x0F) << 28) -#define G_028C10_S11_Y(x) (((x) >> 28) & 0x0F) -#define C_028C10_S11_Y 0x0FFFFFFF -#define R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0x028C14 -#define S_028C14_S12_X(x) (((x) & 0x0F) << 0) -#define G_028C14_S12_X(x) (((x) >> 0) & 0x0F) -#define C_028C14_S12_X 0xFFFFFFF0 -#define S_028C14_S12_Y(x) (((x) & 0x0F) << 4) -#define G_028C14_S12_Y(x) (((x) >> 4) & 0x0F) -#define C_028C14_S12_Y 0xFFFFFF0F -#define S_028C14_S13_X(x) (((x) & 0x0F) << 8) -#define G_028C14_S13_X(x) (((x) >> 8) & 0x0F) -#define C_028C14_S13_X 0xFFFFF0FF -#define S_028C14_S13_Y(x) (((x) & 0x0F) << 12) -#define G_028C14_S13_Y(x) (((x) >> 12) & 0x0F) -#define C_028C14_S13_Y 0xFFFF0FFF -#define S_028C14_S14_X(x) (((x) & 0x0F) << 16) -#define G_028C14_S14_X(x) (((x) >> 16) & 0x0F) -#define C_028C14_S14_X 0xFFF0FFFF -#define S_028C14_S14_Y(x) (((x) & 0x0F) << 20) -#define G_028C14_S14_Y(x) (((x) >> 20) & 0x0F) -#define C_028C14_S14_Y 0xFF0FFFFF -#define S_028C14_S15_X(x) (((x) & 0x0F) << 24) -#define G_028C14_S15_X(x) (((x) >> 24) & 0x0F) -#define C_028C14_S15_X 0xF0FFFFFF -#define S_028C14_S15_Y(x) (((x) & 0x0F) << 28) -#define G_028C14_S15_Y(x) (((x) >> 28) & 0x0F) -#define C_028C14_S15_Y 0x0FFFFFFF -#define R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0x028C18 -#define S_028C18_S0_X(x) (((x) & 0x0F) << 0) -#define G_028C18_S0_X(x) (((x) >> 0) & 0x0F) -#define C_028C18_S0_X 0xFFFFFFF0 -#define S_028C18_S0_Y(x) (((x) & 0x0F) << 4) -#define G_028C18_S0_Y(x) (((x) >> 4) & 0x0F) -#define C_028C18_S0_Y 0xFFFFFF0F -#define S_028C18_S1_X(x) (((x) & 0x0F) << 8) -#define G_028C18_S1_X(x) (((x) >> 8) & 0x0F) -#define C_028C18_S1_X 0xFFFFF0FF -#define S_028C18_S1_Y(x) (((x) & 0x0F) << 12) -#define G_028C18_S1_Y(x) (((x) >> 12) & 0x0F) -#define C_028C18_S1_Y 0xFFFF0FFF -#define S_028C18_S2_X(x) (((x) & 0x0F) << 16) -#define G_028C18_S2_X(x) (((x) >> 16) & 0x0F) -#define C_028C18_S2_X 0xFFF0FFFF -#define S_028C18_S2_Y(x) (((x) & 0x0F) << 20) -#define G_028C18_S2_Y(x) (((x) >> 20) & 0x0F) -#define C_028C18_S2_Y 0xFF0FFFFF -#define S_028C18_S3_X(x) (((x) & 0x0F) << 24) -#define G_028C18_S3_X(x) (((x) >> 24) & 0x0F) -#define C_028C18_S3_X 0xF0FFFFFF -#define S_028C18_S3_Y(x) (((x) & 0x0F) << 28) -#define G_028C18_S3_Y(x) (((x) >> 28) & 0x0F) -#define C_028C18_S3_Y 0x0FFFFFFF -#define R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0x028C1C -#define S_028C1C_S4_X(x) (((x) & 0x0F) << 0) -#define G_028C1C_S4_X(x) (((x) >> 0) & 0x0F) -#define C_028C1C_S4_X 0xFFFFFFF0 -#define S_028C1C_S4_Y(x) (((x) & 0x0F) << 4) -#define G_028C1C_S4_Y(x) (((x) >> 4) & 0x0F) -#define C_028C1C_S4_Y 0xFFFFFF0F -#define S_028C1C_S5_X(x) (((x) & 0x0F) << 8) -#define G_028C1C_S5_X(x) (((x) >> 8) & 0x0F) -#define C_028C1C_S5_X 0xFFFFF0FF -#define S_028C1C_S5_Y(x) (((x) & 0x0F) << 12) -#define G_028C1C_S5_Y(x) (((x) >> 12) & 0x0F) -#define C_028C1C_S5_Y 0xFFFF0FFF -#define S_028C1C_S6_X(x) (((x) & 0x0F) << 16) -#define G_028C1C_S6_X(x) (((x) >> 16) & 0x0F) -#define C_028C1C_S6_X 0xFFF0FFFF -#define S_028C1C_S6_Y(x) (((x) & 0x0F) << 20) -#define G_028C1C_S6_Y(x) (((x) >> 20) & 0x0F) -#define C_028C1C_S6_Y 0xFF0FFFFF -#define S_028C1C_S7_X(x) (((x) & 0x0F) << 24) -#define G_028C1C_S7_X(x) (((x) >> 24) & 0x0F) -#define C_028C1C_S7_X 0xF0FFFFFF -#define S_028C1C_S7_Y(x) (((x) & 0x0F) << 28) -#define G_028C1C_S7_Y(x) (((x) >> 28) & 0x0F) -#define C_028C1C_S7_Y 0x0FFFFFFF -#define R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0x028C20 -#define S_028C20_S8_X(x) (((x) & 0x0F) << 0) -#define G_028C20_S8_X(x) (((x) >> 0) & 0x0F) -#define C_028C20_S8_X 0xFFFFFFF0 -#define S_028C20_S8_Y(x) (((x) & 0x0F) << 4) -#define G_028C20_S8_Y(x) (((x) >> 4) & 0x0F) -#define C_028C20_S8_Y 0xFFFFFF0F -#define S_028C20_S9_X(x) (((x) & 0x0F) << 8) -#define G_028C20_S9_X(x) (((x) >> 8) & 0x0F) -#define C_028C20_S9_X 0xFFFFF0FF -#define S_028C20_S9_Y(x) (((x) & 0x0F) << 12) -#define G_028C20_S9_Y(x) (((x) >> 12) & 0x0F) -#define C_028C20_S9_Y 0xFFFF0FFF -#define S_028C20_S10_X(x) (((x) & 0x0F) << 16) -#define G_028C20_S10_X(x) (((x) >> 16) & 0x0F) -#define C_028C20_S10_X 0xFFF0FFFF -#define S_028C20_S10_Y(x) (((x) & 0x0F) << 20) -#define G_028C20_S10_Y(x) (((x) >> 20) & 0x0F) -#define C_028C20_S10_Y 0xFF0FFFFF -#define S_028C20_S11_X(x) (((x) & 0x0F) << 24) -#define G_028C20_S11_X(x) (((x) >> 24) & 0x0F) -#define C_028C20_S11_X 0xF0FFFFFF -#define S_028C20_S11_Y(x) (((x) & 0x0F) << 28) -#define G_028C20_S11_Y(x) (((x) >> 28) & 0x0F) -#define C_028C20_S11_Y 0x0FFFFFFF -#define R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0x028C24 -#define S_028C24_S12_X(x) (((x) & 0x0F) << 0) -#define G_028C24_S12_X(x) (((x) >> 0) & 0x0F) -#define C_028C24_S12_X 0xFFFFFFF0 -#define S_028C24_S12_Y(x) (((x) & 0x0F) << 4) -#define G_028C24_S12_Y(x) (((x) >> 4) & 0x0F) -#define C_028C24_S12_Y 0xFFFFFF0F -#define S_028C24_S13_X(x) (((x) & 0x0F) << 8) -#define G_028C24_S13_X(x) (((x) >> 8) & 0x0F) -#define C_028C24_S13_X 0xFFFFF0FF -#define S_028C24_S13_Y(x) (((x) & 0x0F) << 12) -#define G_028C24_S13_Y(x) (((x) >> 12) & 0x0F) -#define C_028C24_S13_Y 0xFFFF0FFF -#define S_028C24_S14_X(x) (((x) & 0x0F) << 16) -#define G_028C24_S14_X(x) (((x) >> 16) & 0x0F) -#define C_028C24_S14_X 0xFFF0FFFF -#define S_028C24_S14_Y(x) (((x) & 0x0F) << 20) -#define G_028C24_S14_Y(x) (((x) >> 20) & 0x0F) -#define C_028C24_S14_Y 0xFF0FFFFF -#define S_028C24_S15_X(x) (((x) & 0x0F) << 24) -#define G_028C24_S15_X(x) (((x) >> 24) & 0x0F) -#define C_028C24_S15_X 0xF0FFFFFF -#define S_028C24_S15_Y(x) (((x) & 0x0F) << 28) -#define G_028C24_S15_Y(x) (((x) >> 28) & 0x0F) -#define C_028C24_S15_Y 0x0FFFFFFF -#define R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0x028C28 -#define S_028C28_S0_X(x) (((x) & 0x0F) << 0) -#define G_028C28_S0_X(x) (((x) >> 0) & 0x0F) -#define C_028C28_S0_X 0xFFFFFFF0 -#define S_028C28_S0_Y(x) (((x) & 0x0F) << 4) -#define G_028C28_S0_Y(x) (((x) >> 4) & 0x0F) -#define C_028C28_S0_Y 0xFFFFFF0F -#define S_028C28_S1_X(x) (((x) & 0x0F) << 8) -#define G_028C28_S1_X(x) (((x) >> 8) & 0x0F) -#define C_028C28_S1_X 0xFFFFF0FF -#define S_028C28_S1_Y(x) (((x) & 0x0F) << 12) -#define G_028C28_S1_Y(x) (((x) >> 12) & 0x0F) -#define C_028C28_S1_Y 0xFFFF0FFF -#define S_028C28_S2_X(x) (((x) & 0x0F) << 16) -#define G_028C28_S2_X(x) (((x) >> 16) & 0x0F) -#define C_028C28_S2_X 0xFFF0FFFF -#define S_028C28_S2_Y(x) (((x) & 0x0F) << 20) -#define G_028C28_S2_Y(x) (((x) >> 20) & 0x0F) -#define C_028C28_S2_Y 0xFF0FFFFF -#define S_028C28_S3_X(x) (((x) & 0x0F) << 24) -#define G_028C28_S3_X(x) (((x) >> 24) & 0x0F) -#define C_028C28_S3_X 0xF0FFFFFF -#define S_028C28_S3_Y(x) (((x) & 0x0F) << 28) -#define G_028C28_S3_Y(x) (((x) >> 28) & 0x0F) -#define C_028C28_S3_Y 0x0FFFFFFF -#define R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0x028C2C -#define S_028C2C_S4_X(x) (((x) & 0x0F) << 0) -#define G_028C2C_S4_X(x) (((x) >> 0) & 0x0F) -#define C_028C2C_S4_X 0xFFFFFFF0 -#define S_028C2C_S4_Y(x) (((x) & 0x0F) << 4) -#define G_028C2C_S4_Y(x) (((x) >> 4) & 0x0F) -#define C_028C2C_S4_Y 0xFFFFFF0F -#define S_028C2C_S5_X(x) (((x) & 0x0F) << 8) -#define G_028C2C_S5_X(x) (((x) >> 8) & 0x0F) -#define C_028C2C_S5_X 0xFFFFF0FF -#define S_028C2C_S5_Y(x) (((x) & 0x0F) << 12) -#define G_028C2C_S5_Y(x) (((x) >> 12) & 0x0F) -#define C_028C2C_S5_Y 0xFFFF0FFF -#define S_028C2C_S6_X(x) (((x) & 0x0F) << 16) -#define G_028C2C_S6_X(x) (((x) >> 16) & 0x0F) -#define C_028C2C_S6_X 0xFFF0FFFF -#define S_028C2C_S6_Y(x) (((x) & 0x0F) << 20) -#define G_028C2C_S6_Y(x) (((x) >> 20) & 0x0F) -#define C_028C2C_S6_Y 0xFF0FFFFF -#define S_028C2C_S7_X(x) (((x) & 0x0F) << 24) -#define G_028C2C_S7_X(x) (((x) >> 24) & 0x0F) -#define C_028C2C_S7_X 0xF0FFFFFF -#define S_028C2C_S7_Y(x) (((x) & 0x0F) << 28) -#define G_028C2C_S7_Y(x) (((x) >> 28) & 0x0F) -#define C_028C2C_S7_Y 0x0FFFFFFF -#define R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0x028C30 -#define S_028C30_S8_X(x) (((x) & 0x0F) << 0) -#define G_028C30_S8_X(x) (((x) >> 0) & 0x0F) -#define C_028C30_S8_X 0xFFFFFFF0 -#define S_028C30_S8_Y(x) (((x) & 0x0F) << 4) -#define G_028C30_S8_Y(x) (((x) >> 4) & 0x0F) -#define C_028C30_S8_Y 0xFFFFFF0F -#define S_028C30_S9_X(x) (((x) & 0x0F) << 8) -#define G_028C30_S9_X(x) (((x) >> 8) & 0x0F) -#define C_028C30_S9_X 0xFFFFF0FF -#define S_028C30_S9_Y(x) (((x) & 0x0F) << 12) -#define G_028C30_S9_Y(x) (((x) >> 12) & 0x0F) -#define C_028C30_S9_Y 0xFFFF0FFF -#define S_028C30_S10_X(x) (((x) & 0x0F) << 16) -#define G_028C30_S10_X(x) (((x) >> 16) & 0x0F) -#define C_028C30_S10_X 0xFFF0FFFF -#define S_028C30_S10_Y(x) (((x) & 0x0F) << 20) -#define G_028C30_S10_Y(x) (((x) >> 20) & 0x0F) -#define C_028C30_S10_Y 0xFF0FFFFF -#define S_028C30_S11_X(x) (((x) & 0x0F) << 24) -#define G_028C30_S11_X(x) (((x) >> 24) & 0x0F) -#define C_028C30_S11_X 0xF0FFFFFF -#define S_028C30_S11_Y(x) (((x) & 0x0F) << 28) -#define G_028C30_S11_Y(x) (((x) >> 28) & 0x0F) -#define C_028C30_S11_Y 0x0FFFFFFF -#define R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0x028C34 -#define S_028C34_S12_X(x) (((x) & 0x0F) << 0) -#define G_028C34_S12_X(x) (((x) >> 0) & 0x0F) -#define C_028C34_S12_X 0xFFFFFFF0 -#define S_028C34_S12_Y(x) (((x) & 0x0F) << 4) -#define G_028C34_S12_Y(x) (((x) >> 4) & 0x0F) -#define C_028C34_S12_Y 0xFFFFFF0F -#define S_028C34_S13_X(x) (((x) & 0x0F) << 8) -#define G_028C34_S13_X(x) (((x) >> 8) & 0x0F) -#define C_028C34_S13_X 0xFFFFF0FF -#define S_028C34_S13_Y(x) (((x) & 0x0F) << 12) -#define G_028C34_S13_Y(x) (((x) >> 12) & 0x0F) -#define C_028C34_S13_Y 0xFFFF0FFF -#define S_028C34_S14_X(x) (((x) & 0x0F) << 16) -#define G_028C34_S14_X(x) (((x) >> 16) & 0x0F) -#define C_028C34_S14_X 0xFFF0FFFF -#define S_028C34_S14_Y(x) (((x) & 0x0F) << 20) -#define G_028C34_S14_Y(x) (((x) >> 20) & 0x0F) -#define C_028C34_S14_Y 0xFF0FFFFF -#define S_028C34_S15_X(x) (((x) & 0x0F) << 24) -#define G_028C34_S15_X(x) (((x) >> 24) & 0x0F) -#define C_028C34_S15_X 0xF0FFFFFF -#define S_028C34_S15_Y(x) (((x) & 0x0F) << 28) -#define G_028C34_S15_Y(x) (((x) >> 28) & 0x0F) -#define C_028C34_S15_Y 0x0FFFFFFF -#define R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0 0x028C38 -#define S_028C38_AA_MASK_X0Y0(x) (((x) & 0xFFFF) << 0) -#define G_028C38_AA_MASK_X0Y0(x) (((x) >> 0) & 0xFFFF) -#define C_028C38_AA_MASK_X0Y0 0xFFFF0000 -#define S_028C38_AA_MASK_X1Y0(x) (((x) & 0xFFFF) << 16) -#define G_028C38_AA_MASK_X1Y0(x) (((x) >> 16) & 0xFFFF) -#define C_028C38_AA_MASK_X1Y0 0x0000FFFF -#define R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1 0x028C3C -#define S_028C3C_AA_MASK_X0Y1(x) (((x) & 0xFFFF) << 0) -#define G_028C3C_AA_MASK_X0Y1(x) (((x) >> 0) & 0xFFFF) -#define C_028C3C_AA_MASK_X0Y1 0xFFFF0000 -#define S_028C3C_AA_MASK_X1Y1(x) (((x) & 0xFFFF) << 16) -#define G_028C3C_AA_MASK_X1Y1(x) (((x) >> 16) & 0xFFFF) -#define C_028C3C_AA_MASK_X1Y1 0x0000FFFF -/* Stoney */ -#define R_028C40_PA_SC_SHADER_CONTROL 0x028C40 -#define S_028C40_REALIGN_DQUADS_AFTER_N_WAVES(x) (((x) & 0x03) << 0) -#define G_028C40_REALIGN_DQUADS_AFTER_N_WAVES(x) (((x) >> 0) & 0x03) -#define C_028C40_REALIGN_DQUADS_AFTER_N_WAVES 0xFFFFFFFC -/* */ -#define R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL 0x028C58 -#define S_028C58_VTX_REUSE_DEPTH(x) (((x) & 0xFF) << 0) -#define G_028C58_VTX_REUSE_DEPTH(x) (((x) >> 0) & 0xFF) -#define C_028C58_VTX_REUSE_DEPTH 0xFFFFFF00 -#define R_028C5C_VGT_OUT_DEALLOC_CNTL 0x028C5C -#define S_028C5C_DEALLOC_DIST(x) (((x) & 0x7F) << 0) -#define G_028C5C_DEALLOC_DIST(x) (((x) >> 0) & 0x7F) -#define C_028C5C_DEALLOC_DIST 0xFFFFFF80 -#define R_028C60_CB_COLOR0_BASE 0x028C60 -#define R_028C64_CB_COLOR0_PITCH 0x028C64 -#define S_028C64_TILE_MAX(x) (((x) & 0x7FF) << 0) -#define G_028C64_TILE_MAX(x) (((x) >> 0) & 0x7FF) -#define C_028C64_TILE_MAX 0xFFFFF800 -/* CIK */ -#define S_028C64_FMASK_TILE_MAX(x) (((x) & 0x7FF) << 20) -#define G_028C64_FMASK_TILE_MAX(x) (((x) >> 20) & 0x7FF) -#define C_028C64_FMASK_TILE_MAX 0x800FFFFF -/* */ -#define R_028C68_CB_COLOR0_SLICE 0x028C68 -#define S_028C68_TILE_MAX(x) (((x) & 0x3FFFFF) << 0) -#define G_028C68_TILE_MAX(x) (((x) >> 0) & 0x3FFFFF) -#define C_028C68_TILE_MAX 0xFFC00000 -#define R_028C6C_CB_COLOR0_VIEW 0x028C6C -#define S_028C6C_SLICE_START(x) (((x) & 0x7FF) << 0) -#define G_028C6C_SLICE_START(x) (((x) >> 0) & 0x7FF) -#define C_028C6C_SLICE_START 0xFFFFF800 -#define S_028C6C_SLICE_MAX(x) (((x) & 0x7FF) << 13) -#define G_028C6C_SLICE_MAX(x) (((x) >> 13) & 0x7FF) -#define C_028C6C_SLICE_MAX 0xFF001FFF -#define R_028C70_CB_COLOR0_INFO 0x028C70 -#define S_028C70_ENDIAN(x) (((x) & 0x03) << 0) -#define G_028C70_ENDIAN(x) (((x) >> 0) & 0x03) -#define C_028C70_ENDIAN 0xFFFFFFFC -#define V_028C70_ENDIAN_NONE 0x00 -#define V_028C70_ENDIAN_8IN16 0x01 -#define V_028C70_ENDIAN_8IN32 0x02 -#define V_028C70_ENDIAN_8IN64 0x03 -#define S_028C70_FORMAT(x) (((x) & 0x1F) << 2) -#define G_028C70_FORMAT(x) (((x) >> 2) & 0x1F) -#define C_028C70_FORMAT 0xFFFFFF83 -#define V_028C70_COLOR_INVALID 0x00 -#define V_028C70_COLOR_8 0x01 -#define V_028C70_COLOR_16 0x02 -#define V_028C70_COLOR_8_8 0x03 -#define V_028C70_COLOR_32 0x04 -#define V_028C70_COLOR_16_16 0x05 -#define V_028C70_COLOR_10_11_11 0x06 -#define V_028C70_COLOR_11_11_10 0x07 -#define V_028C70_COLOR_10_10_10_2 0x08 -#define V_028C70_COLOR_2_10_10_10 0x09 -#define V_028C70_COLOR_8_8_8_8 0x0A -#define V_028C70_COLOR_32_32 0x0B -#define V_028C70_COLOR_16_16_16_16 0x0C -#define V_028C70_COLOR_32_32_32_32 0x0E -#define V_028C70_COLOR_5_6_5 0x10 -#define V_028C70_COLOR_1_5_5_5 0x11 -#define V_028C70_COLOR_5_5_5_1 0x12 -#define V_028C70_COLOR_4_4_4_4 0x13 -#define V_028C70_COLOR_8_24 0x14 -#define V_028C70_COLOR_24_8 0x15 -#define V_028C70_COLOR_X24_8_32_FLOAT 0x16 -#define S_028C70_LINEAR_GENERAL(x) (((x) & 0x1) << 7) -#define G_028C70_LINEAR_GENERAL(x) (((x) >> 7) & 0x1) -#define C_028C70_LINEAR_GENERAL 0xFFFFFF7F -#define S_028C70_NUMBER_TYPE(x) (((x) & 0x07) << 8) -#define G_028C70_NUMBER_TYPE(x) (((x) >> 8) & 0x07) -#define C_028C70_NUMBER_TYPE 0xFFFFF8FF -#define V_028C70_NUMBER_UNORM 0x00 -#define V_028C70_NUMBER_SNORM 0x01 -#define V_028C70_NUMBER_UINT 0x04 -#define V_028C70_NUMBER_SINT 0x05 -#define V_028C70_NUMBER_SRGB 0x06 -#define V_028C70_NUMBER_FLOAT 0x07 -#define S_028C70_COMP_SWAP(x) (((x) & 0x03) << 11) -#define G_028C70_COMP_SWAP(x) (((x) >> 11) & 0x03) -#define C_028C70_COMP_SWAP 0xFFFFE7FF -#define V_028C70_SWAP_STD 0x00 -#define V_028C70_SWAP_ALT 0x01 -#define V_028C70_SWAP_STD_REV 0x02 -#define V_028C70_SWAP_ALT_REV 0x03 -#define S_028C70_FAST_CLEAR(x) (((x) & 0x1) << 13) -#define G_028C70_FAST_CLEAR(x) (((x) >> 13) & 0x1) -#define C_028C70_FAST_CLEAR 0xFFFFDFFF -#define S_028C70_COMPRESSION(x) (((x) & 0x1) << 14) -#define G_028C70_COMPRESSION(x) (((x) >> 14) & 0x1) -#define C_028C70_COMPRESSION 0xFFFFBFFF -#define S_028C70_BLEND_CLAMP(x) (((x) & 0x1) << 15) -#define G_028C70_BLEND_CLAMP(x) (((x) >> 15) & 0x1) -#define C_028C70_BLEND_CLAMP 0xFFFF7FFF -#define S_028C70_BLEND_BYPASS(x) (((x) & 0x1) << 16) -#define G_028C70_BLEND_BYPASS(x) (((x) >> 16) & 0x1) -#define C_028C70_BLEND_BYPASS 0xFFFEFFFF -#define S_028C70_SIMPLE_FLOAT(x) (((x) & 0x1) << 17) -#define G_028C70_SIMPLE_FLOAT(x) (((x) >> 17) & 0x1) -#define C_028C70_SIMPLE_FLOAT 0xFFFDFFFF -#define S_028C70_ROUND_MODE(x) (((x) & 0x1) << 18) -#define G_028C70_ROUND_MODE(x) (((x) >> 18) & 0x1) -#define C_028C70_ROUND_MODE 0xFFFBFFFF -#define S_028C70_CMASK_IS_LINEAR(x) (((x) & 0x1) << 19) -#define G_028C70_CMASK_IS_LINEAR(x) (((x) >> 19) & 0x1) -#define C_028C70_CMASK_IS_LINEAR 0xFFF7FFFF -#define S_028C70_BLEND_OPT_DONT_RD_DST(x) (((x) & 0x07) << 20) -#define G_028C70_BLEND_OPT_DONT_RD_DST(x) (((x) >> 20) & 0x07) -#define C_028C70_BLEND_OPT_DONT_RD_DST 0xFF8FFFFF -#define V_028C70_FORCE_OPT_AUTO 0x00 -#define V_028C70_FORCE_OPT_DISABLE 0x01 -#define V_028C70_FORCE_OPT_ENABLE_IF_SRC_A_0 0x02 -#define V_028C70_FORCE_OPT_ENABLE_IF_SRC_RGB_0 0x03 -#define V_028C70_FORCE_OPT_ENABLE_IF_SRC_ARGB_0 0x04 -#define V_028C70_FORCE_OPT_ENABLE_IF_SRC_A_1 0x05 -#define V_028C70_FORCE_OPT_ENABLE_IF_SRC_RGB_1 0x06 -#define V_028C70_FORCE_OPT_ENABLE_IF_SRC_ARGB_1 0x07 -#define S_028C70_BLEND_OPT_DISCARD_PIXEL(x) (((x) & 0x07) << 23) -#define G_028C70_BLEND_OPT_DISCARD_PIXEL(x) (((x) >> 23) & 0x07) -#define C_028C70_BLEND_OPT_DISCARD_PIXEL 0xFC7FFFFF -#define V_028C70_FORCE_OPT_AUTO 0x00 -#define V_028C70_FORCE_OPT_DISABLE 0x01 -#define V_028C70_FORCE_OPT_ENABLE_IF_SRC_A_0 0x02 -#define V_028C70_FORCE_OPT_ENABLE_IF_SRC_RGB_0 0x03 -#define V_028C70_FORCE_OPT_ENABLE_IF_SRC_ARGB_0 0x04 -#define V_028C70_FORCE_OPT_ENABLE_IF_SRC_A_1 0x05 -#define V_028C70_FORCE_OPT_ENABLE_IF_SRC_RGB_1 0x06 -#define V_028C70_FORCE_OPT_ENABLE_IF_SRC_ARGB_1 0x07 -/* CIK */ -#define S_028C70_FMASK_COMPRESSION_DISABLE(x) (((x) & 0x1) << 26) -#define G_028C70_FMASK_COMPRESSION_DISABLE(x) (((x) >> 26) & 0x1) -#define C_028C70_FMASK_COMPRESSION_DISABLE 0xFBFFFFFF -/* */ -/* VI */ -#define S_028C70_FMASK_COMPRESS_1FRAG_ONLY(x) (((x) & 0x1) << 27) -#define G_028C70_FMASK_COMPRESS_1FRAG_ONLY(x) (((x) >> 27) & 0x1) -#define C_028C70_FMASK_COMPRESS_1FRAG_ONLY 0xF7FFFFFF -#define S_028C70_DCC_ENABLE(x) (((x) & 0x1) << 28) -#define G_028C70_DCC_ENABLE(x) (((x) >> 28) & 0x1) -#define C_028C70_DCC_ENABLE 0xEFFFFFFF -#define S_028C70_CMASK_ADDR_TYPE(x) (((x) & 0x03) << 29) -#define G_028C70_CMASK_ADDR_TYPE(x) (((x) >> 29) & 0x03) -#define C_028C70_CMASK_ADDR_TYPE 0x9FFFFFFF -/* */ -#define R_028C74_CB_COLOR0_ATTRIB 0x028C74 -#define S_028C74_TILE_MODE_INDEX(x) (((x) & 0x1F) << 0) -#define G_028C74_TILE_MODE_INDEX(x) (((x) >> 0) & 0x1F) -#define C_028C74_TILE_MODE_INDEX 0xFFFFFFE0 -#define S_028C74_FMASK_TILE_MODE_INDEX(x) (((x) & 0x1F) << 5) -#define G_028C74_FMASK_TILE_MODE_INDEX(x) (((x) >> 5) & 0x1F) -#define C_028C74_FMASK_TILE_MODE_INDEX 0xFFFFFC1F -#define S_028C74_FMASK_BANK_HEIGHT(x) (((x) & 0x03) << 10) -#define G_028C74_FMASK_BANK_HEIGHT(x) (((x) >> 10) & 0x03) -#define C_028C74_FMASK_BANK_HEIGHT 0xFFFFF3FF -#define S_028C74_NUM_SAMPLES(x) (((x) & 0x07) << 12) -#define G_028C74_NUM_SAMPLES(x) (((x) >> 12) & 0x07) -#define C_028C74_NUM_SAMPLES 0xFFFF8FFF -#define S_028C74_NUM_FRAGMENTS(x) (((x) & 0x03) << 15) -#define G_028C74_NUM_FRAGMENTS(x) (((x) >> 15) & 0x03) -#define C_028C74_NUM_FRAGMENTS 0xFFFE7FFF -#define S_028C74_FORCE_DST_ALPHA_1(x) (((x) & 0x1) << 17) -#define G_028C74_FORCE_DST_ALPHA_1(x) (((x) >> 17) & 0x1) -#define C_028C74_FORCE_DST_ALPHA_1 0xFFFDFFFF -/* VI */ -#define R_028C78_CB_COLOR0_DCC_CONTROL 0x028C78 -#define S_028C78_OVERWRITE_COMBINER_DISABLE(x) (((x) & 0x1) << 0) -#define G_028C78_OVERWRITE_COMBINER_DISABLE(x) (((x) >> 0) & 0x1) -#define C_028C78_OVERWRITE_COMBINER_DISABLE 0xFFFFFFFE -#define S_028C78_KEY_CLEAR_ENABLE(x) (((x) & 0x1) << 1) -#define G_028C78_KEY_CLEAR_ENABLE(x) (((x) >> 1) & 0x1) -#define C_028C78_KEY_CLEAR_ENABLE 0xFFFFFFFD -#define S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(x) (((x) & 0x03) << 2) -#define G_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(x) (((x) >> 2) & 0x03) -#define C_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE 0xFFFFFFF3 -#define S_028C78_MIN_COMPRESSED_BLOCK_SIZE(x) (((x) & 0x1) << 4) -#define G_028C78_MIN_COMPRESSED_BLOCK_SIZE(x) (((x) >> 4) & 0x1) -#define C_028C78_MIN_COMPRESSED_BLOCK_SIZE 0xFFFFFFEF -#define S_028C78_MAX_COMPRESSED_BLOCK_SIZE(x) (((x) & 0x03) << 5) -#define G_028C78_MAX_COMPRESSED_BLOCK_SIZE(x) (((x) >> 5) & 0x03) -#define C_028C78_MAX_COMPRESSED_BLOCK_SIZE 0xFFFFFF9F -#define S_028C78_COLOR_TRANSFORM(x) (((x) & 0x03) << 7) -#define G_028C78_COLOR_TRANSFORM(x) (((x) >> 7) & 0x03) -#define C_028C78_COLOR_TRANSFORM 0xFFFFFE7F -#define S_028C78_INDEPENDENT_64B_BLOCKS(x) (((x) & 0x1) << 9) -#define G_028C78_INDEPENDENT_64B_BLOCKS(x) (((x) >> 9) & 0x1) -#define C_028C78_INDEPENDENT_64B_BLOCKS 0xFFFFFDFF -#define S_028C78_LOSSY_RGB_PRECISION(x) (((x) & 0x0F) << 10) -#define G_028C78_LOSSY_RGB_PRECISION(x) (((x) >> 10) & 0x0F) -#define C_028C78_LOSSY_RGB_PRECISION 0xFFFFC3FF -#define S_028C78_LOSSY_ALPHA_PRECISION(x) (((x) & 0x0F) << 14) -#define G_028C78_LOSSY_ALPHA_PRECISION(x) (((x) >> 14) & 0x0F) -#define C_028C78_LOSSY_ALPHA_PRECISION 0xFFFC3FFF -/* */ -#define R_028C7C_CB_COLOR0_CMASK 0x028C7C -#define R_028C80_CB_COLOR0_CMASK_SLICE 0x028C80 -#define S_028C80_TILE_MAX(x) (((x) & 0x3FFF) << 0) -#define G_028C80_TILE_MAX(x) (((x) >> 0) & 0x3FFF) -#define C_028C80_TILE_MAX 0xFFFFC000 -#define R_028C84_CB_COLOR0_FMASK 0x028C84 -#define R_028C88_CB_COLOR0_FMASK_SLICE 0x028C88 -#define S_028C88_TILE_MAX(x) (((x) & 0x3FFFFF) << 0) -#define G_028C88_TILE_MAX(x) (((x) >> 0) & 0x3FFFFF) -#define C_028C88_TILE_MAX 0xFFC00000 -#define R_028C8C_CB_COLOR0_CLEAR_WORD0 0x028C8C -#define R_028C90_CB_COLOR0_CLEAR_WORD1 0x028C90 -#define R_028C94_CB_COLOR0_DCC_BASE 0x028C94 /* VI */ -#define R_028C9C_CB_COLOR1_BASE 0x028C9C -#define R_028CA0_CB_COLOR1_PITCH 0x028CA0 -#define R_028CA4_CB_COLOR1_SLICE 0x028CA4 -#define R_028CA8_CB_COLOR1_VIEW 0x028CA8 -#define R_028CAC_CB_COLOR1_INFO 0x028CAC -#define R_028CB0_CB_COLOR1_ATTRIB 0x028CB0 -#define R_028CB4_CB_COLOR1_DCC_CONTROL 0x028CB4 /* VI */ -#define R_028CB8_CB_COLOR1_CMASK 0x028CB8 -#define R_028CBC_CB_COLOR1_CMASK_SLICE 0x028CBC -#define R_028CC0_CB_COLOR1_FMASK 0x028CC0 -#define R_028CC4_CB_COLOR1_FMASK_SLICE 0x028CC4 -#define R_028CC8_CB_COLOR1_CLEAR_WORD0 0x028CC8 -#define R_028CCC_CB_COLOR1_CLEAR_WORD1 0x028CCC -#define R_028CD0_CB_COLOR1_DCC_BASE 0x028CD0 /* VI */ -#define R_028CD8_CB_COLOR2_BASE 0x028CD8 -#define R_028CDC_CB_COLOR2_PITCH 0x028CDC -#define R_028CE0_CB_COLOR2_SLICE 0x028CE0 -#define R_028CE4_CB_COLOR2_VIEW 0x028CE4 -#define R_028CE8_CB_COLOR2_INFO 0x028CE8 -#define R_028CEC_CB_COLOR2_ATTRIB 0x028CEC -#define R_028CF0_CB_COLOR2_DCC_CONTROL 0x028CF0 /* VI */ -#define R_028CF4_CB_COLOR2_CMASK 0x028CF4 -#define R_028CF8_CB_COLOR2_CMASK_SLICE 0x028CF8 -#define R_028CFC_CB_COLOR2_FMASK 0x028CFC -#define R_028D00_CB_COLOR2_FMASK_SLICE 0x028D00 -#define R_028D04_CB_COLOR2_CLEAR_WORD0 0x028D04 -#define R_028D08_CB_COLOR2_CLEAR_WORD1 0x028D08 -#define R_028D0C_CB_COLOR2_DCC_BASE 0x028D0C /* VI */ -#define R_028D14_CB_COLOR3_BASE 0x028D14 -#define R_028D18_CB_COLOR3_PITCH 0x028D18 -#define R_028D1C_CB_COLOR3_SLICE 0x028D1C -#define R_028D20_CB_COLOR3_VIEW 0x028D20 -#define R_028D24_CB_COLOR3_INFO 0x028D24 -#define R_028D28_CB_COLOR3_ATTRIB 0x028D28 -#define R_028D2C_CB_COLOR3_DCC_CONTROL 0x028D2C /* VI */ -#define R_028D30_CB_COLOR3_CMASK 0x028D30 -#define R_028D34_CB_COLOR3_CMASK_SLICE 0x028D34 -#define R_028D38_CB_COLOR3_FMASK 0x028D38 -#define R_028D3C_CB_COLOR3_FMASK_SLICE 0x028D3C -#define R_028D40_CB_COLOR3_CLEAR_WORD0 0x028D40 -#define R_028D44_CB_COLOR3_CLEAR_WORD1 0x028D44 -#define R_028D48_CB_COLOR3_DCC_BASE 0x028D48 /* VI */ -#define R_028D50_CB_COLOR4_BASE 0x028D50 -#define R_028D54_CB_COLOR4_PITCH 0x028D54 -#define R_028D58_CB_COLOR4_SLICE 0x028D58 -#define R_028D5C_CB_COLOR4_VIEW 0x028D5C -#define R_028D60_CB_COLOR4_INFO 0x028D60 -#define R_028D64_CB_COLOR4_ATTRIB 0x028D64 -#define R_028D68_CB_COLOR4_DCC_CONTROL 0x028D68 /* VI */ -#define R_028D6C_CB_COLOR4_CMASK 0x028D6C -#define R_028D70_CB_COLOR4_CMASK_SLICE 0x028D70 -#define R_028D74_CB_COLOR4_FMASK 0x028D74 -#define R_028D78_CB_COLOR4_FMASK_SLICE 0x028D78 -#define R_028D7C_CB_COLOR4_CLEAR_WORD0 0x028D7C -#define R_028D80_CB_COLOR4_CLEAR_WORD1 0x028D80 -#define R_028D84_CB_COLOR4_DCC_BASE 0x028D84 /* VI */ -#define R_028D8C_CB_COLOR5_BASE 0x028D8C -#define R_028D90_CB_COLOR5_PITCH 0x028D90 -#define R_028D94_CB_COLOR5_SLICE 0x028D94 -#define R_028D98_CB_COLOR5_VIEW 0x028D98 -#define R_028D9C_CB_COLOR5_INFO 0x028D9C -#define R_028DA0_CB_COLOR5_ATTRIB 0x028DA0 -#define R_028DA4_CB_COLOR5_DCC_CONTROL 0x028DA4 /* VI */ -#define R_028DA8_CB_COLOR5_CMASK 0x028DA8 -#define R_028DAC_CB_COLOR5_CMASK_SLICE 0x028DAC -#define R_028DB0_CB_COLOR5_FMASK 0x028DB0 -#define R_028DB4_CB_COLOR5_FMASK_SLICE 0x028DB4 -#define R_028DB8_CB_COLOR5_CLEAR_WORD0 0x028DB8 -#define R_028DBC_CB_COLOR5_CLEAR_WORD1 0x028DBC -#define R_028DC0_CB_COLOR5_DCC_BASE 0x028DC0 /* VI */ -#define R_028DC8_CB_COLOR6_BASE 0x028DC8 -#define R_028DCC_CB_COLOR6_PITCH 0x028DCC -#define R_028DD0_CB_COLOR6_SLICE 0x028DD0 -#define R_028DD4_CB_COLOR6_VIEW 0x028DD4 -#define R_028DD8_CB_COLOR6_INFO 0x028DD8 -#define R_028DDC_CB_COLOR6_ATTRIB 0x028DDC -#define R_028DE0_CB_COLOR6_DCC_CONTROL 0x028DE0 /* VI */ -#define R_028DE4_CB_COLOR6_CMASK 0x028DE4 -#define R_028DE8_CB_COLOR6_CMASK_SLICE 0x028DE8 -#define R_028DEC_CB_COLOR6_FMASK 0x028DEC -#define R_028DF0_CB_COLOR6_FMASK_SLICE 0x028DF0 -#define R_028DF4_CB_COLOR6_CLEAR_WORD0 0x028DF4 -#define R_028DF8_CB_COLOR6_CLEAR_WORD1 0x028DF8 -#define R_028DFC_CB_COLOR6_DCC_BASE 0x028DFC /* VI */ -#define R_028E04_CB_COLOR7_BASE 0x028E04 -#define R_028E08_CB_COLOR7_PITCH 0x028E08 -#define R_028E0C_CB_COLOR7_SLICE 0x028E0C -#define R_028E10_CB_COLOR7_VIEW 0x028E10 -#define R_028E14_CB_COLOR7_INFO 0x028E14 -#define R_028E18_CB_COLOR7_ATTRIB 0x028E18 -#define R_028E1C_CB_COLOR7_DCC_CONTROL 0x028E1C /* VI */ -#define R_028E20_CB_COLOR7_CMASK 0x028E20 -#define R_028E24_CB_COLOR7_CMASK_SLICE 0x028E24 -#define R_028E28_CB_COLOR7_FMASK 0x028E28 -#define R_028E2C_CB_COLOR7_FMASK_SLICE 0x028E2C -#define R_028E30_CB_COLOR7_CLEAR_WORD0 0x028E30 -#define R_028E34_CB_COLOR7_CLEAR_WORD1 0x028E34 -#define R_028E38_CB_COLOR7_DCC_BASE 0x028E38 /* VI */ - -/* SI async DMA packets */ -#define SI_DMA_PACKET(cmd, sub_cmd, n) ((((cmd) & 0xF) << 28) | \ - (((sub_cmd) & 0xFF) << 20) |\ - (((n) & 0xFFFFF) << 0)) -/* SI async DMA Packet types */ -#define SI_DMA_PACKET_WRITE 0x2 -#define SI_DMA_PACKET_COPY 0x3 -#define SI_DMA_COPY_MAX_SIZE 0xfffe0 -#define SI_DMA_COPY_MAX_SIZE_DW 0xffff8 -#define SI_DMA_COPY_DWORD_ALIGNED 0x00 -#define SI_DMA_COPY_BYTE_ALIGNED 0x40 -#define SI_DMA_COPY_TILED 0x8 -#define SI_DMA_PACKET_INDIRECT_BUFFER 0x4 -#define SI_DMA_PACKET_SEMAPHORE 0x5 -#define SI_DMA_PACKET_FENCE 0x6 -#define SI_DMA_PACKET_TRAP 0x7 -#define SI_DMA_PACKET_SRBM_WRITE 0x9 -#define SI_DMA_PACKET_CONSTANT_FILL 0xd -#define SI_DMA_PACKET_NOP 0xf - -/* CIK async DMA packets */ -#define CIK_SDMA_PACKET(op, sub_op, n) ((((n) & 0xFFFF) << 16) | \ - (((sub_op) & 0xFF) << 8) | \ - (((op) & 0xFF) << 0)) -/* CIK async DMA packet types */ -#define CIK_SDMA_OPCODE_NOP 0x0 -#define CIK_SDMA_OPCODE_COPY 0x1 -#define CIK_SDMA_COPY_SUB_OPCODE_LINEAR 0x0 -#define CIK_SDMA_COPY_SUB_OPCODE_TILED 0x1 -#define CIK_SDMA_COPY_SUB_OPCODE_SOA 0x3 -#define CIK_SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW 0x4 -#define CIK_SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW 0x5 -#define CIK_SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW 0x6 -#define CIK_SDMA_OPCODE_WRITE 0x2 -#define SDMA_WRITE_SUB_OPCODE_LINEAR 0x0 -#define SDMA_WRTIE_SUB_OPCODE_TILED 0x1 -#define CIK_SDMA_OPCODE_INDIRECT_BUFFER 0x4 -#define CIK_SDMA_PACKET_FENCE 0x5 -#define CIK_SDMA_PACKET_TRAP 0x6 -#define CIK_SDMA_PACKET_SEMAPHORE 0x7 -#define CIK_SDMA_PACKET_CONSTANT_FILL 0xb -#define CIK_SDMA_PACKET_SRBM_WRITE 0xe -#define CIK_SDMA_COPY_MAX_SIZE 0x1fffff - -#endif /* _SID_H */ - diff --git a/lib/mesa/src/gallium/drivers/rbug/Makefile.in b/lib/mesa/src/gallium/drivers/rbug/Makefile.in index 6bce471c5..3d1e8c2e7 100644 --- a/lib/mesa/src/gallium/drivers/rbug/Makefile.in +++ b/lib/mesa/src/gallium/drivers/rbug/Makefile.in @@ -222,6 +222,8 @@ GLESv2_LIB_DEPS = @GLESv2_LIB_DEPS@ GLESv2_PC_LIB_PRIV = @GLESv2_PC_LIB_PRIV@ GLPROTO_CFLAGS = @GLPROTO_CFLAGS@ GLPROTO_LIBS = @GLPROTO_LIBS@ +GLVND_CFLAGS = @GLVND_CFLAGS@ +GLVND_LIBS = @GLVND_LIBS@ GLX_TLS = @GLX_TLS@ GL_LIB = @GL_LIB@ GL_LIB_DEPS = @GL_LIB_DEPS@ @@ -253,11 +255,10 @@ LIBELF_CFLAGS = @LIBELF_CFLAGS@ LIBELF_LIBS = @LIBELF_LIBS@ LIBOBJS = @LIBOBJS@ LIBS = @LIBS@ +LIBSENSORS_LDFLAGS = @LIBSENSORS_LDFLAGS@ LIBSHA1_CFLAGS = @LIBSHA1_CFLAGS@ LIBSHA1_LIBS = @LIBSHA1_LIBS@ LIBTOOL = @LIBTOOL@ -LIBUDEV_CFLAGS = @LIBUDEV_CFLAGS@ -LIBUDEV_LIBS = @LIBUDEV_LIBS@ LIB_DIR = @LIB_DIR@ LIB_EXT = @LIB_EXT@ LIPO = @LIPO@ @@ -320,6 +321,8 @@ PKG_CONFIG_PATH = @PKG_CONFIG_PATH@ POSIX_SHELL = @POSIX_SHELL@ PRESENTPROTO_CFLAGS = @PRESENTPROTO_CFLAGS@ PRESENTPROTO_LIBS = @PRESENTPROTO_LIBS@ +PTHREADSTUBS_CFLAGS = @PTHREADSTUBS_CFLAGS@ +PTHREADSTUBS_LIBS = @PTHREADSTUBS_LIBS@ PTHREAD_CC = @PTHREAD_CC@ PTHREAD_CFLAGS = @PTHREAD_CFLAGS@ PTHREAD_LIBS = @PTHREAD_LIBS@ @@ -340,11 +343,19 @@ SIMPENROSE_CFLAGS = @SIMPENROSE_CFLAGS@ SIMPENROSE_LIBS = @SIMPENROSE_LIBS@ SSE41_CFLAGS = @SSE41_CFLAGS@ STRIP = @STRIP@ +SWR_AVX2_CXXFLAGS = @SWR_AVX2_CXXFLAGS@ +SWR_AVX_CXXFLAGS = @SWR_AVX_CXXFLAGS@ +SWR_CXX11_CXXFLAGS = @SWR_CXX11_CXXFLAGS@ +TIMESTAMP_CMD = @TIMESTAMP_CMD@ +VALGRIND_CFLAGS = @VALGRIND_CFLAGS@ +VALGRIND_LIBS = @VALGRIND_LIBS@ VA_CFLAGS = @VA_CFLAGS@ VA_LIBS = @VA_LIBS@ VA_LIB_INSTALL_DIR = @VA_LIB_INSTALL_DIR@ VA_MAJOR = @VA_MAJOR@ VA_MINOR = @VA_MINOR@ +VC4_CFLAGS = @VC4_CFLAGS@ +VC4_LIBS = @VC4_LIBS@ VDPAU_CFLAGS = @VDPAU_CFLAGS@ VDPAU_LIBS = @VDPAU_LIBS@ VDPAU_LIB_INSTALL_DIR = @VDPAU_LIB_INSTALL_DIR@ @@ -356,6 +367,7 @@ VISIBILITY_CFLAGS = @VISIBILITY_CFLAGS@ VISIBILITY_CXXFLAGS = @VISIBILITY_CXXFLAGS@ VL_CFLAGS = @VL_CFLAGS@ VL_LIBS = @VL_LIBS@ +VULKAN_ICD_INSTALL_DIR = @VULKAN_ICD_INSTALL_DIR@ WAYLAND_CFLAGS = @WAYLAND_CFLAGS@ WAYLAND_LIBS = @WAYLAND_LIBS@ WAYLAND_SCANNER = @WAYLAND_SCANNER@ @@ -379,6 +391,7 @@ XVMC_LIBS = @XVMC_LIBS@ XVMC_LIB_INSTALL_DIR = @XVMC_LIB_INSTALL_DIR@ XVMC_MAJOR = @XVMC_MAJOR@ XVMC_MINOR = @XVMC_MINOR@ +XXD = @XXD@ YACC = @YACC@ YFLAGS = @YFLAGS@ abs_builddir = @abs_builddir@ diff --git a/lib/mesa/src/gallium/drivers/softpipe/Makefile.in b/lib/mesa/src/gallium/drivers/softpipe/Makefile.in index b99eaaebb..1bd728b1f 100644 --- a/lib/mesa/src/gallium/drivers/softpipe/Makefile.in +++ b/lib/mesa/src/gallium/drivers/softpipe/Makefile.in @@ -102,12 +102,13 @@ CONFIG_CLEAN_FILES = CONFIG_CLEAN_VPATH_FILES = LTLIBRARIES = $(noinst_LTLIBRARIES) libsoftpipe_la_LIBADD = -am__objects_1 = sp_clear.lo sp_context.lo sp_draw_arrays.lo \ - sp_fence.lo sp_flush.lo sp_fs_exec.lo sp_prim_vbuf.lo \ - sp_quad_blend.lo sp_quad_depth_test.lo sp_quad_fs.lo \ - sp_quad_pipe.lo sp_quad_stipple.lo sp_query.lo sp_screen.lo \ - sp_setup.lo sp_state_blend.lo sp_state_clip.lo \ - sp_state_derived.lo sp_state_rasterizer.lo sp_state_sampler.lo \ +am__objects_1 = sp_buffer.lo sp_clear.lo sp_context.lo sp_compute.lo \ + sp_draw_arrays.lo sp_fence.lo sp_flush.lo sp_fs_exec.lo \ + sp_image.lo sp_prim_vbuf.lo sp_quad_blend.lo \ + sp_quad_depth_test.lo sp_quad_fs.lo sp_quad_pipe.lo \ + sp_quad_stipple.lo sp_query.lo sp_screen.lo sp_setup.lo \ + sp_state_blend.lo sp_state_clip.lo sp_state_derived.lo \ + sp_state_image.lo sp_state_rasterizer.lo sp_state_sampler.lo \ sp_state_shader.lo sp_state_so.lo sp_state_surface.lo \ sp_state_vertex.lo sp_surface.lo sp_tex_sample.lo \ sp_tex_tile_cache.lo sp_texture.lo sp_tile_cache.lo @@ -229,6 +230,8 @@ GLESv2_LIB_DEPS = @GLESv2_LIB_DEPS@ GLESv2_PC_LIB_PRIV = @GLESv2_PC_LIB_PRIV@ GLPROTO_CFLAGS = @GLPROTO_CFLAGS@ GLPROTO_LIBS = @GLPROTO_LIBS@ +GLVND_CFLAGS = @GLVND_CFLAGS@ +GLVND_LIBS = @GLVND_LIBS@ GLX_TLS = @GLX_TLS@ GL_LIB = @GL_LIB@ GL_LIB_DEPS = @GL_LIB_DEPS@ @@ -260,11 +263,10 @@ LIBELF_CFLAGS = @LIBELF_CFLAGS@ LIBELF_LIBS = @LIBELF_LIBS@ LIBOBJS = @LIBOBJS@ LIBS = @LIBS@ +LIBSENSORS_LDFLAGS = @LIBSENSORS_LDFLAGS@ LIBSHA1_CFLAGS = @LIBSHA1_CFLAGS@ LIBSHA1_LIBS = @LIBSHA1_LIBS@ LIBTOOL = @LIBTOOL@ -LIBUDEV_CFLAGS = @LIBUDEV_CFLAGS@ -LIBUDEV_LIBS = @LIBUDEV_LIBS@ LIB_DIR = @LIB_DIR@ LIB_EXT = @LIB_EXT@ LIPO = @LIPO@ @@ -327,6 +329,8 @@ PKG_CONFIG_PATH = @PKG_CONFIG_PATH@ POSIX_SHELL = @POSIX_SHELL@ PRESENTPROTO_CFLAGS = @PRESENTPROTO_CFLAGS@ PRESENTPROTO_LIBS = @PRESENTPROTO_LIBS@ +PTHREADSTUBS_CFLAGS = @PTHREADSTUBS_CFLAGS@ +PTHREADSTUBS_LIBS = @PTHREADSTUBS_LIBS@ PTHREAD_CC = @PTHREAD_CC@ PTHREAD_CFLAGS = @PTHREAD_CFLAGS@ PTHREAD_LIBS = @PTHREAD_LIBS@ @@ -347,11 +351,19 @@ SIMPENROSE_CFLAGS = @SIMPENROSE_CFLAGS@ SIMPENROSE_LIBS = @SIMPENROSE_LIBS@ SSE41_CFLAGS = @SSE41_CFLAGS@ STRIP = @STRIP@ +SWR_AVX2_CXXFLAGS = @SWR_AVX2_CXXFLAGS@ +SWR_AVX_CXXFLAGS = @SWR_AVX_CXXFLAGS@ +SWR_CXX11_CXXFLAGS = @SWR_CXX11_CXXFLAGS@ +TIMESTAMP_CMD = @TIMESTAMP_CMD@ +VALGRIND_CFLAGS = @VALGRIND_CFLAGS@ +VALGRIND_LIBS = @VALGRIND_LIBS@ VA_CFLAGS = @VA_CFLAGS@ VA_LIBS = @VA_LIBS@ VA_LIB_INSTALL_DIR = @VA_LIB_INSTALL_DIR@ VA_MAJOR = @VA_MAJOR@ VA_MINOR = @VA_MINOR@ +VC4_CFLAGS = @VC4_CFLAGS@ +VC4_LIBS = @VC4_LIBS@ VDPAU_CFLAGS = @VDPAU_CFLAGS@ VDPAU_LIBS = @VDPAU_LIBS@ VDPAU_LIB_INSTALL_DIR = @VDPAU_LIB_INSTALL_DIR@ @@ -363,6 +375,7 @@ VISIBILITY_CFLAGS = @VISIBILITY_CFLAGS@ VISIBILITY_CXXFLAGS = @VISIBILITY_CXXFLAGS@ VL_CFLAGS = @VL_CFLAGS@ VL_LIBS = @VL_LIBS@ +VULKAN_ICD_INSTALL_DIR = @VULKAN_ICD_INSTALL_DIR@ WAYLAND_CFLAGS = @WAYLAND_CFLAGS@ WAYLAND_LIBS = @WAYLAND_LIBS@ WAYLAND_SCANNER = @WAYLAND_SCANNER@ @@ -386,6 +399,7 @@ XVMC_LIBS = @XVMC_LIBS@ XVMC_LIB_INSTALL_DIR = @XVMC_LIB_INSTALL_DIR@ XVMC_MAJOR = @XVMC_MAJOR@ XVMC_MINOR = @XVMC_MINOR@ +XXD = @XXD@ YACC = @YACC@ YFLAGS = @YFLAGS@ abs_builddir = @abs_builddir@ @@ -449,10 +463,13 @@ top_build_prefix = @top_build_prefix@ top_builddir = @top_builddir@ top_srcdir = @top_srcdir@ C_SOURCES := \ + sp_buffer.c \ + sp_buffer.h \ sp_clear.c \ sp_clear.h \ sp_context.c \ sp_context.h \ + sp_compute.c \ sp_draw_arrays.c \ sp_fence.c \ sp_fence.h \ @@ -460,6 +477,8 @@ C_SOURCES := \ sp_flush.h \ sp_fs_exec.c \ sp_fs.h \ + sp_image.c \ + sp_image.h \ sp_limits.h \ sp_prim_vbuf.c \ sp_prim_vbuf.h \ @@ -481,6 +500,7 @@ C_SOURCES := \ sp_state_blend.c \ sp_state_clip.c \ sp_state_derived.c \ + sp_state_image.c \ sp_state.h \ sp_state_rasterizer.c \ sp_state_sampler.c \ @@ -626,12 +646,15 @@ mostlyclean-compile: distclean-compile: -rm -f *.tab.c +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sp_buffer.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sp_clear.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sp_compute.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sp_context.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sp_draw_arrays.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sp_fence.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sp_flush.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sp_fs_exec.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sp_image.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sp_prim_vbuf.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sp_quad_blend.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sp_quad_depth_test.Plo@am__quote@ @@ -644,6 +667,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sp_state_blend.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sp_state_clip.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sp_state_derived.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sp_state_image.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sp_state_rasterizer.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sp_state_sampler.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sp_state_shader.Plo@am__quote@ diff --git a/lib/mesa/src/gallium/drivers/svga/Makefile.in b/lib/mesa/src/gallium/drivers/svga/Makefile.in index 11e8b76be..dbecdd672 100644 --- a/lib/mesa/src/gallium/drivers/svga/Makefile.in +++ b/lib/mesa/src/gallium/drivers/svga/Makefile.in @@ -247,6 +247,8 @@ GLESv2_LIB_DEPS = @GLESv2_LIB_DEPS@ GLESv2_PC_LIB_PRIV = @GLESv2_PC_LIB_PRIV@ GLPROTO_CFLAGS = @GLPROTO_CFLAGS@ GLPROTO_LIBS = @GLPROTO_LIBS@ +GLVND_CFLAGS = @GLVND_CFLAGS@ +GLVND_LIBS = @GLVND_LIBS@ GLX_TLS = @GLX_TLS@ GL_LIB = @GL_LIB@ GL_LIB_DEPS = @GL_LIB_DEPS@ @@ -278,11 +280,10 @@ LIBELF_CFLAGS = @LIBELF_CFLAGS@ LIBELF_LIBS = @LIBELF_LIBS@ LIBOBJS = @LIBOBJS@ LIBS = @LIBS@ +LIBSENSORS_LDFLAGS = @LIBSENSORS_LDFLAGS@ LIBSHA1_CFLAGS = @LIBSHA1_CFLAGS@ LIBSHA1_LIBS = @LIBSHA1_LIBS@ LIBTOOL = @LIBTOOL@ -LIBUDEV_CFLAGS = @LIBUDEV_CFLAGS@ -LIBUDEV_LIBS = @LIBUDEV_LIBS@ LIB_DIR = @LIB_DIR@ LIB_EXT = @LIB_EXT@ LIPO = @LIPO@ @@ -345,6 +346,8 @@ PKG_CONFIG_PATH = @PKG_CONFIG_PATH@ POSIX_SHELL = @POSIX_SHELL@ PRESENTPROTO_CFLAGS = @PRESENTPROTO_CFLAGS@ PRESENTPROTO_LIBS = @PRESENTPROTO_LIBS@ +PTHREADSTUBS_CFLAGS = @PTHREADSTUBS_CFLAGS@ +PTHREADSTUBS_LIBS = @PTHREADSTUBS_LIBS@ PTHREAD_CC = @PTHREAD_CC@ PTHREAD_CFLAGS = @PTHREAD_CFLAGS@ PTHREAD_LIBS = @PTHREAD_LIBS@ @@ -365,11 +368,19 @@ SIMPENROSE_CFLAGS = @SIMPENROSE_CFLAGS@ SIMPENROSE_LIBS = @SIMPENROSE_LIBS@ SSE41_CFLAGS = @SSE41_CFLAGS@ STRIP = @STRIP@ +SWR_AVX2_CXXFLAGS = @SWR_AVX2_CXXFLAGS@ +SWR_AVX_CXXFLAGS = @SWR_AVX_CXXFLAGS@ +SWR_CXX11_CXXFLAGS = @SWR_CXX11_CXXFLAGS@ +TIMESTAMP_CMD = @TIMESTAMP_CMD@ +VALGRIND_CFLAGS = @VALGRIND_CFLAGS@ +VALGRIND_LIBS = @VALGRIND_LIBS@ VA_CFLAGS = @VA_CFLAGS@ VA_LIBS = @VA_LIBS@ VA_LIB_INSTALL_DIR = @VA_LIB_INSTALL_DIR@ VA_MAJOR = @VA_MAJOR@ VA_MINOR = @VA_MINOR@ +VC4_CFLAGS = @VC4_CFLAGS@ +VC4_LIBS = @VC4_LIBS@ VDPAU_CFLAGS = @VDPAU_CFLAGS@ VDPAU_LIBS = @VDPAU_LIBS@ VDPAU_LIB_INSTALL_DIR = @VDPAU_LIB_INSTALL_DIR@ @@ -381,6 +392,7 @@ VISIBILITY_CFLAGS = @VISIBILITY_CFLAGS@ VISIBILITY_CXXFLAGS = @VISIBILITY_CXXFLAGS@ VL_CFLAGS = @VL_CFLAGS@ VL_LIBS = @VL_LIBS@ +VULKAN_ICD_INSTALL_DIR = @VULKAN_ICD_INSTALL_DIR@ WAYLAND_CFLAGS = @WAYLAND_CFLAGS@ WAYLAND_LIBS = @WAYLAND_LIBS@ WAYLAND_SCANNER = @WAYLAND_SCANNER@ @@ -404,6 +416,7 @@ XVMC_LIBS = @XVMC_LIBS@ XVMC_LIB_INSTALL_DIR = @XVMC_LIB_INSTALL_DIR@ XVMC_MAJOR = @XVMC_MAJOR@ XVMC_MINOR = @XVMC_MINOR@ +XXD = @XXD@ YACC = @YACC@ YFLAGS = @YFLAGS@ abs_builddir = @abs_builddir@ @@ -483,6 +496,7 @@ C_SOURCES := \ svga_hw_reg.h \ svga_link.c \ svga_link.h \ + svga_mksstats.h \ svga_pipe_blend.c \ svga_pipe_blit.c \ svga_pipe_clear.c \ diff --git a/lib/mesa/src/gallium/drivers/swr/Makefile.in b/lib/mesa/src/gallium/drivers/swr/Makefile.in index d197497ff..0b9dfd1f9 100644 --- a/lib/mesa/src/gallium/drivers/swr/Makefile.in +++ b/lib/mesa/src/gallium/drivers/swr/Makefile.in @@ -1,7 +1,7 @@ -# Makefile.in generated by automake 1.15 from Makefile.am. +# Makefile.in generated by automake 1.12.6 from Makefile.am. # @configure_input@ -# Copyright (C) 1994-2014 Free Software Foundation, Inc. +# Copyright (C) 1994-2012 Free Software Foundation, Inc. # This Makefile.in is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, @@ -60,61 +60,23 @@ # a while by putting a link to the driver into /lib of the build tree. VPATH = @srcdir@ -am__is_gnu_make = { \ - if test -z '$(MAKELEVEL)'; then \ - false; \ - elif test -n '$(MAKE_HOST)'; then \ - true; \ - elif test -n '$(MAKE_VERSION)' && test -n '$(CURDIR)'; then \ - true; \ - else \ - false; \ - fi; \ -} -am__make_running_with_option = \ - case $${target_option-} in \ - ?) ;; \ - *) echo "am__make_running_with_option: internal error: invalid" \ - "target option '$${target_option-}' specified" >&2; \ - exit 1;; \ - esac; \ - has_opt=no; \ - sane_makeflags=$$MAKEFLAGS; \ - if $(am__is_gnu_make); then \ - sane_makeflags=$$MFLAGS; \ - else \ +am__make_dryrun = \ + { \ + am__dry=no; \ case $$MAKEFLAGS in \ *\\[\ \ ]*) \ - bs=\\; \ - sane_makeflags=`printf '%s\n' "$$MAKEFLAGS" \ - | sed "s/$$bs$$bs[$$bs $$bs ]*//g"`;; \ - esac; \ - fi; \ - skip_next=no; \ - strip_trailopt () \ - { \ - flg=`printf '%s\n' "$$flg" | sed "s/$$1.*$$//"`; \ - }; \ - for flg in $$sane_makeflags; do \ - test $$skip_next = yes && { skip_next=no; continue; }; \ - case $$flg in \ - *=*|--*) continue;; \ - -*I) strip_trailopt 'I'; skip_next=yes;; \ - -*I?*) strip_trailopt 'I';; \ - -*O) strip_trailopt 'O'; skip_next=yes;; \ - -*O?*) strip_trailopt 'O';; \ - -*l) strip_trailopt 'l'; skip_next=yes;; \ - -*l?*) strip_trailopt 'l';; \ - -[dEDm]) skip_next=yes;; \ - -[JT]) skip_next=yes;; \ + echo 'am--echo: ; @echo "AM" OK' | $(MAKE) -f - 2>/dev/null \ + | grep '^AM OK$$' >/dev/null || am__dry=yes;; \ + *) \ + for am__flg in $$MAKEFLAGS; do \ + case $$am__flg in \ + *=*|--*) ;; \ + *n*) am__dry=yes; break;; \ + esac; \ + done;; \ esac; \ - case $$flg in \ - *$$target_option*) has_opt=yes; break;; \ - esac; \ - done; \ - test $$has_opt = yes -am__make_dryrun = (target_option=n; $(am__make_running_with_option)) -am__make_keepgoing = (target_option=k; $(am__make_running_with_option)) + test $$am__dry = yes; \ + } pkgdatadir = $(datadir)/@PACKAGE@ pkgincludedir = $(includedir)/@PACKAGE@ pkglibdir = $(libdir)/@PACKAGE@ @@ -134,6 +96,10 @@ POST_UNINSTALL = : build_triplet = @build@ host_triplet = @host@ target_triplet = @target@ +DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in \ + $(srcdir)/Makefile.sources $(top_srcdir)/bin/depcomp \ + $(top_srcdir)/install-gallium-links.mk \ + $(top_srcdir)/src/gallium/Automake.inc @HAVE_DRISW_TRUE@am__append_1 = \ @HAVE_DRISW_TRUE@ $(top_builddir)/src/gallium/winsys/sw/dri/libswdri.la @@ -155,7 +121,6 @@ am__aclocal_m4_deps = $(top_srcdir)/m4/ax_check_gnu_make.m4 \ $(top_srcdir)/VERSION $(top_srcdir)/configure.ac am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ $(ACLOCAL_M4) -DIST_COMMON = $(srcdir)/Makefile.am $(am__DIST_COMMON) mkinstalldirs = $(install_sh) -d CONFIG_CLEAN_FILES = CONFIG_CLEAN_VPATH_FILES = @@ -374,29 +339,8 @@ am__can_run_installinfo = \ n|no|NO) false;; \ *) (install-info --version) >/dev/null 2>&1;; \ esac -am__tagged_files = $(HEADERS) $(SOURCES) $(TAGS_FILES) $(LISP) -# Read a list of newline-separated strings from the standard input, -# and print each of them once, without duplicates. Input order is -# *not* preserved. -am__uniquify_input = $(AWK) '\ - BEGIN { nonempty = 0; } \ - { items[$$0] = 1; nonempty = 1; } \ - END { if (nonempty) { for (i in items) print i; }; } \ -' -# Make sure the list of sources is unique. This is necessary because, -# e.g., the same source file might be shared among _SOURCES variables -# for different programs/libraries. -am__define_uniq_tagged_files = \ - list='$(am__tagged_files)'; \ - unique=`for i in $$list; do \ - if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \ - done | $(am__uniquify_input)` ETAGS = etags CTAGS = ctags -am__DIST_COMMON = $(srcdir)/Makefile.in $(srcdir)/Makefile.sources \ - $(top_srcdir)/bin/depcomp \ - $(top_srcdir)/install-gallium-links.mk \ - $(top_srcdir)/src/gallium/Automake.inc DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) ACLOCAL = @ACLOCAL@ AMDGPU_CFLAGS = @AMDGPU_CFLAGS@ @@ -518,7 +462,7 @@ LLVM_LIBS = @LLVM_LIBS@ LLVM_VERSION = @LLVM_VERSION@ LN_S = @LN_S@ LTLIBOBJS = @LTLIBOBJS@ -LT_SYS_LIBRARY_PATH = @LT_SYS_LIBRARY_PATH@ +MAINT = @MAINT@ MAKEINFO = @MAKEINFO@ MANIFEST_TOOL = @MANIFEST_TOOL@ MESA_LLVM = @MESA_LLVM@ @@ -1023,7 +967,7 @@ all: $(BUILT_SOURCES) .SUFFIXES: .SUFFIXES: .cpp .lo .o .obj -$(srcdir)/Makefile.in: $(srcdir)/Makefile.am $(srcdir)/Makefile.sources $(top_srcdir)/src/gallium/Automake.inc $(top_srcdir)/install-gallium-links.mk $(am__configure_deps) +$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(srcdir)/Makefile.sources $(top_srcdir)/src/gallium/Automake.inc $(top_srcdir)/install-gallium-links.mk $(am__configure_deps) @for dep in $?; do \ case '$(am__configure_deps)' in \ *$$dep*) \ @@ -1035,6 +979,7 @@ $(srcdir)/Makefile.in: $(srcdir)/Makefile.am $(srcdir)/Makefile.sources $(top_s echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign src/gallium/drivers/swr/Makefile'; \ $(am__cd) $(top_srcdir) && \ $(AUTOMAKE) --foreign src/gallium/drivers/swr/Makefile +.PRECIOUS: Makefile Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status @case '$?' in \ *config.status*) \ @@ -1043,17 +988,16 @@ Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \ esac; -$(srcdir)/Makefile.sources $(top_srcdir)/src/gallium/Automake.inc $(top_srcdir)/install-gallium-links.mk $(am__empty): +$(srcdir)/Makefile.sources $(top_srcdir)/src/gallium/Automake.inc $(top_srcdir)/install-gallium-links.mk: $(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES) cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh -$(top_srcdir)/configure: $(am__configure_deps) +$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps) cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh -$(ACLOCAL_M4): $(am__aclocal_m4_deps) +$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps) cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh $(am__aclocal_m4_deps): - install-libLTLIBRARIES: $(lib_LTLIBRARIES) @$(NORMAL_INSTALL) @list='$(lib_LTLIBRARIES)'; test -n "$(libdir)" || list=; \ @@ -1099,7 +1043,6 @@ clean-noinstLTLIBRARIES: echo rm -f $${locs}; \ rm -f $${locs}; \ } - libmesaswr.la: $(libmesaswr_la_OBJECTS) $(libmesaswr_la_DEPENDENCIES) $(EXTRA_libmesaswr_la_DEPENDENCIES) $(AM_V_CXXLD)$(CXXLINK) $(libmesaswr_la_OBJECTS) $(libmesaswr_la_LIBADD) $(LIBS) rasterizer/archrast/$(am__dirstamp): @@ -1250,7 +1193,6 @@ rasterizer/archrast/libswrAVX_la-gen_ar_event.lo: \ rasterizer/jitter/libswrAVX_la-builder_gen.lo: \ rasterizer/jitter/$(am__dirstamp) \ rasterizer/jitter/$(DEPDIR)/$(am__dirstamp) - libswrAVX.la: $(libswrAVX_la_OBJECTS) $(libswrAVX_la_DEPENDENCIES) $(EXTRA_libswrAVX_la_DEPENDENCIES) $(AM_V_CXXLD)$(libswrAVX_la_LINK) -rpath $(libdir) $(libswrAVX_la_OBJECTS) $(libswrAVX_la_LIBADD) $(LIBS) rasterizer/archrast/libswrAVX2_la-archrast.lo: \ @@ -1366,7 +1308,6 @@ rasterizer/archrast/libswrAVX2_la-gen_ar_event.lo: \ rasterizer/jitter/libswrAVX2_la-builder_gen.lo: \ rasterizer/jitter/$(am__dirstamp) \ rasterizer/jitter/$(DEPDIR)/$(am__dirstamp) - libswrAVX2.la: $(libswrAVX2_la_OBJECTS) $(libswrAVX2_la_DEPENDENCIES) $(EXTRA_libswrAVX2_la_DEPENDENCIES) $(AM_V_CXXLD)$(libswrAVX2_la_LINK) -rpath $(libdir) $(libswrAVX2_la_OBJECTS) $(libswrAVX2_la_LIBADD) $(LIBS) @@ -2194,15 +2135,26 @@ clean-libtool: -rm -rf rasterizer/memory/.libs rasterizer/memory/_libs -rm -rf rasterizer/scripts/.libs rasterizer/scripts/_libs -ID: $(am__tagged_files) - $(am__define_uniq_tagged_files); mkid -fID $$unique -tags: tags-am -TAGS: tags - -tags-am: $(TAGS_DEPENDENCIES) $(am__tagged_files) +ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES) + list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \ + unique=`for i in $$list; do \ + if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \ + done | \ + $(AWK) '{ files[$$0] = 1; nonempty = 1; } \ + END { if (nonempty) { for (i in files) print i; }; }'`; \ + mkid -fID $$unique +tags: TAGS + +TAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \ + $(TAGS_FILES) $(LISP) set x; \ here=`pwd`; \ - $(am__define_uniq_tagged_files); \ + list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \ + unique=`for i in $$list; do \ + if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \ + done | \ + $(AWK) '{ files[$$0] = 1; nonempty = 1; } \ + END { if (nonempty) { for (i in files) print i; }; }'`; \ shift; \ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \ test -n "$$unique" || unique=$$empty_fix; \ @@ -2214,11 +2166,15 @@ tags-am: $(TAGS_DEPENDENCIES) $(am__tagged_files) $$unique; \ fi; \ fi -ctags: ctags-am - -CTAGS: ctags -ctags-am: $(TAGS_DEPENDENCIES) $(am__tagged_files) - $(am__define_uniq_tagged_files); \ +ctags: CTAGS +CTAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \ + $(TAGS_FILES) $(LISP) + list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \ + unique=`for i in $$list; do \ + if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \ + done | \ + $(AWK) '{ files[$$0] = 1; nonempty = 1; } \ + END { if (nonempty) { for (i in files) print i; }; }'`; \ test -z "$(CTAGS_ARGS)$$unique" \ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \ $$unique @@ -2227,10 +2183,9 @@ GTAGS: here=`$(am__cd) $(top_builddir) && pwd` \ && $(am__cd) $(top_srcdir) \ && gtags -i $(GTAGS_ARGS) "$$here" -cscopelist: cscopelist-am -cscopelist-am: $(am__tagged_files) - list='$(am__tagged_files)'; \ +cscopelist: $(HEADERS) $(SOURCES) $(LISP) + list='$(SOURCES) $(HEADERS) $(LISP)'; \ case "$(srcdir)" in \ [\\/]* | ?:[\\/]*) sdir="$(srcdir)" ;; \ *) sdir=$(subdir)/$(srcdir) ;; \ @@ -2405,9 +2360,9 @@ uninstall-am: uninstall-libLTLIBRARIES .MAKE: all check install install-am install-strip -.PHONY: CTAGS GTAGS TAGS all all-am all-local check check-am clean \ +.PHONY: CTAGS GTAGS all all-am all-local check check-am clean \ clean-generic clean-libLTLIBRARIES clean-libtool clean-local \ - clean-noinstLTLIBRARIES cscopelist-am ctags ctags-am distclean \ + clean-noinstLTLIBRARIES cscopelist ctags distclean \ distclean-compile distclean-generic distclean-libtool \ distclean-local distclean-tags distdir dvi dvi-am html html-am \ info info-am install install-am install-data install-data-am \ @@ -2418,9 +2373,7 @@ uninstall-am: uninstall-libLTLIBRARIES installcheck-am installdirs maintainer-clean \ maintainer-clean-generic mostlyclean mostlyclean-compile \ mostlyclean-generic mostlyclean-libtool pdf pdf-am ps ps-am \ - tags tags-am uninstall uninstall-am uninstall-libLTLIBRARIES - -.PRECIOUS: Makefile + tags uninstall uninstall-am uninstall-libLTLIBRARIES swr_context_llvm.h: rasterizer/jitter/scripts/gen_llvm_types.py swr_context.h $(PYTHON_GEN) \ diff --git a/lib/mesa/src/gallium/drivers/trace/Makefile.in b/lib/mesa/src/gallium/drivers/trace/Makefile.in index 458589d4c..e851e33fe 100644 --- a/lib/mesa/src/gallium/drivers/trace/Makefile.in +++ b/lib/mesa/src/gallium/drivers/trace/Makefile.in @@ -200,6 +200,8 @@ GLESv2_LIB_DEPS = @GLESv2_LIB_DEPS@ GLESv2_PC_LIB_PRIV = @GLESv2_PC_LIB_PRIV@ GLPROTO_CFLAGS = @GLPROTO_CFLAGS@ GLPROTO_LIBS = @GLPROTO_LIBS@ +GLVND_CFLAGS = @GLVND_CFLAGS@ +GLVND_LIBS = @GLVND_LIBS@ GLX_TLS = @GLX_TLS@ GL_LIB = @GL_LIB@ GL_LIB_DEPS = @GL_LIB_DEPS@ @@ -231,11 +233,10 @@ LIBELF_CFLAGS = @LIBELF_CFLAGS@ LIBELF_LIBS = @LIBELF_LIBS@ LIBOBJS = @LIBOBJS@ LIBS = @LIBS@ +LIBSENSORS_LDFLAGS = @LIBSENSORS_LDFLAGS@ LIBSHA1_CFLAGS = @LIBSHA1_CFLAGS@ LIBSHA1_LIBS = @LIBSHA1_LIBS@ LIBTOOL = @LIBTOOL@ -LIBUDEV_CFLAGS = @LIBUDEV_CFLAGS@ -LIBUDEV_LIBS = @LIBUDEV_LIBS@ LIB_DIR = @LIB_DIR@ LIB_EXT = @LIB_EXT@ LIPO = @LIPO@ @@ -298,6 +299,8 @@ PKG_CONFIG_PATH = @PKG_CONFIG_PATH@ POSIX_SHELL = @POSIX_SHELL@ PRESENTPROTO_CFLAGS = @PRESENTPROTO_CFLAGS@ PRESENTPROTO_LIBS = @PRESENTPROTO_LIBS@ +PTHREADSTUBS_CFLAGS = @PTHREADSTUBS_CFLAGS@ +PTHREADSTUBS_LIBS = @PTHREADSTUBS_LIBS@ PTHREAD_CC = @PTHREAD_CC@ PTHREAD_CFLAGS = @PTHREAD_CFLAGS@ PTHREAD_LIBS = @PTHREAD_LIBS@ @@ -318,11 +321,19 @@ SIMPENROSE_CFLAGS = @SIMPENROSE_CFLAGS@ SIMPENROSE_LIBS = @SIMPENROSE_LIBS@ SSE41_CFLAGS = @SSE41_CFLAGS@ STRIP = @STRIP@ +SWR_AVX2_CXXFLAGS = @SWR_AVX2_CXXFLAGS@ +SWR_AVX_CXXFLAGS = @SWR_AVX_CXXFLAGS@ +SWR_CXX11_CXXFLAGS = @SWR_CXX11_CXXFLAGS@ +TIMESTAMP_CMD = @TIMESTAMP_CMD@ +VALGRIND_CFLAGS = @VALGRIND_CFLAGS@ +VALGRIND_LIBS = @VALGRIND_LIBS@ VA_CFLAGS = @VA_CFLAGS@ VA_LIBS = @VA_LIBS@ VA_LIB_INSTALL_DIR = @VA_LIB_INSTALL_DIR@ VA_MAJOR = @VA_MAJOR@ VA_MINOR = @VA_MINOR@ +VC4_CFLAGS = @VC4_CFLAGS@ +VC4_LIBS = @VC4_LIBS@ VDPAU_CFLAGS = @VDPAU_CFLAGS@ VDPAU_LIBS = @VDPAU_LIBS@ VDPAU_LIB_INSTALL_DIR = @VDPAU_LIB_INSTALL_DIR@ @@ -334,6 +345,7 @@ VISIBILITY_CFLAGS = @VISIBILITY_CFLAGS@ VISIBILITY_CXXFLAGS = @VISIBILITY_CXXFLAGS@ VL_CFLAGS = @VL_CFLAGS@ VL_LIBS = @VL_LIBS@ +VULKAN_ICD_INSTALL_DIR = @VULKAN_ICD_INSTALL_DIR@ WAYLAND_CFLAGS = @WAYLAND_CFLAGS@ WAYLAND_LIBS = @WAYLAND_LIBS@ WAYLAND_SCANNER = @WAYLAND_SCANNER@ @@ -357,6 +369,7 @@ XVMC_LIBS = @XVMC_LIBS@ XVMC_LIB_INSTALL_DIR = @XVMC_LIB_INSTALL_DIR@ XVMC_MAJOR = @XVMC_MAJOR@ XVMC_MINOR = @XVMC_MINOR@ +XXD = @XXD@ YACC = @YACC@ YFLAGS = @YFLAGS@ abs_builddir = @abs_builddir@ diff --git a/lib/mesa/src/gallium/drivers/vc4/Makefile.in b/lib/mesa/src/gallium/drivers/vc4/Makefile.in index a7c300624..5e027a504 100644 --- a/lib/mesa/src/gallium/drivers/vc4/Makefile.in +++ b/lib/mesa/src/gallium/drivers/vc4/Makefile.in @@ -100,7 +100,8 @@ mkinstalldirs = $(install_sh) -d CONFIG_CLEAN_FILES = CONFIG_CLEAN_VPATH_FILES = LTLIBRARIES = $(noinst_LTLIBRARIES) -libvc4_la_DEPENDENCIES = +am__DEPENDENCIES_1 = +libvc4_la_DEPENDENCIES = $(am__DEPENDENCIES_1) am__dirstamp = $(am__leading_dot)dirstamp am__objects_1 = kernel/vc4_gem.lo kernel/vc4_render_cl.lo \ kernel/vc4_validate.lo kernel/vc4_validate_shaders.lo \ @@ -109,10 +110,12 @@ am__objects_1 = kernel/vc4_gem.lo kernel/vc4_render_cl.lo \ vc4_formats.lo vc4_job.lo vc4_nir_lower_blend.lo \ vc4_nir_lower_io.lo vc4_nir_lower_txf_ms.lo \ vc4_opt_algebraic.lo vc4_opt_constant_folding.lo \ - vc4_opt_copy_propagation.lo vc4_opt_cse.lo \ - vc4_opt_dead_code.lo vc4_opt_small_immediates.lo \ - vc4_opt_vpm_writes.lo vc4_program.lo vc4_qir.lo \ - vc4_qir_lower_uniforms.lo vc4_qir_schedule.lo vc4_qpu.lo \ + vc4_opt_copy_propagation.lo vc4_opt_dead_code.lo \ + vc4_opt_peephole_sf.lo vc4_opt_small_immediates.lo \ + vc4_opt_vpm.lo vc4_program.lo vc4_qir.lo \ + vc4_qir_emit_uniform_stream_resets.lo \ + vc4_qir_live_variables.lo vc4_qir_lower_uniforms.lo \ + vc4_qir_schedule.lo vc4_qir_validate.lo vc4_qpu.lo \ vc4_qpu_disasm.lo vc4_qpu_emit.lo vc4_qpu_schedule.lo \ vc4_qpu_validate.lo vc4_query.lo vc4_register_allocate.lo \ vc4_reorder_uniforms.lo vc4_resource.lo vc4_screen.lo \ @@ -238,6 +241,8 @@ GLESv2_LIB_DEPS = @GLESv2_LIB_DEPS@ GLESv2_PC_LIB_PRIV = @GLESv2_PC_LIB_PRIV@ GLPROTO_CFLAGS = @GLPROTO_CFLAGS@ GLPROTO_LIBS = @GLPROTO_LIBS@ +GLVND_CFLAGS = @GLVND_CFLAGS@ +GLVND_LIBS = @GLVND_LIBS@ GLX_TLS = @GLX_TLS@ GL_LIB = @GL_LIB@ GL_LIB_DEPS = @GL_LIB_DEPS@ @@ -269,11 +274,10 @@ LIBELF_CFLAGS = @LIBELF_CFLAGS@ LIBELF_LIBS = @LIBELF_LIBS@ LIBOBJS = @LIBOBJS@ LIBS = @LIBS@ +LIBSENSORS_LDFLAGS = @LIBSENSORS_LDFLAGS@ LIBSHA1_CFLAGS = @LIBSHA1_CFLAGS@ LIBSHA1_LIBS = @LIBSHA1_LIBS@ LIBTOOL = @LIBTOOL@ -LIBUDEV_CFLAGS = @LIBUDEV_CFLAGS@ -LIBUDEV_LIBS = @LIBUDEV_LIBS@ LIB_DIR = @LIB_DIR@ LIB_EXT = @LIB_EXT@ LIPO = @LIPO@ @@ -336,6 +340,8 @@ PKG_CONFIG_PATH = @PKG_CONFIG_PATH@ POSIX_SHELL = @POSIX_SHELL@ PRESENTPROTO_CFLAGS = @PRESENTPROTO_CFLAGS@ PRESENTPROTO_LIBS = @PRESENTPROTO_LIBS@ +PTHREADSTUBS_CFLAGS = @PTHREADSTUBS_CFLAGS@ +PTHREADSTUBS_LIBS = @PTHREADSTUBS_LIBS@ PTHREAD_CC = @PTHREAD_CC@ PTHREAD_CFLAGS = @PTHREAD_CFLAGS@ PTHREAD_LIBS = @PTHREAD_LIBS@ @@ -356,11 +362,19 @@ SIMPENROSE_CFLAGS = @SIMPENROSE_CFLAGS@ SIMPENROSE_LIBS = @SIMPENROSE_LIBS@ SSE41_CFLAGS = @SSE41_CFLAGS@ STRIP = @STRIP@ +SWR_AVX2_CXXFLAGS = @SWR_AVX2_CXXFLAGS@ +SWR_AVX_CXXFLAGS = @SWR_AVX_CXXFLAGS@ +SWR_CXX11_CXXFLAGS = @SWR_CXX11_CXXFLAGS@ +TIMESTAMP_CMD = @TIMESTAMP_CMD@ +VALGRIND_CFLAGS = @VALGRIND_CFLAGS@ +VALGRIND_LIBS = @VALGRIND_LIBS@ VA_CFLAGS = @VA_CFLAGS@ VA_LIBS = @VA_LIBS@ VA_LIB_INSTALL_DIR = @VA_LIB_INSTALL_DIR@ VA_MAJOR = @VA_MAJOR@ VA_MINOR = @VA_MINOR@ +VC4_CFLAGS = @VC4_CFLAGS@ +VC4_LIBS = @VC4_LIBS@ VDPAU_CFLAGS = @VDPAU_CFLAGS@ VDPAU_LIBS = @VDPAU_LIBS@ VDPAU_LIB_INSTALL_DIR = @VDPAU_LIB_INSTALL_DIR@ @@ -372,6 +386,7 @@ VISIBILITY_CFLAGS = @VISIBILITY_CFLAGS@ VISIBILITY_CXXFLAGS = @VISIBILITY_CXXFLAGS@ VL_CFLAGS = @VL_CFLAGS@ VL_LIBS = @VL_LIBS@ +VULKAN_ICD_INSTALL_DIR = @VULKAN_ICD_INSTALL_DIR@ WAYLAND_CFLAGS = @WAYLAND_CFLAGS@ WAYLAND_LIBS = @WAYLAND_LIBS@ WAYLAND_SCANNER = @WAYLAND_SCANNER@ @@ -395,6 +410,7 @@ XVMC_LIBS = @XVMC_LIBS@ XVMC_LIB_INSTALL_DIR = @XVMC_LIB_INSTALL_DIR@ XVMC_MAJOR = @XVMC_MAJOR@ XVMC_MINOR = @XVMC_MINOR@ +XXD = @XXD@ YACC = @YACC@ YFLAGS = @YFLAGS@ abs_builddir = @abs_builddir@ @@ -473,7 +489,6 @@ C_SOURCES := \ vc4_context.c \ vc4_context.h \ vc4_draw.c \ - vc4_drm.h \ vc4_emit.c \ vc4_fence.c \ vc4_formats.c \ @@ -484,14 +499,17 @@ C_SOURCES := \ vc4_opt_algebraic.c \ vc4_opt_constant_folding.c \ vc4_opt_copy_propagation.c \ - vc4_opt_cse.c \ vc4_opt_dead_code.c \ + vc4_opt_peephole_sf.c \ vc4_opt_small_immediates.c \ - vc4_opt_vpm_writes.c \ + vc4_opt_vpm.c \ vc4_program.c \ vc4_qir.c \ + vc4_qir_emit_uniform_stream_resets.c \ + vc4_qir_live_variables.c \ vc4_qir_lower_uniforms.c \ vc4_qir_schedule.c \ + vc4_qir_validate.c \ vc4_qir.h \ vc4_qpu.c \ vc4_qpu_defines.h \ @@ -584,13 +602,15 @@ GALLIUM_PIPE_LOADER_WINSYS_LIBS = \ AM_CFLAGS = \ -I$(top_builddir)/src/compiler/nir \ $(LIBDRM_CFLAGS) \ + $(VC4_CFLAGS) \ $(GALLIUM_DRIVER_CFLAGS) \ $(SIM_CFLAGS) \ + $(VALGRIND_CFLAGS) \ $() noinst_LTLIBRARIES = libvc4.la libvc4_la_SOURCES = $(C_SOURCES) -libvc4_la_LIBADD = $(SIM_LIB) +libvc4_la_LIBADD = $(SIM_LIB) $(VC4_LIBS) libvc4_la_LDFLAGS = $(SIM_LDFLAGS) all: all-am @@ -679,14 +699,17 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vc4_opt_algebraic.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vc4_opt_constant_folding.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vc4_opt_copy_propagation.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vc4_opt_cse.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vc4_opt_dead_code.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vc4_opt_peephole_sf.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vc4_opt_small_immediates.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vc4_opt_vpm_writes.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vc4_opt_vpm.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vc4_program.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vc4_qir.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vc4_qir_emit_uniform_stream_resets.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vc4_qir_live_variables.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vc4_qir_lower_uniforms.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vc4_qir_schedule.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vc4_qir_validate.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vc4_qpu.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vc4_qpu_disasm.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/vc4_qpu_emit.Plo@am__quote@ diff --git a/lib/mesa/src/gallium/drivers/vc4/vc4_drm.h b/lib/mesa/src/gallium/drivers/vc4/vc4_drm.h deleted file mode 100644 index 863ef8da8..000000000 --- a/lib/mesa/src/gallium/drivers/vc4/vc4_drm.h +++ /dev/null @@ -1,229 +0,0 @@ -/* - * Copyright © 2014-2015 Broadcom - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -#ifndef _UAPI_VC4_DRM_H_ -#define _UAPI_VC4_DRM_H_ - -#include <drm.h> - -#define DRM_VC4_SUBMIT_CL 0x00 -#define DRM_VC4_WAIT_SEQNO 0x01 -#define DRM_VC4_WAIT_BO 0x02 -#define DRM_VC4_CREATE_BO 0x03 -#define DRM_VC4_MMAP_BO 0x04 -#define DRM_VC4_CREATE_SHADER_BO 0x05 - -#define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl) -#define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno) -#define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo) -#define DRM_IOCTL_VC4_CREATE_BO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo) -#define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo) -#define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo) - -struct drm_vc4_submit_rcl_surface { - uint32_t hindex; /* Handle index, or ~0 if not present. */ - uint32_t offset; /* Offset to start of buffer. */ - /* - * Bits for either render config (color_ms_write) or load/store packet. - */ - uint16_t bits; - uint16_t pad; -}; - -/** - * struct drm_vc4_submit_cl - ioctl argument for submitting commands to the 3D - * engine. - * - * Drivers typically use GPU BOs to store batchbuffers / command lists and - * their associated state. However, because the VC4 lacks an MMU, we have to - * do validation of memory accesses by the GPU commands. If we were to store - * our commands in BOs, we'd need to do uncached readback from them to do the - * validation process, which is too expensive. Instead, userspace accumulates - * commands and associated state in plain memory, then the kernel copies the - * data to its own address space, and then validates and stores it in a GPU - * BO. - */ -struct drm_vc4_submit_cl { - /* Pointer to the binner command list. - * - * This is the first set of commands executed, which runs the - * coordinate shader to determine where primitives land on the screen, - * then writes out the state updates and draw calls necessary per tile - * to the tile allocation BO. - */ - uint64_t bin_cl; - - /* Pointer to the shader records. - * - * Shader records are the structures read by the hardware that contain - * pointers to uniforms, shaders, and vertex attributes. The - * reference to the shader record has enough information to determine - * how many pointers are necessary (fixed number for shaders/uniforms, - * and an attribute count), so those BO indices into bo_handles are - * just stored as uint32_ts before each shader record passed in. - */ - uint64_t shader_rec; - - /* Pointer to uniform data and texture handles for the textures - * referenced by the shader. - * - * For each shader state record, there is a set of uniform data in the - * order referenced by the record (FS, VS, then CS). Each set of - * uniform data has a uint32_t index into bo_handles per texture - * sample operation, in the order the QPU_W_TMUn_S writes appear in - * the program. Following the texture BO handle indices is the actual - * uniform data. - * - * The individual uniform state blocks don't have sizes passed in, - * because the kernel has to determine the sizes anyway during shader - * code validation. - */ - uint64_t uniforms; - uint64_t bo_handles; - - /* Size in bytes of the binner command list. */ - uint32_t bin_cl_size; - /* Size in bytes of the set of shader records. */ - uint32_t shader_rec_size; - /* Number of shader records. - * - * This could just be computed from the contents of shader_records and - * the address bits of references to them from the bin CL, but it - * keeps the kernel from having to resize some allocations it makes. - */ - uint32_t shader_rec_count; - /* Size in bytes of the uniform state. */ - uint32_t uniforms_size; - - /* Number of BO handles passed in (size is that times 4). */ - uint32_t bo_handle_count; - - /* RCL setup: */ - uint16_t width; - uint16_t height; - uint8_t min_x_tile; - uint8_t min_y_tile; - uint8_t max_x_tile; - uint8_t max_y_tile; - struct drm_vc4_submit_rcl_surface color_read; - struct drm_vc4_submit_rcl_surface color_ms_write; - struct drm_vc4_submit_rcl_surface zs_read; - struct drm_vc4_submit_rcl_surface zs_write; - uint32_t clear_color[2]; - uint32_t clear_z; - uint8_t clear_s; - - uint32_t pad:24; - -#define VC4_SUBMIT_CL_USE_CLEAR_COLOR (1 << 0) - uint32_t flags; - - /* Returned value of the seqno of this render job (for the - * wait ioctl). - */ - uint64_t seqno; -}; - -/** - * struct drm_vc4_wait_seqno - ioctl argument for waiting for - * DRM_VC4_SUBMIT_CL completion using its returned seqno. - * - * timeout_ns is the timeout in nanoseconds, where "0" means "don't - * block, just return the status." - */ -struct drm_vc4_wait_seqno { - uint64_t seqno; - uint64_t timeout_ns; -}; - -/** - * struct drm_vc4_wait_bo - ioctl argument for waiting for - * completion of the last DRM_VC4_SUBMIT_CL on a BO. - * - * This is useful for cases where multiple processes might be - * rendering to a BO and you want to wait for all rendering to be - * completed. - */ -struct drm_vc4_wait_bo { - uint32_t handle; - uint32_t pad; - uint64_t timeout_ns; -}; - -/** - * struct drm_vc4_create_bo - ioctl argument for creating VC4 BOs. - * - * There are currently no values for the flags argument, but it may be - * used in a future extension. - */ -struct drm_vc4_create_bo { - uint32_t size; - uint32_t flags; - /** Returned GEM handle for the BO. */ - uint32_t handle; - uint32_t pad; -}; - -/** - * struct drm_vc4_create_shader_bo - ioctl argument for creating VC4 - * shader BOs. - * - * Since allowing a shader to be overwritten while it's also being - * executed from would allow privlege escalation, shaders must be - * created using this ioctl, and they can't be mmapped later. - */ -struct drm_vc4_create_shader_bo { - /* Size of the data argument. */ - uint32_t size; - /* Flags, currently must be 0. */ - uint32_t flags; - - /* Pointer to the data. */ - uint64_t data; - - /** Returned GEM handle for the BO. */ - uint32_t handle; - /* Pad, must be 0. */ - uint32_t pad; -}; - -/** - * struct drm_vc4_mmap_bo - ioctl argument for mapping VC4 BOs. - * - * This doesn't actually perform an mmap. Instead, it returns the - * offset you need to use in an mmap on the DRM device node. This - * means that tools like valgrind end up knowing about the mapped - * memory. - * - * There are currently no values for the flags argument, but it may be - * used in a future extension. - */ -struct drm_vc4_mmap_bo { - /** Handle for the object being mapped. */ - uint32_t handle; - uint32_t flags; - /** offset into the drm node to use for subsequent mmap call. */ - uint64_t offset; -}; - -#endif /* _UAPI_VC4_DRM_H_ */ diff --git a/lib/mesa/src/gallium/drivers/vc4/vc4_opt_cse.c b/lib/mesa/src/gallium/drivers/vc4/vc4_opt_cse.c deleted file mode 100644 index 0e5480ea7..000000000 --- a/lib/mesa/src/gallium/drivers/vc4/vc4_opt_cse.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - * Copyright © 2014 Broadcom - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -/** - * @file vc4_opt_cse.c - * - * Implements CSE for QIR without control flow. - * - * For each operation that writes a destination (and isn't just a MOV), put it - * in the hash table of all instructions that do so. When faced with another - * one, look it up in the hash table by its opcode and operands. If there's - * an entry in the table, then just reuse the entry's destination as the - * source of a MOV instead of reproducing the computation. That MOV will then - * get cleaned up by copy propagation. - */ - -#include "vc4_qir.h" - -#include "util/hash_table.h" -#include "util/ralloc.h" - -static bool debug; - -struct inst_key { - enum qop op; - struct qreg src[4]; - /** - * If the instruction depends on the flags, how many SFs have been - * seen before this instruction. - */ - uint32_t implicit_arg_update_count; -}; - -static bool -inst_key_equals(const void *a, const void *b) -{ - const struct inst_key *key_a = a; - const struct inst_key *key_b = b; - - return memcmp(key_a, key_b, sizeof(*key_a)) == 0; -} - -static struct qinst * -vc4_find_cse(struct vc4_compile *c, struct hash_table *ht, - struct qinst *inst, uint32_t sf_count) -{ - if (inst->dst.file != QFILE_TEMP || - inst->op == QOP_MOV || - qir_get_op_nsrc(inst->op) > 4) { - return NULL; - } - - struct inst_key key; - memset(&key, 0, sizeof(key)); - key.op = inst->op; - memcpy(key.src, inst->src, - qir_get_op_nsrc(inst->op) * sizeof(key.src[0])); - if (qir_depends_on_flags(inst)) - key.implicit_arg_update_count = sf_count; - - uint32_t hash = _mesa_hash_data(&key, sizeof(key)); - struct hash_entry *entry = - _mesa_hash_table_search_pre_hashed(ht, hash, &key); - - if (entry) { - if (debug) { - fprintf(stderr, "CSE found match:\n"); - - fprintf(stderr, " Original inst: "); - qir_dump_inst(c, entry->data); - fprintf(stderr, "\n"); - - fprintf(stderr, " Our inst: "); - qir_dump_inst(c, inst); - fprintf(stderr, "\n"); - } - - return entry->data; - } - - struct inst_key *alloc_key = ralloc(ht, struct inst_key); - if (!alloc_key) - return NULL; - memcpy(alloc_key, &key, sizeof(*alloc_key)); - _mesa_hash_table_insert_pre_hashed(ht, hash, alloc_key, inst); - - if (debug) { - fprintf(stderr, "Added to CSE HT: "); - qir_dump_inst(c, inst); - fprintf(stderr, "\n"); - } - - return NULL; -} - -bool -qir_opt_cse(struct vc4_compile *c) -{ - bool progress = false; - uint32_t sf_count = 0; - - struct hash_table *ht = _mesa_hash_table_create(NULL, NULL, - inst_key_equals); - if (!ht) - return false; - - list_for_each_entry(struct qinst, inst, &c->instructions, link) { - if (qir_has_side_effects(c, inst) || - qir_has_side_effect_reads(c, inst) || - inst->op == QOP_TLB_COLOR_READ) { - continue; - } - - if (inst->sf) { - sf_count++; - } else { - struct qinst *cse = vc4_find_cse(c, ht, inst, sf_count); - if (cse) { - inst->src[0] = cse->dst; - for (int i = 1; i < qir_get_op_nsrc(inst->op); - i++) - inst->src[i] = c->undef; - inst->op = QOP_MOV; - progress = true; - - if (debug) { - fprintf(stderr, " Turned into: "); - qir_dump_inst(c, inst); - fprintf(stderr, "\n"); - } - } - } - } - - ralloc_free(ht); - - return progress; -} diff --git a/lib/mesa/src/gallium/drivers/vc4/vc4_opt_vpm_writes.c b/lib/mesa/src/gallium/drivers/vc4/vc4_opt_vpm_writes.c deleted file mode 100644 index f2cdf8f69..000000000 --- a/lib/mesa/src/gallium/drivers/vc4/vc4_opt_vpm_writes.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright © 2014 Broadcom - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -/** - * @file vc4_opt_vpm_writes.c - * - * This modifies instructions that generate the value consumed by a VPM write - * to write directly into the VPM. - */ - -#include "vc4_qir.h" - -bool -qir_opt_vpm_writes(struct vc4_compile *c) -{ - if (c->stage == QSTAGE_FRAG) - return false; - - bool progress = false; - struct qinst *vpm_writes[64] = { 0 }; - uint32_t use_count[c->num_temps]; - uint32_t vpm_write_count = 0; - memset(&use_count, 0, sizeof(use_count)); - - list_for_each_entry(struct qinst, inst, &c->instructions, link) { - switch (inst->dst.file) { - case QFILE_VPM: - vpm_writes[vpm_write_count++] = inst; - break; - default: - break; - } - - for (int i = 0; i < qir_get_op_nsrc(inst->op); i++) { - if (inst->src[i].file == QFILE_TEMP) - use_count[inst->src[i].index]++; - } - } - - for (int i = 0; i < vpm_write_count; i++) { - if (vpm_writes[i]->op != QOP_MOV || - vpm_writes[i]->src[0].file != QFILE_TEMP) { - continue; - } - - uint32_t temp = vpm_writes[i]->src[0].index; - if (use_count[temp] != 1) - continue; - - struct qinst *inst = c->defs[temp]; - if (!inst || qir_is_multi_instruction(inst)) - continue; - - if (qir_depends_on_flags(inst) || inst->sf) - continue; - - if (qir_has_side_effects(c, inst) || - qir_has_side_effect_reads(c, inst)) { - continue; - } - - /* Move the generating instruction to the end of the program - * to maintain the order of the VPM writes. - */ - assert(!vpm_writes[i]->sf); - list_del(&inst->link); - list_addtail(&inst->link, &vpm_writes[i]->link); - qir_remove_instruction(c, vpm_writes[i]); - - c->defs[inst->dst.index] = NULL; - inst->dst.file = QFILE_VPM; - inst->dst.index = 0; - - progress = true; - } - - return progress; -} diff --git a/lib/mesa/src/gallium/drivers/virgl/Makefile.in b/lib/mesa/src/gallium/drivers/virgl/Makefile.in index 298a77778..35115b8d1 100644 --- a/lib/mesa/src/gallium/drivers/virgl/Makefile.in +++ b/lib/mesa/src/gallium/drivers/virgl/Makefile.in @@ -223,6 +223,8 @@ GLESv2_LIB_DEPS = @GLESv2_LIB_DEPS@ GLESv2_PC_LIB_PRIV = @GLESv2_PC_LIB_PRIV@ GLPROTO_CFLAGS = @GLPROTO_CFLAGS@ GLPROTO_LIBS = @GLPROTO_LIBS@ +GLVND_CFLAGS = @GLVND_CFLAGS@ +GLVND_LIBS = @GLVND_LIBS@ GLX_TLS = @GLX_TLS@ GL_LIB = @GL_LIB@ GL_LIB_DEPS = @GL_LIB_DEPS@ @@ -254,11 +256,10 @@ LIBELF_CFLAGS = @LIBELF_CFLAGS@ LIBELF_LIBS = @LIBELF_LIBS@ LIBOBJS = @LIBOBJS@ LIBS = @LIBS@ +LIBSENSORS_LDFLAGS = @LIBSENSORS_LDFLAGS@ LIBSHA1_CFLAGS = @LIBSHA1_CFLAGS@ LIBSHA1_LIBS = @LIBSHA1_LIBS@ LIBTOOL = @LIBTOOL@ -LIBUDEV_CFLAGS = @LIBUDEV_CFLAGS@ -LIBUDEV_LIBS = @LIBUDEV_LIBS@ LIB_DIR = @LIB_DIR@ LIB_EXT = @LIB_EXT@ LIPO = @LIPO@ @@ -321,6 +322,8 @@ PKG_CONFIG_PATH = @PKG_CONFIG_PATH@ POSIX_SHELL = @POSIX_SHELL@ PRESENTPROTO_CFLAGS = @PRESENTPROTO_CFLAGS@ PRESENTPROTO_LIBS = @PRESENTPROTO_LIBS@ +PTHREADSTUBS_CFLAGS = @PTHREADSTUBS_CFLAGS@ +PTHREADSTUBS_LIBS = @PTHREADSTUBS_LIBS@ PTHREAD_CC = @PTHREAD_CC@ PTHREAD_CFLAGS = @PTHREAD_CFLAGS@ PTHREAD_LIBS = @PTHREAD_LIBS@ @@ -341,11 +344,19 @@ SIMPENROSE_CFLAGS = @SIMPENROSE_CFLAGS@ SIMPENROSE_LIBS = @SIMPENROSE_LIBS@ SSE41_CFLAGS = @SSE41_CFLAGS@ STRIP = @STRIP@ +SWR_AVX2_CXXFLAGS = @SWR_AVX2_CXXFLAGS@ +SWR_AVX_CXXFLAGS = @SWR_AVX_CXXFLAGS@ +SWR_CXX11_CXXFLAGS = @SWR_CXX11_CXXFLAGS@ +TIMESTAMP_CMD = @TIMESTAMP_CMD@ +VALGRIND_CFLAGS = @VALGRIND_CFLAGS@ +VALGRIND_LIBS = @VALGRIND_LIBS@ VA_CFLAGS = @VA_CFLAGS@ VA_LIBS = @VA_LIBS@ VA_LIB_INSTALL_DIR = @VA_LIB_INSTALL_DIR@ VA_MAJOR = @VA_MAJOR@ VA_MINOR = @VA_MINOR@ +VC4_CFLAGS = @VC4_CFLAGS@ +VC4_LIBS = @VC4_LIBS@ VDPAU_CFLAGS = @VDPAU_CFLAGS@ VDPAU_LIBS = @VDPAU_LIBS@ VDPAU_LIB_INSTALL_DIR = @VDPAU_LIB_INSTALL_DIR@ @@ -357,6 +368,7 @@ VISIBILITY_CFLAGS = @VISIBILITY_CFLAGS@ VISIBILITY_CXXFLAGS = @VISIBILITY_CXXFLAGS@ VL_CFLAGS = @VL_CFLAGS@ VL_LIBS = @VL_LIBS@ +VULKAN_ICD_INSTALL_DIR = @VULKAN_ICD_INSTALL_DIR@ WAYLAND_CFLAGS = @WAYLAND_CFLAGS@ WAYLAND_LIBS = @WAYLAND_LIBS@ WAYLAND_SCANNER = @WAYLAND_SCANNER@ @@ -380,6 +392,7 @@ XVMC_LIBS = @XVMC_LIBS@ XVMC_LIB_INSTALL_DIR = @XVMC_LIB_INSTALL_DIR@ XVMC_MAJOR = @XVMC_MAJOR@ XVMC_MINOR = @XVMC_MINOR@ +XXD = @XXD@ YACC = @YACC@ YFLAGS = @YFLAGS@ abs_builddir = @abs_builddir@ |