diff options
Diffstat (limited to 'lib/mesa/src/intel/genxml/genX_bits.h')
| -rw-r--r-- | lib/mesa/src/intel/genxml/genX_bits.h | 3731 |
1 files changed, 1911 insertions, 1820 deletions
diff --git a/lib/mesa/src/intel/genxml/genX_bits.h b/lib/mesa/src/intel/genxml/genX_bits.h index cb2d06f3c..dd3d19e22 100644 --- a/lib/mesa/src/intel/genxml/genX_bits.h +++ b/lib/mesa/src/intel/genxml/genX_bits.h @@ -10272,17 +10272,17 @@ _3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_start(const struct gen_device_info -/* 3DSTATE_BINDING_TABLE_POOL_ALLOC::Surface Object Control State */ +/* 3DSTATE_BINDING_TABLE_POOL_ALLOC::MOCS */ -#define GEN11_3DSTATE_BINDING_TABLE_POOL_ALLOC_SurfaceObjectControlState_bits 7 -#define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_SurfaceObjectControlState_bits 7 -#define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_SurfaceObjectControlState_bits 7 -#define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_SurfaceObjectControlState_bits 7 -#define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_SurfaceObjectControlState_bits 4 +#define GEN11_3DSTATE_BINDING_TABLE_POOL_ALLOC_MOCS_bits 7 +#define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_MOCS_bits 7 +#define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_MOCS_bits 7 +#define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_MOCS_bits 7 +#define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_MOCS_bits 4 static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_BINDING_TABLE_POOL_ALLOC_SurfaceObjectControlState_bits(const struct gen_device_info *devinfo) +_3DSTATE_BINDING_TABLE_POOL_ALLOC_MOCS_bits(const struct gen_device_info *devinfo) { switch (devinfo->gen) { case 11: return 7; @@ -10310,14 +10310,14 @@ _3DSTATE_BINDING_TABLE_POOL_ALLOC_SurfaceObjectControlState_bits(const struct ge -#define GEN11_3DSTATE_BINDING_TABLE_POOL_ALLOC_SurfaceObjectControlState_start 32 -#define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_SurfaceObjectControlState_start 32 -#define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_SurfaceObjectControlState_start 32 -#define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_SurfaceObjectControlState_start 32 -#define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_SurfaceObjectControlState_start 39 +#define GEN11_3DSTATE_BINDING_TABLE_POOL_ALLOC_MOCS_start 32 +#define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_MOCS_start 32 +#define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_MOCS_start 32 +#define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_MOCS_start 32 +#define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_MOCS_start 39 static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_BINDING_TABLE_POOL_ALLOC_SurfaceObjectControlState_start(const struct gen_device_info *devinfo) +_3DSTATE_BINDING_TABLE_POOL_ALLOC_MOCS_start(const struct gen_device_info *devinfo) { switch (devinfo->gen) { case 11: return 32; @@ -15665,14 +15665,14 @@ _3DSTATE_CONSTANT_BODY_ConstantBuffer3ReadLength_start(const struct gen_device_i -/* 3DSTATE_CONSTANT_BODY::Constant Buffer Object Control State */ +/* 3DSTATE_CONSTANT_BODY::MOCS */ -#define GEN75_3DSTATE_CONSTANT_BODY_ConstantBufferObjectControlState_bits 5 -#define GEN7_3DSTATE_CONSTANT_BODY_ConstantBufferObjectControlState_bits 5 +#define GEN75_3DSTATE_CONSTANT_BODY_MOCS_bits 5 +#define GEN7_3DSTATE_CONSTANT_BODY_MOCS_bits 5 static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_CONSTANT_BODY_ConstantBufferObjectControlState_bits(const struct gen_device_info *devinfo) +_3DSTATE_CONSTANT_BODY_MOCS_bits(const struct gen_device_info *devinfo) { switch (devinfo->gen) { case 11: return 0; @@ -15700,11 +15700,11 @@ _3DSTATE_CONSTANT_BODY_ConstantBufferObjectControlState_bits(const struct gen_de -#define GEN75_3DSTATE_CONSTANT_BODY_ConstantBufferObjectControlState_start 64 -#define GEN7_3DSTATE_CONSTANT_BODY_ConstantBufferObjectControlState_start 64 +#define GEN75_3DSTATE_CONSTANT_BODY_MOCS_start 64 +#define GEN7_3DSTATE_CONSTANT_BODY_MOCS_start 64 static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_CONSTANT_BODY_ConstantBufferObjectControlState_start(const struct gen_device_info *devinfo) +_3DSTATE_CONSTANT_BODY_MOCS_start(const struct gen_device_info *devinfo) { switch (devinfo->gen) { case 11: return 0; @@ -17138,27 +17138,29 @@ _3DSTATE_CONSTANT_DS_ConstantBody_start(const struct gen_device_info *devinfo) -/* 3DSTATE_CONSTANT_DS::Constant Buffer Object Control State */ +/* 3DSTATE_CONSTANT_DS::DWord Length */ -#define GEN11_3DSTATE_CONSTANT_DS_ConstantBufferObjectControlState_bits 7 -#define GEN10_3DSTATE_CONSTANT_DS_ConstantBufferObjectControlState_bits 7 -#define GEN9_3DSTATE_CONSTANT_DS_ConstantBufferObjectControlState_bits 7 -#define GEN8_3DSTATE_CONSTANT_DS_ConstantBufferObjectControlState_bits 7 +#define GEN11_3DSTATE_CONSTANT_DS_DWordLength_bits 8 +#define GEN10_3DSTATE_CONSTANT_DS_DWordLength_bits 8 +#define GEN9_3DSTATE_CONSTANT_DS_DWordLength_bits 8 +#define GEN8_3DSTATE_CONSTANT_DS_DWordLength_bits 8 +#define GEN75_3DSTATE_CONSTANT_DS_DWordLength_bits 8 +#define GEN7_3DSTATE_CONSTANT_DS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_CONSTANT_DS_ConstantBufferObjectControlState_bits(const struct gen_device_info *devinfo) +_3DSTATE_CONSTANT_DS_DWordLength_bits(const struct gen_device_info *devinfo) { switch (devinfo->gen) { - case 11: return 7; - case 10: return 7; - case 9: return 7; - case 8: return 7; + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; case 7: if (devinfo->is_haswell) { - return 0; + return 8; } else { - return 0; + return 8; } case 6: return 0; case 5: return 0; @@ -17175,19 +17177,21 @@ _3DSTATE_CONSTANT_DS_ConstantBufferObjectControlState_bits(const struct gen_devi -#define GEN11_3DSTATE_CONSTANT_DS_ConstantBufferObjectControlState_start 8 -#define GEN10_3DSTATE_CONSTANT_DS_ConstantBufferObjectControlState_start 8 -#define GEN9_3DSTATE_CONSTANT_DS_ConstantBufferObjectControlState_start 8 -#define GEN8_3DSTATE_CONSTANT_DS_ConstantBufferObjectControlState_start 8 +#define GEN11_3DSTATE_CONSTANT_DS_DWordLength_start 0 +#define GEN10_3DSTATE_CONSTANT_DS_DWordLength_start 0 +#define GEN9_3DSTATE_CONSTANT_DS_DWordLength_start 0 +#define GEN8_3DSTATE_CONSTANT_DS_DWordLength_start 0 +#define GEN75_3DSTATE_CONSTANT_DS_DWordLength_start 0 +#define GEN7_3DSTATE_CONSTANT_DS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_CONSTANT_DS_ConstantBufferObjectControlState_start(const struct gen_device_info *devinfo) +_3DSTATE_CONSTANT_DS_DWordLength_start(const struct gen_device_info *devinfo) { switch (devinfo->gen) { - case 11: return 8; - case 10: return 8; - case 9: return 8; - case 8: return 8; + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; case 7: if (devinfo->is_haswell) { return 0; @@ -17209,29 +17213,27 @@ _3DSTATE_CONSTANT_DS_ConstantBufferObjectControlState_start(const struct gen_dev -/* 3DSTATE_CONSTANT_DS::DWord Length */ +/* 3DSTATE_CONSTANT_DS::MOCS */ -#define GEN11_3DSTATE_CONSTANT_DS_DWordLength_bits 8 -#define GEN10_3DSTATE_CONSTANT_DS_DWordLength_bits 8 -#define GEN9_3DSTATE_CONSTANT_DS_DWordLength_bits 8 -#define GEN8_3DSTATE_CONSTANT_DS_DWordLength_bits 8 -#define GEN75_3DSTATE_CONSTANT_DS_DWordLength_bits 8 -#define GEN7_3DSTATE_CONSTANT_DS_DWordLength_bits 8 +#define GEN11_3DSTATE_CONSTANT_DS_MOCS_bits 7 +#define GEN10_3DSTATE_CONSTANT_DS_MOCS_bits 7 +#define GEN9_3DSTATE_CONSTANT_DS_MOCS_bits 7 +#define GEN8_3DSTATE_CONSTANT_DS_MOCS_bits 7 static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_CONSTANT_DS_DWordLength_bits(const struct gen_device_info *devinfo) +_3DSTATE_CONSTANT_DS_MOCS_bits(const struct gen_device_info *devinfo) { switch (devinfo->gen) { - case 11: return 8; - case 10: return 8; - case 9: return 8; - case 8: return 8; + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; case 7: if (devinfo->is_haswell) { - return 8; + return 0; } else { - return 8; + return 0; } case 6: return 0; case 5: return 0; @@ -17248,21 +17250,19 @@ _3DSTATE_CONSTANT_DS_DWordLength_bits(const struct gen_device_info *devinfo) -#define GEN11_3DSTATE_CONSTANT_DS_DWordLength_start 0 -#define GEN10_3DSTATE_CONSTANT_DS_DWordLength_start 0 -#define GEN9_3DSTATE_CONSTANT_DS_DWordLength_start 0 -#define GEN8_3DSTATE_CONSTANT_DS_DWordLength_start 0 -#define GEN75_3DSTATE_CONSTANT_DS_DWordLength_start 0 -#define GEN7_3DSTATE_CONSTANT_DS_DWordLength_start 0 +#define GEN11_3DSTATE_CONSTANT_DS_MOCS_start 8 +#define GEN10_3DSTATE_CONSTANT_DS_MOCS_start 8 +#define GEN9_3DSTATE_CONSTANT_DS_MOCS_start 8 +#define GEN8_3DSTATE_CONSTANT_DS_MOCS_start 8 static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_CONSTANT_DS_DWordLength_start(const struct gen_device_info *devinfo) +_3DSTATE_CONSTANT_DS_MOCS_start(const struct gen_device_info *devinfo) { switch (devinfo->gen) { - case 11: return 0; - case 10: return 0; - case 9: return 0; - case 8: return 0; + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; case 7: if (devinfo->is_haswell) { return 0; @@ -17969,30 +17969,32 @@ _3DSTATE_CONSTANT_GS_ConstantBody_start(const struct gen_device_info *devinfo) -/* 3DSTATE_CONSTANT_GS::Constant Buffer Object Control State */ +/* 3DSTATE_CONSTANT_GS::DWord Length */ -#define GEN11_3DSTATE_CONSTANT_GS_ConstantBufferObjectControlState_bits 7 -#define GEN10_3DSTATE_CONSTANT_GS_ConstantBufferObjectControlState_bits 7 -#define GEN9_3DSTATE_CONSTANT_GS_ConstantBufferObjectControlState_bits 7 -#define GEN8_3DSTATE_CONSTANT_GS_ConstantBufferObjectControlState_bits 7 -#define GEN6_3DSTATE_CONSTANT_GS_ConstantBufferObjectControlState_bits 4 +#define GEN11_3DSTATE_CONSTANT_GS_DWordLength_bits 8 +#define GEN10_3DSTATE_CONSTANT_GS_DWordLength_bits 8 +#define GEN9_3DSTATE_CONSTANT_GS_DWordLength_bits 8 +#define GEN8_3DSTATE_CONSTANT_GS_DWordLength_bits 8 +#define GEN75_3DSTATE_CONSTANT_GS_DWordLength_bits 8 +#define GEN7_3DSTATE_CONSTANT_GS_DWordLength_bits 8 +#define GEN6_3DSTATE_CONSTANT_GS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_CONSTANT_GS_ConstantBufferObjectControlState_bits(const struct gen_device_info *devinfo) +_3DSTATE_CONSTANT_GS_DWordLength_bits(const struct gen_device_info *devinfo) { switch (devinfo->gen) { - case 11: return 7; - case 10: return 7; - case 9: return 7; - case 8: return 7; + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; case 7: if (devinfo->is_haswell) { - return 0; + return 8; } else { - return 0; + return 8; } - case 6: return 4; + case 6: return 8; case 5: return 0; case 4: if (devinfo->is_g4x) { @@ -18007,27 +18009,29 @@ _3DSTATE_CONSTANT_GS_ConstantBufferObjectControlState_bits(const struct gen_devi -#define GEN11_3DSTATE_CONSTANT_GS_ConstantBufferObjectControlState_start 8 -#define GEN10_3DSTATE_CONSTANT_GS_ConstantBufferObjectControlState_start 8 -#define GEN9_3DSTATE_CONSTANT_GS_ConstantBufferObjectControlState_start 8 -#define GEN8_3DSTATE_CONSTANT_GS_ConstantBufferObjectControlState_start 8 -#define GEN6_3DSTATE_CONSTANT_GS_ConstantBufferObjectControlState_start 8 +#define GEN11_3DSTATE_CONSTANT_GS_DWordLength_start 0 +#define GEN10_3DSTATE_CONSTANT_GS_DWordLength_start 0 +#define GEN9_3DSTATE_CONSTANT_GS_DWordLength_start 0 +#define GEN8_3DSTATE_CONSTANT_GS_DWordLength_start 0 +#define GEN75_3DSTATE_CONSTANT_GS_DWordLength_start 0 +#define GEN7_3DSTATE_CONSTANT_GS_DWordLength_start 0 +#define GEN6_3DSTATE_CONSTANT_GS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_CONSTANT_GS_ConstantBufferObjectControlState_start(const struct gen_device_info *devinfo) +_3DSTATE_CONSTANT_GS_DWordLength_start(const struct gen_device_info *devinfo) { switch (devinfo->gen) { - case 11: return 8; - case 10: return 8; - case 9: return 8; - case 8: return 8; + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; case 7: if (devinfo->is_haswell) { return 0; } else { return 0; } - case 6: return 8; + case 6: return 0; case 5: return 0; case 4: if (devinfo->is_g4x) { @@ -18042,32 +18046,30 @@ _3DSTATE_CONSTANT_GS_ConstantBufferObjectControlState_start(const struct gen_dev -/* 3DSTATE_CONSTANT_GS::DWord Length */ +/* 3DSTATE_CONSTANT_GS::MOCS */ -#define GEN11_3DSTATE_CONSTANT_GS_DWordLength_bits 8 -#define GEN10_3DSTATE_CONSTANT_GS_DWordLength_bits 8 -#define GEN9_3DSTATE_CONSTANT_GS_DWordLength_bits 8 -#define GEN8_3DSTATE_CONSTANT_GS_DWordLength_bits 8 -#define GEN75_3DSTATE_CONSTANT_GS_DWordLength_bits 8 -#define GEN7_3DSTATE_CONSTANT_GS_DWordLength_bits 8 -#define GEN6_3DSTATE_CONSTANT_GS_DWordLength_bits 8 +#define GEN11_3DSTATE_CONSTANT_GS_MOCS_bits 7 +#define GEN10_3DSTATE_CONSTANT_GS_MOCS_bits 7 +#define GEN9_3DSTATE_CONSTANT_GS_MOCS_bits 7 +#define GEN8_3DSTATE_CONSTANT_GS_MOCS_bits 7 +#define GEN6_3DSTATE_CONSTANT_GS_MOCS_bits 4 static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_CONSTANT_GS_DWordLength_bits(const struct gen_device_info *devinfo) +_3DSTATE_CONSTANT_GS_MOCS_bits(const struct gen_device_info *devinfo) { switch (devinfo->gen) { - case 11: return 8; - case 10: return 8; - case 9: return 8; - case 8: return 8; + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; case 7: if (devinfo->is_haswell) { - return 8; + return 0; } else { - return 8; + return 0; } - case 6: return 8; + case 6: return 4; case 5: return 0; case 4: if (devinfo->is_g4x) { @@ -18082,29 +18084,27 @@ _3DSTATE_CONSTANT_GS_DWordLength_bits(const struct gen_device_info *devinfo) -#define GEN11_3DSTATE_CONSTANT_GS_DWordLength_start 0 -#define GEN10_3DSTATE_CONSTANT_GS_DWordLength_start 0 -#define GEN9_3DSTATE_CONSTANT_GS_DWordLength_start 0 -#define GEN8_3DSTATE_CONSTANT_GS_DWordLength_start 0 -#define GEN75_3DSTATE_CONSTANT_GS_DWordLength_start 0 -#define GEN7_3DSTATE_CONSTANT_GS_DWordLength_start 0 -#define GEN6_3DSTATE_CONSTANT_GS_DWordLength_start 0 +#define GEN11_3DSTATE_CONSTANT_GS_MOCS_start 8 +#define GEN10_3DSTATE_CONSTANT_GS_MOCS_start 8 +#define GEN9_3DSTATE_CONSTANT_GS_MOCS_start 8 +#define GEN8_3DSTATE_CONSTANT_GS_MOCS_start 8 +#define GEN6_3DSTATE_CONSTANT_GS_MOCS_start 8 static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_CONSTANT_GS_DWordLength_start(const struct gen_device_info *devinfo) +_3DSTATE_CONSTANT_GS_MOCS_start(const struct gen_device_info *devinfo) { switch (devinfo->gen) { - case 11: return 0; - case 10: return 0; - case 9: return 0; - case 8: return 0; + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; case 7: if (devinfo->is_haswell) { return 0; } else { return 0; } - case 6: return 0; + case 6: return 8; case 5: return 0; case 4: if (devinfo->is_g4x) { @@ -18533,27 +18533,29 @@ _3DSTATE_CONSTANT_HS_ConstantBody_start(const struct gen_device_info *devinfo) -/* 3DSTATE_CONSTANT_HS::Constant Buffer Object Control State */ +/* 3DSTATE_CONSTANT_HS::DWord Length */ -#define GEN11_3DSTATE_CONSTANT_HS_ConstantBufferObjectControlState_bits 7 -#define GEN10_3DSTATE_CONSTANT_HS_ConstantBufferObjectControlState_bits 7 -#define GEN9_3DSTATE_CONSTANT_HS_ConstantBufferObjectControlState_bits 7 -#define GEN8_3DSTATE_CONSTANT_HS_ConstantBufferObjectControlState_bits 7 +#define GEN11_3DSTATE_CONSTANT_HS_DWordLength_bits 8 +#define GEN10_3DSTATE_CONSTANT_HS_DWordLength_bits 8 +#define GEN9_3DSTATE_CONSTANT_HS_DWordLength_bits 8 +#define GEN8_3DSTATE_CONSTANT_HS_DWordLength_bits 8 +#define GEN75_3DSTATE_CONSTANT_HS_DWordLength_bits 8 +#define GEN7_3DSTATE_CONSTANT_HS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_CONSTANT_HS_ConstantBufferObjectControlState_bits(const struct gen_device_info *devinfo) +_3DSTATE_CONSTANT_HS_DWordLength_bits(const struct gen_device_info *devinfo) { switch (devinfo->gen) { - case 11: return 7; - case 10: return 7; - case 9: return 7; - case 8: return 7; + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; case 7: if (devinfo->is_haswell) { - return 0; + return 8; } else { - return 0; + return 8; } case 6: return 0; case 5: return 0; @@ -18570,19 +18572,21 @@ _3DSTATE_CONSTANT_HS_ConstantBufferObjectControlState_bits(const struct gen_devi -#define GEN11_3DSTATE_CONSTANT_HS_ConstantBufferObjectControlState_start 8 -#define GEN10_3DSTATE_CONSTANT_HS_ConstantBufferObjectControlState_start 8 -#define GEN9_3DSTATE_CONSTANT_HS_ConstantBufferObjectControlState_start 8 -#define GEN8_3DSTATE_CONSTANT_HS_ConstantBufferObjectControlState_start 8 +#define GEN11_3DSTATE_CONSTANT_HS_DWordLength_start 0 +#define GEN10_3DSTATE_CONSTANT_HS_DWordLength_start 0 +#define GEN9_3DSTATE_CONSTANT_HS_DWordLength_start 0 +#define GEN8_3DSTATE_CONSTANT_HS_DWordLength_start 0 +#define GEN75_3DSTATE_CONSTANT_HS_DWordLength_start 0 +#define GEN7_3DSTATE_CONSTANT_HS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_CONSTANT_HS_ConstantBufferObjectControlState_start(const struct gen_device_info *devinfo) +_3DSTATE_CONSTANT_HS_DWordLength_start(const struct gen_device_info *devinfo) { switch (devinfo->gen) { - case 11: return 8; - case 10: return 8; - case 9: return 8; - case 8: return 8; + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; case 7: if (devinfo->is_haswell) { return 0; @@ -18604,29 +18608,27 @@ _3DSTATE_CONSTANT_HS_ConstantBufferObjectControlState_start(const struct gen_dev -/* 3DSTATE_CONSTANT_HS::DWord Length */ +/* 3DSTATE_CONSTANT_HS::MOCS */ -#define GEN11_3DSTATE_CONSTANT_HS_DWordLength_bits 8 -#define GEN10_3DSTATE_CONSTANT_HS_DWordLength_bits 8 -#define GEN9_3DSTATE_CONSTANT_HS_DWordLength_bits 8 -#define GEN8_3DSTATE_CONSTANT_HS_DWordLength_bits 8 -#define GEN75_3DSTATE_CONSTANT_HS_DWordLength_bits 8 -#define GEN7_3DSTATE_CONSTANT_HS_DWordLength_bits 8 +#define GEN11_3DSTATE_CONSTANT_HS_MOCS_bits 7 +#define GEN10_3DSTATE_CONSTANT_HS_MOCS_bits 7 +#define GEN9_3DSTATE_CONSTANT_HS_MOCS_bits 7 +#define GEN8_3DSTATE_CONSTANT_HS_MOCS_bits 7 static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_CONSTANT_HS_DWordLength_bits(const struct gen_device_info *devinfo) +_3DSTATE_CONSTANT_HS_MOCS_bits(const struct gen_device_info *devinfo) { switch (devinfo->gen) { - case 11: return 8; - case 10: return 8; - case 9: return 8; - case 8: return 8; + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; case 7: if (devinfo->is_haswell) { - return 8; + return 0; } else { - return 8; + return 0; } case 6: return 0; case 5: return 0; @@ -18643,21 +18645,19 @@ _3DSTATE_CONSTANT_HS_DWordLength_bits(const struct gen_device_info *devinfo) -#define GEN11_3DSTATE_CONSTANT_HS_DWordLength_start 0 -#define GEN10_3DSTATE_CONSTANT_HS_DWordLength_start 0 -#define GEN9_3DSTATE_CONSTANT_HS_DWordLength_start 0 -#define GEN8_3DSTATE_CONSTANT_HS_DWordLength_start 0 -#define GEN75_3DSTATE_CONSTANT_HS_DWordLength_start 0 -#define GEN7_3DSTATE_CONSTANT_HS_DWordLength_start 0 +#define GEN11_3DSTATE_CONSTANT_HS_MOCS_start 8 +#define GEN10_3DSTATE_CONSTANT_HS_MOCS_start 8 +#define GEN9_3DSTATE_CONSTANT_HS_MOCS_start 8 +#define GEN8_3DSTATE_CONSTANT_HS_MOCS_start 8 static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_CONSTANT_HS_DWordLength_start(const struct gen_device_info *devinfo) +_3DSTATE_CONSTANT_HS_MOCS_start(const struct gen_device_info *devinfo) { switch (devinfo->gen) { - case 11: return 0; - case 10: return 0; - case 9: return 0; - case 8: return 0; + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; case 7: if (devinfo->is_haswell) { return 0; @@ -19364,30 +19364,32 @@ _3DSTATE_CONSTANT_PS_ConstantBody_start(const struct gen_device_info *devinfo) -/* 3DSTATE_CONSTANT_PS::Constant Buffer Object Control State */ +/* 3DSTATE_CONSTANT_PS::DWord Length */ -#define GEN11_3DSTATE_CONSTANT_PS_ConstantBufferObjectControlState_bits 7 -#define GEN10_3DSTATE_CONSTANT_PS_ConstantBufferObjectControlState_bits 7 -#define GEN9_3DSTATE_CONSTANT_PS_ConstantBufferObjectControlState_bits 7 -#define GEN8_3DSTATE_CONSTANT_PS_ConstantBufferObjectControlState_bits 7 -#define GEN6_3DSTATE_CONSTANT_PS_ConstantBufferObjectControlState_bits 4 +#define GEN11_3DSTATE_CONSTANT_PS_DWordLength_bits 8 +#define GEN10_3DSTATE_CONSTANT_PS_DWordLength_bits 8 +#define GEN9_3DSTATE_CONSTANT_PS_DWordLength_bits 8 +#define GEN8_3DSTATE_CONSTANT_PS_DWordLength_bits 8 +#define GEN75_3DSTATE_CONSTANT_PS_DWordLength_bits 8 +#define GEN7_3DSTATE_CONSTANT_PS_DWordLength_bits 8 +#define GEN6_3DSTATE_CONSTANT_PS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_CONSTANT_PS_ConstantBufferObjectControlState_bits(const struct gen_device_info *devinfo) +_3DSTATE_CONSTANT_PS_DWordLength_bits(const struct gen_device_info *devinfo) { switch (devinfo->gen) { - case 11: return 7; - case 10: return 7; - case 9: return 7; - case 8: return 7; + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; case 7: if (devinfo->is_haswell) { - return 0; + return 8; } else { - return 0; + return 8; } - case 6: return 4; + case 6: return 8; case 5: return 0; case 4: if (devinfo->is_g4x) { @@ -19402,27 +19404,29 @@ _3DSTATE_CONSTANT_PS_ConstantBufferObjectControlState_bits(const struct gen_devi -#define GEN11_3DSTATE_CONSTANT_PS_ConstantBufferObjectControlState_start 8 -#define GEN10_3DSTATE_CONSTANT_PS_ConstantBufferObjectControlState_start 8 -#define GEN9_3DSTATE_CONSTANT_PS_ConstantBufferObjectControlState_start 8 -#define GEN8_3DSTATE_CONSTANT_PS_ConstantBufferObjectControlState_start 8 -#define GEN6_3DSTATE_CONSTANT_PS_ConstantBufferObjectControlState_start 8 +#define GEN11_3DSTATE_CONSTANT_PS_DWordLength_start 0 +#define GEN10_3DSTATE_CONSTANT_PS_DWordLength_start 0 +#define GEN9_3DSTATE_CONSTANT_PS_DWordLength_start 0 +#define GEN8_3DSTATE_CONSTANT_PS_DWordLength_start 0 +#define GEN75_3DSTATE_CONSTANT_PS_DWordLength_start 0 +#define GEN7_3DSTATE_CONSTANT_PS_DWordLength_start 0 +#define GEN6_3DSTATE_CONSTANT_PS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_CONSTANT_PS_ConstantBufferObjectControlState_start(const struct gen_device_info *devinfo) +_3DSTATE_CONSTANT_PS_DWordLength_start(const struct gen_device_info *devinfo) { switch (devinfo->gen) { - case 11: return 8; - case 10: return 8; - case 9: return 8; - case 8: return 8; + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; case 7: if (devinfo->is_haswell) { return 0; } else { return 0; } - case 6: return 8; + case 6: return 0; case 5: return 0; case 4: if (devinfo->is_g4x) { @@ -19437,32 +19441,27 @@ _3DSTATE_CONSTANT_PS_ConstantBufferObjectControlState_start(const struct gen_dev -/* 3DSTATE_CONSTANT_PS::DWord Length */ +/* 3DSTATE_CONSTANT_PS::Disable Gather at Set Shader Hint */ -#define GEN11_3DSTATE_CONSTANT_PS_DWordLength_bits 8 -#define GEN10_3DSTATE_CONSTANT_PS_DWordLength_bits 8 -#define GEN9_3DSTATE_CONSTANT_PS_DWordLength_bits 8 -#define GEN8_3DSTATE_CONSTANT_PS_DWordLength_bits 8 -#define GEN75_3DSTATE_CONSTANT_PS_DWordLength_bits 8 -#define GEN7_3DSTATE_CONSTANT_PS_DWordLength_bits 8 -#define GEN6_3DSTATE_CONSTANT_PS_DWordLength_bits 8 +#define GEN11_3DSTATE_CONSTANT_PS_DisableGatheratSetShaderHint_bits 1 +#define GEN10_3DSTATE_CONSTANT_PS_DisableGatheratSetShaderHint_bits 1 static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_CONSTANT_PS_DWordLength_bits(const struct gen_device_info *devinfo) +_3DSTATE_CONSTANT_PS_DisableGatheratSetShaderHint_bits(const struct gen_device_info *devinfo) { switch (devinfo->gen) { - case 11: return 8; - case 10: return 8; - case 9: return 8; - case 8: return 8; + case 11: return 1; + case 10: return 1; + case 9: return 0; + case 8: return 0; case 7: if (devinfo->is_haswell) { - return 8; + return 0; } else { - return 8; + return 0; } - case 6: return 8; + case 6: return 0; case 5: return 0; case 4: if (devinfo->is_g4x) { @@ -19477,20 +19476,15 @@ _3DSTATE_CONSTANT_PS_DWordLength_bits(const struct gen_device_info *devinfo) -#define GEN11_3DSTATE_CONSTANT_PS_DWordLength_start 0 -#define GEN10_3DSTATE_CONSTANT_PS_DWordLength_start 0 -#define GEN9_3DSTATE_CONSTANT_PS_DWordLength_start 0 -#define GEN8_3DSTATE_CONSTANT_PS_DWordLength_start 0 -#define GEN75_3DSTATE_CONSTANT_PS_DWordLength_start 0 -#define GEN7_3DSTATE_CONSTANT_PS_DWordLength_start 0 -#define GEN6_3DSTATE_CONSTANT_PS_DWordLength_start 0 +#define GEN11_3DSTATE_CONSTANT_PS_DisableGatheratSetShaderHint_start 15 +#define GEN10_3DSTATE_CONSTANT_PS_DisableGatheratSetShaderHint_start 15 static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_CONSTANT_PS_DWordLength_start(const struct gen_device_info *devinfo) +_3DSTATE_CONSTANT_PS_DisableGatheratSetShaderHint_start(const struct gen_device_info *devinfo) { switch (devinfo->gen) { - case 11: return 0; - case 10: return 0; + case 11: return 15; + case 10: return 15; case 9: return 0; case 8: return 0; case 7: @@ -19514,27 +19508,30 @@ _3DSTATE_CONSTANT_PS_DWordLength_start(const struct gen_device_info *devinfo) -/* 3DSTATE_CONSTANT_PS::Disable Gather at Set Shader Hint */ +/* 3DSTATE_CONSTANT_PS::MOCS */ -#define GEN11_3DSTATE_CONSTANT_PS_DisableGatheratSetShaderHint_bits 1 -#define GEN10_3DSTATE_CONSTANT_PS_DisableGatheratSetShaderHint_bits 1 +#define GEN11_3DSTATE_CONSTANT_PS_MOCS_bits 7 +#define GEN10_3DSTATE_CONSTANT_PS_MOCS_bits 7 +#define GEN9_3DSTATE_CONSTANT_PS_MOCS_bits 7 +#define GEN8_3DSTATE_CONSTANT_PS_MOCS_bits 7 +#define GEN6_3DSTATE_CONSTANT_PS_MOCS_bits 4 static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_CONSTANT_PS_DisableGatheratSetShaderHint_bits(const struct gen_device_info *devinfo) +_3DSTATE_CONSTANT_PS_MOCS_bits(const struct gen_device_info *devinfo) { switch (devinfo->gen) { - case 11: return 1; - case 10: return 1; - case 9: return 0; - case 8: return 0; + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; case 7: if (devinfo->is_haswell) { return 0; } else { return 0; } - case 6: return 0; + case 6: return 4; case 5: return 0; case 4: if (devinfo->is_g4x) { @@ -19549,24 +19546,27 @@ _3DSTATE_CONSTANT_PS_DisableGatheratSetShaderHint_bits(const struct gen_device_i -#define GEN11_3DSTATE_CONSTANT_PS_DisableGatheratSetShaderHint_start 15 -#define GEN10_3DSTATE_CONSTANT_PS_DisableGatheratSetShaderHint_start 15 +#define GEN11_3DSTATE_CONSTANT_PS_MOCS_start 8 +#define GEN10_3DSTATE_CONSTANT_PS_MOCS_start 8 +#define GEN9_3DSTATE_CONSTANT_PS_MOCS_start 8 +#define GEN8_3DSTATE_CONSTANT_PS_MOCS_start 8 +#define GEN6_3DSTATE_CONSTANT_PS_MOCS_start 8 static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_CONSTANT_PS_DisableGatheratSetShaderHint_start(const struct gen_device_info *devinfo) +_3DSTATE_CONSTANT_PS_MOCS_start(const struct gen_device_info *devinfo) { switch (devinfo->gen) { - case 11: return 15; - case 10: return 15; - case 9: return 0; - case 8: return 0; + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; case 7: if (devinfo->is_haswell) { return 0; } else { return 0; } - case 6: return 0; + case 6: return 8; case 5: return 0; case 4: if (devinfo->is_g4x) { @@ -20266,30 +20266,32 @@ _3DSTATE_CONSTANT_VS_ConstantBody_start(const struct gen_device_info *devinfo) -/* 3DSTATE_CONSTANT_VS::Constant Buffer Object Control State */ +/* 3DSTATE_CONSTANT_VS::DWord Length */ -#define GEN11_3DSTATE_CONSTANT_VS_ConstantBufferObjectControlState_bits 7 -#define GEN10_3DSTATE_CONSTANT_VS_ConstantBufferObjectControlState_bits 7 -#define GEN9_3DSTATE_CONSTANT_VS_ConstantBufferObjectControlState_bits 7 -#define GEN8_3DSTATE_CONSTANT_VS_ConstantBufferObjectControlState_bits 7 -#define GEN6_3DSTATE_CONSTANT_VS_ConstantBufferObjectControlState_bits 4 +#define GEN11_3DSTATE_CONSTANT_VS_DWordLength_bits 8 +#define GEN10_3DSTATE_CONSTANT_VS_DWordLength_bits 8 +#define GEN9_3DSTATE_CONSTANT_VS_DWordLength_bits 8 +#define GEN8_3DSTATE_CONSTANT_VS_DWordLength_bits 8 +#define GEN75_3DSTATE_CONSTANT_VS_DWordLength_bits 8 +#define GEN7_3DSTATE_CONSTANT_VS_DWordLength_bits 8 +#define GEN6_3DSTATE_CONSTANT_VS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_CONSTANT_VS_ConstantBufferObjectControlState_bits(const struct gen_device_info *devinfo) +_3DSTATE_CONSTANT_VS_DWordLength_bits(const struct gen_device_info *devinfo) { switch (devinfo->gen) { - case 11: return 7; - case 10: return 7; - case 9: return 7; - case 8: return 7; + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; case 7: if (devinfo->is_haswell) { - return 0; + return 8; } else { - return 0; + return 8; } - case 6: return 4; + case 6: return 8; case 5: return 0; case 4: if (devinfo->is_g4x) { @@ -20304,27 +20306,29 @@ _3DSTATE_CONSTANT_VS_ConstantBufferObjectControlState_bits(const struct gen_devi -#define GEN11_3DSTATE_CONSTANT_VS_ConstantBufferObjectControlState_start 8 -#define GEN10_3DSTATE_CONSTANT_VS_ConstantBufferObjectControlState_start 8 -#define GEN9_3DSTATE_CONSTANT_VS_ConstantBufferObjectControlState_start 8 -#define GEN8_3DSTATE_CONSTANT_VS_ConstantBufferObjectControlState_start 8 -#define GEN6_3DSTATE_CONSTANT_VS_ConstantBufferObjectControlState_start 8 +#define GEN11_3DSTATE_CONSTANT_VS_DWordLength_start 0 +#define GEN10_3DSTATE_CONSTANT_VS_DWordLength_start 0 +#define GEN9_3DSTATE_CONSTANT_VS_DWordLength_start 0 +#define GEN8_3DSTATE_CONSTANT_VS_DWordLength_start 0 +#define GEN75_3DSTATE_CONSTANT_VS_DWordLength_start 0 +#define GEN7_3DSTATE_CONSTANT_VS_DWordLength_start 0 +#define GEN6_3DSTATE_CONSTANT_VS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_CONSTANT_VS_ConstantBufferObjectControlState_start(const struct gen_device_info *devinfo) +_3DSTATE_CONSTANT_VS_DWordLength_start(const struct gen_device_info *devinfo) { switch (devinfo->gen) { - case 11: return 8; - case 10: return 8; - case 9: return 8; - case 8: return 8; + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; case 7: if (devinfo->is_haswell) { return 0; } else { return 0; } - case 6: return 8; + case 6: return 0; case 5: return 0; case 4: if (devinfo->is_g4x) { @@ -20339,32 +20343,30 @@ _3DSTATE_CONSTANT_VS_ConstantBufferObjectControlState_start(const struct gen_dev -/* 3DSTATE_CONSTANT_VS::DWord Length */ +/* 3DSTATE_CONSTANT_VS::MOCS */ -#define GEN11_3DSTATE_CONSTANT_VS_DWordLength_bits 8 -#define GEN10_3DSTATE_CONSTANT_VS_DWordLength_bits 8 -#define GEN9_3DSTATE_CONSTANT_VS_DWordLength_bits 8 -#define GEN8_3DSTATE_CONSTANT_VS_DWordLength_bits 8 -#define GEN75_3DSTATE_CONSTANT_VS_DWordLength_bits 8 -#define GEN7_3DSTATE_CONSTANT_VS_DWordLength_bits 8 -#define GEN6_3DSTATE_CONSTANT_VS_DWordLength_bits 8 +#define GEN11_3DSTATE_CONSTANT_VS_MOCS_bits 7 +#define GEN10_3DSTATE_CONSTANT_VS_MOCS_bits 7 +#define GEN9_3DSTATE_CONSTANT_VS_MOCS_bits 7 +#define GEN8_3DSTATE_CONSTANT_VS_MOCS_bits 7 +#define GEN6_3DSTATE_CONSTANT_VS_MOCS_bits 4 static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_CONSTANT_VS_DWordLength_bits(const struct gen_device_info *devinfo) +_3DSTATE_CONSTANT_VS_MOCS_bits(const struct gen_device_info *devinfo) { switch (devinfo->gen) { - case 11: return 8; - case 10: return 8; - case 9: return 8; - case 8: return 8; + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; case 7: if (devinfo->is_haswell) { - return 8; + return 0; } else { - return 8; + return 0; } - case 6: return 8; + case 6: return 4; case 5: return 0; case 4: if (devinfo->is_g4x) { @@ -20379,29 +20381,27 @@ _3DSTATE_CONSTANT_VS_DWordLength_bits(const struct gen_device_info *devinfo) -#define GEN11_3DSTATE_CONSTANT_VS_DWordLength_start 0 -#define GEN10_3DSTATE_CONSTANT_VS_DWordLength_start 0 -#define GEN9_3DSTATE_CONSTANT_VS_DWordLength_start 0 -#define GEN8_3DSTATE_CONSTANT_VS_DWordLength_start 0 -#define GEN75_3DSTATE_CONSTANT_VS_DWordLength_start 0 -#define GEN7_3DSTATE_CONSTANT_VS_DWordLength_start 0 -#define GEN6_3DSTATE_CONSTANT_VS_DWordLength_start 0 +#define GEN11_3DSTATE_CONSTANT_VS_MOCS_start 8 +#define GEN10_3DSTATE_CONSTANT_VS_MOCS_start 8 +#define GEN9_3DSTATE_CONSTANT_VS_MOCS_start 8 +#define GEN8_3DSTATE_CONSTANT_VS_MOCS_start 8 +#define GEN6_3DSTATE_CONSTANT_VS_MOCS_start 8 static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_CONSTANT_VS_DWordLength_start(const struct gen_device_info *devinfo) +_3DSTATE_CONSTANT_VS_MOCS_start(const struct gen_device_info *devinfo) { switch (devinfo->gen) { - case 11: return 0; - case 10: return 0; - case 9: return 0; - case 8: return 0; + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; case 7: if (devinfo->is_haswell) { return 0; } else { return 0; } - case 6: return 0; + case 6: return 8; case 5: return 0; case 4: if (devinfo->is_g4x) { @@ -21024,160 +21024,6 @@ _3DSTATE_DEPTH_BUFFER_DepthBufferCoordinateOffsetDisable_start(const struct gen_ -/* 3DSTATE_DEPTH_BUFFER::Depth Buffer MOCS */ - - -#define GEN11_3DSTATE_DEPTH_BUFFER_DepthBufferMOCS_bits 7 -#define GEN10_3DSTATE_DEPTH_BUFFER_DepthBufferMOCS_bits 7 -#define GEN9_3DSTATE_DEPTH_BUFFER_DepthBufferMOCS_bits 7 -#define GEN8_3DSTATE_DEPTH_BUFFER_DepthBufferMOCS_bits 7 -#define GEN75_3DSTATE_DEPTH_BUFFER_DepthBufferMOCS_bits 4 -#define GEN7_3DSTATE_DEPTH_BUFFER_DepthBufferMOCS_bits 4 -#define GEN6_3DSTATE_DEPTH_BUFFER_DepthBufferMOCS_bits 5 - -static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_DEPTH_BUFFER_DepthBufferMOCS_bits(const struct gen_device_info *devinfo) -{ - switch (devinfo->gen) { - case 11: return 7; - case 10: return 7; - case 9: return 7; - case 8: return 7; - case 7: - if (devinfo->is_haswell) { - return 4; - } else { - return 4; - } - case 6: return 5; - case 5: return 0; - case 4: - if (devinfo->is_g4x) { - return 0; - } else { - return 0; - } - default: - unreachable("Invalid hardware generation"); - } -} - - - -#define GEN11_3DSTATE_DEPTH_BUFFER_DepthBufferMOCS_start 160 -#define GEN10_3DSTATE_DEPTH_BUFFER_DepthBufferMOCS_start 160 -#define GEN9_3DSTATE_DEPTH_BUFFER_DepthBufferMOCS_start 160 -#define GEN8_3DSTATE_DEPTH_BUFFER_DepthBufferMOCS_start 160 -#define GEN75_3DSTATE_DEPTH_BUFFER_DepthBufferMOCS_start 128 -#define GEN7_3DSTATE_DEPTH_BUFFER_DepthBufferMOCS_start 128 -#define GEN6_3DSTATE_DEPTH_BUFFER_DepthBufferMOCS_start 219 - -static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_DEPTH_BUFFER_DepthBufferMOCS_start(const struct gen_device_info *devinfo) -{ - switch (devinfo->gen) { - case 11: return 160; - case 10: return 160; - case 9: return 160; - case 8: return 160; - case 7: - if (devinfo->is_haswell) { - return 128; - } else { - return 128; - } - case 6: return 219; - case 5: return 0; - case 4: - if (devinfo->is_g4x) { - return 0; - } else { - return 0; - } - default: - unreachable("Invalid hardware generation"); - } -} - - - -/* 3DSTATE_DEPTH_BUFFER::Depth Buffer Object Control State */ - - -#define GEN11_3DSTATE_DEPTH_BUFFER_DepthBufferObjectControlState_bits 7 -#define GEN10_3DSTATE_DEPTH_BUFFER_DepthBufferObjectControlState_bits 7 -#define GEN9_3DSTATE_DEPTH_BUFFER_DepthBufferObjectControlState_bits 7 -#define GEN8_3DSTATE_DEPTH_BUFFER_DepthBufferObjectControlState_bits 7 -#define GEN75_3DSTATE_DEPTH_BUFFER_DepthBufferObjectControlState_bits 4 -#define GEN7_3DSTATE_DEPTH_BUFFER_DepthBufferObjectControlState_bits 4 -#define GEN6_3DSTATE_DEPTH_BUFFER_DepthBufferObjectControlState_bits 5 - -static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_DEPTH_BUFFER_DepthBufferObjectControlState_bits(const struct gen_device_info *devinfo) -{ - switch (devinfo->gen) { - case 11: return 7; - case 10: return 7; - case 9: return 7; - case 8: return 7; - case 7: - if (devinfo->is_haswell) { - return 4; - } else { - return 4; - } - case 6: return 5; - case 5: return 0; - case 4: - if (devinfo->is_g4x) { - return 0; - } else { - return 0; - } - default: - unreachable("Invalid hardware generation"); - } -} - - - -#define GEN11_3DSTATE_DEPTH_BUFFER_DepthBufferObjectControlState_start 160 -#define GEN10_3DSTATE_DEPTH_BUFFER_DepthBufferObjectControlState_start 160 -#define GEN9_3DSTATE_DEPTH_BUFFER_DepthBufferObjectControlState_start 160 -#define GEN8_3DSTATE_DEPTH_BUFFER_DepthBufferObjectControlState_start 160 -#define GEN75_3DSTATE_DEPTH_BUFFER_DepthBufferObjectControlState_start 128 -#define GEN7_3DSTATE_DEPTH_BUFFER_DepthBufferObjectControlState_start 128 -#define GEN6_3DSTATE_DEPTH_BUFFER_DepthBufferObjectControlState_start 219 - -static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_DEPTH_BUFFER_DepthBufferObjectControlState_start(const struct gen_device_info *devinfo) -{ - switch (devinfo->gen) { - case 11: return 160; - case 10: return 160; - case 9: return 160; - case 8: return 160; - case 7: - if (devinfo->is_haswell) { - return 128; - } else { - return 128; - } - case 6: return 219; - case 5: return 0; - case 4: - if (devinfo->is_g4x) { - return 0; - } else { - return 0; - } - default: - unreachable("Invalid hardware generation"); - } -} - - - /* 3DSTATE_DEPTH_BUFFER::Depth Coordinate Offset X */ @@ -21715,6 +21561,83 @@ _3DSTATE_DEPTH_BUFFER_MIPMapLayoutMode_start(const struct gen_device_info *devin +/* 3DSTATE_DEPTH_BUFFER::MOCS */ + + +#define GEN11_3DSTATE_DEPTH_BUFFER_MOCS_bits 7 +#define GEN10_3DSTATE_DEPTH_BUFFER_MOCS_bits 7 +#define GEN9_3DSTATE_DEPTH_BUFFER_MOCS_bits 7 +#define GEN8_3DSTATE_DEPTH_BUFFER_MOCS_bits 7 +#define GEN75_3DSTATE_DEPTH_BUFFER_MOCS_bits 4 +#define GEN7_3DSTATE_DEPTH_BUFFER_MOCS_bits 4 +#define GEN6_3DSTATE_DEPTH_BUFFER_MOCS_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_MOCS_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 5; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DEPTH_BUFFER_MOCS_start 160 +#define GEN10_3DSTATE_DEPTH_BUFFER_MOCS_start 160 +#define GEN9_3DSTATE_DEPTH_BUFFER_MOCS_start 160 +#define GEN8_3DSTATE_DEPTH_BUFFER_MOCS_start 160 +#define GEN75_3DSTATE_DEPTH_BUFFER_MOCS_start 128 +#define GEN7_3DSTATE_DEPTH_BUFFER_MOCS_start 128 +#define GEN6_3DSTATE_DEPTH_BUFFER_MOCS_start 219 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_MOCS_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 160; + case 10: return 160; + case 9: return 160; + case 8: return 160; + case 7: + if (devinfo->is_haswell) { + return 128; + } else { + return 128; + } + case 6: return 219; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + /* 3DSTATE_DEPTH_BUFFER::Minimum Array Element */ @@ -32411,17 +32334,17 @@ _3DSTATE_GATHER_POOL_ALLOC_GatherPoolUpperBound_start(const struct gen_device_in -/* 3DSTATE_GATHER_POOL_ALLOC::Memory Object Control State */ +/* 3DSTATE_GATHER_POOL_ALLOC::MOCS */ -#define GEN11_3DSTATE_GATHER_POOL_ALLOC_MemoryObjectControlState_bits 7 -#define GEN10_3DSTATE_GATHER_POOL_ALLOC_MemoryObjectControlState_bits 7 -#define GEN9_3DSTATE_GATHER_POOL_ALLOC_MemoryObjectControlState_bits 7 -#define GEN8_3DSTATE_GATHER_POOL_ALLOC_MemoryObjectControlState_bits 7 -#define GEN75_3DSTATE_GATHER_POOL_ALLOC_MemoryObjectControlState_bits 4 +#define GEN11_3DSTATE_GATHER_POOL_ALLOC_MOCS_bits 7 +#define GEN10_3DSTATE_GATHER_POOL_ALLOC_MOCS_bits 7 +#define GEN9_3DSTATE_GATHER_POOL_ALLOC_MOCS_bits 7 +#define GEN8_3DSTATE_GATHER_POOL_ALLOC_MOCS_bits 7 +#define GEN75_3DSTATE_GATHER_POOL_ALLOC_MOCS_bits 4 static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_GATHER_POOL_ALLOC_MemoryObjectControlState_bits(const struct gen_device_info *devinfo) +_3DSTATE_GATHER_POOL_ALLOC_MOCS_bits(const struct gen_device_info *devinfo) { switch (devinfo->gen) { case 11: return 7; @@ -32449,14 +32372,14 @@ _3DSTATE_GATHER_POOL_ALLOC_MemoryObjectControlState_bits(const struct gen_device -#define GEN11_3DSTATE_GATHER_POOL_ALLOC_MemoryObjectControlState_start 32 -#define GEN10_3DSTATE_GATHER_POOL_ALLOC_MemoryObjectControlState_start 32 -#define GEN9_3DSTATE_GATHER_POOL_ALLOC_MemoryObjectControlState_start 32 -#define GEN8_3DSTATE_GATHER_POOL_ALLOC_MemoryObjectControlState_start 32 -#define GEN75_3DSTATE_GATHER_POOL_ALLOC_MemoryObjectControlState_start 32 +#define GEN11_3DSTATE_GATHER_POOL_ALLOC_MOCS_start 32 +#define GEN10_3DSTATE_GATHER_POOL_ALLOC_MOCS_start 32 +#define GEN9_3DSTATE_GATHER_POOL_ALLOC_MOCS_start 32 +#define GEN8_3DSTATE_GATHER_POOL_ALLOC_MOCS_start 32 +#define GEN75_3DSTATE_GATHER_POOL_ALLOC_MOCS_start 32 static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_GATHER_POOL_ALLOC_MemoryObjectControlState_start(const struct gen_device_info *devinfo) +_3DSTATE_GATHER_POOL_ALLOC_MOCS_start(const struct gen_device_info *devinfo) { switch (devinfo->gen) { case 11: return 32; @@ -38062,19 +37985,19 @@ _3DSTATE_HIER_DEPTH_BUFFER_DWordLength_start(const struct gen_device_info *devin -/* 3DSTATE_HIER_DEPTH_BUFFER::Hierarchical Depth Buffer MOCS */ +/* 3DSTATE_HIER_DEPTH_BUFFER::MOCS */ -#define GEN11_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferMOCS_bits 7 -#define GEN10_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferMOCS_bits 7 -#define GEN9_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferMOCS_bits 7 -#define GEN8_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferMOCS_bits 7 -#define GEN75_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferMOCS_bits 4 -#define GEN7_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferMOCS_bits 4 -#define GEN6_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferMOCS_bits 4 +#define GEN11_3DSTATE_HIER_DEPTH_BUFFER_MOCS_bits 7 +#define GEN10_3DSTATE_HIER_DEPTH_BUFFER_MOCS_bits 7 +#define GEN9_3DSTATE_HIER_DEPTH_BUFFER_MOCS_bits 7 +#define GEN8_3DSTATE_HIER_DEPTH_BUFFER_MOCS_bits 7 +#define GEN75_3DSTATE_HIER_DEPTH_BUFFER_MOCS_bits 4 +#define GEN7_3DSTATE_HIER_DEPTH_BUFFER_MOCS_bits 4 +#define GEN6_3DSTATE_HIER_DEPTH_BUFFER_MOCS_bits 4 static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferMOCS_bits(const struct gen_device_info *devinfo) +_3DSTATE_HIER_DEPTH_BUFFER_MOCS_bits(const struct gen_device_info *devinfo) { switch (devinfo->gen) { case 11: return 7; @@ -38102,93 +38025,16 @@ _3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferMOCS_bits(const struct gen_dev -#define GEN11_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferMOCS_start 57 -#define GEN10_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferMOCS_start 57 -#define GEN9_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferMOCS_start 57 -#define GEN8_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferMOCS_start 57 -#define GEN75_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferMOCS_start 57 -#define GEN7_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferMOCS_start 57 -#define GEN6_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferMOCS_start 57 +#define GEN11_3DSTATE_HIER_DEPTH_BUFFER_MOCS_start 57 +#define GEN10_3DSTATE_HIER_DEPTH_BUFFER_MOCS_start 57 +#define GEN9_3DSTATE_HIER_DEPTH_BUFFER_MOCS_start 57 +#define GEN8_3DSTATE_HIER_DEPTH_BUFFER_MOCS_start 57 +#define GEN75_3DSTATE_HIER_DEPTH_BUFFER_MOCS_start 57 +#define GEN7_3DSTATE_HIER_DEPTH_BUFFER_MOCS_start 57 +#define GEN6_3DSTATE_HIER_DEPTH_BUFFER_MOCS_start 57 static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferMOCS_start(const struct gen_device_info *devinfo) -{ - switch (devinfo->gen) { - case 11: return 57; - case 10: return 57; - case 9: return 57; - case 8: return 57; - case 7: - if (devinfo->is_haswell) { - return 57; - } else { - return 57; - } - case 6: return 57; - case 5: return 0; - case 4: - if (devinfo->is_g4x) { - return 0; - } else { - return 0; - } - default: - unreachable("Invalid hardware generation"); - } -} - - - -/* 3DSTATE_HIER_DEPTH_BUFFER::Hierarchical Depth Buffer Object Control State */ - - -#define GEN11_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferObjectControlState_bits 7 -#define GEN10_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferObjectControlState_bits 7 -#define GEN9_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferObjectControlState_bits 7 -#define GEN8_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferObjectControlState_bits 7 -#define GEN75_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferObjectControlState_bits 4 -#define GEN7_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferObjectControlState_bits 4 -#define GEN6_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferObjectControlState_bits 4 - -static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferObjectControlState_bits(const struct gen_device_info *devinfo) -{ - switch (devinfo->gen) { - case 11: return 7; - case 10: return 7; - case 9: return 7; - case 8: return 7; - case 7: - if (devinfo->is_haswell) { - return 4; - } else { - return 4; - } - case 6: return 4; - case 5: return 0; - case 4: - if (devinfo->is_g4x) { - return 0; - } else { - return 0; - } - default: - unreachable("Invalid hardware generation"); - } -} - - - -#define GEN11_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferObjectControlState_start 57 -#define GEN10_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferObjectControlState_start 57 -#define GEN9_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferObjectControlState_start 57 -#define GEN8_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferObjectControlState_start 57 -#define GEN75_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferObjectControlState_start 57 -#define GEN7_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferObjectControlState_start 57 -#define GEN6_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferObjectControlState_start 57 - -static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferObjectControlState_start(const struct gen_device_info *devinfo) +_3DSTATE_HIER_DEPTH_BUFFER_MOCS_start(const struct gen_device_info *devinfo) { switch (devinfo->gen) { case 11: return 57; @@ -41600,96 +41446,19 @@ _3DSTATE_INDEX_BUFFER_IndexFormat_start(const struct gen_device_info *devinfo) -/* 3DSTATE_INDEX_BUFFER::IndexBufferMOCS */ - - -#define GEN11_3DSTATE_INDEX_BUFFER_IndexBufferMOCS_bits 7 -#define GEN10_3DSTATE_INDEX_BUFFER_IndexBufferMOCS_bits 7 -#define GEN9_3DSTATE_INDEX_BUFFER_IndexBufferMOCS_bits 7 -#define GEN8_3DSTATE_INDEX_BUFFER_IndexBufferMOCS_bits 7 -#define GEN75_3DSTATE_INDEX_BUFFER_IndexBufferMOCS_bits 4 -#define GEN7_3DSTATE_INDEX_BUFFER_IndexBufferMOCS_bits 4 -#define GEN6_3DSTATE_INDEX_BUFFER_IndexBufferMOCS_bits 4 - -static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_INDEX_BUFFER_IndexBufferMOCS_bits(const struct gen_device_info *devinfo) -{ - switch (devinfo->gen) { - case 11: return 7; - case 10: return 7; - case 9: return 7; - case 8: return 7; - case 7: - if (devinfo->is_haswell) { - return 4; - } else { - return 4; - } - case 6: return 4; - case 5: return 0; - case 4: - if (devinfo->is_g4x) { - return 0; - } else { - return 0; - } - default: - unreachable("Invalid hardware generation"); - } -} - - - -#define GEN11_3DSTATE_INDEX_BUFFER_IndexBufferMOCS_start 32 -#define GEN10_3DSTATE_INDEX_BUFFER_IndexBufferMOCS_start 32 -#define GEN9_3DSTATE_INDEX_BUFFER_IndexBufferMOCS_start 32 -#define GEN8_3DSTATE_INDEX_BUFFER_IndexBufferMOCS_start 32 -#define GEN75_3DSTATE_INDEX_BUFFER_IndexBufferMOCS_start 12 -#define GEN7_3DSTATE_INDEX_BUFFER_IndexBufferMOCS_start 12 -#define GEN6_3DSTATE_INDEX_BUFFER_IndexBufferMOCS_start 12 - -static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_INDEX_BUFFER_IndexBufferMOCS_start(const struct gen_device_info *devinfo) -{ - switch (devinfo->gen) { - case 11: return 32; - case 10: return 32; - case 9: return 32; - case 8: return 32; - case 7: - if (devinfo->is_haswell) { - return 12; - } else { - return 12; - } - case 6: return 12; - case 5: return 0; - case 4: - if (devinfo->is_g4x) { - return 0; - } else { - return 0; - } - default: - unreachable("Invalid hardware generation"); - } -} - - - -/* 3DSTATE_INDEX_BUFFER::Memory Object Control State */ +/* 3DSTATE_INDEX_BUFFER::MOCS */ -#define GEN11_3DSTATE_INDEX_BUFFER_MemoryObjectControlState_bits 7 -#define GEN10_3DSTATE_INDEX_BUFFER_MemoryObjectControlState_bits 7 -#define GEN9_3DSTATE_INDEX_BUFFER_MemoryObjectControlState_bits 7 -#define GEN8_3DSTATE_INDEX_BUFFER_MemoryObjectControlState_bits 7 -#define GEN75_3DSTATE_INDEX_BUFFER_MemoryObjectControlState_bits 4 -#define GEN7_3DSTATE_INDEX_BUFFER_MemoryObjectControlState_bits 4 -#define GEN6_3DSTATE_INDEX_BUFFER_MemoryObjectControlState_bits 4 +#define GEN11_3DSTATE_INDEX_BUFFER_MOCS_bits 7 +#define GEN10_3DSTATE_INDEX_BUFFER_MOCS_bits 7 +#define GEN9_3DSTATE_INDEX_BUFFER_MOCS_bits 7 +#define GEN8_3DSTATE_INDEX_BUFFER_MOCS_bits 7 +#define GEN75_3DSTATE_INDEX_BUFFER_MOCS_bits 4 +#define GEN7_3DSTATE_INDEX_BUFFER_MOCS_bits 4 +#define GEN6_3DSTATE_INDEX_BUFFER_MOCS_bits 4 static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_INDEX_BUFFER_MemoryObjectControlState_bits(const struct gen_device_info *devinfo) +_3DSTATE_INDEX_BUFFER_MOCS_bits(const struct gen_device_info *devinfo) { switch (devinfo->gen) { case 11: return 7; @@ -41717,16 +41486,16 @@ _3DSTATE_INDEX_BUFFER_MemoryObjectControlState_bits(const struct gen_device_info -#define GEN11_3DSTATE_INDEX_BUFFER_MemoryObjectControlState_start 32 -#define GEN10_3DSTATE_INDEX_BUFFER_MemoryObjectControlState_start 32 -#define GEN9_3DSTATE_INDEX_BUFFER_MemoryObjectControlState_start 32 -#define GEN8_3DSTATE_INDEX_BUFFER_MemoryObjectControlState_start 32 -#define GEN75_3DSTATE_INDEX_BUFFER_MemoryObjectControlState_start 12 -#define GEN7_3DSTATE_INDEX_BUFFER_MemoryObjectControlState_start 12 -#define GEN6_3DSTATE_INDEX_BUFFER_MemoryObjectControlState_start 12 +#define GEN11_3DSTATE_INDEX_BUFFER_MOCS_start 32 +#define GEN10_3DSTATE_INDEX_BUFFER_MOCS_start 32 +#define GEN9_3DSTATE_INDEX_BUFFER_MOCS_start 32 +#define GEN8_3DSTATE_INDEX_BUFFER_MOCS_start 32 +#define GEN75_3DSTATE_INDEX_BUFFER_MOCS_start 12 +#define GEN7_3DSTATE_INDEX_BUFFER_MOCS_start 12 +#define GEN6_3DSTATE_INDEX_BUFFER_MOCS_start 12 static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_INDEX_BUFFER_MemoryObjectControlState_start(const struct gen_device_info *devinfo) +_3DSTATE_INDEX_BUFFER_MOCS_start(const struct gen_device_info *devinfo) { switch (devinfo->gen) { case 11: return 32; @@ -79048,27 +78817,29 @@ _3DSTATE_SO_BUFFER_DWordLength_start(const struct gen_device_info *devinfo) -/* 3DSTATE_SO_BUFFER::SO Buffer Enable */ +/* 3DSTATE_SO_BUFFER::MOCS */ -#define GEN11_3DSTATE_SO_BUFFER_SOBufferEnable_bits 1 -#define GEN10_3DSTATE_SO_BUFFER_SOBufferEnable_bits 1 -#define GEN9_3DSTATE_SO_BUFFER_SOBufferEnable_bits 1 -#define GEN8_3DSTATE_SO_BUFFER_SOBufferEnable_bits 1 +#define GEN11_3DSTATE_SO_BUFFER_MOCS_bits 7 +#define GEN10_3DSTATE_SO_BUFFER_MOCS_bits 7 +#define GEN9_3DSTATE_SO_BUFFER_MOCS_bits 7 +#define GEN8_3DSTATE_SO_BUFFER_MOCS_bits 7 +#define GEN75_3DSTATE_SO_BUFFER_MOCS_bits 4 +#define GEN7_3DSTATE_SO_BUFFER_MOCS_bits 4 static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_SO_BUFFER_SOBufferEnable_bits(const struct gen_device_info *devinfo) +_3DSTATE_SO_BUFFER_MOCS_bits(const struct gen_device_info *devinfo) { switch (devinfo->gen) { - case 11: return 1; - case 10: return 1; - case 9: return 1; - case 8: return 1; + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; case 7: if (devinfo->is_haswell) { - return 0; + return 4; } else { - return 0; + return 4; } case 6: return 0; case 5: return 0; @@ -79085,24 +78856,26 @@ _3DSTATE_SO_BUFFER_SOBufferEnable_bits(const struct gen_device_info *devinfo) -#define GEN11_3DSTATE_SO_BUFFER_SOBufferEnable_start 63 -#define GEN10_3DSTATE_SO_BUFFER_SOBufferEnable_start 63 -#define GEN9_3DSTATE_SO_BUFFER_SOBufferEnable_start 63 -#define GEN8_3DSTATE_SO_BUFFER_SOBufferEnable_start 63 +#define GEN11_3DSTATE_SO_BUFFER_MOCS_start 54 +#define GEN10_3DSTATE_SO_BUFFER_MOCS_start 54 +#define GEN9_3DSTATE_SO_BUFFER_MOCS_start 54 +#define GEN8_3DSTATE_SO_BUFFER_MOCS_start 54 +#define GEN75_3DSTATE_SO_BUFFER_MOCS_start 57 +#define GEN7_3DSTATE_SO_BUFFER_MOCS_start 57 static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_SO_BUFFER_SOBufferEnable_start(const struct gen_device_info *devinfo) +_3DSTATE_SO_BUFFER_MOCS_start(const struct gen_device_info *devinfo) { switch (devinfo->gen) { - case 11: return 63; - case 10: return 63; - case 9: return 63; - case 8: return 63; + case 11: return 54; + case 10: return 54; + case 9: return 54; + case 8: return 54; case 7: if (devinfo->is_haswell) { - return 0; + return 57; } else { - return 0; + return 57; } case 6: return 0; case 5: return 0; @@ -79119,66 +78892,28 @@ _3DSTATE_SO_BUFFER_SOBufferEnable_start(const struct gen_device_info *devinfo) -/* 3DSTATE_SO_BUFFER::SO Buffer Index */ +/* 3DSTATE_SO_BUFFER::SO Buffer Enable */ -#define GEN11_3DSTATE_SO_BUFFER_SOBufferIndex_bits 2 -#define GEN10_3DSTATE_SO_BUFFER_SOBufferIndex_bits 2 -#define GEN9_3DSTATE_SO_BUFFER_SOBufferIndex_bits 2 -#define GEN8_3DSTATE_SO_BUFFER_SOBufferIndex_bits 2 -#define GEN75_3DSTATE_SO_BUFFER_SOBufferIndex_bits 2 -#define GEN7_3DSTATE_SO_BUFFER_SOBufferIndex_bits 2 +#define GEN11_3DSTATE_SO_BUFFER_SOBufferEnable_bits 1 +#define GEN10_3DSTATE_SO_BUFFER_SOBufferEnable_bits 1 +#define GEN9_3DSTATE_SO_BUFFER_SOBufferEnable_bits 1 +#define GEN8_3DSTATE_SO_BUFFER_SOBufferEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_SO_BUFFER_SOBufferIndex_bits(const struct gen_device_info *devinfo) +_3DSTATE_SO_BUFFER_SOBufferEnable_bits(const struct gen_device_info *devinfo) { switch (devinfo->gen) { - case 11: return 2; - case 10: return 2; - case 9: return 2; - case 8: return 2; + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; case 7: if (devinfo->is_haswell) { - return 2; - } else { - return 2; - } - case 6: return 0; - case 5: return 0; - case 4: - if (devinfo->is_g4x) { return 0; } else { return 0; } - default: - unreachable("Invalid hardware generation"); - } -} - - - -#define GEN11_3DSTATE_SO_BUFFER_SOBufferIndex_start 61 -#define GEN10_3DSTATE_SO_BUFFER_SOBufferIndex_start 61 -#define GEN9_3DSTATE_SO_BUFFER_SOBufferIndex_start 61 -#define GEN8_3DSTATE_SO_BUFFER_SOBufferIndex_start 61 -#define GEN75_3DSTATE_SO_BUFFER_SOBufferIndex_start 61 -#define GEN7_3DSTATE_SO_BUFFER_SOBufferIndex_start 61 - -static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_SO_BUFFER_SOBufferIndex_start(const struct gen_device_info *devinfo) -{ - switch (devinfo->gen) { - case 11: return 61; - case 10: return 61; - case 9: return 61; - case 8: return 61; - case 7: - if (devinfo->is_haswell) { - return 61; - } else { - return 61; - } case 6: return 0; case 5: return 0; case 4: @@ -79194,66 +78929,25 @@ _3DSTATE_SO_BUFFER_SOBufferIndex_start(const struct gen_device_info *devinfo) -/* 3DSTATE_SO_BUFFER::SO Buffer MOCS */ - - -#define GEN11_3DSTATE_SO_BUFFER_SOBufferMOCS_bits 7 -#define GEN10_3DSTATE_SO_BUFFER_SOBufferMOCS_bits 7 -#define GEN9_3DSTATE_SO_BUFFER_SOBufferMOCS_bits 7 -#define GEN8_3DSTATE_SO_BUFFER_SOBufferMOCS_bits 7 -#define GEN75_3DSTATE_SO_BUFFER_SOBufferMOCS_bits 4 -#define GEN7_3DSTATE_SO_BUFFER_SOBufferMOCS_bits 4 +#define GEN11_3DSTATE_SO_BUFFER_SOBufferEnable_start 63 +#define GEN10_3DSTATE_SO_BUFFER_SOBufferEnable_start 63 +#define GEN9_3DSTATE_SO_BUFFER_SOBufferEnable_start 63 +#define GEN8_3DSTATE_SO_BUFFER_SOBufferEnable_start 63 static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_SO_BUFFER_SOBufferMOCS_bits(const struct gen_device_info *devinfo) +_3DSTATE_SO_BUFFER_SOBufferEnable_start(const struct gen_device_info *devinfo) { switch (devinfo->gen) { - case 11: return 7; - case 10: return 7; - case 9: return 7; - case 8: return 7; + case 11: return 63; + case 10: return 63; + case 9: return 63; + case 8: return 63; case 7: if (devinfo->is_haswell) { - return 4; - } else { - return 4; - } - case 6: return 0; - case 5: return 0; - case 4: - if (devinfo->is_g4x) { return 0; } else { return 0; } - default: - unreachable("Invalid hardware generation"); - } -} - - - -#define GEN11_3DSTATE_SO_BUFFER_SOBufferMOCS_start 54 -#define GEN10_3DSTATE_SO_BUFFER_SOBufferMOCS_start 54 -#define GEN9_3DSTATE_SO_BUFFER_SOBufferMOCS_start 54 -#define GEN8_3DSTATE_SO_BUFFER_SOBufferMOCS_start 54 -#define GEN75_3DSTATE_SO_BUFFER_SOBufferMOCS_start 57 -#define GEN7_3DSTATE_SO_BUFFER_SOBufferMOCS_start 57 - -static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_SO_BUFFER_SOBufferMOCS_start(const struct gen_device_info *devinfo) -{ - switch (devinfo->gen) { - case 11: return 54; - case 10: return 54; - case 9: return 54; - case 8: return 54; - case 7: - if (devinfo->is_haswell) { - return 57; - } else { - return 57; - } case 6: return 0; case 5: return 0; case 4: @@ -79269,29 +78963,29 @@ _3DSTATE_SO_BUFFER_SOBufferMOCS_start(const struct gen_device_info *devinfo) -/* 3DSTATE_SO_BUFFER::SO Buffer Object Control State */ +/* 3DSTATE_SO_BUFFER::SO Buffer Index */ -#define GEN11_3DSTATE_SO_BUFFER_SOBufferObjectControlState_bits 7 -#define GEN10_3DSTATE_SO_BUFFER_SOBufferObjectControlState_bits 7 -#define GEN9_3DSTATE_SO_BUFFER_SOBufferObjectControlState_bits 7 -#define GEN8_3DSTATE_SO_BUFFER_SOBufferObjectControlState_bits 7 -#define GEN75_3DSTATE_SO_BUFFER_SOBufferObjectControlState_bits 4 -#define GEN7_3DSTATE_SO_BUFFER_SOBufferObjectControlState_bits 4 +#define GEN11_3DSTATE_SO_BUFFER_SOBufferIndex_bits 2 +#define GEN10_3DSTATE_SO_BUFFER_SOBufferIndex_bits 2 +#define GEN9_3DSTATE_SO_BUFFER_SOBufferIndex_bits 2 +#define GEN8_3DSTATE_SO_BUFFER_SOBufferIndex_bits 2 +#define GEN75_3DSTATE_SO_BUFFER_SOBufferIndex_bits 2 +#define GEN7_3DSTATE_SO_BUFFER_SOBufferIndex_bits 2 static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_SO_BUFFER_SOBufferObjectControlState_bits(const struct gen_device_info *devinfo) +_3DSTATE_SO_BUFFER_SOBufferIndex_bits(const struct gen_device_info *devinfo) { switch (devinfo->gen) { - case 11: return 7; - case 10: return 7; - case 9: return 7; - case 8: return 7; + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; case 7: if (devinfo->is_haswell) { - return 4; + return 2; } else { - return 4; + return 2; } case 6: return 0; case 5: return 0; @@ -79308,26 +79002,26 @@ _3DSTATE_SO_BUFFER_SOBufferObjectControlState_bits(const struct gen_device_info -#define GEN11_3DSTATE_SO_BUFFER_SOBufferObjectControlState_start 54 -#define GEN10_3DSTATE_SO_BUFFER_SOBufferObjectControlState_start 54 -#define GEN9_3DSTATE_SO_BUFFER_SOBufferObjectControlState_start 54 -#define GEN8_3DSTATE_SO_BUFFER_SOBufferObjectControlState_start 54 -#define GEN75_3DSTATE_SO_BUFFER_SOBufferObjectControlState_start 57 -#define GEN7_3DSTATE_SO_BUFFER_SOBufferObjectControlState_start 57 +#define GEN11_3DSTATE_SO_BUFFER_SOBufferIndex_start 61 +#define GEN10_3DSTATE_SO_BUFFER_SOBufferIndex_start 61 +#define GEN9_3DSTATE_SO_BUFFER_SOBufferIndex_start 61 +#define GEN8_3DSTATE_SO_BUFFER_SOBufferIndex_start 61 +#define GEN75_3DSTATE_SO_BUFFER_SOBufferIndex_start 61 +#define GEN7_3DSTATE_SO_BUFFER_SOBufferIndex_start 61 static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_SO_BUFFER_SOBufferObjectControlState_start(const struct gen_device_info *devinfo) +_3DSTATE_SO_BUFFER_SOBufferIndex_start(const struct gen_device_info *devinfo) { switch (devinfo->gen) { - case 11: return 54; - case 10: return 54; - case 9: return 54; - case 8: return 54; + case 11: return 61; + case 10: return 61; + case 9: return 61; + case 8: return 61; case 7: if (devinfo->is_haswell) { - return 57; + return 61; } else { - return 57; + return 61; } case 6: return 0; case 5: return 0; @@ -81400,92 +81094,19 @@ _3DSTATE_STENCIL_BUFFER_DWordLength_start(const struct gen_device_info *devinfo) -/* 3DSTATE_STENCIL_BUFFER::Stencil Buffer Enable */ +/* 3DSTATE_STENCIL_BUFFER::MOCS */ -#define GEN11_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_bits 1 -#define GEN10_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_bits 1 -#define GEN9_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_bits 1 -#define GEN8_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_bits 1 -#define GEN75_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_bits 1 +#define GEN11_3DSTATE_STENCIL_BUFFER_MOCS_bits 7 +#define GEN10_3DSTATE_STENCIL_BUFFER_MOCS_bits 7 +#define GEN9_3DSTATE_STENCIL_BUFFER_MOCS_bits 7 +#define GEN8_3DSTATE_STENCIL_BUFFER_MOCS_bits 7 +#define GEN75_3DSTATE_STENCIL_BUFFER_MOCS_bits 4 +#define GEN7_3DSTATE_STENCIL_BUFFER_MOCS_bits 4 +#define GEN6_3DSTATE_STENCIL_BUFFER_MOCS_bits 4 static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_bits(const struct gen_device_info *devinfo) -{ - switch (devinfo->gen) { - case 11: return 1; - case 10: return 1; - case 9: return 1; - case 8: return 1; - case 7: - if (devinfo->is_haswell) { - return 1; - } else { - return 0; - } - case 6: return 0; - case 5: return 0; - case 4: - if (devinfo->is_g4x) { - return 0; - } else { - return 0; - } - default: - unreachable("Invalid hardware generation"); - } -} - - - -#define GEN11_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_start 63 -#define GEN10_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_start 63 -#define GEN9_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_start 63 -#define GEN8_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_start 63 -#define GEN75_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_start 63 - -static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_start(const struct gen_device_info *devinfo) -{ - switch (devinfo->gen) { - case 11: return 63; - case 10: return 63; - case 9: return 63; - case 8: return 63; - case 7: - if (devinfo->is_haswell) { - return 63; - } else { - return 0; - } - case 6: return 0; - case 5: return 0; - case 4: - if (devinfo->is_g4x) { - return 0; - } else { - return 0; - } - default: - unreachable("Invalid hardware generation"); - } -} - - - -/* 3DSTATE_STENCIL_BUFFER::Stencil Buffer MOCS */ - - -#define GEN11_3DSTATE_STENCIL_BUFFER_StencilBufferMOCS_bits 7 -#define GEN10_3DSTATE_STENCIL_BUFFER_StencilBufferMOCS_bits 7 -#define GEN9_3DSTATE_STENCIL_BUFFER_StencilBufferMOCS_bits 7 -#define GEN8_3DSTATE_STENCIL_BUFFER_StencilBufferMOCS_bits 7 -#define GEN75_3DSTATE_STENCIL_BUFFER_StencilBufferMOCS_bits 4 -#define GEN7_3DSTATE_STENCIL_BUFFER_StencilBufferMOCS_bits 4 -#define GEN6_3DSTATE_STENCIL_BUFFER_StencilBufferMOCS_bits 4 - -static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_STENCIL_BUFFER_StencilBufferMOCS_bits(const struct gen_device_info *devinfo) +_3DSTATE_STENCIL_BUFFER_MOCS_bits(const struct gen_device_info *devinfo) { switch (devinfo->gen) { case 11: return 7; @@ -81513,16 +81134,16 @@ _3DSTATE_STENCIL_BUFFER_StencilBufferMOCS_bits(const struct gen_device_info *dev -#define GEN11_3DSTATE_STENCIL_BUFFER_StencilBufferMOCS_start 54 -#define GEN10_3DSTATE_STENCIL_BUFFER_StencilBufferMOCS_start 54 -#define GEN9_3DSTATE_STENCIL_BUFFER_StencilBufferMOCS_start 54 -#define GEN8_3DSTATE_STENCIL_BUFFER_StencilBufferMOCS_start 54 -#define GEN75_3DSTATE_STENCIL_BUFFER_StencilBufferMOCS_start 57 -#define GEN7_3DSTATE_STENCIL_BUFFER_StencilBufferMOCS_start 57 -#define GEN6_3DSTATE_STENCIL_BUFFER_StencilBufferMOCS_start 57 +#define GEN11_3DSTATE_STENCIL_BUFFER_MOCS_start 54 +#define GEN10_3DSTATE_STENCIL_BUFFER_MOCS_start 54 +#define GEN9_3DSTATE_STENCIL_BUFFER_MOCS_start 54 +#define GEN8_3DSTATE_STENCIL_BUFFER_MOCS_start 54 +#define GEN75_3DSTATE_STENCIL_BUFFER_MOCS_start 57 +#define GEN7_3DSTATE_STENCIL_BUFFER_MOCS_start 57 +#define GEN6_3DSTATE_STENCIL_BUFFER_MOCS_start 57 static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_STENCIL_BUFFER_StencilBufferMOCS_start(const struct gen_device_info *devinfo) +_3DSTATE_STENCIL_BUFFER_MOCS_start(const struct gen_device_info *devinfo) { switch (devinfo->gen) { case 11: return 54; @@ -81550,32 +81171,30 @@ _3DSTATE_STENCIL_BUFFER_StencilBufferMOCS_start(const struct gen_device_info *de -/* 3DSTATE_STENCIL_BUFFER::Stencil Buffer Object Control State */ +/* 3DSTATE_STENCIL_BUFFER::Stencil Buffer Enable */ -#define GEN11_3DSTATE_STENCIL_BUFFER_StencilBufferObjectControlState_bits 7 -#define GEN10_3DSTATE_STENCIL_BUFFER_StencilBufferObjectControlState_bits 7 -#define GEN9_3DSTATE_STENCIL_BUFFER_StencilBufferObjectControlState_bits 7 -#define GEN8_3DSTATE_STENCIL_BUFFER_StencilBufferObjectControlState_bits 7 -#define GEN75_3DSTATE_STENCIL_BUFFER_StencilBufferObjectControlState_bits 4 -#define GEN7_3DSTATE_STENCIL_BUFFER_StencilBufferObjectControlState_bits 4 -#define GEN6_3DSTATE_STENCIL_BUFFER_StencilBufferObjectControlState_bits 4 +#define GEN11_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_bits 1 +#define GEN10_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_bits 1 +#define GEN9_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_bits 1 +#define GEN8_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_bits 1 +#define GEN75_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_STENCIL_BUFFER_StencilBufferObjectControlState_bits(const struct gen_device_info *devinfo) +_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_bits(const struct gen_device_info *devinfo) { switch (devinfo->gen) { - case 11: return 7; - case 10: return 7; - case 9: return 7; - case 8: return 7; + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; case 7: if (devinfo->is_haswell) { - return 4; + return 1; } else { - return 4; + return 0; } - case 6: return 4; + case 6: return 0; case 5: return 0; case 4: if (devinfo->is_g4x) { @@ -81590,29 +81209,27 @@ _3DSTATE_STENCIL_BUFFER_StencilBufferObjectControlState_bits(const struct gen_de -#define GEN11_3DSTATE_STENCIL_BUFFER_StencilBufferObjectControlState_start 54 -#define GEN10_3DSTATE_STENCIL_BUFFER_StencilBufferObjectControlState_start 54 -#define GEN9_3DSTATE_STENCIL_BUFFER_StencilBufferObjectControlState_start 54 -#define GEN8_3DSTATE_STENCIL_BUFFER_StencilBufferObjectControlState_start 54 -#define GEN75_3DSTATE_STENCIL_BUFFER_StencilBufferObjectControlState_start 57 -#define GEN7_3DSTATE_STENCIL_BUFFER_StencilBufferObjectControlState_start 57 -#define GEN6_3DSTATE_STENCIL_BUFFER_StencilBufferObjectControlState_start 57 +#define GEN11_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_start 63 +#define GEN10_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_start 63 +#define GEN9_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_start 63 +#define GEN8_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_start 63 +#define GEN75_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_start 63 static inline uint32_t ATTRIBUTE_PURE -_3DSTATE_STENCIL_BUFFER_StencilBufferObjectControlState_start(const struct gen_device_info *devinfo) +_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_start(const struct gen_device_info *devinfo) { switch (devinfo->gen) { - case 11: return 54; - case 10: return 54; - case 9: return 54; - case 8: return 54; + case 11: return 63; + case 10: return 63; + case 9: return 63; + case 8: return 63; case 7: if (devinfo->is_haswell) { - return 57; + return 63; } else { - return 57; + return 0; } - case 6: return 57; + case 6: return 0; case 5: return 0; case 4: if (devinfo->is_g4x) { @@ -124506,6 +124123,180 @@ CONSTANT_BUFFER_Valid_start(const struct gen_device_info *devinfo) +/* CS_CHICKEN1 */ + + +#define GEN11_CS_CHICKEN1_length 1 +#define GEN10_CS_CHICKEN1_length 1 +#define GEN9_CS_CHICKEN1_length 1 + +static inline uint32_t ATTRIBUTE_PURE +CS_CHICKEN1_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CS_CHICKEN1::Replay Mode */ + + +#define GEN11_CS_CHICKEN1_ReplayMode_bits 1 +#define GEN10_CS_CHICKEN1_ReplayMode_bits 1 +#define GEN9_CS_CHICKEN1_ReplayMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CS_CHICKEN1_ReplayMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CS_CHICKEN1_ReplayMode_start 0 +#define GEN10_CS_CHICKEN1_ReplayMode_start 0 +#define GEN9_CS_CHICKEN1_ReplayMode_start 0 + +static inline uint32_t ATTRIBUTE_PURE +CS_CHICKEN1_ReplayMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CS_CHICKEN1::Replay Mode Mask */ + + +#define GEN11_CS_CHICKEN1_ReplayModeMask_bits 1 +#define GEN10_CS_CHICKEN1_ReplayModeMask_bits 1 +#define GEN9_CS_CHICKEN1_ReplayModeMask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CS_CHICKEN1_ReplayModeMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CS_CHICKEN1_ReplayModeMask_start 16 +#define GEN10_CS_CHICKEN1_ReplayModeMask_start 16 +#define GEN9_CS_CHICKEN1_ReplayModeMask_start 16 + +static inline uint32_t ATTRIBUTE_PURE +CS_CHICKEN1_ReplayModeMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + /* CS_DEBUG_MODE2 */ @@ -144661,6 +144452,71 @@ L3CNTLREG_DCAllocation_start(const struct gen_device_info *devinfo) +/* L3CNTLREG::Error Detection Behavior Control */ + + +#define GEN11_L3CNTLREG_ErrorDetectionBehaviorControl_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG_ErrorDetectionBehaviorControl_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_L3CNTLREG_ErrorDetectionBehaviorControl_start 9 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG_ErrorDetectionBehaviorControl_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 9; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + /* L3CNTLREG::RO Allocation */ @@ -144874,6 +144730,71 @@ L3CNTLREG_URBAllocation_start(const struct gen_device_info *devinfo) +/* L3CNTLREG::Use Full Ways */ + + +#define GEN11_L3CNTLREG_UseFullWays_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG_UseFullWays_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_L3CNTLREG_UseFullWays_start 10 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG_UseFullWays_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 10; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + /* L3CNTLREG2 */ @@ -159271,9 +159192,6 @@ MEDIA_VFE_STATE_URBEntryAllocationSize_start(const struct gen_device_info *devin /* MEMORY_OBJECT_CONTROL_STATE */ -#define GEN11_MEMORY_OBJECT_CONTROL_STATE_length 1 -#define GEN10_MEMORY_OBJECT_CONTROL_STATE_length 1 -#define GEN9_MEMORY_OBJECT_CONTROL_STATE_length 1 #define GEN8_MEMORY_OBJECT_CONTROL_STATE_length 1 #define GEN75_MEMORY_OBJECT_CONTROL_STATE_length 1 #define GEN7_MEMORY_OBJECT_CONTROL_STATE_length 1 @@ -159284,9 +159202,9 @@ static inline uint32_t ATTRIBUTE_PURE MEMORY_OBJECT_CONTROL_STATE_length(const struct gen_device_info *devinfo) { switch (devinfo->gen) { - case 11: return 1; - case 10: return 1; - case 9: return 1; + case 11: return 0; + case 10: return 0; + case 9: return 0; case 8: return 1; case 7: if (devinfo->is_haswell) { @@ -159575,75 +159493,6 @@ MEMORY_OBJECT_CONTROL_STATE_GraphicsDataTypeGFDT_start(const struct gen_device_i -/* MEMORY_OBJECT_CONTROL_STATE::Index to MOCS Tables */ - - -#define GEN11_MEMORY_OBJECT_CONTROL_STATE_IndextoMOCSTables_bits 6 -#define GEN10_MEMORY_OBJECT_CONTROL_STATE_IndextoMOCSTables_bits 6 -#define GEN9_MEMORY_OBJECT_CONTROL_STATE_IndextoMOCSTables_bits 6 - -static inline uint32_t ATTRIBUTE_PURE -MEMORY_OBJECT_CONTROL_STATE_IndextoMOCSTables_bits(const struct gen_device_info *devinfo) -{ - switch (devinfo->gen) { - case 11: return 6; - case 10: return 6; - case 9: return 6; - case 8: return 0; - case 7: - if (devinfo->is_haswell) { - return 0; - } else { - return 0; - } - case 6: return 0; - case 5: return 0; - case 4: - if (devinfo->is_g4x) { - return 0; - } else { - return 0; - } - default: - unreachable("Invalid hardware generation"); - } -} - - - -#define GEN11_MEMORY_OBJECT_CONTROL_STATE_IndextoMOCSTables_start 1 -#define GEN10_MEMORY_OBJECT_CONTROL_STATE_IndextoMOCSTables_start 1 -#define GEN9_MEMORY_OBJECT_CONTROL_STATE_IndextoMOCSTables_start 1 - -static inline uint32_t ATTRIBUTE_PURE -MEMORY_OBJECT_CONTROL_STATE_IndextoMOCSTables_start(const struct gen_device_info *devinfo) -{ - switch (devinfo->gen) { - case 11: return 1; - case 10: return 1; - case 9: return 1; - case 8: return 0; - case 7: - if (devinfo->is_haswell) { - return 0; - } else { - return 0; - } - case 6: return 0; - case 5: return 0; - case 4: - if (devinfo->is_g4x) { - return 0; - } else { - return 0; - } - default: - unreachable("Invalid hardware generation"); - } -} - - - /* MEMORY_OBJECT_CONTROL_STATE::L3 Cacheability Control (L3CC) */ @@ -191013,77 +190862,6 @@ RENDER_SURFACE_STATE_MemoryCompressionMode_start(const struct gen_device_info *d -/* RENDER_SURFACE_STATE::Memory Object Control State */ - - -#define GEN11_RENDER_SURFACE_STATE_MemoryObjectControlState_bits 7 -#define GEN10_RENDER_SURFACE_STATE_MemoryObjectControlState_bits 7 -#define GEN9_RENDER_SURFACE_STATE_MemoryObjectControlState_bits 7 -#define GEN8_RENDER_SURFACE_STATE_MemoryObjectControlState_bits 7 - -static inline uint32_t ATTRIBUTE_PURE -RENDER_SURFACE_STATE_MemoryObjectControlState_bits(const struct gen_device_info *devinfo) -{ - switch (devinfo->gen) { - case 11: return 7; - case 10: return 7; - case 9: return 7; - case 8: return 7; - case 7: - if (devinfo->is_haswell) { - return 0; - } else { - return 0; - } - case 6: return 0; - case 5: return 0; - case 4: - if (devinfo->is_g4x) { - return 0; - } else { - return 0; - } - default: - unreachable("Invalid hardware generation"); - } -} - - - -#define GEN11_RENDER_SURFACE_STATE_MemoryObjectControlState_start 56 -#define GEN10_RENDER_SURFACE_STATE_MemoryObjectControlState_start 56 -#define GEN9_RENDER_SURFACE_STATE_MemoryObjectControlState_start 56 -#define GEN8_RENDER_SURFACE_STATE_MemoryObjectControlState_start 56 - -static inline uint32_t ATTRIBUTE_PURE -RENDER_SURFACE_STATE_MemoryObjectControlState_start(const struct gen_device_info *devinfo) -{ - switch (devinfo->gen) { - case 11: return 56; - case 10: return 56; - case 9: return 56; - case 8: return 56; - case 7: - if (devinfo->is_haswell) { - return 0; - } else { - return 0; - } - case 6: return 0; - case 5: return 0; - case 4: - if (devinfo->is_g4x) { - return 0; - } else { - return 0; - } - default: - unreachable("Invalid hardware generation"); - } -} - - - /* RENDER_SURFACE_STATE::Minimum Array Element */ @@ -193095,75 +192873,6 @@ RENDER_SURFACE_STATE_SurfaceMinLOD_start(const struct gen_device_info *devinfo) -/* RENDER_SURFACE_STATE::Surface Object Control State */ - - -#define GEN75_RENDER_SURFACE_STATE_SurfaceObjectControlState_bits 4 -#define GEN7_RENDER_SURFACE_STATE_SurfaceObjectControlState_bits 4 -#define GEN6_RENDER_SURFACE_STATE_SurfaceObjectControlState_bits 4 - -static inline uint32_t ATTRIBUTE_PURE -RENDER_SURFACE_STATE_SurfaceObjectControlState_bits(const struct gen_device_info *devinfo) -{ - switch (devinfo->gen) { - case 11: return 0; - case 10: return 0; - case 9: return 0; - case 8: return 0; - case 7: - if (devinfo->is_haswell) { - return 4; - } else { - return 4; - } - case 6: return 4; - case 5: return 0; - case 4: - if (devinfo->is_g4x) { - return 0; - } else { - return 0; - } - default: - unreachable("Invalid hardware generation"); - } -} - - - -#define GEN75_RENDER_SURFACE_STATE_SurfaceObjectControlState_start 176 -#define GEN7_RENDER_SURFACE_STATE_SurfaceObjectControlState_start 176 -#define GEN6_RENDER_SURFACE_STATE_SurfaceObjectControlState_start 176 - -static inline uint32_t ATTRIBUTE_PURE -RENDER_SURFACE_STATE_SurfaceObjectControlState_start(const struct gen_device_info *devinfo) -{ - switch (devinfo->gen) { - case 11: return 0; - case 10: return 0; - case 9: return 0; - case 8: return 0; - case 7: - if (devinfo->is_haswell) { - return 176; - } else { - return 176; - } - case 6: return 176; - case 5: return 0; - case 4: - if (devinfo->is_g4x) { - return 0; - } else { - return 0; - } - default: - unreachable("Invalid hardware generation"); - } -} - - - /* RENDER_SURFACE_STATE::Surface Pitch */ @@ -215821,6 +215530,918 @@ SO_DECL_ENTRY_Stream3Decl_start(const struct gen_device_info *devinfo) +/* SO_NUM_PRIMS_WRITTEN0 */ + + +#define GEN11_SO_NUM_PRIMS_WRITTEN0_length 2 +#define GEN10_SO_NUM_PRIMS_WRITTEN0_length 2 +#define GEN9_SO_NUM_PRIMS_WRITTEN0_length 2 +#define GEN8_SO_NUM_PRIMS_WRITTEN0_length 2 +#define GEN75_SO_NUM_PRIMS_WRITTEN0_length 2 +#define GEN7_SO_NUM_PRIMS_WRITTEN0_length 2 + +static inline uint32_t ATTRIBUTE_PURE +SO_NUM_PRIMS_WRITTEN0_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_NUM_PRIMS_WRITTEN0::Num Prims Written Count */ + + +#define GEN11_SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_bits 64 +#define GEN10_SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_bits 64 +#define GEN9_SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_bits 64 +#define GEN8_SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_bits 64 +#define GEN75_SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_bits 64 +#define GEN7_SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_bits 64 + +static inline uint32_t ATTRIBUTE_PURE +SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_start 0 +#define GEN10_SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_start 0 +#define GEN9_SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_start 0 +#define GEN8_SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_start 0 +#define GEN75_SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_start 0 +#define GEN7_SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_start 0 + +static inline uint32_t ATTRIBUTE_PURE +SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_NUM_PRIMS_WRITTEN1 */ + + +#define GEN11_SO_NUM_PRIMS_WRITTEN1_length 2 +#define GEN10_SO_NUM_PRIMS_WRITTEN1_length 2 +#define GEN9_SO_NUM_PRIMS_WRITTEN1_length 2 +#define GEN8_SO_NUM_PRIMS_WRITTEN1_length 2 +#define GEN75_SO_NUM_PRIMS_WRITTEN1_length 2 +#define GEN7_SO_NUM_PRIMS_WRITTEN1_length 2 + +static inline uint32_t ATTRIBUTE_PURE +SO_NUM_PRIMS_WRITTEN1_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_NUM_PRIMS_WRITTEN1::Num Prims Written Count */ + + +#define GEN11_SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_bits 64 +#define GEN10_SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_bits 64 +#define GEN9_SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_bits 64 +#define GEN8_SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_bits 64 +#define GEN75_SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_bits 64 +#define GEN7_SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_bits 64 + +static inline uint32_t ATTRIBUTE_PURE +SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_start 0 +#define GEN10_SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_start 0 +#define GEN9_SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_start 0 +#define GEN8_SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_start 0 +#define GEN75_SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_start 0 +#define GEN7_SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_start 0 + +static inline uint32_t ATTRIBUTE_PURE +SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_NUM_PRIMS_WRITTEN2 */ + + +#define GEN11_SO_NUM_PRIMS_WRITTEN2_length 2 +#define GEN10_SO_NUM_PRIMS_WRITTEN2_length 2 +#define GEN9_SO_NUM_PRIMS_WRITTEN2_length 2 +#define GEN8_SO_NUM_PRIMS_WRITTEN2_length 2 +#define GEN75_SO_NUM_PRIMS_WRITTEN2_length 2 +#define GEN7_SO_NUM_PRIMS_WRITTEN2_length 2 + +static inline uint32_t ATTRIBUTE_PURE +SO_NUM_PRIMS_WRITTEN2_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_NUM_PRIMS_WRITTEN2::Num Prims Written Count */ + + +#define GEN11_SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_bits 64 +#define GEN10_SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_bits 64 +#define GEN9_SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_bits 64 +#define GEN8_SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_bits 64 +#define GEN75_SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_bits 64 +#define GEN7_SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_bits 64 + +static inline uint32_t ATTRIBUTE_PURE +SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_start 0 +#define GEN10_SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_start 0 +#define GEN9_SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_start 0 +#define GEN8_SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_start 0 +#define GEN75_SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_start 0 +#define GEN7_SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_start 0 + +static inline uint32_t ATTRIBUTE_PURE +SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_NUM_PRIMS_WRITTEN3 */ + + +#define GEN11_SO_NUM_PRIMS_WRITTEN3_length 2 +#define GEN10_SO_NUM_PRIMS_WRITTEN3_length 2 +#define GEN9_SO_NUM_PRIMS_WRITTEN3_length 2 +#define GEN8_SO_NUM_PRIMS_WRITTEN3_length 2 +#define GEN75_SO_NUM_PRIMS_WRITTEN3_length 2 +#define GEN7_SO_NUM_PRIMS_WRITTEN3_length 2 + +static inline uint32_t ATTRIBUTE_PURE +SO_NUM_PRIMS_WRITTEN3_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_NUM_PRIMS_WRITTEN3::Num Prims Written Count */ + + +#define GEN11_SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_bits 64 +#define GEN10_SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_bits 64 +#define GEN9_SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_bits 64 +#define GEN8_SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_bits 64 +#define GEN75_SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_bits 64 +#define GEN7_SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_bits 64 + +static inline uint32_t ATTRIBUTE_PURE +SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_start 0 +#define GEN10_SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_start 0 +#define GEN9_SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_start 0 +#define GEN8_SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_start 0 +#define GEN75_SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_start 0 +#define GEN7_SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_start 0 + +static inline uint32_t ATTRIBUTE_PURE +SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_PRIM_STORAGE_NEEDED0 */ + + +#define GEN11_SO_PRIM_STORAGE_NEEDED0_length 2 +#define GEN10_SO_PRIM_STORAGE_NEEDED0_length 2 +#define GEN9_SO_PRIM_STORAGE_NEEDED0_length 2 +#define GEN8_SO_PRIM_STORAGE_NEEDED0_length 2 +#define GEN75_SO_PRIM_STORAGE_NEEDED0_length 2 +#define GEN7_SO_PRIM_STORAGE_NEEDED0_length 2 + +static inline uint32_t ATTRIBUTE_PURE +SO_PRIM_STORAGE_NEEDED0_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_PRIM_STORAGE_NEEDED0::Prim Storage Needed Count */ + + +#define GEN11_SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_bits 64 +#define GEN10_SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_bits 64 +#define GEN9_SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_bits 64 +#define GEN8_SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_bits 64 +#define GEN75_SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_bits 64 +#define GEN7_SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_bits 64 + +static inline uint32_t ATTRIBUTE_PURE +SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_start 0 +#define GEN10_SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_start 0 +#define GEN9_SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_start 0 +#define GEN8_SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_start 0 +#define GEN75_SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_start 0 +#define GEN7_SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_start 0 + +static inline uint32_t ATTRIBUTE_PURE +SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_PRIM_STORAGE_NEEDED1 */ + + +#define GEN11_SO_PRIM_STORAGE_NEEDED1_length 2 +#define GEN10_SO_PRIM_STORAGE_NEEDED1_length 2 +#define GEN9_SO_PRIM_STORAGE_NEEDED1_length 2 +#define GEN8_SO_PRIM_STORAGE_NEEDED1_length 2 +#define GEN75_SO_PRIM_STORAGE_NEEDED1_length 2 +#define GEN7_SO_PRIM_STORAGE_NEEDED1_length 2 + +static inline uint32_t ATTRIBUTE_PURE +SO_PRIM_STORAGE_NEEDED1_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_PRIM_STORAGE_NEEDED1::Prim Storage Needed Count */ + + +#define GEN11_SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_bits 64 +#define GEN10_SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_bits 64 +#define GEN9_SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_bits 64 +#define GEN8_SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_bits 64 +#define GEN75_SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_bits 64 +#define GEN7_SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_bits 64 + +static inline uint32_t ATTRIBUTE_PURE +SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_start 0 +#define GEN10_SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_start 0 +#define GEN9_SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_start 0 +#define GEN8_SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_start 0 +#define GEN75_SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_start 0 +#define GEN7_SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_start 0 + +static inline uint32_t ATTRIBUTE_PURE +SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_PRIM_STORAGE_NEEDED2 */ + + +#define GEN11_SO_PRIM_STORAGE_NEEDED2_length 2 +#define GEN10_SO_PRIM_STORAGE_NEEDED2_length 2 +#define GEN9_SO_PRIM_STORAGE_NEEDED2_length 2 +#define GEN8_SO_PRIM_STORAGE_NEEDED2_length 2 +#define GEN75_SO_PRIM_STORAGE_NEEDED2_length 2 +#define GEN7_SO_PRIM_STORAGE_NEEDED2_length 2 + +static inline uint32_t ATTRIBUTE_PURE +SO_PRIM_STORAGE_NEEDED2_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_PRIM_STORAGE_NEEDED2::Prim Storage Needed Count */ + + +#define GEN11_SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_bits 64 +#define GEN10_SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_bits 64 +#define GEN9_SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_bits 64 +#define GEN8_SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_bits 64 +#define GEN75_SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_bits 64 +#define GEN7_SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_bits 64 + +static inline uint32_t ATTRIBUTE_PURE +SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_start 0 +#define GEN10_SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_start 0 +#define GEN9_SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_start 0 +#define GEN8_SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_start 0 +#define GEN75_SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_start 0 +#define GEN7_SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_start 0 + +static inline uint32_t ATTRIBUTE_PURE +SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_PRIM_STORAGE_NEEDED3 */ + + +#define GEN11_SO_PRIM_STORAGE_NEEDED3_length 2 +#define GEN10_SO_PRIM_STORAGE_NEEDED3_length 2 +#define GEN9_SO_PRIM_STORAGE_NEEDED3_length 2 +#define GEN8_SO_PRIM_STORAGE_NEEDED3_length 2 +#define GEN75_SO_PRIM_STORAGE_NEEDED3_length 2 +#define GEN7_SO_PRIM_STORAGE_NEEDED3_length 2 + +static inline uint32_t ATTRIBUTE_PURE +SO_PRIM_STORAGE_NEEDED3_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_PRIM_STORAGE_NEEDED3::Prim Storage Needed Count */ + + +#define GEN11_SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_bits 64 +#define GEN10_SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_bits 64 +#define GEN9_SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_bits 64 +#define GEN8_SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_bits 64 +#define GEN75_SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_bits 64 +#define GEN7_SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_bits 64 + +static inline uint32_t ATTRIBUTE_PURE +SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_start 0 +#define GEN10_SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_start 0 +#define GEN9_SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_start 0 +#define GEN8_SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_start 0 +#define GEN75_SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_start 0 +#define GEN7_SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_start 0 + +static inline uint32_t ATTRIBUTE_PURE +SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + /* SO_WRITE_OFFSET0 */ @@ -216687,14 +217308,14 @@ STATE_BASE_ADDRESS_BindlessSamplerStateBufferSize_start(const struct gen_device_ -/* STATE_BASE_ADDRESS::Bindless Sampler State Memory Object Control State */ +/* STATE_BASE_ADDRESS::Bindless Sampler State MOCS */ -#define GEN11_STATE_BASE_ADDRESS_BindlessSamplerStateMemoryObjectControlState_bits 7 -#define GEN10_STATE_BASE_ADDRESS_BindlessSamplerStateMemoryObjectControlState_bits 7 +#define GEN11_STATE_BASE_ADDRESS_BindlessSamplerStateMOCS_bits 7 +#define GEN10_STATE_BASE_ADDRESS_BindlessSamplerStateMOCS_bits 7 static inline uint32_t ATTRIBUTE_PURE -STATE_BASE_ADDRESS_BindlessSamplerStateMemoryObjectControlState_bits(const struct gen_device_info *devinfo) +STATE_BASE_ADDRESS_BindlessSamplerStateMOCS_bits(const struct gen_device_info *devinfo) { switch (devinfo->gen) { case 11: return 7; @@ -216722,11 +217343,11 @@ STATE_BASE_ADDRESS_BindlessSamplerStateMemoryObjectControlState_bits(const struc -#define GEN11_STATE_BASE_ADDRESS_BindlessSamplerStateMemoryObjectControlState_start 612 -#define GEN10_STATE_BASE_ADDRESS_BindlessSamplerStateMemoryObjectControlState_start 612 +#define GEN11_STATE_BASE_ADDRESS_BindlessSamplerStateMOCS_start 612 +#define GEN10_STATE_BASE_ADDRESS_BindlessSamplerStateMOCS_start 612 static inline uint32_t ATTRIBUTE_PURE -STATE_BASE_ADDRESS_BindlessSamplerStateMemoryObjectControlState_start(const struct gen_device_info *devinfo) +STATE_BASE_ADDRESS_BindlessSamplerStateMOCS_start(const struct gen_device_info *devinfo) { switch (devinfo->gen) { case 11: return 612; @@ -216892,15 +217513,15 @@ STATE_BASE_ADDRESS_BindlessSurfaceStateBaseAddressModifyEnable_start(const struc -/* STATE_BASE_ADDRESS::Bindless Surface State Memory Object Control State */ +/* STATE_BASE_ADDRESS::Bindless Surface State MOCS */ -#define GEN11_STATE_BASE_ADDRESS_BindlessSurfaceStateMemoryObjectControlState_bits 7 -#define GEN10_STATE_BASE_ADDRESS_BindlessSurfaceStateMemoryObjectControlState_bits 7 -#define GEN9_STATE_BASE_ADDRESS_BindlessSurfaceStateMemoryObjectControlState_bits 7 +#define GEN11_STATE_BASE_ADDRESS_BindlessSurfaceStateMOCS_bits 7 +#define GEN10_STATE_BASE_ADDRESS_BindlessSurfaceStateMOCS_bits 7 +#define GEN9_STATE_BASE_ADDRESS_BindlessSurfaceStateMOCS_bits 7 static inline uint32_t ATTRIBUTE_PURE -STATE_BASE_ADDRESS_BindlessSurfaceStateMemoryObjectControlState_bits(const struct gen_device_info *devinfo) +STATE_BASE_ADDRESS_BindlessSurfaceStateMOCS_bits(const struct gen_device_info *devinfo) { switch (devinfo->gen) { case 11: return 7; @@ -216928,12 +217549,12 @@ STATE_BASE_ADDRESS_BindlessSurfaceStateMemoryObjectControlState_bits(const struc -#define GEN11_STATE_BASE_ADDRESS_BindlessSurfaceStateMemoryObjectControlState_start 516 -#define GEN10_STATE_BASE_ADDRESS_BindlessSurfaceStateMemoryObjectControlState_start 516 -#define GEN9_STATE_BASE_ADDRESS_BindlessSurfaceStateMemoryObjectControlState_start 516 +#define GEN11_STATE_BASE_ADDRESS_BindlessSurfaceStateMOCS_start 516 +#define GEN10_STATE_BASE_ADDRESS_BindlessSurfaceStateMOCS_start 516 +#define GEN9_STATE_BASE_ADDRESS_BindlessSurfaceStateMOCS_start 516 static inline uint32_t ATTRIBUTE_PURE -STATE_BASE_ADDRESS_BindlessSurfaceStateMemoryObjectControlState_start(const struct gen_device_info *devinfo) +STATE_BASE_ADDRESS_BindlessSurfaceStateMOCS_start(const struct gen_device_info *devinfo) { switch (devinfo->gen) { case 11: return 516; @@ -217716,83 +218337,18 @@ STATE_BASE_ADDRESS_DynamicStateBufferSizeModifyEnable_start(const struct gen_dev /* STATE_BASE_ADDRESS::Dynamic State MOCS */ +#define GEN11_STATE_BASE_ADDRESS_DynamicStateMOCS_bits 7 +#define GEN10_STATE_BASE_ADDRESS_DynamicStateMOCS_bits 7 +#define GEN9_STATE_BASE_ADDRESS_DynamicStateMOCS_bits 7 +#define GEN8_STATE_BASE_ADDRESS_DynamicStateMOCS_bits 7 +#define GEN75_STATE_BASE_ADDRESS_DynamicStateMOCS_bits 4 +#define GEN7_STATE_BASE_ADDRESS_DynamicStateMOCS_bits 4 #define GEN6_STATE_BASE_ADDRESS_DynamicStateMOCS_bits 4 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_DynamicStateMOCS_bits(const struct gen_device_info *devinfo) { switch (devinfo->gen) { - case 11: return 0; - case 10: return 0; - case 9: return 0; - case 8: return 0; - case 7: - if (devinfo->is_haswell) { - return 0; - } else { - return 0; - } - case 6: return 4; - case 5: return 0; - case 4: - if (devinfo->is_g4x) { - return 0; - } else { - return 0; - } - default: - unreachable("Invalid hardware generation"); - } -} - - - -#define GEN6_STATE_BASE_ADDRESS_DynamicStateMOCS_start 104 - -static inline uint32_t ATTRIBUTE_PURE -STATE_BASE_ADDRESS_DynamicStateMOCS_start(const struct gen_device_info *devinfo) -{ - switch (devinfo->gen) { - case 11: return 0; - case 10: return 0; - case 9: return 0; - case 8: return 0; - case 7: - if (devinfo->is_haswell) { - return 0; - } else { - return 0; - } - case 6: return 104; - case 5: return 0; - case 4: - if (devinfo->is_g4x) { - return 0; - } else { - return 0; - } - default: - unreachable("Invalid hardware generation"); - } -} - - - -/* STATE_BASE_ADDRESS::Dynamic State Memory Object Control State */ - - -#define GEN11_STATE_BASE_ADDRESS_DynamicStateMemoryObjectControlState_bits 7 -#define GEN10_STATE_BASE_ADDRESS_DynamicStateMemoryObjectControlState_bits 7 -#define GEN9_STATE_BASE_ADDRESS_DynamicStateMemoryObjectControlState_bits 7 -#define GEN8_STATE_BASE_ADDRESS_DynamicStateMemoryObjectControlState_bits 7 -#define GEN75_STATE_BASE_ADDRESS_DynamicStateMemoryObjectControlState_bits 4 -#define GEN7_STATE_BASE_ADDRESS_DynamicStateMemoryObjectControlState_bits 4 -#define GEN6_STATE_BASE_ADDRESS_DynamicStateMemoryObjectControlState_bits 4 - -static inline uint32_t ATTRIBUTE_PURE -STATE_BASE_ADDRESS_DynamicStateMemoryObjectControlState_bits(const struct gen_device_info *devinfo) -{ - switch (devinfo->gen) { case 11: return 7; case 10: return 7; case 9: return 7; @@ -217818,16 +218374,16 @@ STATE_BASE_ADDRESS_DynamicStateMemoryObjectControlState_bits(const struct gen_de -#define GEN11_STATE_BASE_ADDRESS_DynamicStateMemoryObjectControlState_start 196 -#define GEN10_STATE_BASE_ADDRESS_DynamicStateMemoryObjectControlState_start 196 -#define GEN9_STATE_BASE_ADDRESS_DynamicStateMemoryObjectControlState_start 196 -#define GEN8_STATE_BASE_ADDRESS_DynamicStateMemoryObjectControlState_start 196 -#define GEN75_STATE_BASE_ADDRESS_DynamicStateMemoryObjectControlState_start 104 -#define GEN7_STATE_BASE_ADDRESS_DynamicStateMemoryObjectControlState_start 104 -#define GEN6_STATE_BASE_ADDRESS_DynamicStateMemoryObjectControlState_start 104 +#define GEN11_STATE_BASE_ADDRESS_DynamicStateMOCS_start 196 +#define GEN10_STATE_BASE_ADDRESS_DynamicStateMOCS_start 196 +#define GEN9_STATE_BASE_ADDRESS_DynamicStateMOCS_start 196 +#define GEN8_STATE_BASE_ADDRESS_DynamicStateMOCS_start 196 +#define GEN75_STATE_BASE_ADDRESS_DynamicStateMOCS_start 104 +#define GEN7_STATE_BASE_ADDRESS_DynamicStateMOCS_start 104 +#define GEN6_STATE_BASE_ADDRESS_DynamicStateMOCS_start 104 static inline uint32_t ATTRIBUTE_PURE -STATE_BASE_ADDRESS_DynamicStateMemoryObjectControlState_start(const struct gen_device_info *devinfo) +STATE_BASE_ADDRESS_DynamicStateMOCS_start(const struct gen_device_info *devinfo) { switch (devinfo->gen) { case 11: return 196; @@ -218316,83 +218872,18 @@ STATE_BASE_ADDRESS_GeneralStateBufferSizeModifyEnable_start(const struct gen_dev /* STATE_BASE_ADDRESS::General State MOCS */ +#define GEN11_STATE_BASE_ADDRESS_GeneralStateMOCS_bits 7 +#define GEN10_STATE_BASE_ADDRESS_GeneralStateMOCS_bits 7 +#define GEN9_STATE_BASE_ADDRESS_GeneralStateMOCS_bits 7 +#define GEN8_STATE_BASE_ADDRESS_GeneralStateMOCS_bits 7 +#define GEN75_STATE_BASE_ADDRESS_GeneralStateMOCS_bits 4 +#define GEN7_STATE_BASE_ADDRESS_GeneralStateMOCS_bits 4 #define GEN6_STATE_BASE_ADDRESS_GeneralStateMOCS_bits 4 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_GeneralStateMOCS_bits(const struct gen_device_info *devinfo) { switch (devinfo->gen) { - case 11: return 0; - case 10: return 0; - case 9: return 0; - case 8: return 0; - case 7: - if (devinfo->is_haswell) { - return 0; - } else { - return 0; - } - case 6: return 4; - case 5: return 0; - case 4: - if (devinfo->is_g4x) { - return 0; - } else { - return 0; - } - default: - unreachable("Invalid hardware generation"); - } -} - - - -#define GEN6_STATE_BASE_ADDRESS_GeneralStateMOCS_start 40 - -static inline uint32_t ATTRIBUTE_PURE -STATE_BASE_ADDRESS_GeneralStateMOCS_start(const struct gen_device_info *devinfo) -{ - switch (devinfo->gen) { - case 11: return 0; - case 10: return 0; - case 9: return 0; - case 8: return 0; - case 7: - if (devinfo->is_haswell) { - return 0; - } else { - return 0; - } - case 6: return 40; - case 5: return 0; - case 4: - if (devinfo->is_g4x) { - return 0; - } else { - return 0; - } - default: - unreachable("Invalid hardware generation"); - } -} - - - -/* STATE_BASE_ADDRESS::General State Memory Object Control State */ - - -#define GEN11_STATE_BASE_ADDRESS_GeneralStateMemoryObjectControlState_bits 7 -#define GEN10_STATE_BASE_ADDRESS_GeneralStateMemoryObjectControlState_bits 7 -#define GEN9_STATE_BASE_ADDRESS_GeneralStateMemoryObjectControlState_bits 7 -#define GEN8_STATE_BASE_ADDRESS_GeneralStateMemoryObjectControlState_bits 7 -#define GEN75_STATE_BASE_ADDRESS_GeneralStateMemoryObjectControlState_bits 4 -#define GEN7_STATE_BASE_ADDRESS_GeneralStateMemoryObjectControlState_bits 4 -#define GEN6_STATE_BASE_ADDRESS_GeneralStateMemoryObjectControlState_bits 4 - -static inline uint32_t ATTRIBUTE_PURE -STATE_BASE_ADDRESS_GeneralStateMemoryObjectControlState_bits(const struct gen_device_info *devinfo) -{ - switch (devinfo->gen) { case 11: return 7; case 10: return 7; case 9: return 7; @@ -218418,16 +218909,16 @@ STATE_BASE_ADDRESS_GeneralStateMemoryObjectControlState_bits(const struct gen_de -#define GEN11_STATE_BASE_ADDRESS_GeneralStateMemoryObjectControlState_start 36 -#define GEN10_STATE_BASE_ADDRESS_GeneralStateMemoryObjectControlState_start 36 -#define GEN9_STATE_BASE_ADDRESS_GeneralStateMemoryObjectControlState_start 36 -#define GEN8_STATE_BASE_ADDRESS_GeneralStateMemoryObjectControlState_start 36 -#define GEN75_STATE_BASE_ADDRESS_GeneralStateMemoryObjectControlState_start 40 -#define GEN7_STATE_BASE_ADDRESS_GeneralStateMemoryObjectControlState_start 40 -#define GEN6_STATE_BASE_ADDRESS_GeneralStateMemoryObjectControlState_start 40 +#define GEN11_STATE_BASE_ADDRESS_GeneralStateMOCS_start 36 +#define GEN10_STATE_BASE_ADDRESS_GeneralStateMOCS_start 36 +#define GEN9_STATE_BASE_ADDRESS_GeneralStateMOCS_start 36 +#define GEN8_STATE_BASE_ADDRESS_GeneralStateMOCS_start 36 +#define GEN75_STATE_BASE_ADDRESS_GeneralStateMOCS_start 40 +#define GEN7_STATE_BASE_ADDRESS_GeneralStateMOCS_start 40 +#define GEN6_STATE_BASE_ADDRESS_GeneralStateMOCS_start 40 static inline uint32_t ATTRIBUTE_PURE -STATE_BASE_ADDRESS_GeneralStateMemoryObjectControlState_start(const struct gen_device_info *devinfo) +STATE_BASE_ADDRESS_GeneralStateMOCS_start(const struct gen_device_info *devinfo) { switch (devinfo->gen) { case 11: return 36; @@ -218912,83 +219403,18 @@ STATE_BASE_ADDRESS_IndirectObjectBufferSizeModifyEnable_start(const struct gen_d /* STATE_BASE_ADDRESS::Indirect Object MOCS */ +#define GEN11_STATE_BASE_ADDRESS_IndirectObjectMOCS_bits 7 +#define GEN10_STATE_BASE_ADDRESS_IndirectObjectMOCS_bits 7 +#define GEN9_STATE_BASE_ADDRESS_IndirectObjectMOCS_bits 7 +#define GEN8_STATE_BASE_ADDRESS_IndirectObjectMOCS_bits 7 +#define GEN75_STATE_BASE_ADDRESS_IndirectObjectMOCS_bits 4 +#define GEN7_STATE_BASE_ADDRESS_IndirectObjectMOCS_bits 4 #define GEN6_STATE_BASE_ADDRESS_IndirectObjectMOCS_bits 4 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_IndirectObjectMOCS_bits(const struct gen_device_info *devinfo) { switch (devinfo->gen) { - case 11: return 0; - case 10: return 0; - case 9: return 0; - case 8: return 0; - case 7: - if (devinfo->is_haswell) { - return 0; - } else { - return 0; - } - case 6: return 4; - case 5: return 0; - case 4: - if (devinfo->is_g4x) { - return 0; - } else { - return 0; - } - default: - unreachable("Invalid hardware generation"); - } -} - - - -#define GEN6_STATE_BASE_ADDRESS_IndirectObjectMOCS_start 136 - -static inline uint32_t ATTRIBUTE_PURE -STATE_BASE_ADDRESS_IndirectObjectMOCS_start(const struct gen_device_info *devinfo) -{ - switch (devinfo->gen) { - case 11: return 0; - case 10: return 0; - case 9: return 0; - case 8: return 0; - case 7: - if (devinfo->is_haswell) { - return 0; - } else { - return 0; - } - case 6: return 136; - case 5: return 0; - case 4: - if (devinfo->is_g4x) { - return 0; - } else { - return 0; - } - default: - unreachable("Invalid hardware generation"); - } -} - - - -/* STATE_BASE_ADDRESS::Indirect Object Memory Object Control State */ - - -#define GEN11_STATE_BASE_ADDRESS_IndirectObjectMemoryObjectControlState_bits 7 -#define GEN10_STATE_BASE_ADDRESS_IndirectObjectMemoryObjectControlState_bits 7 -#define GEN9_STATE_BASE_ADDRESS_IndirectObjectMemoryObjectControlState_bits 7 -#define GEN8_STATE_BASE_ADDRESS_IndirectObjectMemoryObjectControlState_bits 7 -#define GEN75_STATE_BASE_ADDRESS_IndirectObjectMemoryObjectControlState_bits 4 -#define GEN7_STATE_BASE_ADDRESS_IndirectObjectMemoryObjectControlState_bits 4 -#define GEN6_STATE_BASE_ADDRESS_IndirectObjectMemoryObjectControlState_bits 4 - -static inline uint32_t ATTRIBUTE_PURE -STATE_BASE_ADDRESS_IndirectObjectMemoryObjectControlState_bits(const struct gen_device_info *devinfo) -{ - switch (devinfo->gen) { case 11: return 7; case 10: return 7; case 9: return 7; @@ -219014,16 +219440,16 @@ STATE_BASE_ADDRESS_IndirectObjectMemoryObjectControlState_bits(const struct gen_ -#define GEN11_STATE_BASE_ADDRESS_IndirectObjectMemoryObjectControlState_start 260 -#define GEN10_STATE_BASE_ADDRESS_IndirectObjectMemoryObjectControlState_start 260 -#define GEN9_STATE_BASE_ADDRESS_IndirectObjectMemoryObjectControlState_start 260 -#define GEN8_STATE_BASE_ADDRESS_IndirectObjectMemoryObjectControlState_start 260 -#define GEN75_STATE_BASE_ADDRESS_IndirectObjectMemoryObjectControlState_start 136 -#define GEN7_STATE_BASE_ADDRESS_IndirectObjectMemoryObjectControlState_start 136 -#define GEN6_STATE_BASE_ADDRESS_IndirectObjectMemoryObjectControlState_start 136 +#define GEN11_STATE_BASE_ADDRESS_IndirectObjectMOCS_start 260 +#define GEN10_STATE_BASE_ADDRESS_IndirectObjectMOCS_start 260 +#define GEN9_STATE_BASE_ADDRESS_IndirectObjectMOCS_start 260 +#define GEN8_STATE_BASE_ADDRESS_IndirectObjectMOCS_start 260 +#define GEN75_STATE_BASE_ADDRESS_IndirectObjectMOCS_start 136 +#define GEN7_STATE_BASE_ADDRESS_IndirectObjectMOCS_start 136 +#define GEN6_STATE_BASE_ADDRESS_IndirectObjectMOCS_start 136 static inline uint32_t ATTRIBUTE_PURE -STATE_BASE_ADDRESS_IndirectObjectMemoryObjectControlState_start(const struct gen_device_info *devinfo) +STATE_BASE_ADDRESS_IndirectObjectMOCS_start(const struct gen_device_info *devinfo) { switch (devinfo->gen) { case 11: return 260; @@ -219500,83 +219926,18 @@ STATE_BASE_ADDRESS_InstructionBuffersizeModifyEnable_start(const struct gen_devi /* STATE_BASE_ADDRESS::Instruction MOCS */ +#define GEN11_STATE_BASE_ADDRESS_InstructionMOCS_bits 7 +#define GEN10_STATE_BASE_ADDRESS_InstructionMOCS_bits 7 +#define GEN9_STATE_BASE_ADDRESS_InstructionMOCS_bits 7 +#define GEN8_STATE_BASE_ADDRESS_InstructionMOCS_bits 7 +#define GEN75_STATE_BASE_ADDRESS_InstructionMOCS_bits 4 +#define GEN7_STATE_BASE_ADDRESS_InstructionMOCS_bits 4 #define GEN6_STATE_BASE_ADDRESS_InstructionMOCS_bits 4 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_InstructionMOCS_bits(const struct gen_device_info *devinfo) { switch (devinfo->gen) { - case 11: return 0; - case 10: return 0; - case 9: return 0; - case 8: return 0; - case 7: - if (devinfo->is_haswell) { - return 0; - } else { - return 0; - } - case 6: return 4; - case 5: return 0; - case 4: - if (devinfo->is_g4x) { - return 0; - } else { - return 0; - } - default: - unreachable("Invalid hardware generation"); - } -} - - - -#define GEN6_STATE_BASE_ADDRESS_InstructionMOCS_start 168 - -static inline uint32_t ATTRIBUTE_PURE -STATE_BASE_ADDRESS_InstructionMOCS_start(const struct gen_device_info *devinfo) -{ - switch (devinfo->gen) { - case 11: return 0; - case 10: return 0; - case 9: return 0; - case 8: return 0; - case 7: - if (devinfo->is_haswell) { - return 0; - } else { - return 0; - } - case 6: return 168; - case 5: return 0; - case 4: - if (devinfo->is_g4x) { - return 0; - } else { - return 0; - } - default: - unreachable("Invalid hardware generation"); - } -} - - - -/* STATE_BASE_ADDRESS::Instruction Memory Object Control State */ - - -#define GEN11_STATE_BASE_ADDRESS_InstructionMemoryObjectControlState_bits 7 -#define GEN10_STATE_BASE_ADDRESS_InstructionMemoryObjectControlState_bits 7 -#define GEN9_STATE_BASE_ADDRESS_InstructionMemoryObjectControlState_bits 7 -#define GEN8_STATE_BASE_ADDRESS_InstructionMemoryObjectControlState_bits 7 -#define GEN75_STATE_BASE_ADDRESS_InstructionMemoryObjectControlState_bits 4 -#define GEN7_STATE_BASE_ADDRESS_InstructionMemoryObjectControlState_bits 4 -#define GEN6_STATE_BASE_ADDRESS_InstructionMemoryObjectControlState_bits 4 - -static inline uint32_t ATTRIBUTE_PURE -STATE_BASE_ADDRESS_InstructionMemoryObjectControlState_bits(const struct gen_device_info *devinfo) -{ - switch (devinfo->gen) { case 11: return 7; case 10: return 7; case 9: return 7; @@ -219602,16 +219963,16 @@ STATE_BASE_ADDRESS_InstructionMemoryObjectControlState_bits(const struct gen_dev -#define GEN11_STATE_BASE_ADDRESS_InstructionMemoryObjectControlState_start 324 -#define GEN10_STATE_BASE_ADDRESS_InstructionMemoryObjectControlState_start 324 -#define GEN9_STATE_BASE_ADDRESS_InstructionMemoryObjectControlState_start 324 -#define GEN8_STATE_BASE_ADDRESS_InstructionMemoryObjectControlState_start 324 -#define GEN75_STATE_BASE_ADDRESS_InstructionMemoryObjectControlState_start 168 -#define GEN7_STATE_BASE_ADDRESS_InstructionMemoryObjectControlState_start 168 -#define GEN6_STATE_BASE_ADDRESS_InstructionMemoryObjectControlState_start 168 +#define GEN11_STATE_BASE_ADDRESS_InstructionMOCS_start 324 +#define GEN10_STATE_BASE_ADDRESS_InstructionMOCS_start 324 +#define GEN9_STATE_BASE_ADDRESS_InstructionMOCS_start 324 +#define GEN8_STATE_BASE_ADDRESS_InstructionMOCS_start 324 +#define GEN75_STATE_BASE_ADDRESS_InstructionMOCS_start 168 +#define GEN7_STATE_BASE_ADDRESS_InstructionMOCS_start 168 +#define GEN6_STATE_BASE_ADDRESS_InstructionMOCS_start 168 static inline uint32_t ATTRIBUTE_PURE -STATE_BASE_ADDRESS_InstructionMemoryObjectControlState_start(const struct gen_device_info *devinfo) +STATE_BASE_ADDRESS_InstructionMOCS_start(const struct gen_device_info *devinfo) { switch (devinfo->gen) { case 11: return 324; @@ -219709,83 +220070,18 @@ STATE_BASE_ADDRESS_StatelessDataPortAccessForceWriteThru_start(const struct gen_ /* STATE_BASE_ADDRESS::Stateless Data Port Access MOCS */ +#define GEN11_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_bits 7 +#define GEN10_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_bits 7 +#define GEN9_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_bits 7 +#define GEN8_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_bits 7 +#define GEN75_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_bits 4 +#define GEN7_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_bits 4 #define GEN6_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_bits 4 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_bits(const struct gen_device_info *devinfo) { switch (devinfo->gen) { - case 11: return 0; - case 10: return 0; - case 9: return 0; - case 8: return 0; - case 7: - if (devinfo->is_haswell) { - return 0; - } else { - return 0; - } - case 6: return 4; - case 5: return 0; - case 4: - if (devinfo->is_g4x) { - return 0; - } else { - return 0; - } - default: - unreachable("Invalid hardware generation"); - } -} - - - -#define GEN6_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_start 36 - -static inline uint32_t ATTRIBUTE_PURE -STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_start(const struct gen_device_info *devinfo) -{ - switch (devinfo->gen) { - case 11: return 0; - case 10: return 0; - case 9: return 0; - case 8: return 0; - case 7: - if (devinfo->is_haswell) { - return 0; - } else { - return 0; - } - case 6: return 36; - case 5: return 0; - case 4: - if (devinfo->is_g4x) { - return 0; - } else { - return 0; - } - default: - unreachable("Invalid hardware generation"); - } -} - - - -/* STATE_BASE_ADDRESS::Stateless Data Port Access Memory Object Control State */ - - -#define GEN11_STATE_BASE_ADDRESS_StatelessDataPortAccessMemoryObjectControlState_bits 7 -#define GEN10_STATE_BASE_ADDRESS_StatelessDataPortAccessMemoryObjectControlState_bits 7 -#define GEN9_STATE_BASE_ADDRESS_StatelessDataPortAccessMemoryObjectControlState_bits 7 -#define GEN8_STATE_BASE_ADDRESS_StatelessDataPortAccessMemoryObjectControlState_bits 7 -#define GEN75_STATE_BASE_ADDRESS_StatelessDataPortAccessMemoryObjectControlState_bits 4 -#define GEN7_STATE_BASE_ADDRESS_StatelessDataPortAccessMemoryObjectControlState_bits 4 -#define GEN6_STATE_BASE_ADDRESS_StatelessDataPortAccessMemoryObjectControlState_bits 4 - -static inline uint32_t ATTRIBUTE_PURE -STATE_BASE_ADDRESS_StatelessDataPortAccessMemoryObjectControlState_bits(const struct gen_device_info *devinfo) -{ - switch (devinfo->gen) { case 11: return 7; case 10: return 7; case 9: return 7; @@ -219811,16 +220107,16 @@ STATE_BASE_ADDRESS_StatelessDataPortAccessMemoryObjectControlState_bits(const st -#define GEN11_STATE_BASE_ADDRESS_StatelessDataPortAccessMemoryObjectControlState_start 112 -#define GEN10_STATE_BASE_ADDRESS_StatelessDataPortAccessMemoryObjectControlState_start 112 -#define GEN9_STATE_BASE_ADDRESS_StatelessDataPortAccessMemoryObjectControlState_start 112 -#define GEN8_STATE_BASE_ADDRESS_StatelessDataPortAccessMemoryObjectControlState_start 112 -#define GEN75_STATE_BASE_ADDRESS_StatelessDataPortAccessMemoryObjectControlState_start 36 -#define GEN7_STATE_BASE_ADDRESS_StatelessDataPortAccessMemoryObjectControlState_start 36 -#define GEN6_STATE_BASE_ADDRESS_StatelessDataPortAccessMemoryObjectControlState_start 36 +#define GEN11_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_start 112 +#define GEN10_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_start 112 +#define GEN9_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_start 112 +#define GEN8_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_start 112 +#define GEN75_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_start 36 +#define GEN7_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_start 36 +#define GEN6_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_start 36 static inline uint32_t ATTRIBUTE_PURE -STATE_BASE_ADDRESS_StatelessDataPortAccessMemoryObjectControlState_start(const struct gen_device_info *devinfo) +STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_start(const struct gen_device_info *devinfo) { switch (devinfo->gen) { case 11: return 112; @@ -220017,83 +220313,18 @@ STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_start(const struct gen_de /* STATE_BASE_ADDRESS::Surface State MOCS */ +#define GEN11_STATE_BASE_ADDRESS_SurfaceStateMOCS_bits 7 +#define GEN10_STATE_BASE_ADDRESS_SurfaceStateMOCS_bits 7 +#define GEN9_STATE_BASE_ADDRESS_SurfaceStateMOCS_bits 7 +#define GEN8_STATE_BASE_ADDRESS_SurfaceStateMOCS_bits 7 +#define GEN75_STATE_BASE_ADDRESS_SurfaceStateMOCS_bits 4 +#define GEN7_STATE_BASE_ADDRESS_SurfaceStateMOCS_bits 4 #define GEN6_STATE_BASE_ADDRESS_SurfaceStateMOCS_bits 4 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_SurfaceStateMOCS_bits(const struct gen_device_info *devinfo) { switch (devinfo->gen) { - case 11: return 0; - case 10: return 0; - case 9: return 0; - case 8: return 0; - case 7: - if (devinfo->is_haswell) { - return 0; - } else { - return 0; - } - case 6: return 4; - case 5: return 0; - case 4: - if (devinfo->is_g4x) { - return 0; - } else { - return 0; - } - default: - unreachable("Invalid hardware generation"); - } -} - - - -#define GEN6_STATE_BASE_ADDRESS_SurfaceStateMOCS_start 72 - -static inline uint32_t ATTRIBUTE_PURE -STATE_BASE_ADDRESS_SurfaceStateMOCS_start(const struct gen_device_info *devinfo) -{ - switch (devinfo->gen) { - case 11: return 0; - case 10: return 0; - case 9: return 0; - case 8: return 0; - case 7: - if (devinfo->is_haswell) { - return 0; - } else { - return 0; - } - case 6: return 72; - case 5: return 0; - case 4: - if (devinfo->is_g4x) { - return 0; - } else { - return 0; - } - default: - unreachable("Invalid hardware generation"); - } -} - - - -/* STATE_BASE_ADDRESS::Surface State Memory Object Control State */ - - -#define GEN11_STATE_BASE_ADDRESS_SurfaceStateMemoryObjectControlState_bits 7 -#define GEN10_STATE_BASE_ADDRESS_SurfaceStateMemoryObjectControlState_bits 7 -#define GEN9_STATE_BASE_ADDRESS_SurfaceStateMemoryObjectControlState_bits 7 -#define GEN8_STATE_BASE_ADDRESS_SurfaceStateMemoryObjectControlState_bits 7 -#define GEN75_STATE_BASE_ADDRESS_SurfaceStateMemoryObjectControlState_bits 4 -#define GEN7_STATE_BASE_ADDRESS_SurfaceStateMemoryObjectControlState_bits 4 -#define GEN6_STATE_BASE_ADDRESS_SurfaceStateMemoryObjectControlState_bits 4 - -static inline uint32_t ATTRIBUTE_PURE -STATE_BASE_ADDRESS_SurfaceStateMemoryObjectControlState_bits(const struct gen_device_info *devinfo) -{ - switch (devinfo->gen) { case 11: return 7; case 10: return 7; case 9: return 7; @@ -220119,16 +220350,16 @@ STATE_BASE_ADDRESS_SurfaceStateMemoryObjectControlState_bits(const struct gen_de -#define GEN11_STATE_BASE_ADDRESS_SurfaceStateMemoryObjectControlState_start 132 -#define GEN10_STATE_BASE_ADDRESS_SurfaceStateMemoryObjectControlState_start 132 -#define GEN9_STATE_BASE_ADDRESS_SurfaceStateMemoryObjectControlState_start 132 -#define GEN8_STATE_BASE_ADDRESS_SurfaceStateMemoryObjectControlState_start 132 -#define GEN75_STATE_BASE_ADDRESS_SurfaceStateMemoryObjectControlState_start 72 -#define GEN7_STATE_BASE_ADDRESS_SurfaceStateMemoryObjectControlState_start 72 -#define GEN6_STATE_BASE_ADDRESS_SurfaceStateMemoryObjectControlState_start 72 +#define GEN11_STATE_BASE_ADDRESS_SurfaceStateMOCS_start 132 +#define GEN10_STATE_BASE_ADDRESS_SurfaceStateMOCS_start 132 +#define GEN9_STATE_BASE_ADDRESS_SurfaceStateMOCS_start 132 +#define GEN8_STATE_BASE_ADDRESS_SurfaceStateMOCS_start 132 +#define GEN75_STATE_BASE_ADDRESS_SurfaceStateMOCS_start 72 +#define GEN7_STATE_BASE_ADDRESS_SurfaceStateMOCS_start 72 +#define GEN6_STATE_BASE_ADDRESS_SurfaceStateMOCS_start 72 static inline uint32_t ATTRIBUTE_PURE -STATE_BASE_ADDRESS_SurfaceStateMemoryObjectControlState_start(const struct gen_device_info *devinfo) +STATE_BASE_ADDRESS_SurfaceStateMOCS_start(const struct gen_device_info *devinfo) { switch (devinfo->gen) { case 11: return 132; @@ -221696,15 +221927,15 @@ SWTESS_BASE_ADDRESS_SWTessellationBaseAddress_start(const struct gen_device_info -/* SWTESS_BASE_ADDRESS::SW Tessellation Memory Object Control State */ +/* SWTESS_BASE_ADDRESS::SW Tessellation MOCS */ -#define GEN8_SWTESS_BASE_ADDRESS_SWTessellationMemoryObjectControlState_bits 4 -#define GEN75_SWTESS_BASE_ADDRESS_SWTessellationMemoryObjectControlState_bits 4 -#define GEN7_SWTESS_BASE_ADDRESS_SWTessellationMemoryObjectControlState_bits 4 +#define GEN8_SWTESS_BASE_ADDRESS_SWTessellationMOCS_bits 4 +#define GEN75_SWTESS_BASE_ADDRESS_SWTessellationMOCS_bits 4 +#define GEN7_SWTESS_BASE_ADDRESS_SWTessellationMOCS_bits 4 static inline uint32_t ATTRIBUTE_PURE -SWTESS_BASE_ADDRESS_SWTessellationMemoryObjectControlState_bits(const struct gen_device_info *devinfo) +SWTESS_BASE_ADDRESS_SWTessellationMOCS_bits(const struct gen_device_info *devinfo) { switch (devinfo->gen) { case 11: return 0; @@ -221732,12 +221963,12 @@ SWTESS_BASE_ADDRESS_SWTessellationMemoryObjectControlState_bits(const struct gen -#define GEN8_SWTESS_BASE_ADDRESS_SWTessellationMemoryObjectControlState_start 40 -#define GEN75_SWTESS_BASE_ADDRESS_SWTessellationMemoryObjectControlState_start 40 -#define GEN7_SWTESS_BASE_ADDRESS_SWTessellationMemoryObjectControlState_start 40 +#define GEN8_SWTESS_BASE_ADDRESS_SWTessellationMOCS_start 40 +#define GEN75_SWTESS_BASE_ADDRESS_SWTessellationMOCS_start 40 +#define GEN7_SWTESS_BASE_ADDRESS_SWTessellationMOCS_start 40 static inline uint32_t ATTRIBUTE_PURE -SWTESS_BASE_ADDRESS_SWTessellationMemoryObjectControlState_start(const struct gen_device_info *devinfo) +SWTESS_BASE_ADDRESS_SWTessellationMOCS_start(const struct gen_device_info *devinfo) { switch (devinfo->gen) { case 11: return 0; @@ -228605,33 +228836,38 @@ VERTEX_BUFFER_STATE_InstanceDataStepRate_start(const struct gen_device_info *dev -/* VERTEX_BUFFER_STATE::Max Index */ +/* VERTEX_BUFFER_STATE::MOCS */ -#define GEN45_VERTEX_BUFFER_STATE_MaxIndex_bits 32 -#define GEN4_VERTEX_BUFFER_STATE_MaxIndex_bits 32 +#define GEN11_VERTEX_BUFFER_STATE_MOCS_bits 7 +#define GEN10_VERTEX_BUFFER_STATE_MOCS_bits 7 +#define GEN9_VERTEX_BUFFER_STATE_MOCS_bits 7 +#define GEN8_VERTEX_BUFFER_STATE_MOCS_bits 7 +#define GEN75_VERTEX_BUFFER_STATE_MOCS_bits 4 +#define GEN7_VERTEX_BUFFER_STATE_MOCS_bits 4 +#define GEN6_VERTEX_BUFFER_STATE_MOCS_bits 4 static inline uint32_t ATTRIBUTE_PURE -VERTEX_BUFFER_STATE_MaxIndex_bits(const struct gen_device_info *devinfo) +VERTEX_BUFFER_STATE_MOCS_bits(const struct gen_device_info *devinfo) { switch (devinfo->gen) { - case 11: return 0; - case 10: return 0; - case 9: return 0; - case 8: return 0; + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; case 7: if (devinfo->is_haswell) { - return 0; + return 4; } else { - return 0; + return 4; } - case 6: return 0; + case 6: return 4; case 5: return 0; case 4: if (devinfo->is_g4x) { - return 32; + return 0; } else { - return 32; + return 0; } default: unreachable("Invalid hardware generation"); @@ -228640,30 +228876,35 @@ VERTEX_BUFFER_STATE_MaxIndex_bits(const struct gen_device_info *devinfo) -#define GEN45_VERTEX_BUFFER_STATE_MaxIndex_start 64 -#define GEN4_VERTEX_BUFFER_STATE_MaxIndex_start 64 +#define GEN11_VERTEX_BUFFER_STATE_MOCS_start 16 +#define GEN10_VERTEX_BUFFER_STATE_MOCS_start 16 +#define GEN9_VERTEX_BUFFER_STATE_MOCS_start 16 +#define GEN8_VERTEX_BUFFER_STATE_MOCS_start 16 +#define GEN75_VERTEX_BUFFER_STATE_MOCS_start 16 +#define GEN7_VERTEX_BUFFER_STATE_MOCS_start 16 +#define GEN6_VERTEX_BUFFER_STATE_MOCS_start 16 static inline uint32_t ATTRIBUTE_PURE -VERTEX_BUFFER_STATE_MaxIndex_start(const struct gen_device_info *devinfo) +VERTEX_BUFFER_STATE_MOCS_start(const struct gen_device_info *devinfo) { switch (devinfo->gen) { - case 11: return 0; - case 10: return 0; - case 9: return 0; - case 8: return 0; + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; case 7: if (devinfo->is_haswell) { - return 0; + return 16; } else { - return 0; + return 16; } - case 6: return 0; + case 6: return 16; case 5: return 0; case 4: if (devinfo->is_g4x) { - return 64; + return 0; } else { - return 64; + return 0; } default: unreachable("Invalid hardware generation"); @@ -228672,22 +228913,20 @@ VERTEX_BUFFER_STATE_MaxIndex_start(const struct gen_device_info *devinfo) -/* VERTEX_BUFFER_STATE::Memory Object Control State */ +/* VERTEX_BUFFER_STATE::Max Index */ -#define GEN11_VERTEX_BUFFER_STATE_MemoryObjectControlState_bits 7 -#define GEN10_VERTEX_BUFFER_STATE_MemoryObjectControlState_bits 7 -#define GEN9_VERTEX_BUFFER_STATE_MemoryObjectControlState_bits 7 -#define GEN8_VERTEX_BUFFER_STATE_MemoryObjectControlState_bits 7 +#define GEN45_VERTEX_BUFFER_STATE_MaxIndex_bits 32 +#define GEN4_VERTEX_BUFFER_STATE_MaxIndex_bits 32 static inline uint32_t ATTRIBUTE_PURE -VERTEX_BUFFER_STATE_MemoryObjectControlState_bits(const struct gen_device_info *devinfo) +VERTEX_BUFFER_STATE_MaxIndex_bits(const struct gen_device_info *devinfo) { switch (devinfo->gen) { - case 11: return 7; - case 10: return 7; - case 9: return 7; - case 8: return 7; + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; case 7: if (devinfo->is_haswell) { return 0; @@ -228698,9 +228937,9 @@ VERTEX_BUFFER_STATE_MemoryObjectControlState_bits(const struct gen_device_info * case 5: return 0; case 4: if (devinfo->is_g4x) { - return 0; + return 32; } else { - return 0; + return 32; } default: unreachable("Invalid hardware generation"); @@ -228709,19 +228948,17 @@ VERTEX_BUFFER_STATE_MemoryObjectControlState_bits(const struct gen_device_info * -#define GEN11_VERTEX_BUFFER_STATE_MemoryObjectControlState_start 16 -#define GEN10_VERTEX_BUFFER_STATE_MemoryObjectControlState_start 16 -#define GEN9_VERTEX_BUFFER_STATE_MemoryObjectControlState_start 16 -#define GEN8_VERTEX_BUFFER_STATE_MemoryObjectControlState_start 16 +#define GEN45_VERTEX_BUFFER_STATE_MaxIndex_start 64 +#define GEN4_VERTEX_BUFFER_STATE_MaxIndex_start 64 static inline uint32_t ATTRIBUTE_PURE -VERTEX_BUFFER_STATE_MemoryObjectControlState_start(const struct gen_device_info *devinfo) +VERTEX_BUFFER_STATE_MaxIndex_start(const struct gen_device_info *devinfo) { switch (devinfo->gen) { - case 11: return 16; - case 10: return 16; - case 9: return 16; - case 8: return 16; + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; case 7: if (devinfo->is_haswell) { return 0; @@ -228732,9 +228969,9 @@ VERTEX_BUFFER_STATE_MemoryObjectControlState_start(const struct gen_device_info case 5: return 0; case 4: if (devinfo->is_g4x) { - return 0; + return 64; } else { - return 0; + return 64; } default: unreachable("Invalid hardware generation"); @@ -228905,152 +229142,6 @@ VERTEX_BUFFER_STATE_VertexBufferIndex_start(const struct gen_device_info *devinf -/* VERTEX_BUFFER_STATE::Vertex Buffer MOCS */ - - -#define GEN11_VERTEX_BUFFER_STATE_VertexBufferMOCS_bits 7 -#define GEN10_VERTEX_BUFFER_STATE_VertexBufferMOCS_bits 7 -#define GEN9_VERTEX_BUFFER_STATE_VertexBufferMOCS_bits 7 -#define GEN8_VERTEX_BUFFER_STATE_VertexBufferMOCS_bits 7 -#define GEN75_VERTEX_BUFFER_STATE_VertexBufferMOCS_bits 4 -#define GEN7_VERTEX_BUFFER_STATE_VertexBufferMOCS_bits 4 -#define GEN6_VERTEX_BUFFER_STATE_VertexBufferMOCS_bits 4 - -static inline uint32_t ATTRIBUTE_PURE -VERTEX_BUFFER_STATE_VertexBufferMOCS_bits(const struct gen_device_info *devinfo) -{ - switch (devinfo->gen) { - case 11: return 7; - case 10: return 7; - case 9: return 7; - case 8: return 7; - case 7: - if (devinfo->is_haswell) { - return 4; - } else { - return 4; - } - case 6: return 4; - case 5: return 0; - case 4: - if (devinfo->is_g4x) { - return 0; - } else { - return 0; - } - default: - unreachable("Invalid hardware generation"); - } -} - - - -#define GEN11_VERTEX_BUFFER_STATE_VertexBufferMOCS_start 16 -#define GEN10_VERTEX_BUFFER_STATE_VertexBufferMOCS_start 16 -#define GEN9_VERTEX_BUFFER_STATE_VertexBufferMOCS_start 16 -#define GEN8_VERTEX_BUFFER_STATE_VertexBufferMOCS_start 16 -#define GEN75_VERTEX_BUFFER_STATE_VertexBufferMOCS_start 16 -#define GEN7_VERTEX_BUFFER_STATE_VertexBufferMOCS_start 16 -#define GEN6_VERTEX_BUFFER_STATE_VertexBufferMOCS_start 16 - -static inline uint32_t ATTRIBUTE_PURE -VERTEX_BUFFER_STATE_VertexBufferMOCS_start(const struct gen_device_info *devinfo) -{ - switch (devinfo->gen) { - case 11: return 16; - case 10: return 16; - case 9: return 16; - case 8: return 16; - case 7: - if (devinfo->is_haswell) { - return 16; - } else { - return 16; - } - case 6: return 16; - case 5: return 0; - case 4: - if (devinfo->is_g4x) { - return 0; - } else { - return 0; - } - default: - unreachable("Invalid hardware generation"); - } -} - - - -/* VERTEX_BUFFER_STATE::Vertex Buffer Memory Object Control State */ - - -#define GEN75_VERTEX_BUFFER_STATE_VertexBufferMemoryObjectControlState_bits 4 -#define GEN7_VERTEX_BUFFER_STATE_VertexBufferMemoryObjectControlState_bits 4 -#define GEN6_VERTEX_BUFFER_STATE_VertexBufferMemoryObjectControlState_bits 4 - -static inline uint32_t ATTRIBUTE_PURE -VERTEX_BUFFER_STATE_VertexBufferMemoryObjectControlState_bits(const struct gen_device_info *devinfo) -{ - switch (devinfo->gen) { - case 11: return 0; - case 10: return 0; - case 9: return 0; - case 8: return 0; - case 7: - if (devinfo->is_haswell) { - return 4; - } else { - return 4; - } - case 6: return 4; - case 5: return 0; - case 4: - if (devinfo->is_g4x) { - return 0; - } else { - return 0; - } - default: - unreachable("Invalid hardware generation"); - } -} - - - -#define GEN75_VERTEX_BUFFER_STATE_VertexBufferMemoryObjectControlState_start 16 -#define GEN7_VERTEX_BUFFER_STATE_VertexBufferMemoryObjectControlState_start 16 -#define GEN6_VERTEX_BUFFER_STATE_VertexBufferMemoryObjectControlState_start 16 - -static inline uint32_t ATTRIBUTE_PURE -VERTEX_BUFFER_STATE_VertexBufferMemoryObjectControlState_start(const struct gen_device_info *devinfo) -{ - switch (devinfo->gen) { - case 11: return 0; - case 10: return 0; - case 9: return 0; - case 8: return 0; - case 7: - if (devinfo->is_haswell) { - return 16; - } else { - return 16; - } - case 6: return 16; - case 5: return 0; - case 4: - if (devinfo->is_g4x) { - return 0; - } else { - return 0; - } - default: - unreachable("Invalid hardware generation"); - } -} - - - /* VERTEX_BUFFER_STATE::Vertex Fetch Invalidate */ |