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authorRoel Kluin <roel.kluin@gmail.com>2009-10-06 18:31:17 -0400
committerAlex Deucher <alexdeucher@gmail.com>2009-10-06 18:31:17 -0400
commite08411af1aa8c7d4233ba593b84360397cdbb307 (patch)
tree125468d7826ac1cffa229b21cd3876f4a96becc1 /src/radeon_pm.c
parente59ae08270711512e64b70f79b6476cc2c52d230 (diff)
radeon: Fix duplicated bit settings
[agd5f: adapted from kms patch] Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Diffstat (limited to 'src/radeon_pm.c')
-rw-r--r--src/radeon_pm.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/radeon_pm.c b/src/radeon_pm.c
index fe8f2143..d5152c80 100644
--- a/src/radeon_pm.c
+++ b/src/radeon_pm.c
@@ -226,7 +226,7 @@ static void LegacySetClockGating(ScrnInfoPtr pScrn, Bool enable)
R300_PIXCLK_TRANS_ALWAYS_ONb |
R300_PIXCLK_TVO_ALWAYS_ONb |
R300_P2G2CLK_ALWAYS_ONb |
- R300_P2G2CLK_ALWAYS_ONb);
+ R300_P2G2CLK_DAC_ALWAYS_ONb);
OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp);
} else if (info->ChipFamily >= CHIP_FAMILY_RV350) {
tmp = INPLL(pScrn, R300_SCLK_CNTL2);
@@ -273,7 +273,7 @@ static void LegacySetClockGating(ScrnInfoPtr pScrn, Bool enable)
R300_PIXCLK_TRANS_ALWAYS_ONb |
R300_PIXCLK_TVO_ALWAYS_ONb |
R300_P2G2CLK_ALWAYS_ONb |
- R300_P2G2CLK_ALWAYS_ONb);
+ R300_P2G2CLK_DAC_ALWAYS_ONb);
OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp);
tmp = INPLL(pScrn, RADEON_MCLK_MISC);
@@ -454,8 +454,8 @@ static void LegacySetClockGating(ScrnInfoPtr pScrn, Bool enable)
RADEON_PIXCLK_TMDS_ALWAYS_ONb |
R300_PIXCLK_TRANS_ALWAYS_ONb |
R300_PIXCLK_TVO_ALWAYS_ONb |
- R300_P2G2CLK_ALWAYS_ONb |
R300_P2G2CLK_ALWAYS_ONb |
+ R300_P2G2CLK_DAC_ALWAYS_ONb |
R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp);
} else if (info->ChipFamily >= CHIP_FAMILY_RV350) {
@@ -507,8 +507,8 @@ static void LegacySetClockGating(ScrnInfoPtr pScrn, Bool enable)
RADEON_PIXCLK_TMDS_ALWAYS_ONb |
R300_PIXCLK_TRANS_ALWAYS_ONb |
R300_PIXCLK_TVO_ALWAYS_ONb |
- R300_P2G2CLK_ALWAYS_ONb |
R300_P2G2CLK_ALWAYS_ONb |
+ R300_P2G2CLK_DAC_ALWAYS_ONb |
R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp);
} else {