rev 1.62

Possibloe fix for some bge chip revisions taking a long time to reset
(e.g., polling for a half-second or more at splnet(), blocking most
interrupts, durin an ifconfig down/ifconfig up).

Appears to help for a 5704C rev A3, which is the only chip I've
ever seen that had even a mild version of the reported problem.

rev 1.61

Check for BGE_PCI_PCISTATE register failing to revert on reset.
if it occurs, print a message indicating why the reset took so long.

From NetBSD

1 files changed, 10 insertions, 1 deletions

diff --git a/sys/dev/pci/if_bgereg.h b/sys/dev/pci/if_bgereg.h
index 0581a7d7ae9..045c206856e 100644
--- a/sys/dev/pci/if_bgereg.h
+++ b/sys/dev/pci/if_bgereg.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: if_bgereg.h,v 1.16 2004/12/16 14:30:32 brad Exp $ */
+/* $OpenBSD: if_bgereg.h,v 1.17 2004/12/17 03:13:59 brad Exp $ */
 /*
  * Copyright (c) 2001 Wind River Systems
  * Copyright (c) 1997, 1998, 1999, 2001
@@ -311,6 +311,15 @@
 #define BGE_PCISTATE_PCI_TGT_RETRY_MAX	0x00000E00
 
 /*
+ * The following bits in PCI state register are reserved.
+ * If we check that the register values reverts on reset,
+ * do not check these bits. On some 5704C (rev A3) and some
+ * Altima chips, these bits do not revert until much later
+ * in the bge driver's bge_reset() chip-reset state machine.
+ */
+#define BGE_PCISTATE_RESERVED	((1 << 12) + (1 <<7))
+
+/*
  * PCI Clock Control register -- note, this register is read only
  * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control
  * register is set.