Proide a mips_sync() macro to wrap asm("sync"), and replace gazillions of

such statements with it.

25 files changed, 109 insertions, 97 deletions

diff --git a/sys/arch/loongson/dev/bonito.c b/sys/arch/loongson/dev/bonito.c
index daf6c1ef3c7..026fdb06eee 100644
--- a/sys/arch/loongson/dev/bonito.c
+++ b/sys/arch/loongson/dev/bonito.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: bonito.c,v 1.19 2011/03/31 20:37:44 miod Exp $	*/
+/*	$OpenBSD: bonito.c,v 1.20 2012/09/29 18:54:36 miod Exp $	*/
 /*	$NetBSD: bonito_mainbus.c,v 1.11 2008/04/28 20:23:10 martin Exp $	*/
 /*	$NetBSD: bonito_pci.c,v 1.5 2008/04/28 20:23:28 martin Exp $	*/
 
@@ -59,6 +59,7 @@
 
 #include <machine/autoconf.h>
 #include <machine/bus.h>
+#include <machine/cpu.h>
 #include <machine/intr.h>
 
 #include <dev/pci/pcidevs.h>
@@ -88,7 +89,7 @@ struct cfdriver bonito_cd = {
 	NULL, "bonito", DV_DULL
 };
 
-#define	wbflush()	__asm__ __volatile__ ("sync" ::: "memory")
+#define	wbflush()	mips_sync()
 
 bus_addr_t	bonito_pa_to_device(paddr_t);
 paddr_t		bonito_device_to_pa(bus_addr_t);
@@ -477,7 +478,8 @@ bonito_splx(int newipl)
 	/* Update masks to new ipl. Order highly important! */
 	__asm__ (".set noreorder\n");
 	ci->ci_ipl = newipl;
-	__asm__ ("sync\n\t.set reorder\n");
+	mips_sync();
+	__asm__ (".set reorder\n");
 	bonito_setintrmask(newipl);
 	/* If we still have softints pending trigger processing. */
 	if (ci->ci_softpending != 0 && newipl < IPL_SOFTINT)
@@ -697,7 +699,8 @@ bonito_intr_dispatch(uint64_t isr, int startbit, struct trap_frame *frame)
 				}
 				__asm__ (".set noreorder\n");
 				curcpu()->ci_ipl = frame->ipl;
-				__asm__ ("sync\n\t.set reorder\n");
+				mips_sync();
+				__asm__ (".set reorder\n");
 			}
 			if (rc == 0) {
 				printf("spurious interrupt %d\n", bitno);
diff --git a/sys/arch/loongson/loongson/generic2e_machdep.c b/sys/arch/loongson/loongson/generic2e_machdep.c
index f98d7ae034d..be8a7d2f4ad 100644
--- a/sys/arch/loongson/loongson/generic2e_machdep.c
+++ b/sys/arch/loongson/loongson/generic2e_machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: generic2e_machdep.c,v 1.2 2011/04/15 20:40:06 deraadt Exp $	*/
+/*	$OpenBSD: generic2e_machdep.c,v 1.3 2012/09/29 18:54:38 miod Exp $	*/
 
 /*
  * Copyright (c) 2010 Miodrag Vallat.
@@ -54,6 +54,7 @@
 
 #include <mips64/archtype.h>
 #include <machine/autoconf.h>
+#include <machine/cpu.h>
 #include <machine/pmon.h>
 
 #include <dev/ic/i8259reg.h>
@@ -291,7 +292,8 @@ generic2e_isa_intr(uint32_t hwpend, struct trap_frame *frame)
 
 			__asm__ (".set noreorder\n");
 			curcpu()->ci_ipl = frame->ipl;
-			__asm__ ("sync\n\t.set reorder\n");
+			mips_sync();
+			__asm__ (".set reorder\n");
 			if (ret == 1)
 				break;
 		}
@@ -560,7 +562,7 @@ via686sb_setup(pci_chipset_tag_t pc, int dev)
 	REGVAL8(BONITO_PCIIO_BASE + 0x4d0) = (elcr >> 0) & 0xff;
 	REGVAL8(BONITO_PCIIO_BASE + 0x4d1) = (elcr >> 8) & 0xff;
 
-	__asm__ __volatile__ ("sync" ::: "memory");
+	mips_sync();
 
 	/*
 	 * Update interrupt information for secondary functions.
diff --git a/sys/arch/loongson/loongson/isa_machdep.c b/sys/arch/loongson/loongson/isa_machdep.c
index 389dac292fc..3d91916df04 100644
--- a/sys/arch/loongson/loongson/isa_machdep.c
+++ b/sys/arch/loongson/loongson/isa_machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: isa_machdep.c,v 1.1 2010/05/08 21:59:56 miod Exp $	*/
+/*	$OpenBSD: isa_machdep.c,v 1.2 2012/09/29 18:54:38 miod Exp $	*/
 
 /*
  * Copyright (c) 2009, 2010 Miodrag Vallat.
@@ -25,6 +25,7 @@
 #include <sys/device.h>
 
 #include <machine/autoconf.h>
+#include <machine/cpu.h>
 #include <machine/intr.h>
 
 #include <dev/ic/i8259reg.h>
@@ -87,7 +88,8 @@ loongson_isa_splx(int newipl)
 	/* Update masks to new ipl. Order highly important! */
 	__asm__ (".set noreorder\n");
 	ci->ci_ipl = newipl;
-	__asm__ ("sync\n\t.set reorder\n");
+	mips_sync();
+	__asm__ (".set reorder\n");
 	loongson_isa_setintrmask(newipl);
 	/* If we still have softints pending trigger processing. */
 	if (ci->ci_softpending != 0 && newipl < IPL_SOFTINT)
diff --git a/sys/arch/loongson/loongson/yeeloong_machdep.c b/sys/arch/loongson/loongson/yeeloong_machdep.c
index 08baf14833b..d5d2baeba9c 100644
--- a/sys/arch/loongson/loongson/yeeloong_machdep.c
+++ b/sys/arch/loongson/loongson/yeeloong_machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: yeeloong_machdep.c,v 1.17 2011/07/21 20:36:12 miod Exp $	*/
+/*	$OpenBSD: yeeloong_machdep.c,v 1.18 2012/09/29 18:54:38 miod Exp $	*/
 
 /*
  * Copyright (c) 2009, 2010 Miodrag Vallat.
@@ -28,6 +28,7 @@
 
 #include <mips64/archtype.h>
 #include <machine/autoconf.h>
+#include <machine/cpu.h>
 #include <machine/pmon.h>
 
 #include <dev/isa/isareg.h>
@@ -396,7 +397,8 @@ lemote_isa_intr(uint32_t hwpend, struct trap_frame *frame)
 					}
 					__asm__ (".set noreorder\n");
 					curcpu()->ci_ipl = frame->ipl;
-					__asm__ ("sync\n\t.set reorder\n");
+					mips_sync();
+					__asm__ (".set reorder\n");
 					if (ret == 1)
 						break;
 				}
diff --git a/sys/arch/mips64/include/cpu.h b/sys/arch/mips64/include/cpu.h
index 08a468ec8ad..def32138a9b 100644
--- a/sys/arch/mips64/include/cpu.h
+++ b/sys/arch/mips64/include/cpu.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpu.h,v 1.83 2012/07/14 19:50:11 miod Exp $	*/
+/*	$OpenBSD: cpu.h,v 1.84 2012/09/29 18:54:38 miod Exp $	*/
 
 /*-
  * Copyright (c) 1992, 1993
@@ -518,6 +518,8 @@ void	cp0_calibrate(struct cpu_info *);
 
 #define	aston(p)		p->p_md.md_astpending = 1
 
+#define	mips_sync()		__asm__ __volatile__ ("sync" ::: "memory")
+
 #endif /* _KERNEL && !_LOCORE */
 
 /*
diff --git a/sys/arch/mips64/mips64/cache_loongson2.c b/sys/arch/mips64/mips64/cache_loongson2.c
index b0fb0dd8821..9c2a172d6aa 100644
--- a/sys/arch/mips64/mips64/cache_loongson2.c
+++ b/sys/arch/mips64/mips64/cache_loongson2.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cache_loongson2.c,v 1.2 2012/06/24 16:26:04 miod Exp $	*/
+/*	$OpenBSD: cache_loongson2.c,v 1.3 2012/09/29 18:54:38 miod Exp $	*/
 
 /*
  * Copyright (c) 2009, 2012 Miodrag Vallat.
@@ -57,8 +57,6 @@
 #define	cache(op,set,addr) \
     __asm__ __volatile__ \
       ("cache %0, %1(%2)" :: "i"(op), "i"(set), "r"(addr) : "memory")
-#define	sync() \
-    __asm__ __volatile__ ("sync" ::: "memory")
 
 static __inline__ void	ls2f_hitinv_primary(vaddr_t, vsize_t);
 static __inline__ void	ls2f_hitinv_secondary(vaddr_t, vsize_t);
@@ -107,7 +105,7 @@ Loongson2_SyncCache(struct cpu_info *ci)
 {
 	vaddr_t sva, eva;
 
-	sync();
+	mips_sync();
 
 	sva = PHYS_TO_XKPHYS(0, CCA_CACHED);
 	eva = sva + LS2F_L1_SIZE / LS2F_CACHE_WAYS;
@@ -172,7 +170,7 @@ Loongson2_SyncDCachePage(struct cpu_info *ci, vaddr_t va, paddr_t pa)
 {
 	vaddr_t sva, eva;
 
-	sync();
+	mips_sync();
 
 	sva = PHYS_TO_XKPHYS(pa, CCA_CACHED);
 	eva = sva + PAGE_SIZE;
@@ -218,7 +216,7 @@ Loongson2_HitSyncDCache(struct cpu_info *ci, vaddr_t _va, size_t _sz)
 	vaddr_t va;
 	vsize_t sz;
 
-	sync();
+	mips_sync();
 
 	/* extend the range to integral cache lines */
 	va = _va & ~(LS2F_CACHE_LINE - 1);
@@ -271,7 +269,7 @@ Loongson2_HitInvalidateDCache(struct cpu_info *ci, vaddr_t _va, size_t _sz)
 	ls2f_hitinv_primary(va, sz);
 	ls2f_hitinv_secondary(va, sz);
 
-	sync();
+	mips_sync();
 }
 
 /*
diff --git a/sys/arch/mips64/mips64/cache_octeon.c b/sys/arch/mips64/mips64/cache_octeon.c
index 70bdde195af..5a5b99db62e 100644
--- a/sys/arch/mips64/mips64/cache_octeon.c
+++ b/sys/arch/mips64/mips64/cache_octeon.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cache_octeon.c,v 1.5 2012/06/24 16:26:04 miod Exp $	*/
+/*	$OpenBSD: cache_octeon.c,v 1.6 2012/09/29 18:54:38 miod Exp $	*/
 /*
  * Copyright (c) 2010 Takuya ASADA.
  *
@@ -49,7 +49,6 @@
 #include <mips64/cache.h>
 #include <machine/cpu.h>
 
-#define SYNC() asm volatile("sync\n" ::: "memory")
 #define SYNCI() \
 	asm volatile( \
 		".set push\n" \
@@ -81,7 +80,7 @@ Octeon_ConfigCache(struct cpu_info *ci)
 void
 Octeon_SyncCache(struct cpu_info *ci)
 {
-	SYNC();
+	mips_sync();
 }
 
 void
@@ -115,7 +114,7 @@ Octeon_IOSyncDCache(struct cpu_info *ci, vaddr_t va, size_t len, int how)
 		break;
 	case CACHE_SYNC_W: /* writeback */
 	case CACHE_SYNC_X: /* writeback and invalidate */
-		SYNC();
+		mips_sync();
 		break;
 	}
 }
diff --git a/sys/arch/mips64/mips64/cache_r4k.c b/sys/arch/mips64/mips64/cache_r4k.c
index d9955e7bc96..201684c5e0e 100644
--- a/sys/arch/mips64/mips64/cache_r4k.c
+++ b/sys/arch/mips64/mips64/cache_r4k.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cache_r4k.c,v 1.7 2012/06/24 20:25:58 miod Exp $	*/
+/*	$OpenBSD: cache_r4k.c,v 1.8 2012/09/29 18:54:38 miod Exp $	*/
 
 /*
  * Copyright (c) 2012 Miodrag Vallat.
@@ -36,8 +36,6 @@
 
 #define	cache(op,addr) \
     __asm__ __volatile__ ("cache %0, 0(%1)" :: "i"(op), "r"(addr) : "memory")
-#define	sync() \
-    __asm__ __volatile__ ("sync" ::: "memory")
 
 static __inline__ void	mips4k_hitinv_primary(vaddr_t, vsize_t, vsize_t);
 static __inline__ void	mips4k_hitinv_secondary(vaddr_t, vsize_t, vsize_t);
@@ -156,7 +154,7 @@ Mips4k_SyncCache(struct cpu_info *ci)
 		}
 	}
 
-	sync();
+	mips_sync();
 }
 
 /*
@@ -188,7 +186,7 @@ Mips4k_InvalidateICache(struct cpu_info *ci, vaddr_t _va, size_t _sz)
 		sva += line;
 	}
 
-	sync();
+	mips_sync();
 }
 
 /*
@@ -220,7 +218,7 @@ Mips4k_SyncDCachePage(struct cpu_info *ci, vaddr_t va, paddr_t pa)
 		}
 	}
 
-	sync();
+	mips_sync();
 }
 
 /*
@@ -279,7 +277,7 @@ Mips4k_HitSyncDCache(struct cpu_info *ci, vaddr_t _va, size_t _sz)
 		mips4k_hitwbinv_secondary(va, sz, line);
 	}
 
-	sync();
+	mips_sync();
 }
 
 /*
@@ -338,7 +336,7 @@ Mips4k_HitInvalidateDCache(struct cpu_info *ci, vaddr_t _va, size_t _sz)
 		mips4k_hitinv_secondary(va, sz, line);
 	}
 
-	sync();
+	mips_sync();
 }
 
 /*
diff --git a/sys/arch/mips64/mips64/cache_r5k.c b/sys/arch/mips64/mips64/cache_r5k.c
index 8c3cc93c02f..06e0f6cb31f 100644
--- a/sys/arch/mips64/mips64/cache_r5k.c
+++ b/sys/arch/mips64/mips64/cache_r5k.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cache_r5k.c,v 1.3 2012/06/24 20:24:46 miod Exp $	*/
+/*	$OpenBSD: cache_r5k.c,v 1.4 2012/09/29 18:54:38 miod Exp $	*/
 
 /*
  * Copyright (c) 2012 Miodrag Vallat.
@@ -115,8 +115,6 @@
 #define	cache(op,offs,addr)	__asm__ __volatile__ \
 	("cache %0, %1(%2)" :: "i"(op), "i"(offs), "r"(addr) : "memory")
 
-#define	sync()			__asm__ __volatile__ ("sync" ::: "memory")
-
 #define	reset_taglo()		__asm__ __volatile__ \
 	("mtc0 $zero, $28")	/* COP_0_TAG_LO */
 #define	reset_taghi()		__asm__ __volatile__ \
@@ -227,7 +225,7 @@ mips7k_l2_init(uint32_t l2size)
 		va += R5K_LINE;
 		cache(IndexStoreTag_S, -4, va);
 	}
-	sync();
+	mips_sync();
 
 	va = PHYS_TO_XKPHYS(0, CCA_CACHED);
 	eva = va + l2size;
@@ -236,7 +234,7 @@ mips7k_l2_init(uint32_t l2size)
 		__asm__ __volatile__
 		    ("lw $zero, %0(%1)" :: "i"(-4), "r"(va));
 	}
-	sync();
+	mips_sync();
 
 	va = PHYS_TO_XKPHYS(0, CCA_CACHED);
 	eva = va + l2size;
@@ -244,7 +242,7 @@ mips7k_l2_init(uint32_t l2size)
 		va += R5K_LINE;
 		cache(IndexStoreTag_S, -4, va);
 	}
-	sync();
+	mips_sync();
 }
 
 /*
@@ -462,7 +460,7 @@ Mips5k_SyncCache(struct cpu_info *ci)
 	}
 #endif
 
-	sync();
+	mips_sync();
 }
 
 /*
@@ -524,7 +522,7 @@ Mips5k_InvalidateICache(struct cpu_info *ci, vaddr_t _va, size_t _sz)
 #ifdef CPU_R4600
 	setsr(sr);
 #endif
-	sync();
+	mips_sync();
 }
 
 static __inline__ void
@@ -618,7 +616,7 @@ Mips5k_SyncDCachePage(struct cpu_info *ci, vaddr_t va, paddr_t pa)
 	}
 #endif
 
-	sync();
+	mips_sync();
 }
 
 /*
@@ -656,7 +654,7 @@ Mips5k_HitSyncDCache(struct cpu_info *ci, vaddr_t _va, size_t _sz)
 		mips5k_hitwbinv_primary(va, sz);
 	}
 
-	sync();
+	mips_sync();
 }
 
 /*
@@ -719,7 +717,7 @@ Mips5k_HitInvalidateDCache(struct cpu_info *ci, vaddr_t _va, size_t _sz)
 		mips5k_hitinv_primary(va, sz);
 	}
 
-	sync();
+	mips_sync();
 }
 
 /*
@@ -841,5 +839,5 @@ Mips5k_IOSyncDCache(struct cpu_info *ci, vaddr_t _va, size_t _sz, int how)
 		break;
 	}
 
-	sync();
+	mips_sync();
 }
diff --git a/sys/arch/mips64/mips64/interrupt.c b/sys/arch/mips64/mips64/interrupt.c
index fc7e579d8ae..259d6e6ca63 100644
--- a/sys/arch/mips64/mips64/interrupt.c
+++ b/sys/arch/mips64/mips64/interrupt.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: interrupt.c,v 1.60 2010/09/20 06:33:47 matthew Exp $ */
+/*	$OpenBSD: interrupt.c,v 1.61 2012/09/29 18:54:38 miod Exp $ */
 
 /*
  * Copyright (c) 2001-2004 Opsycon AB  (www.opsycon.se / www.opsycon.com)
@@ -147,7 +147,8 @@ interrupt(struct trap_frame *trapframe)
 		dosoftint();
 		__asm__ (".set noreorder\n");
 		ci->ci_ipl = s;	/* no-overhead splx */
-		__asm__ ("sync\n\t.set reorder\n");
+		mips_sync();
+		__asm__ (".set reorder\n");
 	}
 
 	ci->ci_intrdepth--;
@@ -230,7 +231,8 @@ splraise(int newipl)
 		__asm__("nop");
 		ci->ci_ipl = newipl;
 	}
-	__asm__ ("sync\n\t.set reorder\n");
+	mips_sync();
+	__asm__ (".set reorder\n");
 	return oldipl;
 }
 
diff --git a/sys/arch/octeon/dev/octeon_intr.c b/sys/arch/octeon/dev/octeon_intr.c
index 01dc7172788..4b8fab58dd7 100644
--- a/sys/arch/octeon/dev/octeon_intr.c
+++ b/sys/arch/octeon/dev/octeon_intr.c
@@ -144,7 +144,8 @@ octeon_splx(int newipl)
 	/* Update masks to new ipl. Order highly important! */
 	__asm__ (".set noreorder\n");
 	ci->ci_ipl = newipl;
-	__asm__ ("sync\n\t.set reorder\n");
+	mips_sync();
+	__asm__ (".set reorder\n");
 	if (CPU_IS_PRIMARY(ci))
 		octeon_setintrmask(newipl);
 	/* If we still have softints pending trigger processing. */
@@ -252,7 +253,8 @@ octeon_iointr(uint32_t hwpend, struct trap_frame *frame)
 
 		__asm__ (".set noreorder\n");
 		ipl = ci->ci_ipl;
-		__asm__ ("sync\n\t.set reorder\n");
+		mips_sync();
+		__asm__ (".set reorder\n");
 
 		/* Service higher level interrupts first */
 		for (lvl = NIPLS - 1; lvl != IPL_NONE; lvl--) {
@@ -293,7 +295,8 @@ octeon_iointr(uint32_t hwpend, struct trap_frame *frame)
 #endif
 					__asm__ (".set noreorder\n");
 					ci->ci_ipl = ipl;
-					__asm__ ("sync\n\t.set reorder\n");
+					mips_sync();
+					__asm__ (".set reorder\n");
 				}
 				if (rc == 0)
 					printf("spurious interrupt %d\n", bitno);
diff --git a/sys/arch/octeon/octeon/lock_machdep.c b/sys/arch/octeon/octeon/lock_machdep.c
index 5d7198529e9..5aec43e79a1 100644
--- a/sys/arch/octeon/octeon/lock_machdep.c
+++ b/sys/arch/octeon/octeon/lock_machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: lock_machdep.c,v 1.1 2010/09/20 06:32:30 syuu Exp $	*/
+/*	$OpenBSD: lock_machdep.c,v 1.2 2012/09/29 18:54:38 miod Exp $	*/
 
 /*
  * Copyright (c) 2007 Artur Grabowski <art@openbsd.org>
@@ -22,6 +22,7 @@
 #include <sys/systm.h>
 
 #include <machine/atomic.h>
+#include <machine/cpu.h>
 #include <machine/lock.h>
 
 #include <ddb/db_output.h>
@@ -83,7 +84,7 @@ __mp_lock(struct __mp_lock *mpl)
 	while (1) {
 		sr = disableintr();
 		if (__cpu_cas(&mpl->mpl_count, 0, 1) == 0) {
-			__asm__ __volatile__ ("sync" ::: "memory");
+			mips_sync();
 			mpl->mpl_cpu = ci;
 		}
 
@@ -113,7 +114,7 @@ __mp_unlock(struct __mp_lock *mpl)
 	sr = disableintr();
 	if (--mpl->mpl_count == 1) {
 		mpl->mpl_cpu = NULL;
-		__asm__ __volatile__ ("sync" ::: "memory");
+		mips_sync();
 		mpl->mpl_count = 0;
 	}
 
@@ -135,7 +136,7 @@ __mp_release_all(struct __mp_lock *mpl)
 
 	sr = disableintr();
 	mpl->mpl_cpu = NULL;
-	__asm__ __volatile__ ("sync" ::: "memory");
+	mips_sync();
 	mpl->mpl_count = 0;
 	setsr(sr);
 
diff --git a/sys/arch/sgi/hpc/hpc.c b/sys/arch/sgi/hpc/hpc.c
index 6c21704dd51..c04b5676f10 100644
--- a/sys/arch/sgi/hpc/hpc.c
+++ b/sys/arch/sgi/hpc/hpc.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: hpc.c,v 1.13 2012/05/27 14:27:08 miod Exp $	*/
+/*	$OpenBSD: hpc.c,v 1.14 2012/09/29 18:54:38 miod Exp $	*/
 /*	$NetBSD: hpc.c,v 1.66 2011/07/01 18:53:46 dyoung Exp $	*/
 /*	$NetBSD: ioc.c,v 1.9 2011/07/01 18:53:47 dyoung Exp $	 */
 
@@ -889,8 +889,7 @@ void
 hpc3_space_barrier(bus_space_tag_t t, bus_space_handle_t h, bus_size_t offs,
     bus_size_t sz, int how)
 {
-	__asm__ __volatile__ ("sync" ::: "memory");
-
+	mips_sync();
 	/* just read a side-effect free register */
 	(void)*(volatile uint32_t *)
 	    PHYS_TO_XKPHYS(HPC_BASE_ADDRESS_0 + HPC3_INTRSTAT_40, CCA_NC);
diff --git a/sys/arch/sgi/hpc/zs.c b/sys/arch/sgi/hpc/zs.c
index a825fa552d3..4ff3aeba452 100644
--- a/sys/arch/sgi/hpc/zs.c
+++ b/sys/arch/sgi/hpc/zs.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: zs.c,v 1.9 2012/05/12 16:47:44 miod Exp $	*/
+/*	$OpenBSD: zs.c,v 1.10 2012/09/29 18:54:39 miod Exp $	*/
 /*	$NetBSD: zs.c,v 1.37 2011/02/20 07:59:50 matt Exp $	*/
 
 /*-
@@ -677,7 +677,7 @@ zs_putc(void *arg, int c)
 	zc->zc_data = c;
 
 	/* inline bus_space_barrier() */
-	__asm__ __volatile__ ("sync" ::: "memory");
+	mips_sync();
 	if (sys_config.system_type != SGI_IP20) {
 		(void)*(volatile uint32_t *)PHYS_TO_XKPHYS(HPC_BASE_ADDRESS_0 +
 		    HPC3_INTRSTAT_40, CCA_NC);
diff --git a/sys/arch/sgi/localbus/imc.c b/sys/arch/sgi/localbus/imc.c
index e60237d69eb..ad05070f182 100644
--- a/sys/arch/sgi/localbus/imc.c
+++ b/sys/arch/sgi/localbus/imc.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: imc.c,v 1.9 2012/05/27 14:12:55 miod Exp $	*/
+/*	$OpenBSD: imc.c,v 1.10 2012/09/29 18:54:39 miod Exp $	*/
 /*	$NetBSD: imc.c,v 1.32 2011/07/01 18:53:46 dyoung Exp $	*/
 
 /*
@@ -330,7 +330,7 @@ void
 imc_space_barrier(bus_space_tag_t t, bus_space_handle_t h, bus_size_t offs,
     bus_size_t len, int flags)
 {
-	__asm__ __volatile__ ("sync" ::: "memory");
+	mips_sync();
 }
 
 #if NEISA > 0
diff --git a/sys/arch/sgi/localbus/int.c b/sys/arch/sgi/localbus/int.c
index 076ea6f17c5..7ca9437d126 100644
--- a/sys/arch/sgi/localbus/int.c
+++ b/sys/arch/sgi/localbus/int.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: int.c,v 1.6 2012/07/18 19:56:02 miod Exp $	*/
+/*	$OpenBSD: int.c,v 1.7 2012/09/29 18:54:39 miod Exp $	*/
 /*	$NetBSD: int.c,v 1.24 2011/07/01 18:53:46 dyoung Exp $	*/
 
 /*
@@ -245,8 +245,8 @@ int2_splx(int newipl)
 
 	__asm__ (".set noreorder");
 	ci->ci_ipl = newipl;
-	__asm__ ("sync" ::: "memory");
-	__asm__ (".set reorder");
+	mips_sync();
+	__asm__ (".set reorder\n");
 
 	sr = disableintr();	/* XXX overkill? */
 	int2_write(INT2_LOCAL1_MASK, (int2_intem >> 8) & ~int2_l1imask[newipl]);
@@ -350,7 +350,7 @@ int2_attach(struct device *parent, struct device *self, void *aux)
 	    TIMER_SEL1 | TIMER_16BIT | TIMER_SWSTROBE);
 	int2_write(INT2_TIMER_CONTROL,
 	    TIMER_SEL2 | TIMER_16BIT | TIMER_SWSTROBE);
-	__asm__ __volatile__ ("sync" ::: "memory");
+	mips_sync();
 	delay(4);
 	int2_write(INT2_TIMER_CLEAR, 0x03);
 
@@ -493,7 +493,7 @@ int_8254_cal(void)
 	int2_write(INT2_TIMER_CONTROL,
 	    TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
 	int2_write(INT2_TIMER_0, freq & 0xff);
-	__asm__ ("sync" ::: "memory");
+	mips_sync();
 	delay(4);
 	int2_write(INT2_TIMER_0, freq >> 8);
 
@@ -501,7 +501,7 @@ int_8254_cal(void)
 	int2_write(INT2_TIMER_CONTROL,
 	    TIMER_SEL2 | TIMER_RATEGEN | TIMER_16BIT);
 	int2_write(INT2_TIMER_2, 2);
-	__asm__ ("sync" ::: "memory");
+	mips_sync();
 	delay(4);
 	int2_write(INT2_TIMER_2, 0);
 
diff --git a/sys/arch/sgi/localbus/macebus.c b/sys/arch/sgi/localbus/macebus.c
index 4ec6b54161c..ecdab990db0 100644
--- a/sys/arch/sgi/localbus/macebus.c
+++ b/sys/arch/sgi/localbus/macebus.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: macebus.c,v 1.59 2012/03/15 18:52:56 miod Exp $ */
+/*	$OpenBSD: macebus.c,v 1.60 2012/09/29 18:54:39 miod Exp $ */
 
 /*
  * Copyright (c) 2000-2004 Opsycon AB  (www.opsycon.se)
@@ -447,7 +447,7 @@ void
 mace_space_barrier(bus_space_tag_t t, bus_space_handle_t h, bus_size_t offs,
     bus_size_t len, int flags)
 {
-	__asm__ __volatile__ ("sync" ::: "memory");
+	mips_sync();
 }
 
 /*
@@ -551,7 +551,8 @@ macebus_splx(int newipl)
 	/* Update masks to new ipl. Order highly important! */
 	__asm__ (".set noreorder\n");
 	ci->ci_ipl = newipl;
-	__asm__ ("sync\n\t.set reorder\n");
+	mips_sync();
+	__asm__ (".set reorder\n");
 	crime_setintrmask(newipl);
 	/* If we still have softints pending trigger processing. */
 	if (ci->ci_softpending != 0 && newipl < IPL_SOFTINT)
diff --git a/sys/arch/sgi/pci/macepcibridge.c b/sys/arch/sgi/pci/macepcibridge.c
index df7e4444e94..85bf32a9b34 100644
--- a/sys/arch/sgi/pci/macepcibridge.c
+++ b/sys/arch/sgi/pci/macepcibridge.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: macepcibridge.c,v 1.44 2012/03/15 18:52:56 miod Exp $ */
+/*	$OpenBSD: macepcibridge.c,v 1.45 2012/09/29 18:54:39 miod Exp $ */
 
 /*
  * Copyright (c) 2009 Miodrag Vallat.
@@ -703,7 +703,7 @@ void
 mace_pcib_space_barrier(bus_space_tag_t t, bus_space_handle_t h,
     bus_size_t offs, bus_size_t len, int flags)
 {
-	__asm__ __volatile__ ("sync" ::: "memory");
+	mips_sync();
 }
 
 /*
diff --git a/sys/arch/sgi/sgi/intr_template.c b/sys/arch/sgi/sgi/intr_template.c
index 2f9f6e95b3e..d66be2e1e11 100644
--- a/sys/arch/sgi/sgi/intr_template.c
+++ b/sys/arch/sgi/sgi/intr_template.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: intr_template.c,v 1.11 2011/04/15 20:40:06 deraadt Exp $	*/
+/*	$OpenBSD: intr_template.c,v 1.12 2012/09/29 18:54:39 miod Exp $	*/
 
 /*
  * Copyright (c) 2009 Miodrag Vallat.
@@ -135,7 +135,8 @@ INTR_FUNCTIONNAME(uint32_t hwpend, struct trap_frame *frame)
 
 		__asm__ (".set noreorder\n");
 		ipl = ci->ci_ipl;
-		__asm__ ("sync\n\t.set reorder\n");
+		mips_sync();
+		__asm__ (".set reorder\n");
 
 		/* Service higher level interrupts first */
 		for (lvl = NIPLS - 1; lvl != IPL_NONE; lvl--) {
@@ -180,7 +181,8 @@ INTR_FUNCTIONNAME(uint32_t hwpend, struct trap_frame *frame)
 #endif
 					__asm__ (".set noreorder\n");
 					ci->ci_ipl = ipl;
-					__asm__ ("sync\n\t.set reorder\n");
+					mips_sync();
+					__asm__ (".set reorder\n");
 					if (ret == 1)
 						break;
 				}
diff --git a/sys/arch/sgi/sgi/ip22_machdep.c b/sys/arch/sgi/sgi/ip22_machdep.c
index 3f4a63bc142..588d34e39b6 100644
--- a/sys/arch/sgi/sgi/ip22_machdep.c
+++ b/sys/arch/sgi/sgi/ip22_machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ip22_machdep.c,v 1.12 2012/06/24 20:29:46 miod Exp $	*/
+/*	$OpenBSD: ip22_machdep.c,v 1.13 2012/09/29 18:54:39 miod Exp $	*/
 
 /*
  * Copyright (c) 2012 Miodrag Vallat.
@@ -559,9 +559,6 @@ ip22_post_autoconf()
  * ECC board specific routines
  */
 
-#define	sync() \
-    __asm__ __volatile__ ("sync" ::: "memory");
-
 #define ecc_write(o,v) \
 	*(volatile uint64_t *)PHYS_TO_XKPHYS(ECC_BASE + (o), CCA_NC) = (v)
 
@@ -580,7 +577,7 @@ ip22_ecc_map()
 	nmemc1 |= IMC_MEMC_VALID | (ECC_BASE >> IMC_MEMC_LSHIFT_HUGE);
 	imc_write(IMC_MEMCFG1, nmemc1);
 	(void)imc_read(IMC_MEMCFG1);
-	sync();
+	mips_sync();
 
 	return omemc1;
 }
@@ -590,7 +587,7 @@ ip22_ecc_unmap(uint32_t omemc1)
 {
 	imc_write(IMC_MEMCFG1, omemc1);
 	(void)imc_read(IMC_MEMCFG1);
-	sync();
+	mips_sync();
 }
 
 int
@@ -601,7 +598,7 @@ ip22_fast_mode()
 	if (ip22_ecc_mode == 0) {
 		memc1 = ip22_ecc_map();
 		ecc_write(ECC_CTRL, ECC_CTRL_ENABLE);
-		sync();
+		mips_sync();
 		(void)imc_read(IMC_MEMCFG1);
 		imc_write(IMC_CPU_MEMACC, imc_read(IMC_CPU_MEMACC) & ~2);
 		ip22_ecc_unmap(memc1);
@@ -621,7 +618,7 @@ ip22_slow_mode()
 		memc1 = ip22_ecc_map();
 		imc_write(IMC_CPU_MEMACC, imc_read(IMC_CPU_MEMACC) | 2);
 		ecc_write(ECC_CTRL, ECC_CTRL_DISABLE);
-		sync();
+		mips_sync();
 		(void)imc_read(IMC_MEMCFG1);
 		ip22_ecc_unmap(memc1);
 		ip22_ecc_mode = 0;
@@ -645,13 +642,13 @@ ip22_ecc_init()
 	memc1 = ip22_ecc_map();
 	imc_write(IMC_CPU_MEMACC, imc_read(IMC_CPU_MEMACC) | 2);
 	ecc_write(ECC_CTRL, ECC_CTRL_DISABLE);
-	sync();
+	mips_sync();
 	(void)imc_read(IMC_MEMCFG1);
 	ecc_write(ECC_CTRL, ECC_CTRL_INT_CLR);
-	sync();
+	mips_sync();
 	(void)imc_read(IMC_MEMCFG1);
 	ecc_write(ECC_CTRL, ECC_CTRL_CHK_DISABLE);	/* XXX for now */
-	sync();
+	mips_sync();
 	(void)imc_read(IMC_MEMCFG1);
 	ip22_ecc_unmap(memc1);
 	ip22_ecc_mode = 0;
diff --git a/sys/arch/sgi/sgi/ip27_machdep.c b/sys/arch/sgi/sgi/ip27_machdep.c
index c59608804a6..f43757df18c 100644
--- a/sys/arch/sgi/sgi/ip27_machdep.c
+++ b/sys/arch/sgi/sgi/ip27_machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ip27_machdep.c,v 1.55 2012/04/03 21:17:35 miod Exp $	*/
+/*	$OpenBSD: ip27_machdep.c,v 1.56 2012/09/29 18:54:39 miod Exp $	*/
 
 /*
  * Copyright (c) 2008, 2009 Miodrag Vallat.
@@ -806,7 +806,8 @@ ip27_hub_splx(int newipl)
 	/* Update masks to new ipl. Order highly important! */
 	__asm__ (".set noreorder\n");
 	ci->ci_ipl = newipl;
-	__asm__ ("sync\n\t.set reorder\n");
+	mips_sync();
+	__asm__ (".set reorder\n");
 	if (CPU_IS_PRIMARY(ci))
 		ip27_hub_setintrmask(newipl);
 	/* If we still have softints pending trigger processing. */
diff --git a/sys/arch/sgi/sgi/lock_machdep.c b/sys/arch/sgi/sgi/lock_machdep.c
index c2f1fc7f8d1..97159770158 100644
--- a/sys/arch/sgi/sgi/lock_machdep.c
+++ b/sys/arch/sgi/sgi/lock_machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: lock_machdep.c,v 1.2 2010/01/26 04:56:04 miod Exp $	*/
+/*	$OpenBSD: lock_machdep.c,v 1.3 2012/09/29 18:54:39 miod Exp $	*/
 
 /*
  * Copyright (c) 2007 Artur Grabowski <art@openbsd.org>
@@ -22,6 +22,7 @@
 #include <sys/systm.h>
 
 #include <machine/atomic.h>
+#include <machine/cpu.h>
 #include <machine/lock.h>
 
 #include <ddb/db_output.h>
@@ -83,7 +84,7 @@ __mp_lock(struct __mp_lock *mpl)
 	while (1) {
 		sr = disableintr();
 		if (__cpu_cas(&mpl->mpl_count, 0, 1) == 0) {
-			__asm__ __volatile__ ("sync" ::: "memory");
+			mips_sync();
 			mpl->mpl_cpu = ci;
 		}
 
@@ -113,7 +114,7 @@ __mp_unlock(struct __mp_lock *mpl)
 	sr = disableintr();
 	if (--mpl->mpl_count == 1) {
 		mpl->mpl_cpu = NULL;
-		__asm__ __volatile__ ("sync" ::: "memory");
+		mips_sync();
 		mpl->mpl_count = 0;
 	}
 
@@ -135,7 +136,7 @@ __mp_release_all(struct __mp_lock *mpl)
 
 	sr = disableintr();
 	mpl->mpl_cpu = NULL;
-	__asm__ __volatile__ ("sync" ::: "memory");
+	mips_sync();
 	mpl->mpl_count = 0;
 	setsr(sr);
 
diff --git a/sys/arch/sgi/xbow/xbow.c b/sys/arch/sgi/xbow/xbow.c
index d2d9e9f249d..9857bb11c2e 100644
--- a/sys/arch/sgi/xbow/xbow.c
+++ b/sys/arch/sgi/xbow/xbow.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: xbow.c,v 1.33 2012/03/15 18:52:57 miod Exp $	*/
+/*	$OpenBSD: xbow.c,v 1.34 2012/09/29 18:54:39 miod Exp $	*/
 
 /*
  * Copyright (c) 2008, 2009, 2011 Miodrag Vallat.
@@ -641,7 +641,7 @@ void
 xbow_space_barrier(bus_space_tag_t t, bus_space_handle_t h, bus_size_t offs,
     bus_size_t len, int flags)
 {
-	__asm__ __volatile__ ("sync" ::: "memory");
+	mips_sync();
 }
 
 /*
diff --git a/sys/arch/sgi/xbow/xbridge.c b/sys/arch/sgi/xbow/xbridge.c
index 62df1687eb0..4c2d12de3cf 100644
--- a/sys/arch/sgi/xbow/xbridge.c
+++ b/sys/arch/sgi/xbow/xbridge.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: xbridge.c,v 1.85 2012/05/20 11:41:11 miod Exp $	*/
+/*	$OpenBSD: xbridge.c,v 1.86 2012/09/29 18:54:39 miod Exp $	*/
 
 /*
  * Copyright (c) 2008, 2009, 2011  Miodrag Vallat.
@@ -1660,7 +1660,7 @@ xbridge_space_barrier(bus_space_tag_t t, bus_space_handle_t h, bus_size_t offs,
 	bus_addr_t bpa, start, end;
 	uint d, devmin, devmax;
 
-	__asm__ __volatile__ ("sync" ::: "memory");
+	mips_sync();
 
 	if (flags & BUS_SPACE_BARRIER_WRITE) {
 		/*
diff --git a/sys/arch/sgi/xbow/xheart.c b/sys/arch/sgi/xbow/xheart.c
index d729b5a52d0..70d88b08749 100644
--- a/sys/arch/sgi/xbow/xheart.c
+++ b/sys/arch/sgi/xbow/xheart.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: xheart.c,v 1.23 2011/07/10 17:48:25 miod Exp $	*/
+/*	$OpenBSD: xheart.c,v 1.24 2012/09/29 18:54:39 miod Exp $	*/
 
 /*
  * Copyright (c) 2008 Miodrag Vallat.
@@ -398,7 +398,8 @@ xheart_splx(int newipl)
 	/* Update masks to new ipl. Order highly important! */
 	__asm__ (".set noreorder\n");
 	ci->ci_ipl = newipl;
-	__asm__ ("sync\n\t.set reorder\n");
+	mips_sync();
+	__asm__ (".set reorder\n");
 
 	if (CPU_IS_PRIMARY(ci))
 		xheart_setintrmask(newipl);