diff options
Diffstat (limited to 'lib/mesa/src/intel/vulkan/gfx8_cmd_buffer.c')
| -rw-r--r-- | lib/mesa/src/intel/vulkan/gfx8_cmd_buffer.c | 77 |
1 files changed, 73 insertions, 4 deletions
diff --git a/lib/mesa/src/intel/vulkan/gfx8_cmd_buffer.c b/lib/mesa/src/intel/vulkan/gfx8_cmd_buffer.c index 34337c21f..f9c13954d 100644 --- a/lib/mesa/src/intel/vulkan/gfx8_cmd_buffer.c +++ b/lib/mesa/src/intel/vulkan/gfx8_cmd_buffer.c @@ -55,7 +55,9 @@ genX(cmd_buffer_enable_pma_fix)(struct anv_cmd_buffer *cmd_buffer, bool enable) pc.RenderTargetCacheFlushEnable = true; #if GFX_VER >= 12 pc.TileCacheFlushEnable = true; +#endif +#if INTEL_NEEDS_WA_1409600907 /* Wa_1409600907: "PIPE_CONTROL with Depth Stall Enable bit must * be set with any PIPE_CONTROL with Depth Flush Enable bit set. */ @@ -209,6 +211,24 @@ want_stencil_pma_fix(struct anv_cmd_buffer *cmd_buffer, wm_prog_data->computed_depth_mode != PSCDEPTH_OFF; } +static UNUSED bool +geom_or_tess_prim_id_used(struct anv_graphics_pipeline *pipeline) +{ + const struct brw_tcs_prog_data *tcs_prog_data = + anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_CTRL) ? + get_tcs_prog_data(pipeline) : NULL; + const struct brw_tes_prog_data *tes_prog_data = + anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL) ? + get_tes_prog_data(pipeline) : NULL; + const struct brw_gs_prog_data *gs_prog_data = + anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY) ? + get_gs_prog_data(pipeline) : NULL; + + return (tcs_prog_data && tcs_prog_data->include_primitive_id) || + (tes_prog_data && tes_prog_data->include_primitive_id) || + (gs_prog_data && gs_prog_data->include_primitive_id); +} + static void genX(cmd_emit_te)(struct anv_cmd_buffer *cmd_buffer) { @@ -230,7 +250,21 @@ genX(cmd_emit_te)(struct anv_cmd_buffer *cmd_buffer) te.MaximumTessellationFactorOdd = 63.0; te.MaximumTessellationFactorNotOdd = 64.0; #if GFX_VERx10 >= 125 - te.TessellationDistributionMode = TEDMODE_RR_FREE; + if (intel_needs_workaround(cmd_buffer->device->info, 22012785325)) + te.TessellationDistributionMode = TEDMODE_RR_STRICT; + else + te.TessellationDistributionMode = TEDMODE_RR_FREE; + + if (intel_needs_workaround(cmd_buffer->device->info, 14015297576)) { + /* Wa_14015297576: + * + * Disable Tessellation Distribution when primitive Id is enabled. + */ + if (pipeline->primitive_id_override || + geom_or_tess_prim_id_used(pipeline)) + te.TessellationDistributionMode = TEDMODE_OFF; + } + te.TessellationDistributionLevel = TEDLEVEL_PATCH; /* 64_TRIANGLES */ te.SmallPatchThreshold = 3; @@ -315,7 +349,8 @@ genX(emit_shading_rate)(struct anv_batch *batch, const struct vk_fragment_shading_rate_state *fsr) { const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline); - const bool cps_enable = wm_prog_data && wm_prog_data->per_coarse_pixel_dispatch; + const bool cps_enable = wm_prog_data && + brw_wm_prog_data_is_coarse(wm_prog_data, 0); #if GFX_VER == 11 anv_batch_emit(batch, GENX(3DSTATE_CPS), cps) { @@ -392,6 +427,36 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer) &cmd_buffer->vk.dynamic_graphics_state; if ((cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_PIPELINE) || + BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_VI)) { + const uint32_t ve_count = + pipeline->vs_input_elements + pipeline->svgs_count; + const uint32_t num_dwords = 1 + 2 * MAX2(1, ve_count); + uint32_t *p = anv_batch_emitn(&cmd_buffer->batch, num_dwords, + GENX(3DSTATE_VERTEX_ELEMENTS)); + + if (p) { + if (ve_count == 0) { + memcpy(p + 1, cmd_buffer->device->empty_vs_input, + sizeof(cmd_buffer->device->empty_vs_input)); + } else if (ve_count == pipeline->vertex_input_elems) { + /* MESA_VK_DYNAMIC_VI is not dynamic for this pipeline, so + * everything is in pipeline->vertex_input_data and we can just + * memcpy + */ + memcpy(p + 1, pipeline->vertex_input_data, 4 * 2 * ve_count); + } else { + /* Use dyn->vi to emit the dynamic VERTEX_ELEMENT_STATE input. */ + genX(emit_vertex_input)(&cmd_buffer->batch, p + 1, + pipeline, dyn->vi); + /* Then append the VERTEX_ELEMENT_STATE for the draw parameters */ + memcpy(p + 1 + 2 * pipeline->vs_input_elements, + pipeline->vertex_input_data, + 4 * 2 * pipeline->vertex_input_elems); + } + } + } + + if ((cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_PIPELINE) || BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_TS_DOMAIN_ORIGIN)) { genX(cmd_emit_te)(cmd_buffer); } @@ -650,8 +715,12 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer) #endif if (pipeline->base.device->vk.enabled_extensions.EXT_sample_locations && - BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_MS_SAMPLE_LOCATIONS)) - genX(emit_sample_pattern)(&cmd_buffer->batch, dyn->ms.sample_locations); + (BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_MS_SAMPLE_LOCATIONS) || + BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_MS_SAMPLE_LOCATIONS_ENABLE))) { + genX(emit_sample_pattern)(&cmd_buffer->batch, + dyn->ms.sample_locations_enable ? + dyn->ms.sample_locations : NULL); + } if ((cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_PIPELINE) || BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_COLOR_WRITE_ENABLES) || |